root/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

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   1 /*
   2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _gc_9_0_SH_MASK_HEADER
  22 #define _gc_9_0_SH_MASK_HEADER
  23 
  24 //GCEA_EDC_CNT
  25 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
  26 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
  27 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
  28 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
  29 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
  30 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
  31 #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                            0xc
  32 #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                            0xe
  33 #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                            0x10
  34 #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                            0x12
  35 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                         0x14
  36 #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                         0x16
  37 #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                            0x18
  38 #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                            0x1a
  39 #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                           0x1c
  40 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
  41 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
  42 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
  43 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
  44 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
  45 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
  46 #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                              0x00003000L
  47 #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                              0x0000C000L
  48 #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                              0x00030000L
  49 #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                              0x000C0000L
  50 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                           0x00300000L
  51 #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                           0x00C00000L
  52 #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                              0x03000000L
  53 #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                              0x0C000000L
  54 #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                             0x30000000L
  55 
  56 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
  57 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
  58 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
  59 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
  60 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
  61 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
  62 #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                         0xc
  63 #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                         0xe
  64 #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                             0x10
  65 #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                             0x12
  66 #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                             0x14
  67 #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                             0x16
  68 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
  69 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
  70 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
  71 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
  72 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
  73 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
  74 #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                           0x00003000L
  75 #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                           0x0000C000L
  76 #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                               0x00030000L
  77 #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                               0x000C0000L
  78 #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                               0x00300000L
  79 #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                               0x00C00000L
  80 
  81 // addressBlock: gc_cppdec2
  82 //CPF_EDC_TAG_CNT
  83 #define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT                                                                     0x0
  84 #define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT                                                                     0x2
  85 #define CPF_EDC_TAG_CNT__DED_COUNT_MASK                                                                       0x00000003L
  86 #define CPF_EDC_TAG_CNT__SEC_COUNT_MASK                                                                       0x0000000CL
  87 //CPF_EDC_ROQ_CNT
  88 #define CPF_EDC_ROQ_CNT__COUNT_ME1__SHIFT                                                                     0x0
  89 #define CPF_EDC_ROQ_CNT__COUNT_ME2__SHIFT                                                                     0x2
  90 #define CPF_EDC_ROQ_CNT__COUNT_ME1_MASK                                                                       0x00000003L
  91 #define CPF_EDC_ROQ_CNT__COUNT_ME2_MASK                                                                       0x0000000CL
  92 //CPG_EDC_TAG_CNT
  93 #define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT                                                                     0x0
  94 #define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT                                                                     0x2
  95 #define CPG_EDC_TAG_CNT__DED_COUNT_MASK                                                                       0x00000003L
  96 #define CPG_EDC_TAG_CNT__SEC_COUNT_MASK                                                                       0x0000000CL
  97 //CPG_EDC_DMA_CNT
  98 #define CPG_EDC_DMA_CNT__ROQ_COUNT__SHIFT                                                                     0x0
  99 #define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT                                                                 0x2
 100 #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT                                                                 0x4
 101 #define CPG_EDC_DMA_CNT__ROQ_COUNT_MASK                                                                       0x00000003L
 102 #define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK                                                                   0x0000000CL
 103 #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK                                                                   0x00000030L
 104 //CPC_EDC_SCRATCH_CNT
 105 #define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT                                                                 0x0
 106 #define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT                                                                 0x2
 107 #define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK                                                                   0x00000003L
 108 #define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK                                                                   0x0000000CL
 109 //CPC_EDC_UCODE_CNT
 110 #define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT                                                                   0x0
 111 #define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT                                                                   0x2
 112 #define CPC_EDC_UCODE_CNT__DED_COUNT_MASK                                                                     0x00000003L
 113 #define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK                                                                     0x0000000CL
 114 //DC_EDC_STATE_CNT
 115 #define DC_EDC_STATE_CNT__COUNT_ME1__SHIFT                                                                    0x0
 116 #define DC_EDC_STATE_CNT__COUNT_ME1_MASK                                                                      0x00000003L
 117 //DC_EDC_CSINVOC_CNT
 118 #define DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT                                                                  0x0
 119 #define DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK                                                                    0x00000003L
 120 //DC_EDC_RESTORE_CNT
 121 #define DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT                                                                  0x0
 122 #define DC_EDC_RESTORE_CNT__COUNT_ME1_MASK                                                                    0x00000003L
 123 
 124 // addressBlock: gc_grbmdec
 125 //GRBM_CNTL
 126 #define GRBM_CNTL__READ_TIMEOUT__SHIFT                                                                        0x0
 127 #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT                                                                   0x1f
 128 #define GRBM_CNTL__READ_TIMEOUT_MASK                                                                          0x000000FFL
 129 #define GRBM_CNTL__REPORT_LAST_RDERR_MASK                                                                     0x80000000L
 130 //GRBM_SKEW_CNTL
 131 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT                                                             0x0
 132 #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT                                                                     0x6
 133 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK                                                               0x0000003FL
 134 #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK                                                                       0x00000FC0L
 135 //GRBM_STATUS2
 136 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT                                                           0x0
 137 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT                                                           0x4
 138 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT                                                           0x5
 139 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT                                                              0x6
 140 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT                                                              0x7
 141 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT                                                              0x8
 142 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT                                                              0x9
 143 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT                                                              0xa
 144 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT                                                              0xb
 145 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT                                                              0xc
 146 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT                                                              0xd
 147 #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT                                                                   0xe
 148 #define GRBM_STATUS2__UTCL2_BUSY__SHIFT                                                                       0xf
 149 #define GRBM_STATUS2__EA_BUSY__SHIFT                                                                          0x10
 150 #define GRBM_STATUS2__RMI_BUSY__SHIFT                                                                         0x11
 151 #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT                                                                 0x12
 152 #define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT                                                                   0x13
 153 #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT                                                                     0x14
 154 #define GRBM_STATUS2__RLC_BUSY__SHIFT                                                                         0x18
 155 #define GRBM_STATUS2__TC_BUSY__SHIFT                                                                          0x19
 156 #define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT                                                                  0x1a
 157 #define GRBM_STATUS2__CPF_BUSY__SHIFT                                                                         0x1c
 158 #define GRBM_STATUS2__CPC_BUSY__SHIFT                                                                         0x1d
 159 #define GRBM_STATUS2__CPG_BUSY__SHIFT                                                                         0x1e
 160 #define GRBM_STATUS2__CPAXI_BUSY__SHIFT                                                                       0x1f
 161 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK                                                             0x0000000FL
 162 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK                                                             0x00000010L
 163 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK                                                             0x00000020L
 164 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK                                                                0x00000040L
 165 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK                                                                0x00000080L
 166 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK                                                                0x00000100L
 167 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK                                                                0x00000200L
 168 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK                                                                0x00000400L
 169 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK                                                                0x00000800L
 170 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK                                                                0x00001000L
 171 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK                                                                0x00002000L
 172 #define GRBM_STATUS2__RLC_RQ_PENDING_MASK                                                                     0x00004000L
 173 #define GRBM_STATUS2__UTCL2_BUSY_MASK                                                                         0x00008000L
 174 #define GRBM_STATUS2__EA_BUSY_MASK                                                                            0x00010000L
 175 #define GRBM_STATUS2__RMI_BUSY_MASK                                                                           0x00020000L
 176 #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK                                                                   0x00040000L
 177 #define GRBM_STATUS2__CPF_RQ_PENDING_MASK                                                                     0x00080000L
 178 #define GRBM_STATUS2__EA_LINK_BUSY_MASK                                                                       0x00100000L
 179 #define GRBM_STATUS2__RLC_BUSY_MASK                                                                           0x01000000L
 180 #define GRBM_STATUS2__TC_BUSY_MASK                                                                            0x02000000L
 181 #define GRBM_STATUS2__TCC_CC_RESIDENT_MASK                                                                    0x04000000L
 182 #define GRBM_STATUS2__CPF_BUSY_MASK                                                                           0x10000000L
 183 #define GRBM_STATUS2__CPC_BUSY_MASK                                                                           0x20000000L
 184 #define GRBM_STATUS2__CPG_BUSY_MASK                                                                           0x40000000L
 185 #define GRBM_STATUS2__CPAXI_BUSY_MASK                                                                         0x80000000L
 186 //GRBM_PWR_CNTL
 187 #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT                                                                    0x0
 188 #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT                                                                    0x2
 189 #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT                                                                    0x4
 190 #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT                                                                    0x6
 191 #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT                                                                      0xe
 192 #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT                                                                      0xf
 193 #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK                                                                      0x00000003L
 194 #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK                                                                      0x0000000CL
 195 #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK                                                                      0x00000030L
 196 #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK                                                                      0x000000C0L
 197 #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK                                                                        0x00004000L
 198 #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK                                                                        0x00008000L
 199 //GRBM_STATUS
 200 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT                                                            0x0
 201 #define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT                                                                   0x5
 202 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT                                                            0x7
 203 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT                                                            0x8
 204 #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT                                                                0x9
 205 #define GRBM_STATUS__DB_CLEAN__SHIFT                                                                          0xc
 206 #define GRBM_STATUS__CB_CLEAN__SHIFT                                                                          0xd
 207 #define GRBM_STATUS__TA_BUSY__SHIFT                                                                           0xe
 208 #define GRBM_STATUS__GDS_BUSY__SHIFT                                                                          0xf
 209 #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT                                                                    0x10
 210 #define GRBM_STATUS__VGT_BUSY__SHIFT                                                                          0x11
 211 #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT                                                                    0x12
 212 #define GRBM_STATUS__IA_BUSY__SHIFT                                                                           0x13
 213 #define GRBM_STATUS__SX_BUSY__SHIFT                                                                           0x14
 214 #define GRBM_STATUS__WD_BUSY__SHIFT                                                                           0x15
 215 #define GRBM_STATUS__SPI_BUSY__SHIFT                                                                          0x16
 216 #define GRBM_STATUS__BCI_BUSY__SHIFT                                                                          0x17
 217 #define GRBM_STATUS__SC_BUSY__SHIFT                                                                           0x18
 218 #define GRBM_STATUS__PA_BUSY__SHIFT                                                                           0x19
 219 #define GRBM_STATUS__DB_BUSY__SHIFT                                                                           0x1a
 220 #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT                                                                 0x1c
 221 #define GRBM_STATUS__CP_BUSY__SHIFT                                                                           0x1d
 222 #define GRBM_STATUS__CB_BUSY__SHIFT                                                                           0x1e
 223 #define GRBM_STATUS__GUI_ACTIVE__SHIFT                                                                        0x1f
 224 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK                                                              0x0000000FL
 225 #define GRBM_STATUS__RSMU_RQ_PENDING_MASK                                                                     0x00000020L
 226 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK                                                              0x00000080L
 227 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK                                                              0x00000100L
 228 #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK                                                                  0x00000200L
 229 #define GRBM_STATUS__DB_CLEAN_MASK                                                                            0x00001000L
 230 #define GRBM_STATUS__CB_CLEAN_MASK                                                                            0x00002000L
 231 #define GRBM_STATUS__TA_BUSY_MASK                                                                             0x00004000L
 232 #define GRBM_STATUS__GDS_BUSY_MASK                                                                            0x00008000L
 233 #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK                                                                      0x00010000L
 234 #define GRBM_STATUS__VGT_BUSY_MASK                                                                            0x00020000L
 235 #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK                                                                      0x00040000L
 236 #define GRBM_STATUS__IA_BUSY_MASK                                                                             0x00080000L
 237 #define GRBM_STATUS__SX_BUSY_MASK                                                                             0x00100000L
 238 #define GRBM_STATUS__WD_BUSY_MASK                                                                             0x00200000L
 239 #define GRBM_STATUS__SPI_BUSY_MASK                                                                            0x00400000L
 240 #define GRBM_STATUS__BCI_BUSY_MASK                                                                            0x00800000L
 241 #define GRBM_STATUS__SC_BUSY_MASK                                                                             0x01000000L
 242 #define GRBM_STATUS__PA_BUSY_MASK                                                                             0x02000000L
 243 #define GRBM_STATUS__DB_BUSY_MASK                                                                             0x04000000L
 244 #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK                                                                   0x10000000L
 245 #define GRBM_STATUS__CP_BUSY_MASK                                                                             0x20000000L
 246 #define GRBM_STATUS__CB_BUSY_MASK                                                                             0x40000000L
 247 #define GRBM_STATUS__GUI_ACTIVE_MASK                                                                          0x80000000L
 248 //GRBM_STATUS_SE0
 249 #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT                                                                      0x1
 250 #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT                                                                      0x2
 251 #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT                                                                      0x15
 252 #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT                                                                      0x16
 253 #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT                                                                      0x17
 254 #define GRBM_STATUS_SE0__PA_BUSY__SHIFT                                                                       0x18
 255 #define GRBM_STATUS_SE0__TA_BUSY__SHIFT                                                                       0x19
 256 #define GRBM_STATUS_SE0__SX_BUSY__SHIFT                                                                       0x1a
 257 #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT                                                                      0x1b
 258 #define GRBM_STATUS_SE0__SC_BUSY__SHIFT                                                                       0x1d
 259 #define GRBM_STATUS_SE0__DB_BUSY__SHIFT                                                                       0x1e
 260 #define GRBM_STATUS_SE0__CB_BUSY__SHIFT                                                                       0x1f
 261 #define GRBM_STATUS_SE0__DB_CLEAN_MASK                                                                        0x00000002L
 262 #define GRBM_STATUS_SE0__CB_CLEAN_MASK                                                                        0x00000004L
 263 #define GRBM_STATUS_SE0__RMI_BUSY_MASK                                                                        0x00200000L
 264 #define GRBM_STATUS_SE0__BCI_BUSY_MASK                                                                        0x00400000L
 265 #define GRBM_STATUS_SE0__VGT_BUSY_MASK                                                                        0x00800000L
 266 #define GRBM_STATUS_SE0__PA_BUSY_MASK                                                                         0x01000000L
 267 #define GRBM_STATUS_SE0__TA_BUSY_MASK                                                                         0x02000000L
 268 #define GRBM_STATUS_SE0__SX_BUSY_MASK                                                                         0x04000000L
 269 #define GRBM_STATUS_SE0__SPI_BUSY_MASK                                                                        0x08000000L
 270 #define GRBM_STATUS_SE0__SC_BUSY_MASK                                                                         0x20000000L
 271 #define GRBM_STATUS_SE0__DB_BUSY_MASK                                                                         0x40000000L
 272 #define GRBM_STATUS_SE0__CB_BUSY_MASK                                                                         0x80000000L
 273 //GRBM_STATUS_SE1
 274 #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT                                                                      0x1
 275 #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT                                                                      0x2
 276 #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT                                                                      0x15
 277 #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT                                                                      0x16
 278 #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT                                                                      0x17
 279 #define GRBM_STATUS_SE1__PA_BUSY__SHIFT                                                                       0x18
 280 #define GRBM_STATUS_SE1__TA_BUSY__SHIFT                                                                       0x19
 281 #define GRBM_STATUS_SE1__SX_BUSY__SHIFT                                                                       0x1a
 282 #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT                                                                      0x1b
 283 #define GRBM_STATUS_SE1__SC_BUSY__SHIFT                                                                       0x1d
 284 #define GRBM_STATUS_SE1__DB_BUSY__SHIFT                                                                       0x1e
 285 #define GRBM_STATUS_SE1__CB_BUSY__SHIFT                                                                       0x1f
 286 #define GRBM_STATUS_SE1__DB_CLEAN_MASK                                                                        0x00000002L
 287 #define GRBM_STATUS_SE1__CB_CLEAN_MASK                                                                        0x00000004L
 288 #define GRBM_STATUS_SE1__RMI_BUSY_MASK                                                                        0x00200000L
 289 #define GRBM_STATUS_SE1__BCI_BUSY_MASK                                                                        0x00400000L
 290 #define GRBM_STATUS_SE1__VGT_BUSY_MASK                                                                        0x00800000L
 291 #define GRBM_STATUS_SE1__PA_BUSY_MASK                                                                         0x01000000L
 292 #define GRBM_STATUS_SE1__TA_BUSY_MASK                                                                         0x02000000L
 293 #define GRBM_STATUS_SE1__SX_BUSY_MASK                                                                         0x04000000L
 294 #define GRBM_STATUS_SE1__SPI_BUSY_MASK                                                                        0x08000000L
 295 #define GRBM_STATUS_SE1__SC_BUSY_MASK                                                                         0x20000000L
 296 #define GRBM_STATUS_SE1__DB_BUSY_MASK                                                                         0x40000000L
 297 #define GRBM_STATUS_SE1__CB_BUSY_MASK                                                                         0x80000000L
 298 //GRBM_SOFT_RESET
 299 #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT                                                                 0x0
 300 #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT                                                                0x2
 301 #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT                                                                0x10
 302 #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT                                                                0x11
 303 #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT                                                                0x12
 304 #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT                                                                0x13
 305 #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT                                                                0x14
 306 #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT                                                              0x15
 307 #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT                                                                 0x16
 308 #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK                                                                   0x00000001L
 309 #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK                                                                  0x00000004L
 310 #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK                                                                  0x00010000L
 311 #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK                                                                  0x00020000L
 312 #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK                                                                  0x00040000L
 313 #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK                                                                  0x00080000L
 314 #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK                                                                  0x00100000L
 315 #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK                                                                0x00200000L
 316 #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK                                                                   0x00400000L
 317 //GRBM_CGTT_CLK_CNTL
 318 #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT                                                                   0x0
 319 #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT                                                             0x4
 320 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
 321 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
 322 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
 323 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
 324 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
 325 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
 326 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
 327 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
 328 #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT                                                          0x1e
 329 #define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK                                                                     0x0000000FL
 330 #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
 331 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
 332 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
 333 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
 334 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
 335 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
 336 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
 337 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
 338 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
 339 #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK                                                            0x40000000L
 340 //GRBM_GFX_CLKEN_CNTL
 341 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT                                                          0x0
 342 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT                                                            0x8
 343 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK                                                            0x0000000FL
 344 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK                                                              0x00001F00L
 345 //GRBM_WAIT_IDLE_CLOCKS
 346 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT                                                        0x0
 347 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK                                                          0x000000FFL
 348 //GRBM_STATUS_SE2
 349 #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT                                                                      0x1
 350 #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT                                                                      0x2
 351 #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT                                                                      0x15
 352 #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT                                                                      0x16
 353 #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT                                                                      0x17
 354 #define GRBM_STATUS_SE2__PA_BUSY__SHIFT                                                                       0x18
 355 #define GRBM_STATUS_SE2__TA_BUSY__SHIFT                                                                       0x19
 356 #define GRBM_STATUS_SE2__SX_BUSY__SHIFT                                                                       0x1a
 357 #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT                                                                      0x1b
 358 #define GRBM_STATUS_SE2__SC_BUSY__SHIFT                                                                       0x1d
 359 #define GRBM_STATUS_SE2__DB_BUSY__SHIFT                                                                       0x1e
 360 #define GRBM_STATUS_SE2__CB_BUSY__SHIFT                                                                       0x1f
 361 #define GRBM_STATUS_SE2__DB_CLEAN_MASK                                                                        0x00000002L
 362 #define GRBM_STATUS_SE2__CB_CLEAN_MASK                                                                        0x00000004L
 363 #define GRBM_STATUS_SE2__RMI_BUSY_MASK                                                                        0x00200000L
 364 #define GRBM_STATUS_SE2__BCI_BUSY_MASK                                                                        0x00400000L
 365 #define GRBM_STATUS_SE2__VGT_BUSY_MASK                                                                        0x00800000L
 366 #define GRBM_STATUS_SE2__PA_BUSY_MASK                                                                         0x01000000L
 367 #define GRBM_STATUS_SE2__TA_BUSY_MASK                                                                         0x02000000L
 368 #define GRBM_STATUS_SE2__SX_BUSY_MASK                                                                         0x04000000L
 369 #define GRBM_STATUS_SE2__SPI_BUSY_MASK                                                                        0x08000000L
 370 #define GRBM_STATUS_SE2__SC_BUSY_MASK                                                                         0x20000000L
 371 #define GRBM_STATUS_SE2__DB_BUSY_MASK                                                                         0x40000000L
 372 #define GRBM_STATUS_SE2__CB_BUSY_MASK                                                                         0x80000000L
 373 //GRBM_STATUS_SE3
 374 #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT                                                                      0x1
 375 #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT                                                                      0x2
 376 #define GRBM_STATUS_SE3__RMI_BUSY__SHIFT                                                                      0x15
 377 #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT                                                                      0x16
 378 #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT                                                                      0x17
 379 #define GRBM_STATUS_SE3__PA_BUSY__SHIFT                                                                       0x18
 380 #define GRBM_STATUS_SE3__TA_BUSY__SHIFT                                                                       0x19
 381 #define GRBM_STATUS_SE3__SX_BUSY__SHIFT                                                                       0x1a
 382 #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT                                                                      0x1b
 383 #define GRBM_STATUS_SE3__SC_BUSY__SHIFT                                                                       0x1d
 384 #define GRBM_STATUS_SE3__DB_BUSY__SHIFT                                                                       0x1e
 385 #define GRBM_STATUS_SE3__CB_BUSY__SHIFT                                                                       0x1f
 386 #define GRBM_STATUS_SE3__DB_CLEAN_MASK                                                                        0x00000002L
 387 #define GRBM_STATUS_SE3__CB_CLEAN_MASK                                                                        0x00000004L
 388 #define GRBM_STATUS_SE3__RMI_BUSY_MASK                                                                        0x00200000L
 389 #define GRBM_STATUS_SE3__BCI_BUSY_MASK                                                                        0x00400000L
 390 #define GRBM_STATUS_SE3__VGT_BUSY_MASK                                                                        0x00800000L
 391 #define GRBM_STATUS_SE3__PA_BUSY_MASK                                                                         0x01000000L
 392 #define GRBM_STATUS_SE3__TA_BUSY_MASK                                                                         0x02000000L
 393 #define GRBM_STATUS_SE3__SX_BUSY_MASK                                                                         0x04000000L
 394 #define GRBM_STATUS_SE3__SPI_BUSY_MASK                                                                        0x08000000L
 395 #define GRBM_STATUS_SE3__SC_BUSY_MASK                                                                         0x20000000L
 396 #define GRBM_STATUS_SE3__DB_BUSY_MASK                                                                         0x40000000L
 397 #define GRBM_STATUS_SE3__CB_BUSY_MASK                                                                         0x80000000L
 398 //GRBM_READ_ERROR
 399 #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT                                                                  0x2
 400 #define GRBM_READ_ERROR__READ_PIPEID__SHIFT                                                                   0x14
 401 #define GRBM_READ_ERROR__READ_MEID__SHIFT                                                                     0x16
 402 #define GRBM_READ_ERROR__READ_ERROR__SHIFT                                                                    0x1f
 403 #define GRBM_READ_ERROR__READ_ADDRESS_MASK                                                                    0x0003FFFCL
 404 #define GRBM_READ_ERROR__READ_PIPEID_MASK                                                                     0x00300000L
 405 #define GRBM_READ_ERROR__READ_MEID_MASK                                                                       0x00C00000L
 406 #define GRBM_READ_ERROR__READ_ERROR_MASK                                                                      0x80000000L
 407 //GRBM_READ_ERROR2
 408 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT                                                           0x10
 409 #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT                                                          0x11
 410 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT                                                           0x12
 411 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT                                                       0x13
 412 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT                                                   0x14
 413 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT                                                   0x15
 414 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT                                                   0x16
 415 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT                                                   0x17
 416 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT                                                      0x18
 417 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT                                                      0x19
 418 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT                                                      0x1a
 419 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT                                                      0x1b
 420 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT                                                      0x1c
 421 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT                                                      0x1d
 422 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT                                                      0x1e
 423 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT                                                      0x1f
 424 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK                                                             0x00010000L
 425 #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK                                                            0x00020000L
 426 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK                                                             0x00040000L
 427 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK                                                         0x00080000L
 428 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK                                                     0x00100000L
 429 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK                                                     0x00200000L
 430 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK                                                     0x00400000L
 431 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK                                                     0x00800000L
 432 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK                                                        0x01000000L
 433 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK                                                        0x02000000L
 434 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK                                                        0x04000000L
 435 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK                                                        0x08000000L
 436 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK                                                        0x10000000L
 437 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK                                                        0x20000000L
 438 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK                                                        0x40000000L
 439 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK                                                        0x80000000L
 440 //GRBM_INT_CNTL
 441 #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT                                                                0x0
 442 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT                                                             0x13
 443 #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK                                                                  0x00000001L
 444 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK                                                               0x00080000L
 445 //GRBM_TRAP_OP
 446 #define GRBM_TRAP_OP__RW__SHIFT                                                                               0x0
 447 #define GRBM_TRAP_OP__RW_MASK                                                                                 0x00000001L
 448 //GRBM_TRAP_ADDR
 449 #define GRBM_TRAP_ADDR__DATA__SHIFT                                                                           0x0
 450 #define GRBM_TRAP_ADDR__DATA_MASK                                                                             0x0003FFFFL
 451 //GRBM_TRAP_ADDR_MSK
 452 #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT                                                                       0x0
 453 #define GRBM_TRAP_ADDR_MSK__DATA_MASK                                                                         0x0003FFFFL
 454 //GRBM_TRAP_WD
 455 #define GRBM_TRAP_WD__DATA__SHIFT                                                                             0x0
 456 #define GRBM_TRAP_WD__DATA_MASK                                                                               0xFFFFFFFFL
 457 //GRBM_TRAP_WD_MSK
 458 #define GRBM_TRAP_WD_MSK__DATA__SHIFT                                                                         0x0
 459 #define GRBM_TRAP_WD_MSK__DATA_MASK                                                                           0xFFFFFFFFL
 460 //GRBM_DSM_BYPASS
 461 #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT                                                                   0x0
 462 #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT                                                                     0x2
 463 #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK                                                                     0x00000003L
 464 #define GRBM_DSM_BYPASS__BYPASS_EN_MASK                                                                       0x00000004L
 465 //GRBM_WRITE_ERROR
 466 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT                                                          0x0
 467 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT                                                         0x1
 468 #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT                                                                 0x2
 469 #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT                                                                   0x5
 470 #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT                                                                     0xc
 471 #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT                                                                   0xd
 472 #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT                                                                 0x14
 473 #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT                                                                   0x16
 474 #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT                                                                  0x1f
 475 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK                                                            0x00000001L
 476 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK                                                           0x00000002L
 477 #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK                                                                   0x0000001CL
 478 #define GRBM_WRITE_ERROR__WRITE_VFID_MASK                                                                     0x000001E0L
 479 #define GRBM_WRITE_ERROR__WRITE_VF_MASK                                                                       0x00001000L
 480 #define GRBM_WRITE_ERROR__WRITE_VMID_MASK                                                                     0x0001E000L
 481 #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK                                                                   0x00300000L
 482 #define GRBM_WRITE_ERROR__WRITE_MEID_MASK                                                                     0x00C00000L
 483 #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK                                                                    0x80000000L
 484 //GRBM_IOV_ERROR
 485 #define GRBM_IOV_ERROR__IOV_ADDR__SHIFT                                                                       0x2
 486 #define GRBM_IOV_ERROR__IOV_VFID__SHIFT                                                                       0x14
 487 #define GRBM_IOV_ERROR__IOV_VF__SHIFT                                                                         0x1a
 488 #define GRBM_IOV_ERROR__IOV_OP__SHIFT                                                                         0x1b
 489 #define GRBM_IOV_ERROR__IOV_ERROR__SHIFT                                                                      0x1f
 490 #define GRBM_IOV_ERROR__IOV_ADDR_MASK                                                                         0x000FFFFCL
 491 #define GRBM_IOV_ERROR__IOV_VFID_MASK                                                                         0x03F00000L
 492 #define GRBM_IOV_ERROR__IOV_VF_MASK                                                                           0x04000000L
 493 #define GRBM_IOV_ERROR__IOV_OP_MASK                                                                           0x08000000L
 494 #define GRBM_IOV_ERROR__IOV_ERROR_MASK                                                                        0x80000000L
 495 //GRBM_CHIP_REVISION
 496 #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT                                                              0x0
 497 #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK                                                                0x000000FFL
 498 //GRBM_GFX_CNTL
 499 #define GRBM_GFX_CNTL__PIPEID__SHIFT                                                                          0x0
 500 #define GRBM_GFX_CNTL__MEID__SHIFT                                                                            0x2
 501 #define GRBM_GFX_CNTL__VMID__SHIFT                                                                            0x4
 502 #define GRBM_GFX_CNTL__QUEUEID__SHIFT                                                                         0x8
 503 #define GRBM_GFX_CNTL__PIPEID_MASK                                                                            0x00000003L
 504 #define GRBM_GFX_CNTL__MEID_MASK                                                                              0x0000000CL
 505 #define GRBM_GFX_CNTL__VMID_MASK                                                                              0x000000F0L
 506 #define GRBM_GFX_CNTL__QUEUEID_MASK                                                                           0x00000700L
 507 //GRBM_RSMU_CFG
 508 #define GRBM_RSMU_CFG__APERTURE_ID__SHIFT                                                                     0x0
 509 #define GRBM_RSMU_CFG__QOS__SHIFT                                                                             0xc
 510 #define GRBM_RSMU_CFG__POSTED_WR__SHIFT                                                                       0x10
 511 #define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT                                                                      0x11
 512 #define GRBM_RSMU_CFG__APERTURE_ID_MASK                                                                       0x00000FFFL
 513 #define GRBM_RSMU_CFG__QOS_MASK                                                                               0x0000F000L
 514 #define GRBM_RSMU_CFG__POSTED_WR_MASK                                                                         0x00010000L
 515 #define GRBM_RSMU_CFG__DEBUG_MASK_MASK                                                                        0x00020000L
 516 //GRBM_IH_CREDIT
 517 #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                   0x0
 518 #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT                                                                   0x10
 519 #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK                                                                     0x00000003L
 520 #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK                                                                     0x00FF0000L
 521 //GRBM_PWR_CNTL2
 522 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT                                                               0x10
 523 #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT                                                         0x14
 524 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK                                                                 0x00010000L
 525 #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK                                                           0x00100000L
 526 //GRBM_UTCL2_INVAL_RANGE_START
 527 #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT                                                             0x0
 528 #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK                                                               0x0003FFFFL
 529 //GRBM_UTCL2_INVAL_RANGE_END
 530 #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT                                                               0x0
 531 #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK                                                                 0x0003FFFFL
 532 //GRBM_RSMU_READ_ERROR
 533 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT                                                        0x2
 534 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT                                                             0x14
 535 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT                                                           0x15
 536 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT                                                     0x1b
 537 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT                                                          0x1f
 538 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK                                                          0x000FFFFCL
 539 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK                                                               0x00100000L
 540 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK                                                             0x07E00000L
 541 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK                                                       0x08000000L
 542 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK                                                            0x80000000L
 543 //GRBM_CHICKEN_BITS
 544 #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT                                                   0x0
 545 #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK                                                     0x00000001L
 546 //GRBM_NOWHERE
 547 #define GRBM_NOWHERE__DATA__SHIFT                                                                             0x0
 548 #define GRBM_NOWHERE__DATA_MASK                                                                               0xFFFFFFFFL
 549 //GRBM_SCRATCH_REG0
 550 #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                0x0
 551 #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK                                                                  0xFFFFFFFFL
 552 //GRBM_SCRATCH_REG1
 553 #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                0x0
 554 #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK                                                                  0xFFFFFFFFL
 555 //GRBM_SCRATCH_REG2
 556 #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                0x0
 557 #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK                                                                  0xFFFFFFFFL
 558 //GRBM_SCRATCH_REG3
 559 #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                0x0
 560 #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK                                                                  0xFFFFFFFFL
 561 //GRBM_SCRATCH_REG4
 562 #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                0x0
 563 #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK                                                                  0xFFFFFFFFL
 564 //GRBM_SCRATCH_REG5
 565 #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                0x0
 566 #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK                                                                  0xFFFFFFFFL
 567 //GRBM_SCRATCH_REG6
 568 #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                0x0
 569 #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK                                                                  0xFFFFFFFFL
 570 //GRBM_SCRATCH_REG7
 571 #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                0x0
 572 #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK                                                                  0xFFFFFFFFL
 573 
 574 
 575 // addressBlock: gc_cpdec
 576 //CP_CPC_STATUS
 577 #define CP_CPC_STATUS__MEC1_BUSY__SHIFT                                                                       0x0
 578 #define CP_CPC_STATUS__MEC2_BUSY__SHIFT                                                                       0x1
 579 #define CP_CPC_STATUS__DC0_BUSY__SHIFT                                                                        0x2
 580 #define CP_CPC_STATUS__DC1_BUSY__SHIFT                                                                        0x3
 581 #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT                                                                      0x4
 582 #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT                                                                      0x5
 583 #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT                                                                       0x6
 584 #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT                                                                       0x7
 585 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT                                                                       0xa
 586 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT                                                                0xb
 587 #define CP_CPC_STATUS__QU_BUSY__SHIFT                                                                         0xc
 588 #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0xd
 589 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT                                                               0xe
 590 #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT                                                                    0x1d
 591 #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT                                                                    0x1e
 592 #define CP_CPC_STATUS__CPC_BUSY__SHIFT                                                                        0x1f
 593 #define CP_CPC_STATUS__MEC1_BUSY_MASK                                                                         0x00000001L
 594 #define CP_CPC_STATUS__MEC2_BUSY_MASK                                                                         0x00000002L
 595 #define CP_CPC_STATUS__DC0_BUSY_MASK                                                                          0x00000004L
 596 #define CP_CPC_STATUS__DC1_BUSY_MASK                                                                          0x00000008L
 597 #define CP_CPC_STATUS__RCIU1_BUSY_MASK                                                                        0x00000010L
 598 #define CP_CPC_STATUS__RCIU2_BUSY_MASK                                                                        0x00000020L
 599 #define CP_CPC_STATUS__ROQ1_BUSY_MASK                                                                         0x00000040L
 600 #define CP_CPC_STATUS__ROQ2_BUSY_MASK                                                                         0x00000080L
 601 #define CP_CPC_STATUS__TCIU_BUSY_MASK                                                                         0x00000400L
 602 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK                                                                  0x00000800L
 603 #define CP_CPC_STATUS__QU_BUSY_MASK                                                                           0x00001000L
 604 #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00002000L
 605 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK                                                                 0x00004000L
 606 #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK                                                                      0x20000000L
 607 #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK                                                                      0x40000000L
 608 #define CP_CPC_STATUS__CPC_BUSY_MASK                                                                          0x80000000L
 609 //CP_CPC_BUSY_STAT
 610 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT                                                               0x0
 611 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT                                                          0x1
 612 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT                                                              0x2
 613 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT                                                            0x3
 614 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT                                                          0x4
 615 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT                                                           0x5
 616 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT                                                           0x6
 617 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT                                                                 0x7
 618 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT                                                                0x8
 619 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x9
 620 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT                                                              0xa
 621 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT                                                              0xb
 622 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT                                                              0xc
 623 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT                                                              0xd
 624 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT                                                               0x10
 625 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT                                                          0x11
 626 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT                                                              0x12
 627 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT                                                            0x13
 628 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT                                                          0x14
 629 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT                                                           0x15
 630 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT                                                           0x16
 631 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT                                                                 0x17
 632 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT                                                                0x18
 633 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x19
 634 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT                                                              0x1a
 635 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT                                                              0x1b
 636 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT                                                              0x1c
 637 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT                                                              0x1d
 638 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK                                                                 0x00000001L
 639 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK                                                            0x00000002L
 640 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK                                                                0x00000004L
 641 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK                                                              0x00000008L
 642 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK                                                            0x00000010L
 643 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK                                                             0x00000020L
 644 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK                                                             0x00000040L
 645 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK                                                                   0x00000080L
 646 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK                                                                  0x00000100L
 647 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK                                                        0x00000200L
 648 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK                                                                0x00000400L
 649 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK                                                                0x00000800L
 650 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK                                                                0x00001000L
 651 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK                                                                0x00002000L
 652 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK                                                                 0x00010000L
 653 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK                                                            0x00020000L
 654 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK                                                                0x00040000L
 655 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK                                                              0x00080000L
 656 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK                                                            0x00100000L
 657 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK                                                             0x00200000L
 658 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK                                                             0x00400000L
 659 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK                                                                   0x00800000L
 660 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK                                                                  0x01000000L
 661 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK                                                        0x02000000L
 662 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK                                                                0x04000000L
 663 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK                                                                0x08000000L
 664 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK                                                                0x10000000L
 665 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK                                                                0x20000000L
 666 //CP_CPC_STALLED_STAT1
 667 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT                                                       0x3
 668 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT                                                      0x4
 669 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT                                                       0x6
 670 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT                                                     0x8
 671 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT                                                        0x9
 672 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT                                                   0xa
 673 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT                                                    0xd
 674 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT                                                     0x10
 675 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT                                                        0x11
 676 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT                                                   0x12
 677 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT                                                    0x15
 678 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x16
 679 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x17
 680 #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT                                                   0x18
 681 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK                                                         0x00000008L
 682 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK                                                        0x00000010L
 683 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK                                                         0x00000040L
 684 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK                                                       0x00000100L
 685 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK                                                          0x00000200L
 686 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK                                                     0x00000400L
 687 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK                                                      0x00002000L
 688 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK                                                       0x00010000L
 689 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK                                                          0x00020000L
 690 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK                                                     0x00040000L
 691 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK                                                      0x00200000L
 692 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00400000L
 693 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00800000L
 694 #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK                                                     0x01000000L
 695 //CP_CPF_STATUS
 696 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT                                                              0x0
 697 #define CP_CPF_STATUS__CSF_BUSY__SHIFT                                                                        0x1
 698 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT                                                                  0x4
 699 #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT                                                                   0x5
 700 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT                                                              0x6
 701 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT                                                              0x7
 702 #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT                                                                  0x8
 703 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT                                                                0x9
 704 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                           0xa
 705 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                           0xb
 706 #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT                                                                  0xc
 707 #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT                                                                  0xd
 708 #define CP_CPF_STATUS__TCIU_BUSY__SHIFT                                                                       0xe
 709 #define CP_CPF_STATUS__HQD_BUSY__SHIFT                                                                        0xf
 710 #define CP_CPF_STATUS__PRT_BUSY__SHIFT                                                                        0x10
 711 #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0x11
 712 #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT                                                                    0x1a
 713 #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT                                                                    0x1b
 714 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT                                                              0x1c
 715 #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT                                                                    0x1e
 716 #define CP_CPF_STATUS__CPF_BUSY__SHIFT                                                                        0x1f
 717 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK                                                                0x00000001L
 718 #define CP_CPF_STATUS__CSF_BUSY_MASK                                                                          0x00000002L
 719 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK                                                                    0x00000010L
 720 #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK                                                                     0x00000020L
 721 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK                                                                0x00000040L
 722 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK                                                                0x00000080L
 723 #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK                                                                    0x00000100L
 724 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK                                                                  0x00000200L
 725 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK                                                             0x00000400L
 726 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK                                                             0x00000800L
 727 #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK                                                                    0x00001000L
 728 #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK                                                                    0x00002000L
 729 #define CP_CPF_STATUS__TCIU_BUSY_MASK                                                                         0x00004000L
 730 #define CP_CPF_STATUS__HQD_BUSY_MASK                                                                          0x00008000L
 731 #define CP_CPF_STATUS__PRT_BUSY_MASK                                                                          0x00010000L
 732 #define CP_CPF_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00020000L
 733 #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK                                                                      0x04000000L
 734 #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK                                                                      0x08000000L
 735 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK                                                                0x30000000L
 736 #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK                                                                      0x40000000L
 737 #define CP_CPF_STATUS__CPF_BUSY_MASK                                                                          0x80000000L
 738 //CP_CPF_BUSY_STAT
 739 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                            0x0
 740 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT                                                                0x1
 741 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT                                                           0x2
 742 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT                                                           0x3
 743 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT                                                               0x4
 744 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT                                                            0x5
 745 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT                                                            0x6
 746 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT                                                             0x7
 747 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT                                                               0x8
 748 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT                                                        0x9
 749 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT                                                      0xb
 750 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT                                                            0xc
 751 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT                                                            0xd
 752 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT                                                         0xe
 753 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT                                                      0xf
 754 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT                                                    0x10
 755 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT                                                             0x11
 756 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT                                                          0x12
 757 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT                                                          0x13
 758 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT                                                          0x14
 759 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT                                                         0x15
 760 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT                                                       0x16
 761 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT                                                         0x17
 762 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT                                                           0x18
 763 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT                                                             0x19
 764 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT                                                              0x1a
 765 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT                                                              0x1b
 766 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT                                                              0x1c
 767 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT                                                           0x1d
 768 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT                                                                  0x1e
 769 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT                                                                  0x1f
 770 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                              0x00000001L
 771 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK                                                                  0x00000002L
 772 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK                                                             0x00000004L
 773 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK                                                             0x00000008L
 774 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK                                                                 0x00000010L
 775 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK                                                              0x00000020L
 776 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK                                                              0x00000040L
 777 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK                                                               0x00000080L
 778 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK                                                                 0x00000100L
 779 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK                                                          0x00000200L
 780 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK                                                        0x00000800L
 781 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK                                                              0x00001000L
 782 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK                                                              0x00002000L
 783 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK                                                           0x00004000L
 784 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK                                                        0x00008000L
 785 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK                                                      0x00010000L
 786 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK                                                               0x00020000L
 787 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK                                                            0x00040000L
 788 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK                                                            0x00080000L
 789 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK                                                            0x00100000L
 790 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK                                                           0x00200000L
 791 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK                                                         0x00400000L
 792 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK                                                           0x00800000L
 793 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK                                                             0x01000000L
 794 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK                                                               0x02000000L
 795 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK                                                                0x04000000L
 796 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK                                                                0x08000000L
 797 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK                                                                0x10000000L
 798 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK                                                             0x20000000L
 799 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK                                                                    0x40000000L
 800 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK                                                                    0x80000000L
 801 //CP_CPF_STALLED_STAT1
 802 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT                                                       0x0
 803 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT                                                      0x1
 804 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT                                                      0x2
 805 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT                                                      0x3
 806 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT                                                     0x5
 807 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT                                                     0x6
 808 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x7
 809 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x8
 810 #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT                                               0x9
 811 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT                                               0xa
 812 #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT                                                     0xb
 813 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK                                                         0x00000001L
 814 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK                                                        0x00000002L
 815 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK                                                        0x00000004L
 816 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK                                                        0x00000008L
 817 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK                                                       0x00000020L
 818 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK                                                       0x00000040L
 819 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00000080L
 820 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00000100L
 821 #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000200L
 822 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000400L
 823 #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK                                                       0x00000800L
 824 //CP_CPC_GRBM_FREE_COUNT
 825 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
 826 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x0000003FL
 827 //CP_MEC_CNTL
 828 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT                                                             0x4
 829 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT                                                               0x10
 830 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT                                                               0x11
 831 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT                                                               0x12
 832 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT                                                               0x13
 833 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT                                                               0x14
 834 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT                                                               0x15
 835 #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT                                                                      0x1c
 836 #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT                                                                      0x1d
 837 #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT                                                                      0x1e
 838 #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT                                                                      0x1f
 839 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK                                                               0x00000010L
 840 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK                                                                 0x00010000L
 841 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK                                                                 0x00020000L
 842 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK                                                                 0x00040000L
 843 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK                                                                 0x00080000L
 844 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK                                                                 0x00100000L
 845 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK                                                                 0x00200000L
 846 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK                                                                        0x10000000L
 847 #define CP_MEC_CNTL__MEC_ME2_STEP_MASK                                                                        0x20000000L
 848 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK                                                                        0x40000000L
 849 #define CP_MEC_CNTL__MEC_ME1_STEP_MASK                                                                        0x80000000L
 850 //CP_MEC_ME1_HEADER_DUMP
 851 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
 852 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
 853 //CP_MEC_ME2_HEADER_DUMP
 854 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
 855 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
 856 //CP_CPC_SCRATCH_INDEX
 857 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                            0x0
 858 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                              0x000001FFL
 859 //CP_CPC_SCRATCH_DATA
 860 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                              0x0
 861 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                0xFFFFFFFFL
 862 //CP_CPF_GRBM_FREE_COUNT
 863 #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
 864 #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x00000007L
 865 //CP_CPC_HALT_HYST_COUNT
 866 #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT                                                                  0x0
 867 #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK                                                                    0x0000000FL
 868 //CP_PRT_LOD_STATS_CNTL0
 869 #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT                                                                0x0
 870 #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK                                                                  0xFFFFFFFFL
 871 //CP_PRT_LOD_STATS_CNTL1
 872 #define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT                                                                0x0
 873 #define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK                                                                  0xFFFFFFFFL
 874 //CP_PRT_LOD_STATS_CNTL2
 875 #define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT                                                                0x0
 876 #define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK                                                                  0x000003FFL
 877 //CP_PRT_LOD_STATS_CNTL3
 878 #define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT                                                               0x2
 879 #define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT                                                              0xa
 880 #define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT                                                            0x12
 881 #define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT                                                       0x13
 882 #define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT                                                                0x17
 883 #define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT                                                           0x1c
 884 #define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK                                                                 0x000003FCL
 885 #define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK                                                                0x0003FC00L
 886 #define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK                                                              0x00040000L
 887 #define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK                                                         0x00080000L
 888 #define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK                                                                  0x07800000L
 889 #define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK                                                             0x10000000L
 890 //CP_CE_COMPARE_COUNT
 891 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT                                                             0x0
 892 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK                                                               0xFFFFFFFFL
 893 //CP_CE_DE_COUNT
 894 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
 895 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
 896 //CP_DE_CE_COUNT
 897 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT                                                             0x0
 898 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK                                                               0xFFFFFFFFL
 899 //CP_DE_LAST_INVAL_COUNT
 900 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT                                                       0x0
 901 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK                                                         0xFFFFFFFFL
 902 //CP_DE_DE_COUNT
 903 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
 904 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
 905 //CP_STALLED_STAT3
 906 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                     0x0
 907 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT                                        0x1
 908 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT                                     0x2
 909 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT                                                       0x3
 910 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT                                                       0x4
 911 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT                                                      0x5
 912 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT                                                0x6
 913 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT                                                 0x7
 914 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT                                                    0xa
 915 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT                                                 0xb
 916 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT                                                     0xc
 917 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT                                           0xd
 918 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT                                                         0xe
 919 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT                                                         0xf
 920 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0x10
 921 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0x11
 922 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT                                                      0x12
 923 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                      0x13
 924 #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT                                                       0x14
 925 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK                                                       0x00000001L
 926 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK                                          0x00000002L
 927 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK                                       0x00000004L
 928 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK                                                         0x00000008L
 929 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK                                                         0x00000010L
 930 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK                                                        0x00000020L
 931 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK                                                  0x00000040L
 932 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK                                                   0x00000080L
 933 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK                                                      0x00000400L
 934 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK                                                   0x00000800L
 935 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK                                                       0x00001000L
 936 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK                                             0x00002000L
 937 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK                                                           0x00004000L
 938 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK                                                           0x00008000L
 939 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00010000L
 940 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00020000L
 941 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK                                                        0x00040000L
 942 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK                                                        0x00080000L
 943 #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK                                                         0x00100000L
 944 //CP_STALLED_STAT1
 945 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT                                                   0x0
 946 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT                                                   0x2
 947 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT                                                 0x4
 948 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT                                                 0xa
 949 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT                                                 0xb
 950 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0xc
 951 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0xd
 952 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT                                                   0xe
 953 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT                                                  0xf
 954 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT                                                     0x17
 955 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT                                                    0x18
 956 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT                                                     0x19
 957 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT                                                      0x1a
 958 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT                                                     0x1b
 959 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT                                                  0x1c
 960 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT                                                 0x1d
 961 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK                                                     0x00000001L
 962 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK                                                     0x00000004L
 963 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK                                                   0x00000010L
 964 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK                                                   0x00000400L
 965 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK                                                   0x00000800L
 966 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00001000L
 967 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00002000L
 968 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK                                                     0x00004000L
 969 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK                                                    0x00008000L
 970 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK                                                       0x00800000L
 971 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK                                                      0x01000000L
 972 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK                                                       0x02000000L
 973 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK                                                        0x04000000L
 974 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK                                                       0x08000000L
 975 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK                                                    0x10000000L
 976 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK                                                   0x20000000L
 977 //CP_STALLED_STAT2
 978 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                    0x0
 979 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT                                                    0x1
 980 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT                                                   0x2
 981 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT                                                    0x4
 982 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT                                                        0x5
 983 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT                                                   0x8
 984 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT                                                        0x9
 985 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT                                                      0xa
 986 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT                                                     0xb
 987 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT                                                       0xc
 988 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT                                                   0xd
 989 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT                                                     0xe
 990 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT                                                  0xf
 991 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x10
 992 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x11
 993 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT                                                     0x12
 994 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                 0x13
 995 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                               0x14
 996 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT                                                  0x15
 997 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT                                                   0x16
 998 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT                                                0x17
 999 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT                                                   0x18
1000 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT                                                   0x19
1001 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT                                                   0x1a
1002 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT                                                    0x1b
1003 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT                                                      0x1c
1004 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT                                              0x1d
1005 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT                                                   0x1e
1006 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT                                                    0x1f
1007 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK                                                      0x00000001L
1008 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK                                                      0x00000002L
1009 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK                                                     0x00000004L
1010 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK                                                      0x00000010L
1011 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK                                                          0x00000020L
1012 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK                                                     0x00000100L
1013 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK                                                          0x00000200L
1014 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK                                                        0x00000400L
1015 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK                                                       0x00000800L
1016 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK                                                         0x00001000L
1017 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK                                                     0x00002000L
1018 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK                                                       0x00004000L
1019 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK                                                    0x00008000L
1020 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00010000L
1021 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00020000L
1022 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK                                                       0x00040000L
1023 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK                                                   0x00080000L
1024 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                 0x00100000L
1025 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK                                                    0x00200000L
1026 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK                                                     0x00400000L
1027 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK                                                  0x00800000L
1028 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK                                                     0x01000000L
1029 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK                                                     0x02000000L
1030 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK                                                     0x04000000L
1031 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK                                                      0x08000000L
1032 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK                                                        0x10000000L
1033 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK                                                0x20000000L
1034 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK                                                     0x40000000L
1035 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK                                                      0x80000000L
1036 //CP_BUSY_STAT
1037 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                                0x0
1038 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT                                                               0x6
1039 #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT                                                              0x7
1040 #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT                                                               0x8
1041 #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT                                                                    0x9
1042 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT                                                                     0xa
1043 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT                                                            0xc
1044 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT                                                           0xd
1045 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT                                                             0xe
1046 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT                                                                 0xf
1047 #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT                                                                   0x11
1048 #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT                                                                    0x12
1049 #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT                                                                    0x13
1050 #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT                                                                  0x14
1051 #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT                                                                     0x15
1052 #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT                                                               0x16
1053 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                                  0x00000001L
1054 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK                                                                 0x00000040L
1055 #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK                                                                0x00000080L
1056 #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK                                                                 0x00000100L
1057 #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK                                                                      0x00000200L
1058 #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK                                                                       0x00000400L
1059 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK                                                              0x00001000L
1060 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK                                                             0x00002000L
1061 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK                                                               0x00004000L
1062 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK                                                                   0x00008000L
1063 #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK                                                                     0x00020000L
1064 #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK                                                                      0x00040000L
1065 #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK                                                                      0x00080000L
1066 #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK                                                                    0x00100000L
1067 #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK                                                                       0x00200000L
1068 #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK                                                                 0x00400000L
1069 //CP_STAT
1070 #define CP_STAT__ROQ_RING_BUSY__SHIFT                                                                         0x9
1071 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT                                                                    0xa
1072 #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT                                                                    0xb
1073 #define CP_STAT__ROQ_STATE_BUSY__SHIFT                                                                        0xc
1074 #define CP_STAT__DC_BUSY__SHIFT                                                                               0xd
1075 #define CP_STAT__UTCL2IU_BUSY__SHIFT                                                                          0xe
1076 #define CP_STAT__PFP_BUSY__SHIFT                                                                              0xf
1077 #define CP_STAT__MEQ_BUSY__SHIFT                                                                              0x10
1078 #define CP_STAT__ME_BUSY__SHIFT                                                                               0x11
1079 #define CP_STAT__QUERY_BUSY__SHIFT                                                                            0x12
1080 #define CP_STAT__SEMAPHORE_BUSY__SHIFT                                                                        0x13
1081 #define CP_STAT__INTERRUPT_BUSY__SHIFT                                                                        0x14
1082 #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT                                                                     0x15
1083 #define CP_STAT__DMA_BUSY__SHIFT                                                                              0x16
1084 #define CP_STAT__RCIU_BUSY__SHIFT                                                                             0x17
1085 #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT                                                                      0x18
1086 #define CP_STAT__CE_BUSY__SHIFT                                                                               0x1a
1087 #define CP_STAT__TCIU_BUSY__SHIFT                                                                             0x1b
1088 #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT                                                                      0x1c
1089 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                                 0x1d
1090 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                                 0x1e
1091 #define CP_STAT__CP_BUSY__SHIFT                                                                               0x1f
1092 #define CP_STAT__ROQ_RING_BUSY_MASK                                                                           0x00000200L
1093 #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK                                                                      0x00000400L
1094 #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK                                                                      0x00000800L
1095 #define CP_STAT__ROQ_STATE_BUSY_MASK                                                                          0x00001000L
1096 #define CP_STAT__DC_BUSY_MASK                                                                                 0x00002000L
1097 #define CP_STAT__UTCL2IU_BUSY_MASK                                                                            0x00004000L
1098 #define CP_STAT__PFP_BUSY_MASK                                                                                0x00008000L
1099 #define CP_STAT__MEQ_BUSY_MASK                                                                                0x00010000L
1100 #define CP_STAT__ME_BUSY_MASK                                                                                 0x00020000L
1101 #define CP_STAT__QUERY_BUSY_MASK                                                                              0x00040000L
1102 #define CP_STAT__SEMAPHORE_BUSY_MASK                                                                          0x00080000L
1103 #define CP_STAT__INTERRUPT_BUSY_MASK                                                                          0x00100000L
1104 #define CP_STAT__SURFACE_SYNC_BUSY_MASK                                                                       0x00200000L
1105 #define CP_STAT__DMA_BUSY_MASK                                                                                0x00400000L
1106 #define CP_STAT__RCIU_BUSY_MASK                                                                               0x00800000L
1107 #define CP_STAT__SCRATCH_RAM_BUSY_MASK                                                                        0x01000000L
1108 #define CP_STAT__CE_BUSY_MASK                                                                                 0x04000000L
1109 #define CP_STAT__TCIU_BUSY_MASK                                                                               0x08000000L
1110 #define CP_STAT__ROQ_CE_RING_BUSY_MASK                                                                        0x10000000L
1111 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK                                                                   0x20000000L
1112 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK                                                                   0x40000000L
1113 #define CP_STAT__CP_BUSY_MASK                                                                                 0x80000000L
1114 //CP_ME_HEADER_DUMP
1115 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT                                                              0x0
1116 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
1117 //CP_PFP_HEADER_DUMP
1118 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT                                                            0x0
1119 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK                                                              0xFFFFFFFFL
1120 //CP_GRBM_FREE_COUNT
1121 #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                                 0x0
1122 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT                                                             0x8
1123 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT                                                             0x10
1124 #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                                   0x0000003FL
1125 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK                                                               0x00003F00L
1126 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK                                                               0x003F0000L
1127 //CP_CE_HEADER_DUMP
1128 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT                                                              0x0
1129 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
1130 //CP_PFP_INSTR_PNTR
1131 #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                  0x0
1132 #define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK                                                                    0x0000FFFFL
1133 //CP_ME_INSTR_PNTR
1134 #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
1135 #define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
1136 //CP_CE_INSTR_PNTR
1137 #define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
1138 #define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
1139 //CP_MEC1_INSTR_PNTR
1140 #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
1141 #define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
1142 //CP_MEC2_INSTR_PNTR
1143 #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
1144 #define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
1145 //CP_CSF_STAT
1146 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT                                                              0x8
1147 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK                                                                0x0001FF00L
1148 //CP_ME_CNTL
1149 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT                                                               0x4
1150 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT                                                              0x6
1151 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT                                                               0x8
1152 #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT                                                                     0x10
1153 #define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT                                                                     0x11
1154 #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT                                                                    0x12
1155 #define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT                                                                    0x13
1156 #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT                                                                     0x14
1157 #define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT                                                                     0x15
1158 #define CP_ME_CNTL__CE_HALT__SHIFT                                                                            0x18
1159 #define CP_ME_CNTL__CE_STEP__SHIFT                                                                            0x19
1160 #define CP_ME_CNTL__PFP_HALT__SHIFT                                                                           0x1a
1161 #define CP_ME_CNTL__PFP_STEP__SHIFT                                                                           0x1b
1162 #define CP_ME_CNTL__ME_HALT__SHIFT                                                                            0x1c
1163 #define CP_ME_CNTL__ME_STEP__SHIFT                                                                            0x1d
1164 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK                                                                 0x00000010L
1165 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK                                                                0x00000040L
1166 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK                                                                 0x00000100L
1167 #define CP_ME_CNTL__CE_PIPE0_RESET_MASK                                                                       0x00010000L
1168 #define CP_ME_CNTL__CE_PIPE1_RESET_MASK                                                                       0x00020000L
1169 #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK                                                                      0x00040000L
1170 #define CP_ME_CNTL__PFP_PIPE1_RESET_MASK                                                                      0x00080000L
1171 #define CP_ME_CNTL__ME_PIPE0_RESET_MASK                                                                       0x00100000L
1172 #define CP_ME_CNTL__ME_PIPE1_RESET_MASK                                                                       0x00200000L
1173 #define CP_ME_CNTL__CE_HALT_MASK                                                                              0x01000000L
1174 #define CP_ME_CNTL__CE_STEP_MASK                                                                              0x02000000L
1175 #define CP_ME_CNTL__PFP_HALT_MASK                                                                             0x04000000L
1176 #define CP_ME_CNTL__PFP_STEP_MASK                                                                             0x08000000L
1177 #define CP_ME_CNTL__ME_HALT_MASK                                                                              0x10000000L
1178 #define CP_ME_CNTL__ME_STEP_MASK                                                                              0x20000000L
1179 //CP_CNTX_STAT
1180 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT                                                             0x0
1181 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT                                                             0x8
1182 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT                                                              0x14
1183 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT                                                              0x1c
1184 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK                                                               0x000000FFL
1185 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK                                                               0x00000700L
1186 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK                                                                0x0FF00000L
1187 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK                                                                0x70000000L
1188 //CP_ME_PREEMPTION
1189 #define CP_ME_PREEMPTION__OBSOLETE__SHIFT                                                                     0x0
1190 #define CP_ME_PREEMPTION__OBSOLETE_MASK                                                                       0x00000001L
1191 //CP_ROQ_THRESHOLDS
1192 #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT                                                                   0x0
1193 #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT                                                                   0x8
1194 #define CP_ROQ_THRESHOLDS__IB1_START_MASK                                                                     0x000000FFL
1195 #define CP_ROQ_THRESHOLDS__IB2_START_MASK                                                                     0x0000FF00L
1196 //CP_MEQ_STQ_THRESHOLD
1197 #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT                                                                0x0
1198 #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK                                                                  0x000000FFL
1199 //CP_RB2_RPTR
1200 #define CP_RB2_RPTR__RB_RPTR__SHIFT                                                                           0x0
1201 #define CP_RB2_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
1202 //CP_RB1_RPTR
1203 #define CP_RB1_RPTR__RB_RPTR__SHIFT                                                                           0x0
1204 #define CP_RB1_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
1205 //CP_RB0_RPTR
1206 #define CP_RB0_RPTR__RB_RPTR__SHIFT                                                                           0x0
1207 #define CP_RB0_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
1208 //CP_RB_RPTR
1209 #define CP_RB_RPTR__RB_RPTR__SHIFT                                                                            0x0
1210 #define CP_RB_RPTR__RB_RPTR_MASK                                                                              0x000FFFFFL
1211 //CP_RB_WPTR_DELAY
1212 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT                                                              0x0
1213 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT                                                              0x1c
1214 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK                                                                0x0FFFFFFFL
1215 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK                                                                0xF0000000L
1216 //CP_RB_WPTR_POLL_CNTL
1217 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT                                                           0x0
1218 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                          0x10
1219 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK                                                             0x0000FFFFL
1220 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                            0xFFFF0000L
1221 //CP_ROQ1_THRESHOLDS
1222 #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT                                                                  0x0
1223 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT                                                                  0x8
1224 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT                                                               0x10
1225 #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT                                                               0x18
1226 #define CP_ROQ1_THRESHOLDS__RB1_START_MASK                                                                    0x000000FFL
1227 #define CP_ROQ1_THRESHOLDS__RB2_START_MASK                                                                    0x0000FF00L
1228 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK                                                                 0x00FF0000L
1229 #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK                                                                 0xFF000000L
1230 //CP_ROQ2_THRESHOLDS
1231 #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT                                                               0x0
1232 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT                                                               0x8
1233 #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT                                                               0x10
1234 #define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT                                                               0x18
1235 #define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK                                                                 0x000000FFL
1236 #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK                                                                 0x0000FF00L
1237 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK                                                                 0x00FF0000L
1238 #define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK                                                                 0xFF000000L
1239 //CP_STQ_THRESHOLDS
1240 #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT                                                                  0x0
1241 #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT                                                                  0x8
1242 #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT                                                                  0x10
1243 #define CP_STQ_THRESHOLDS__STQ0_START_MASK                                                                    0x000000FFL
1244 #define CP_STQ_THRESHOLDS__STQ1_START_MASK                                                                    0x0000FF00L
1245 #define CP_STQ_THRESHOLDS__STQ2_START_MASK                                                                    0x00FF0000L
1246 //CP_QUEUE_THRESHOLDS
1247 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT                                                             0x0
1248 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT                                                             0x8
1249 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK                                                               0x0000003FL
1250 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK                                                               0x00003F00L
1251 //CP_MEQ_THRESHOLDS
1252 #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT                                                                  0x0
1253 #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT                                                                  0x8
1254 #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK                                                                    0x000000FFL
1255 #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK                                                                    0x0000FF00L
1256 //CP_ROQ_AVAIL
1257 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT                                                                     0x0
1258 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT                                                                      0x10
1259 #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK                                                                       0x000007FFL
1260 #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK                                                                        0x07FF0000L
1261 //CP_STQ_AVAIL
1262 #define CP_STQ_AVAIL__STQ_CNT__SHIFT                                                                          0x0
1263 #define CP_STQ_AVAIL__STQ_CNT_MASK                                                                            0x000001FFL
1264 //CP_ROQ2_AVAIL
1265 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT                                                                     0x0
1266 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK                                                                       0x000007FFL
1267 //CP_MEQ_AVAIL
1268 #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                                                                          0x0
1269 #define CP_MEQ_AVAIL__MEQ_CNT_MASK                                                                            0x000003FFL
1270 //CP_CMD_INDEX
1271 #define CP_CMD_INDEX__CMD_INDEX__SHIFT                                                                        0x0
1272 #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT                                                                       0xc
1273 #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                                                                    0x10
1274 #define CP_CMD_INDEX__CMD_INDEX_MASK                                                                          0x000007FFL
1275 #define CP_CMD_INDEX__CMD_ME_SEL_MASK                                                                         0x00003000L
1276 #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                                                                      0x00070000L
1277 //CP_CMD_DATA
1278 #define CP_CMD_DATA__CMD_DATA__SHIFT                                                                          0x0
1279 #define CP_CMD_DATA__CMD_DATA_MASK                                                                            0xFFFFFFFFL
1280 //CP_ROQ_RB_STAT
1281 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT                                                               0x0
1282 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT                                                               0x10
1283 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK                                                                 0x000003FFL
1284 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK                                                                 0x03FF0000L
1285 //CP_ROQ_IB1_STAT
1286 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT                                                            0x0
1287 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT                                                            0x10
1288 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK                                                              0x000003FFL
1289 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK                                                              0x03FF0000L
1290 //CP_ROQ_IB2_STAT
1291 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT                                                            0x0
1292 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT                                                            0x10
1293 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK                                                              0x000003FFL
1294 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK                                                              0x03FF0000L
1295 //CP_STQ_STAT
1296 #define CP_STQ_STAT__STQ_RPTR__SHIFT                                                                          0x0
1297 #define CP_STQ_STAT__STQ_RPTR_MASK                                                                            0x000003FFL
1298 //CP_STQ_WR_STAT
1299 #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT                                                                       0x0
1300 #define CP_STQ_WR_STAT__STQ_WPTR_MASK                                                                         0x000003FFL
1301 //CP_MEQ_STAT
1302 #define CP_MEQ_STAT__MEQ_RPTR__SHIFT                                                                          0x0
1303 #define CP_MEQ_STAT__MEQ_WPTR__SHIFT                                                                          0x10
1304 #define CP_MEQ_STAT__MEQ_RPTR_MASK                                                                            0x000003FFL
1305 #define CP_MEQ_STAT__MEQ_WPTR_MASK                                                                            0x03FF0000L
1306 //CP_CEQ1_AVAIL
1307 #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT                                                                    0x0
1308 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT                                                                     0x10
1309 #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK                                                                      0x000007FFL
1310 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK                                                                       0x07FF0000L
1311 //CP_CEQ2_AVAIL
1312 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT                                                                     0x0
1313 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK                                                                       0x000007FFL
1314 //CP_CE_ROQ_RB_STAT
1315 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT                                                            0x0
1316 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT                                                            0x10
1317 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK                                                              0x000003FFL
1318 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK                                                              0x03FF0000L
1319 //CP_CE_ROQ_IB1_STAT
1320 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT                                                         0x0
1321 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT                                                         0x10
1322 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK                                                           0x000003FFL
1323 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK                                                           0x03FF0000L
1324 //CP_CE_ROQ_IB2_STAT
1325 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT                                                         0x0
1326 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT                                                         0x10
1327 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK                                                           0x000003FFL
1328 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK                                                           0x03FF0000L
1329 //CP_INT_STAT_DEBUG
1330 #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT                                              0xb
1331 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT                                                   0xe
1332 #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT                                                            0x10
1333 #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT                                               0x11
1334 #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT                                                       0x12
1335 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT                                                      0x13
1336 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT                                                     0x14
1337 #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT                                                       0x15
1338 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT                                                     0x16
1339 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                       0x17
1340 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT                                                   0x18
1341 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT                                                     0x1a
1342 #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT                                             0x1b
1343 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT                                                       0x1d
1344 #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT                                                       0x1e
1345 #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT                                                       0x1f
1346 #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK                                                0x00000800L
1347 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK                                                     0x00004000L
1348 #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK                                                              0x00010000L
1349 #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK                                                 0x00020000L
1350 #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK                                                         0x00040000L
1351 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK                                                        0x00080000L
1352 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK                                                       0x00100000L
1353 #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK                                                         0x00200000L
1354 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK                                                       0x00400000L
1355 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                         0x00800000L
1356 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK                                                     0x01000000L
1357 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK                                                       0x04000000L
1358 #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK                                               0x08000000L
1359 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK                                                         0x20000000L
1360 #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK                                                         0x40000000L
1361 #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK                                                         0x80000000L
1362 
1363 
1364 // addressBlock: gc_padec
1365 //VGT_VTX_VECT_EJECT_REG
1366 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT                                                             0x0
1367 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK                                                               0x0000007FL
1368 //VGT_DMA_DATA_FIFO_DEPTH
1369 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT                                                   0x0
1370 #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT                                                   0x9
1371 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK                                                     0x000001FFL
1372 #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK                                                     0x0007FE00L
1373 //VGT_DMA_REQ_FIFO_DEPTH
1374 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT                                                     0x0
1375 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK                                                       0x0000003FL
1376 //VGT_DRAW_INIT_FIFO_DEPTH
1377 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT                                                 0x0
1378 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK                                                   0x0000003FL
1379 //VGT_LAST_COPY_STATE
1380 #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT                                                              0x0
1381 #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT                                                              0x10
1382 #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK                                                                0x00000007L
1383 #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK                                                                0x00070000L
1384 //VGT_CACHE_INVALIDATION
1385 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT                                                     0x0
1386 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT                                                     0x4
1387 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT                                                     0x5
1388 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT                                                          0x6
1389 #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT                                                            0x9
1390 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT                                                   0xb
1391 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT                                                       0xc
1392 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT                                                   0xd
1393 #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT                                                               0x10
1394 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT                                                       0x15
1395 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT                                                        0x16
1396 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT                                                        0x19
1397 #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT                                                          0x1c
1398 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT                                                   0x1d
1399 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK                                                       0x00000003L
1400 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK                                                       0x00000010L
1401 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK                                                       0x00000020L
1402 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK                                                            0x000000C0L
1403 #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK                                                              0x00000200L
1404 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK                                                     0x00000800L
1405 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK                                                         0x00001000L
1406 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK                                                     0x00002000L
1407 #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK                                                                 0x001F0000L
1408 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK                                                         0x00200000L
1409 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK                                                          0x01C00000L
1410 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK                                                          0x0E000000L
1411 #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK                                                            0x10000000L
1412 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK                                                     0x20000000L
1413 //VGT_RESET_DEBUG
1414 #define VGT_RESET_DEBUG__GS_DISABLE__SHIFT                                                                    0x0
1415 #define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT                                                                  0x1
1416 #define VGT_RESET_DEBUG__WD_DISABLE__SHIFT                                                                    0x2
1417 #define VGT_RESET_DEBUG__GS_DISABLE_MASK                                                                      0x00000001L
1418 #define VGT_RESET_DEBUG__TESS_DISABLE_MASK                                                                    0x00000002L
1419 #define VGT_RESET_DEBUG__WD_DISABLE_MASK                                                                      0x00000004L
1420 //VGT_STRMOUT_DELAY
1421 #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT                                                                  0x0
1422 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT                                                                0x8
1423 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT                                                                0xb
1424 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT                                                                0xe
1425 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT                                                                0x11
1426 #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK                                                                    0x000000FFL
1427 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK                                                                  0x00000700L
1428 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK                                                                  0x00003800L
1429 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK                                                                  0x0001C000L
1430 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK                                                                  0x000E0000L
1431 //VGT_FIFO_DEPTHS
1432 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT                                                          0x0
1433 #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT                                                                    0x7
1434 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT                                                              0x8
1435 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT                                                            0x16
1436 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK                                                            0x0000007FL
1437 #define VGT_FIFO_DEPTHS__RESERVED_0_MASK                                                                      0x00000080L
1438 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK                                                                0x003FFF00L
1439 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK                                                              0x0FC00000L
1440 //VGT_GS_VERTEX_REUSE
1441 #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT                                                                0x0
1442 #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK                                                                  0x0000001FL
1443 //VGT_MC_LAT_CNTL
1444 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT                                                             0x0
1445 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK                                                               0x0000000FL
1446 //IA_CNTL_STATUS
1447 #define IA_CNTL_STATUS__IA_BUSY__SHIFT                                                                        0x0
1448 #define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT                                                                    0x1
1449 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT                                                                0x2
1450 #define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT                                                                    0x3
1451 #define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT                                                                    0x4
1452 #define IA_CNTL_STATUS__IA_BUSY_MASK                                                                          0x00000001L
1453 #define IA_CNTL_STATUS__IA_DMA_BUSY_MASK                                                                      0x00000002L
1454 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK                                                                  0x00000004L
1455 #define IA_CNTL_STATUS__IA_GRP_BUSY_MASK                                                                      0x00000008L
1456 #define IA_CNTL_STATUS__IA_ADC_BUSY_MASK                                                                      0x00000010L
1457 //VGT_CNTL_STATUS
1458 #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                                                                      0x0
1459 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT                                                             0x1
1460 #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT                                                                  0x2
1461 #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                                                                   0x3
1462 #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT                                                                   0x4
1463 #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                                                                   0x5
1464 #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT                                                                   0x6
1465 #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT                                                                   0x7
1466 #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT                                                                   0x8
1467 #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT                                                                 0x9
1468 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT                                                              0xa
1469 #define VGT_CNTL_STATUS__VGT_BUSY_MASK                                                                        0x00000001L
1470 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK                                                               0x00000002L
1471 #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                                                                    0x00000004L
1472 #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                                                                     0x00000008L
1473 #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK                                                                     0x00000010L
1474 #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                                                                     0x00000020L
1475 #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK                                                                     0x00000040L
1476 #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK                                                                     0x00000080L
1477 #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK                                                                     0x00000100L
1478 #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK                                                                   0x00000200L
1479 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK                                                                0x00000400L
1480 //WD_CNTL_STATUS
1481 #define WD_CNTL_STATUS__WD_BUSY__SHIFT                                                                        0x0
1482 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT                                                                0x1
1483 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT                                                                 0x2
1484 #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT                                                                    0x3
1485 #define WD_CNTL_STATUS__WD_BUSY_MASK                                                                          0x00000001L
1486 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK                                                                  0x00000002L
1487 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK                                                                   0x00000004L
1488 #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK                                                                      0x00000008L
1489 //CC_GC_PRIM_CONFIG
1490 #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT                                                                 0x10
1491 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT                                                             0x18
1492 #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK                                                                   0x00030000L
1493 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK                                                               0x0F000000L
1494 //GC_USER_PRIM_CONFIG
1495 #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT                                                               0x10
1496 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT                                                           0x18
1497 #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK                                                                 0x00030000L
1498 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK                                                             0x0F000000L
1499 //WD_QOS
1500 #define WD_QOS__DRAW_STALL__SHIFT                                                                             0x0
1501 #define WD_QOS__DRAW_STALL_MASK                                                                               0x00000001L
1502 //WD_UTCL1_CNTL
1503 #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
1504 #define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
1505 #define WD_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
1506 #define WD_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
1507 #define WD_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
1508 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
1509 #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
1510 #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                             0x1d
1511 #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
1512 #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
1513 #define WD_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
1514 #define WD_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
1515 #define WD_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
1516 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
1517 #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
1518 #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                               0x20000000L
1519 //WD_UTCL1_STATUS
1520 #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
1521 #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
1522 #define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
1523 #define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
1524 #define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
1525 #define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
1526 #define WD_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
1527 #define WD_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
1528 #define WD_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
1529 #define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
1530 #define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
1531 #define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
1532 //IA_UTCL1_CNTL
1533 #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
1534 #define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
1535 #define IA_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
1536 #define IA_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
1537 #define IA_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
1538 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
1539 #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
1540 #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                             0x1d
1541 #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
1542 #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
1543 #define IA_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
1544 #define IA_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
1545 #define IA_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
1546 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
1547 #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
1548 #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                               0x20000000L
1549 //IA_UTCL1_STATUS
1550 #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
1551 #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
1552 #define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
1553 #define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
1554 #define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
1555 #define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
1556 #define IA_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
1557 #define IA_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
1558 #define IA_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
1559 #define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
1560 #define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
1561 #define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
1562 //VGT_SYS_CONFIG
1563 #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT                                                                   0x0
1564 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT                                                               0x1
1565 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT                                                       0x7
1566 #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK                                                                     0x00000001L
1567 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK                                                                 0x0000007EL
1568 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK                                                         0x00000080L
1569 //VGT_VS_MAX_WAVE_ID
1570 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
1571 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
1572 //VGT_GS_MAX_WAVE_ID
1573 #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
1574 #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
1575 //GFX_PIPE_CONTROL
1576 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT                                                               0x0
1577 #define GFX_PIPE_CONTROL__RESERVED__SHIFT                                                                     0xd
1578 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT                                                           0x10
1579 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK                                                                 0x00001FFFL
1580 #define GFX_PIPE_CONTROL__RESERVED_MASK                                                                       0x0000E000L
1581 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK                                                             0x00010000L
1582 //CC_GC_SHADER_ARRAY_CONFIG
1583 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT                                                        0x10
1584 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK                                                          0xFFFF0000L
1585 //GC_USER_SHADER_ARRAY_CONFIG
1586 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT                                                      0x10
1587 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK                                                        0xFFFF0000L
1588 //VGT_DMA_PRIMITIVE_TYPE
1589 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                              0x0
1590 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                0x0000003FL
1591 //VGT_DMA_CONTROL
1592 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT                                                                0x0
1593 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT                                                              0x11
1594 #define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT                                                                 0x13
1595 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT                                                              0x14
1596 #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT                                                             0x15
1597 #define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT                                                               0x16
1598 #define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT                                                                   0x17
1599 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK                                                                  0x0000FFFFL
1600 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK                                                                0x00020000L
1601 #define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK                                                                   0x00080000L
1602 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK                                                                0x00100000L
1603 #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK                                                               0x00200000L
1604 #define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK                                                                 0x00400000L
1605 #define VGT_DMA_CONTROL__HW_USE_ONLY_MASK                                                                     0x00800000L
1606 //VGT_DMA_LS_HS_CONFIG
1607 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                          0x8
1608 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                            0x00003F00L
1609 //WD_BUF_RESOURCE_1
1610 #define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT                                                                0x0
1611 #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT                                                              0x10
1612 #define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK                                                                  0x0000FFFFL
1613 #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK                                                                0xFFFF0000L
1614 //WD_BUF_RESOURCE_2
1615 #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT                                                              0x0
1616 #define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT                                                                   0xf
1617 #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT                                                            0x10
1618 #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK                                                                0x00001FFFL
1619 #define WD_BUF_RESOURCE_2__ADDR_MODE_MASK                                                                     0x00008000L
1620 #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK                                                              0xFFFF0000L
1621 //PA_CL_CNTL_STATUS
1622 #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT                                                          0x0
1623 #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT                                                          0x1
1624 #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT                                                            0x2
1625 #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK                                                            0x00000001L
1626 #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK                                                            0x00000002L
1627 #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK                                                              0x00000004L
1628 //PA_CL_ENHANCE
1629 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT                                                            0x0
1630 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT                                                                    0x1
1631 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT                                                          0x3
1632 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT                                                             0x4
1633 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT                                                              0x5
1634 #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT                                                           0x6
1635 #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT                                                           0x7
1636 #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT                                                                0x8
1637 #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT                                                0x9
1638 #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT                                                          0xb
1639 #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT                                                       0xc
1640 #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT                                                     0xe
1641 #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                                                                      0x1c
1642 #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                                                                      0x1d
1643 #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                                                                      0x1e
1644 #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                                                                      0x1f
1645 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK                                                              0x00000001L
1646 #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK                                                                      0x00000006L
1647 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK                                                            0x00000008L
1648 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK                                                               0x00000010L
1649 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK                                                                0x00000020L
1650 #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK                                                             0x00000040L
1651 #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK                                                             0x00000080L
1652 #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK                                                                  0x00000100L
1653 #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK                                                  0x00000600L
1654 #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK                                                            0x00000800L
1655 #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK                                                         0x00003000L
1656 #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK                                                       0x0001C000L
1657 #define PA_CL_ENHANCE__ECO_SPARE3_MASK                                                                        0x10000000L
1658 #define PA_CL_ENHANCE__ECO_SPARE2_MASK                                                                        0x20000000L
1659 #define PA_CL_ENHANCE__ECO_SPARE1_MASK                                                                        0x40000000L
1660 #define PA_CL_ENHANCE__ECO_SPARE0_MASK                                                                        0x80000000L
1661 //PA_CL_RESET_DEBUG
1662 #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT                                                        0x0
1663 #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK                                                          0x00000001L
1664 //PA_SU_CNTL_STATUS
1665 #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                                                                     0x1f
1666 #define PA_SU_CNTL_STATUS__SU_BUSY_MASK                                                                       0x80000000L
1667 //PA_SC_FIFO_DEPTH_CNTL
1668 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT                                                                   0x0
1669 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK                                                                     0x000003FFL
1670 //PA_SC_P3D_TRAP_SCREEN_HV_LOCK
1671 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                         0x0
1672 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                           0x00000001L
1673 //PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
1674 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                        0x0
1675 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                          0x00000001L
1676 //PA_SC_TRAP_SCREEN_HV_LOCK
1677 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                             0x0
1678 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                               0x00000001L
1679 //PA_SC_FORCE_EOV_MAX_CNTS
1680 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT                                                0x0
1681 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT                                                0x10
1682 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK                                                  0x0000FFFFL
1683 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK                                                  0xFFFF0000L
1684 //PA_SC_BINNER_EVENT_CNTL_0
1685 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT                                                          0x0
1686 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT                                              0x2
1687 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT                                              0x4
1688 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT                                              0x6
1689 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT                                                      0x8
1690 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT                                                        0xa
1691 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT                                                         0xc
1692 #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT                                                    0xe
1693 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT                                                  0x10
1694 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT                                                          0x12
1695 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT                                                 0x14
1696 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT                                                 0x16
1697 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT                                                  0x18
1698 #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT                                                         0x1a
1699 #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT                                                         0x1c
1700 #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT                                                    0x1e
1701 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK                                                            0x00000003L
1702 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK                                                0x0000000CL
1703 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK                                                0x00000030L
1704 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK                                                0x000000C0L
1705 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK                                                        0x00000300L
1706 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK                                                          0x00000C00L
1707 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK                                                           0x00003000L
1708 #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK                                                      0x0000C000L
1709 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK                                                    0x00030000L
1710 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK                                                            0x000C0000L
1711 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK                                                   0x00300000L
1712 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK                                                   0x00C00000L
1713 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK                                                    0x03000000L
1714 #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK                                                           0x0C000000L
1715 #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK                                                           0x30000000L
1716 #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK                                                      0xC0000000L
1717 //PA_SC_BINNER_EVENT_CNTL_1
1718 #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT                                                    0x0
1719 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT                                                     0x2
1720 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT                                                          0x4
1721 #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT                                                 0x6
1722 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT                                        0x8
1723 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT                                                          0xa
1724 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT                                           0xc
1725 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT                                                   0xe
1726 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT                                                    0x10
1727 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT                                                  0x12
1728 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT                                                   0x14
1729 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT                                                  0x16
1730 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT                                                     0x18
1731 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT                                                     0x1a
1732 #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT                                                 0x1c
1733 #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT                                               0x1e
1734 #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK                                                      0x00000003L
1735 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK                                                       0x0000000CL
1736 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK                                                            0x00000030L
1737 #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK                                                   0x000000C0L
1738 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK                                          0x00000300L
1739 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK                                                            0x00000C00L
1740 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK                                             0x00003000L
1741 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK                                                     0x0000C000L
1742 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK                                                      0x00030000L
1743 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK                                                    0x000C0000L
1744 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK                                                     0x00300000L
1745 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK                                                    0x00C00000L
1746 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK                                                       0x03000000L
1747 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK                                                       0x0C000000L
1748 #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK                                                   0x30000000L
1749 #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK                                                 0xC0000000L
1750 //PA_SC_BINNER_EVENT_CNTL_2
1751 #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT                                               0x0
1752 #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT                                                       0x2
1753 #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT                                                  0x4
1754 #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT                                                     0x6
1755 #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT                                                           0x8
1756 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT                                                       0xa
1757 #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT                                                        0xc
1758 #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT                                                      0xe
1759 #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT                                                   0x10
1760 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT                                                         0x12
1761 #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT                                              0x14
1762 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT                                            0x16
1763 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT                                               0x18
1764 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT                                            0x1a
1765 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT                                               0x1c
1766 #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT                                                             0x1e
1767 #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK                                                 0x00000003L
1768 #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK                                                         0x0000000CL
1769 #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK                                                    0x00000030L
1770 #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK                                                       0x000000C0L
1771 #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK                                                             0x00000300L
1772 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK                                                         0x00000C00L
1773 #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK                                                          0x00003000L
1774 #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK                                                        0x0000C000L
1775 #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK                                                     0x00030000L
1776 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK                                                           0x000C0000L
1777 #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK                                                0x00300000L
1778 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK                                              0x00C00000L
1779 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK                                                 0x03000000L
1780 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK                                              0x0C000000L
1781 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK                                                 0x30000000L
1782 #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK                                                               0xC0000000L
1783 //PA_SC_BINNER_EVENT_CNTL_3
1784 #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT                                                             0x0
1785 #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT                                         0x2
1786 #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT                                               0x4
1787 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT                                                  0x6
1788 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT                                                   0x8
1789 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT                                                 0xa
1790 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT                                                  0xc
1791 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT                                                 0xe
1792 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT                                             0x10
1793 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT                                                0x12
1794 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT                                               0x14
1795 #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT                                                     0x16
1796 #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT                                                  0x18
1797 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT                                                 0x1a
1798 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT                                              0x1c
1799 #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT                                                         0x1e
1800 #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK                                                               0x00000003L
1801 #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK                                           0x0000000CL
1802 #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK                                                 0x00000030L
1803 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK                                                    0x000000C0L
1804 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK                                                     0x00000300L
1805 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK                                                   0x00000C00L
1806 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK                                                    0x00003000L
1807 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK                                                   0x0000C000L
1808 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK                                               0x00030000L
1809 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK                                                  0x000C0000L
1810 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK                                                 0x00300000L
1811 #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK                                                       0x00C00000L
1812 #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK                                                    0x03000000L
1813 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK                                                   0x0C000000L
1814 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK                                                0x30000000L
1815 #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK                                                           0xC0000000L
1816 //PA_SC_BINNER_TIMEOUT_COUNTER
1817 #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT                                                        0x0
1818 #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK                                                          0xFFFFFFFFL
1819 //PA_SC_BINNER_PERF_CNTL_0
1820 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                         0x0
1821 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                       0xa
1822 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                       0x14
1823 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                     0x17
1824 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK                                           0x000003FFL
1825 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK                                         0x000FFC00L
1826 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK                                         0x00700000L
1827 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK                                       0x03800000L
1828 //PA_SC_BINNER_PERF_CNTL_1
1829 #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                              0x0
1830 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                            0x5
1831 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT                         0xa
1832 #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                                0x0000001FL
1833 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                              0x000003E0L
1834 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK                           0x03FFFC00L
1835 //PA_SC_BINNER_PERF_CNTL_2
1836 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT                               0x0
1837 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT                             0xb
1838 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK                                 0x000007FFL
1839 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK                               0x003FF800L
1840 //PA_SC_BINNER_PERF_CNTL_3
1841 #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT                              0x0
1842 #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK                                0xFFFFFFFFL
1843 //PA_SC_FIFO_SIZE
1844 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT                                                    0x0
1845 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT                                                     0x6
1846 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT                                                         0xf
1847 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT                                                      0x15
1848 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK                                                      0x0000003FL
1849 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK                                                       0x00007FC0L
1850 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK                                                           0x001F8000L
1851 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK                                                        0xFFE00000L
1852 //PA_SC_IF_FIFO_SIZE
1853 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT                                                    0x0
1854 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT                                                    0x6
1855 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT                                                        0xc
1856 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT                                                        0x12
1857 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK                                                      0x0000003FL
1858 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK                                                      0x00000FC0L
1859 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK                                                          0x0003F000L
1860 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK                                                          0x00FC0000L
1861 //PA_SC_PKR_WAVE_TABLE_CNTL
1862 #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT                                                                0x0
1863 #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK                                                                  0x0000003FL
1864 //PA_UTCL1_CNTL1
1865 #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                               0x0
1866 #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT                                                              0x1
1867 #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                                0x2
1868 #define PA_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                      0x3
1869 #define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                                0x5
1870 #define PA_UTCL1_CNTL1__CLIENTID__SHIFT                                                                       0x7
1871 #define PA_UTCL1_CNTL1__SPARE__SHIFT                                                                          0x10
1872 #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                              0x11
1873 #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                           0x12
1874 #define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                   0x13
1875 #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                               0x17
1876 #define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                 0x18
1877 #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT                                                            0x19
1878 #define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                     0x1a
1879 #define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                 0x1b
1880 #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                         0x1c
1881 #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                         0x1e
1882 #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                 0x00000001L
1883 #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK                                                                0x00000002L
1884 #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                  0x00000004L
1885 #define PA_UTCL1_CNTL1__RESP_MODE_MASK                                                                        0x00000018L
1886 #define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                  0x00000060L
1887 #define PA_UTCL1_CNTL1__CLIENTID_MASK                                                                         0x0000FF80L
1888 #define PA_UTCL1_CNTL1__SPARE_MASK                                                                            0x00010000L
1889 #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                                0x00020000L
1890 #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                             0x00040000L
1891 #define PA_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                     0x00780000L
1892 #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                 0x00800000L
1893 #define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                   0x01000000L
1894 #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK                                                              0x02000000L
1895 #define PA_UTCL1_CNTL1__FORCE_MISS_MASK                                                                       0x04000000L
1896 #define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                   0x08000000L
1897 #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                           0x30000000L
1898 #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                           0xC0000000L
1899 //PA_UTCL1_CNTL2
1900 #define PA_UTCL1_CNTL2__SPARE1__SHIFT                                                                         0x0
1901 #define PA_UTCL1_CNTL2__SPARE2__SHIFT                                                                         0x8
1902 #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                 0x9
1903 #define PA_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                     0xa
1904 #define PA_UTCL1_CNTL2__SPARE3__SHIFT                                                                         0xb
1905 #define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                 0xc
1906 #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT                                                           0xd
1907 #define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                    0xe
1908 #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                            0xf
1909 #define PA_UTCL1_CNTL2__SPARE4__SHIFT                                                                         0x10
1910 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                        0x12
1911 #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                               0x13
1912 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                         0x14
1913 #define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT                                                                0x15
1914 #define PA_UTCL1_CNTL2__SPARE5__SHIFT                                                                         0x19
1915 #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                           0x1a
1916 #define PA_UTCL1_CNTL2__RESERVED__SHIFT                                                                       0x1b
1917 #define PA_UTCL1_CNTL2__SPARE1_MASK                                                                           0x000000FFL
1918 #define PA_UTCL1_CNTL2__SPARE2_MASK                                                                           0x00000100L
1919 #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                   0x00000200L
1920 #define PA_UTCL1_CNTL2__LINE_VALID_MASK                                                                       0x00000400L
1921 #define PA_UTCL1_CNTL2__SPARE3_MASK                                                                           0x00000800L
1922 #define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                   0x00001000L
1923 #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK                                                             0x00002000L
1924 #define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                      0x00004000L
1925 #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                              0x00008000L
1926 #define PA_UTCL1_CNTL2__SPARE4_MASK                                                                           0x00030000L
1927 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                          0x00040000L
1928 #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK                                                                 0x00080000L
1929 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                           0x00100000L
1930 #define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK                                                                  0x01E00000L
1931 #define PA_UTCL1_CNTL2__SPARE5_MASK                                                                           0x02000000L
1932 #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                             0x04000000L
1933 #define PA_UTCL1_CNTL2__RESERVED_MASK                                                                         0xF8000000L
1934 //PA_SIDEBAND_REQUEST_DELAYS
1935 #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT                                                        0x0
1936 #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT                                                      0x10
1937 #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK                                                          0x0000FFFFL
1938 #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK                                                        0xFFFF0000L
1939 //PA_SC_ENHANCE
1940 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT                                                       0x0
1941 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT                                                          0x1
1942 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT                                                        0x2
1943 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT                                                  0x3
1944 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT                                               0x4
1945 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT                                                             0x5
1946 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT                                                     0x6
1947 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT                                              0x7
1948 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT                                                   0x8
1949 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT                                              0x9
1950 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT                                                   0xa
1951 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT                                                          0xb
1952 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT                                          0xc
1953 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT                                                 0xd
1954 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT                                             0xe
1955 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT                                                   0xf
1956 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT                                   0x10
1957 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT                                        0x11
1958 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT                               0x12
1959 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT                               0x13
1960 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT                              0x14
1961 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT                                 0x15
1962 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT                                   0x16
1963 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT                           0x17
1964 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT                                          0x18
1965 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT                                       0x19
1966 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT                                                  0x1a
1967 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT                                              0x1b
1968 #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT                      0x1c
1969 #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT                              0x1d
1970 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK                                                         0x00000001L
1971 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK                                                            0x00000002L
1972 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK                                                          0x00000004L
1973 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK                                                    0x00000008L
1974 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK                                                 0x00000010L
1975 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK                                                               0x00000020L
1976 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK                                                       0x00000040L
1977 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK                                                0x00000080L
1978 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK                                                     0x00000100L
1979 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK                                                0x00000200L
1980 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK                                                     0x00000400L
1981 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK                                                            0x00000800L
1982 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK                                            0x00001000L
1983 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK                                                   0x00002000L
1984 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK                                               0x00004000L
1985 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK                                                     0x00008000L
1986 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK                                     0x00010000L
1987 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK                                          0x00020000L
1988 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK                                 0x00040000L
1989 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK                                 0x00080000L
1990 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK                                0x00100000L
1991 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK                                   0x00200000L
1992 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK                                     0x00400000L
1993 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK                             0x00800000L
1994 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK                                            0x01000000L
1995 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK                                         0x02000000L
1996 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK                                                    0x04000000L
1997 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK                                                0x08000000L
1998 #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK                        0x10000000L
1999 #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK                                0x20000000L
2000 //PA_SC_ENHANCE_1
2001 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT                                                0x0
2002 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT                                                       0x1
2003 #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT                                                            0x3
2004 #define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT                                                                    0x4
2005 #define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT                                                                    0x5
2006 #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT                                                                    0x6
2007 #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT                                                                    0x7
2008 #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT                                                                    0x8
2009 #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT                                                  0x9
2010 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT                                                       0xa
2011 #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT                                     0xb
2012 #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT                                                  0xc
2013 #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT                                              0xd
2014 #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT                                       0xe
2015 #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT                              0xf
2016 #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT                                                    0x10
2017 #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT                                       0x11
2018 #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT                                                         0x12
2019 #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT                                                  0x13
2020 #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT                                                  0x14
2021 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT                                          0x15
2022 #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT                                          0x16
2023 #define PA_SC_ENHANCE_1__RSVD__SHIFT                                                                          0x17
2024 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK                                                  0x00000001L
2025 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK                                                         0x00000006L
2026 #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK                                                              0x00000008L
2027 #define PA_SC_ENHANCE_1__BYPASS_PBB_MASK                                                                      0x00000010L
2028 #define PA_SC_ENHANCE_1__ECO_SPARE0_MASK                                                                      0x00000020L
2029 #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK                                                                      0x00000040L
2030 #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK                                                                      0x00000080L
2031 #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK                                                                      0x00000100L
2032 #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK                                                    0x00000200L
2033 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK                                                         0x00000400L
2034 #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK                                       0x00000800L
2035 #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK                                                    0x00001000L
2036 #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK                                                0x00002000L
2037 #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK                                         0x00004000L
2038 #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK                                0x00008000L
2039 #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK                                                      0x00010000L
2040 #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK                                         0x00020000L
2041 #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK                                                           0x00040000L
2042 #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK                                                    0x00080000L
2043 #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK                                                    0x00100000L
2044 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK                                            0x00200000L
2045 #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK                                            0x00400000L
2046 #define PA_SC_ENHANCE_1__RSVD_MASK                                                                            0xFF800000L
2047 //PA_SC_DSM_CNTL
2048 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT                                                                0x0
2049 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT                                                                0x1
2050 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK                                                                  0x00000001L
2051 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK                                                                  0x00000002L
2052 //PA_SC_TILE_STEERING_CREST_OVERRIDE
2053 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT                                         0x0
2054 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT                                                  0x1
2055 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT                                                  0x5
2056 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK                                           0x00000001L
2057 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK                                                    0x00000006L
2058 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK                                                    0x00000060L
2059 
2060 
2061 // addressBlock: gc_sqdec
2062 //SQ_CONFIG
2063 #define SQ_CONFIG__UNUSED__SHIFT                                                                              0x0
2064 #define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT                                                                   0x7
2065 #define SQ_CONFIG__DEBUG_EN__SHIFT                                                                            0x8
2066 #define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT                                                                  0x9
2067 #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT                                                               0xa
2068 #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT                                                               0xb
2069 #define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT                                                               0xc
2070 #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT                                                                0xd
2071 #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT                                                              0xe
2072 #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT                                                       0xf
2073 #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT                                                            0x10
2074 #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT                                                            0x11
2075 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT                                                         0x12
2076 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT                                                              0x13
2077 #define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT                                                                    0x15
2078 #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT                                                          0x1c
2079 #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT                                                  0x1d
2080 #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT                                                            0x1e
2081 #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT                                                            0x1f
2082 #define SQ_CONFIG__UNUSED_MASK                                                                                0x0000007FL
2083 #define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK                                                                     0x00000080L
2084 #define SQ_CONFIG__DEBUG_EN_MASK                                                                              0x00000100L
2085 #define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK                                                                    0x00000200L
2086 #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK                                                                 0x00000400L
2087 #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK                                                                 0x00000800L
2088 #define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK                                                                 0x00001000L
2089 #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK                                                                  0x00002000L
2090 #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK                                                                0x00004000L
2091 #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK                                                         0x00008000L
2092 #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK                                                              0x00010000L
2093 #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK                                                              0x00020000L
2094 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK                                                           0x00040000L
2095 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK                                                                0x00180000L
2096 #define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK                                                                      0x0FE00000L
2097 #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK                                                            0x10000000L
2098 #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK                                                    0x20000000L
2099 #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK                                                              0x40000000L
2100 #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK                                                              0x80000000L
2101 //SQC_CONFIG
2102 #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT                                                                    0x0
2103 #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT                                                                    0x2
2104 #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT                                                                    0x4
2105 #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT                                                                     0x6
2106 #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT                                                                  0x7
2107 #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT                                                                     0x8
2108 #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT                                                                 0x9
2109 #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT                                                                  0xa
2110 #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT                                                               0xb
2111 #define SQC_CONFIG__EVICT_LRU__SHIFT                                                                          0xc
2112 #define SQC_CONFIG__FORCE_2_BANK__SHIFT                                                                       0xe
2113 #define SQC_CONFIG__FORCE_1_BANK__SHIFT                                                                       0xf
2114 #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT                                                                  0x10
2115 #define SQC_CONFIG__INST_PRF_COUNT__SHIFT                                                                     0x18
2116 #define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT                                                                0x1a
2117 #define SQC_CONFIG__INST_CACHE_SIZE_MASK                                                                      0x00000003L
2118 #define SQC_CONFIG__DATA_CACHE_SIZE_MASK                                                                      0x0000000CL
2119 #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK                                                                      0x00000030L
2120 #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK                                                                       0x00000040L
2121 #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK                                                                    0x00000080L
2122 #define SQC_CONFIG__FORCE_IN_ORDER_MASK                                                                       0x00000100L
2123 #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK                                                                   0x00000200L
2124 #define SQC_CONFIG__IDENTITY_HASH_SET_MASK                                                                    0x00000400L
2125 #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK                                                                 0x00000800L
2126 #define SQC_CONFIG__EVICT_LRU_MASK                                                                            0x00003000L
2127 #define SQC_CONFIG__FORCE_2_BANK_MASK                                                                         0x00004000L
2128 #define SQC_CONFIG__FORCE_1_BANK_MASK                                                                         0x00008000L
2129 #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK                                                                    0x00FF0000L
2130 #define SQC_CONFIG__INST_PRF_COUNT_MASK                                                                       0x03000000L
2131 #define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK                                                                  0x04000000L
2132 //LDS_CONFIG
2133 #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT                                                        0x0
2134 #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK                                                          0x00000001L
2135 //SQ_RANDOM_WAVE_PRI
2136 #define SQ_RANDOM_WAVE_PRI__RET__SHIFT                                                                        0x0
2137 #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT                                                                        0x7
2138 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT                                                                        0xa
2139 #define SQ_RANDOM_WAVE_PRI__RET_MASK                                                                          0x0000007FL
2140 #define SQ_RANDOM_WAVE_PRI__RUI_MASK                                                                          0x00000380L
2141 #define SQ_RANDOM_WAVE_PRI__RNG_MASK                                                                          0x007FFC00L
2142 //SQ_REG_CREDITS
2143 #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT                                                                   0x0
2144 #define SQ_REG_CREDITS__CMD_CREDITS__SHIFT                                                                    0x8
2145 #define SQ_REG_CREDITS__REG_BUSY__SHIFT                                                                       0x1c
2146 #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT                                                                  0x1d
2147 #define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT                                                                 0x1e
2148 #define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT                                                                   0x1f
2149 #define SQ_REG_CREDITS__SRBM_CREDITS_MASK                                                                     0x0000003FL
2150 #define SQ_REG_CREDITS__CMD_CREDITS_MASK                                                                      0x00000F00L
2151 #define SQ_REG_CREDITS__REG_BUSY_MASK                                                                         0x10000000L
2152 #define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK                                                                    0x20000000L
2153 #define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK                                                                   0x40000000L
2154 #define SQ_REG_CREDITS__CMD_OVERFLOW_MASK                                                                     0x80000000L
2155 //SQ_FIFO_SIZES
2156 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT                                                             0x0
2157 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT                                                                0x8
2158 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT                                                                 0x10
2159 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT                                                             0x12
2160 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK                                                               0x0000000FL
2161 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK                                                                  0x00000F00L
2162 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK                                                                   0x00030000L
2163 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK                                                               0x000C0000L
2164 //SQ_DSM_CNTL
2165 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT                                                                 0x0
2166 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT                                                                 0x1
2167 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT                                                                0x2
2168 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT                                                                0x3
2169 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT                                                      0x8
2170 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT                                                      0x9
2171 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT                                                          0xa
2172 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT                                                       0x10
2173 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT                                                       0x11
2174 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT                                                         0x12
2175 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT                                                       0x13
2176 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT                                                       0x14
2177 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT                                                         0x15
2178 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT                                                        0x18
2179 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT                                                        0x19
2180 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT                                                            0x1a
2181 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK                                                                   0x00000001L
2182 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK                                                                   0x00000002L
2183 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK                                                                  0x00000004L
2184 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK                                                                  0x00000008L
2185 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK                                                        0x00000100L
2186 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK                                                        0x00000200L
2187 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK                                                            0x00000400L
2188 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK                                                         0x00010000L
2189 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK                                                         0x00020000L
2190 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK                                                           0x00040000L
2191 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK                                                         0x00080000L
2192 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK                                                         0x00100000L
2193 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK                                                           0x00200000L
2194 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK                                                          0x01000000L
2195 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK                                                          0x02000000L
2196 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK                                                              0x04000000L
2197 //SQ_DSM_CNTL2
2198 #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT                                                         0x0
2199 #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT                                                         0x2
2200 #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT                                                        0x3
2201 #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT                                                        0x5
2202 #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT                                                        0x6
2203 #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT                                                        0x8
2204 #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT                                                           0x9
2205 #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT                                                           0xb
2206 #define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT                                                                 0xe
2207 #define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT                                                                  0x14
2208 #define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT                                                                  0x1a
2209 #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK                                                           0x00000003L
2210 #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK                                                           0x00000004L
2211 #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK                                                          0x00000018L
2212 #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK                                                          0x00000020L
2213 #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK                                                          0x000000C0L
2214 #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK                                                          0x00000100L
2215 #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK                                                             0x00000600L
2216 #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK                                                             0x00000800L
2217 #define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK                                                                   0x000FC000L
2218 #define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK                                                                    0x03F00000L
2219 #define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK                                                                    0xFC000000L
2220 //SQ_RUNTIME_CONFIG
2221 #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT                                                       0x0
2222 #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK                                                         0x00000001L
2223 //SH_MEM_BASES
2224 #define SH_MEM_BASES__PRIVATE_BASE__SHIFT                                                                     0x0
2225 #define SH_MEM_BASES__SHARED_BASE__SHIFT                                                                      0x10
2226 #define SH_MEM_BASES__PRIVATE_BASE_MASK                                                                       0x0000FFFFL
2227 #define SH_MEM_BASES__SHARED_BASE_MASK                                                                        0xFFFF0000L
2228 //SH_MEM_CONFIG
2229 #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT                                                                    0x0
2230 #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT                                                                  0x3
2231 #define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT                                                                   0xc
2232 #define SH_MEM_CONFIG__PRIVATE_NV__SHIFT                                                                      0xd
2233 #define SH_MEM_CONFIG__ADDRESS_MODE_MASK                                                                      0x00000001L
2234 #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK                                                                    0x00000018L
2235 #define SH_MEM_CONFIG__RETRY_DISABLE_MASK                                                                     0x00001000L
2236 #define SH_MEM_CONFIG__PRIVATE_NV_MASK                                                                        0x00002000L
2237 //CC_GC_SHADER_RATE_CONFIG
2238 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                            0x1
2239 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                  0x3
2240 #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT                                                             0x4
2241 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                              0x00000006L
2242 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                    0x00000008L
2243 #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK                                                               0x00000010L
2244 //GC_USER_SHADER_RATE_CONFIG
2245 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                          0x1
2246 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                0x3
2247 #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT                                                           0x4
2248 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                            0x00000006L
2249 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                  0x00000008L
2250 #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK                                                             0x00000010L
2251 //SQ_INTERRUPT_AUTO_MASK
2252 #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT                                                                   0x0
2253 #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK                                                                     0x00FFFFFFL
2254 //SQ_INTERRUPT_MSG_CTRL
2255 #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT                                                                   0x0
2256 #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK                                                                     0x00000001L
2257 //SQ_UTCL1_CNTL1
2258 #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                               0x0
2259 #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                                  0x1
2260 #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                                0x2
2261 #define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                      0x3
2262 #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                                0x5
2263 #define SQ_UTCL1_CNTL1__CLIENTID__SHIFT                                                                       0x7
2264 #define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT                                                                     0x10
2265 #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                              0x11
2266 #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                           0x12
2267 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT                                                            0x13
2268 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT                                                        0x17
2269 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT                                                          0x18
2270 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT                                                             0x19
2271 #define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                     0x1a
2272 #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                 0x1b
2273 #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                         0x1c
2274 #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                         0x1e
2275 #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                 0x00000001L
2276 #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                                    0x00000002L
2277 #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                  0x00000004L
2278 #define SQ_UTCL1_CNTL1__RESP_MODE_MASK                                                                        0x00000018L
2279 #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                  0x00000060L
2280 #define SQ_UTCL1_CNTL1__CLIENTID_MASK                                                                         0x0000FF80L
2281 #define SQ_UTCL1_CNTL1__USERVM_DIS_MASK                                                                       0x00010000L
2282 #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                                0x00020000L
2283 #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                             0x00040000L
2284 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK                                                              0x00780000L
2285 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK                                                          0x00800000L
2286 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK                                                            0x01000000L
2287 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK                                                               0x02000000L
2288 #define SQ_UTCL1_CNTL1__FORCE_MISS_MASK                                                                       0x04000000L
2289 #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                   0x08000000L
2290 #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                           0x30000000L
2291 #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                           0xC0000000L
2292 //SQ_UTCL1_CNTL2
2293 #define SQ_UTCL1_CNTL2__SPARE__SHIFT                                                                          0x0
2294 #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                             0x8
2295 #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                 0x9
2296 #define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                     0xa
2297 #define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                        0xb
2298 #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                 0xc
2299 #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                  0xd
2300 #define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                    0xe
2301 #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                            0xf
2302 #define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT                                                                    0x10
2303 #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                           0x1a
2304 #define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT                                                                  0x1c
2305 #define SQ_UTCL1_CNTL2__SPARE_MASK                                                                            0x000000FFL
2306 #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                               0x00000100L
2307 #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                   0x00000200L
2308 #define SQ_UTCL1_CNTL2__LINE_VALID_MASK                                                                       0x00000400L
2309 #define SQ_UTCL1_CNTL2__DIS_EDC_MASK                                                                          0x00000800L
2310 #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                   0x00001000L
2311 #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                                    0x00002000L
2312 #define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                      0x00004000L
2313 #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                              0x00008000L
2314 #define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK                                                                      0x007F0000L
2315 #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                             0x04000000L
2316 #define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK                                                                    0xF0000000L
2317 //SQ_UTCL1_STATUS
2318 #define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
2319 #define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
2320 #define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
2321 #define SQ_UTCL1_STATUS__RESERVED__SHIFT                                                                      0x3
2322 #define SQ_UTCL1_STATUS__UNUSED__SHIFT                                                                        0x10
2323 #define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
2324 #define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
2325 #define SQ_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
2326 #define SQ_UTCL1_STATUS__RESERVED_MASK                                                                        0x0000FFF8L
2327 #define SQ_UTCL1_STATUS__UNUSED_MASK                                                                          0xFFFF0000L
2328 //SQ_SHADER_TBA_LO
2329 #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT                                                                      0x0
2330 #define SQ_SHADER_TBA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
2331 //SQ_SHADER_TBA_HI
2332 #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT                                                                      0x0
2333 #define SQ_SHADER_TBA_HI__ADDR_HI_MASK                                                                        0x000000FFL
2334 //SQ_SHADER_TMA_LO
2335 #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT                                                                      0x0
2336 #define SQ_SHADER_TMA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
2337 //SQ_SHADER_TMA_HI
2338 #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT                                                                      0x0
2339 #define SQ_SHADER_TMA_HI__ADDR_HI_MASK                                                                        0x000000FFL
2340 //SQC_DSM_CNTL
2341 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                              0x0
2342 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                             0x2
2343 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0x3
2344 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0x5
2345 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0x6
2346 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0x8
2347 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0x9
2348 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0xb
2349 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0xc
2350 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0xe
2351 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0xf
2352 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0x11
2353 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0x12
2354 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0x14
2355 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                                0x00000003L
2356 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                               0x00000004L
2357 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00000018L
2358 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00000020L
2359 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x000000C0L
2360 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x00000100L
2361 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00000600L
2362 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00000800L
2363 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x00003000L
2364 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x00004000L
2365 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00018000L
2366 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00020000L
2367 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x000C0000L
2368 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x00100000L
2369 //SQC_DSM_CNTLA
2370 #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0x0
2371 #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0x2
2372 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                         0x3
2373 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                        0x5
2374 #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x6
2375 #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
2376 #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
2377 #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
2378 #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
2379 #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
2380 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                0xf
2381 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
2382 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x12
2383 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x14
2384 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT                                           0x15
2385 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT                                          0x17
2386 #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x18
2387 #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0x1a
2388 #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00000003L
2389 #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000004L
2390 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                           0x00000018L
2391 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                          0x00000020L
2392 #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000000C0L
2393 #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
2394 #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
2395 #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
2396 #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
2397 #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
2398 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
2399 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
2400 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000C0000L
2401 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00100000L
2402 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK                                             0x00600000L
2403 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK                                            0x00800000L
2404 #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x03000000L
2405 #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x04000000L
2406 //SQC_DSM_CNTLB
2407 #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0x0
2408 #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0x2
2409 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                         0x3
2410 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                        0x5
2411 #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x6
2412 #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
2413 #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
2414 #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
2415 #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
2416 #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
2417 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                0xf
2418 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
2419 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x12
2420 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x14
2421 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT                                           0x15
2422 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT                                          0x17
2423 #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x18
2424 #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0x1a
2425 #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00000003L
2426 #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000004L
2427 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                           0x00000018L
2428 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                          0x00000020L
2429 #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000000C0L
2430 #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
2431 #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
2432 #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
2433 #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
2434 #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
2435 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
2436 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
2437 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000C0000L
2438 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00100000L
2439 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK                                             0x00600000L
2440 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK                                            0x00800000L
2441 #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x03000000L
2442 #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x04000000L
2443 //SQC_DSM_CNTL2
2444 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                            0x0
2445 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                            0x2
2446 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                     0x3
2447 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                     0x5
2448 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                        0x6
2449 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                        0x8
2450 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                     0x9
2451 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                     0xb
2452 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                        0xc
2453 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                        0xe
2454 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                     0xf
2455 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                     0x11
2456 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                        0x12
2457 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                        0x14
2458 #define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
2459 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                              0x00000003L
2460 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                              0x00000004L
2461 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                       0x00000018L
2462 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                       0x00000020L
2463 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                          0x000000C0L
2464 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                          0x00000100L
2465 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                       0x00000600L
2466 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                       0x00000800L
2467 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                          0x00003000L
2468 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                          0x00004000L
2469 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                       0x00018000L
2470 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                       0x00020000L
2471 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                          0x000C0000L
2472 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                          0x00100000L
2473 #define SQC_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
2474 //SQC_DSM_CNTL2A
2475 #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0x0
2476 #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0x2
2477 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x3
2478 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                       0x5
2479 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x6
2480 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x8
2481 #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
2482 #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0xb
2483 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
2484 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0xe
2485 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT                                              0xf
2486 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT                                              0x11
2487 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x12
2488 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x14
2489 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT                                         0x15
2490 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT                                         0x17
2491 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x18
2492 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0x1a
2493 #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
2494 #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
2495 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                         0x00000018L
2496 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                         0x00000020L
2497 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
2498 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00000100L
2499 #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
2500 #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
2501 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
2502 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
2503 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
2504 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK                                                0x00020000L
2505 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000C0000L
2506 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00100000L
2507 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK                                           0x00600000L
2508 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK                                           0x00800000L
2509 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x03000000L
2510 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x04000000L
2511 //SQC_DSM_CNTL2B
2512 #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0x0
2513 #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0x2
2514 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x3
2515 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                       0x5
2516 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x6
2517 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x8
2518 #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
2519 #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0xb
2520 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
2521 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0xe
2522 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT                                              0xf
2523 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT                                              0x11
2524 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x12
2525 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x14
2526 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT                                         0x15
2527 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT                                         0x17
2528 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x18
2529 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0x1a
2530 #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
2531 #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
2532 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                         0x00000018L
2533 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                         0x00000020L
2534 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
2535 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00000100L
2536 #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
2537 #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
2538 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
2539 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
2540 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
2541 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK                                                0x00020000L
2542 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000C0000L
2543 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00100000L
2544 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK                                           0x00600000L
2545 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK                                           0x00800000L
2546 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x03000000L
2547 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x04000000L
2548 //SQC_EDC_FUE_CNTL
2549 #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT                                                              0x0
2550 #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT                                                        0x10
2551 #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK                                                                0x0000FFFFL
2552 #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK                                                          0xFFFF0000L
2553 //SQC_EDC_CNT2
2554 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT                                                     0x0
2555 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT                                                     0x2
2556 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT                                                    0x4
2557 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT                                                    0x6
2558 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT                                                     0x8
2559 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT                                                     0xa
2560 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT                                                    0xc
2561 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT                                                    0xe
2562 #define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT                                             0x10
2563 #define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT                                                   0x12
2564 #define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT                                                    0x14
2565 #define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT                                                   0x16
2566 #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT                                               0x18
2567 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                       0x1a
2568 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT                                                       0x1c
2569 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK                                                       0x00000003L
2570 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK                                                       0x0000000CL
2571 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK                                                      0x00000030L
2572 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK                                                      0x000000C0L
2573 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK                                                       0x00000300L
2574 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK                                                       0x00000C00L
2575 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK                                                      0x00003000L
2576 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK                                                      0x0000C000L
2577 #define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK                                               0x00030000L
2578 #define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK                                                     0x000C0000L
2579 #define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK                                                      0x00300000L
2580 #define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK                                                     0x00C00000L
2581 #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK                                                 0x03000000L
2582 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK                                                         0x0C000000L
2583 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK                                                         0x30000000L
2584 //SQC_EDC_CNT3
2585 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT                                                     0x0
2586 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT                                                     0x2
2587 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT                                                    0x4
2588 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT                                                    0x6
2589 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT                                                     0x8
2590 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT                                                     0xa
2591 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT                                                    0xc
2592 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT                                                    0xe
2593 #define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT                                             0x10
2594 #define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT                                                   0x12
2595 #define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT                                                    0x14
2596 #define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT                                                   0x16
2597 #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT                                               0x18
2598 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK                                                       0x00000003L
2599 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK                                                       0x0000000CL
2600 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK                                                      0x00000030L
2601 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK                                                      0x000000C0L
2602 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK                                                       0x00000300L
2603 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK                                                       0x00000C00L
2604 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK                                                      0x00003000L
2605 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK                                                      0x0000C000L
2606 #define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK                                               0x00030000L
2607 #define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK                                                     0x000C0000L
2608 #define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK                                                      0x00300000L
2609 #define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK                                                     0x00C00000L
2610 #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK                                                 0x03000000L
2611 //SQ_REG_TIMESTAMP
2612 #define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT                                                                    0x0
2613 #define SQ_REG_TIMESTAMP__TIMESTAMP_MASK                                                                      0x000000FFL
2614 //SQ_CMD_TIMESTAMP
2615 #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT                                                                    0x0
2616 #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK                                                                      0x000000FFL
2617 //SQ_IND_INDEX
2618 #define SQ_IND_INDEX__WAVE_ID__SHIFT                                                                          0x0
2619 #define SQ_IND_INDEX__SIMD_ID__SHIFT                                                                          0x4
2620 #define SQ_IND_INDEX__THREAD_ID__SHIFT                                                                        0x6
2621 #define SQ_IND_INDEX__AUTO_INCR__SHIFT                                                                        0xc
2622 #define SQ_IND_INDEX__FORCE_READ__SHIFT                                                                       0xd
2623 #define SQ_IND_INDEX__READ_TIMEOUT__SHIFT                                                                     0xe
2624 #define SQ_IND_INDEX__UNINDEXED__SHIFT                                                                        0xf
2625 #define SQ_IND_INDEX__INDEX__SHIFT                                                                            0x10
2626 #define SQ_IND_INDEX__WAVE_ID_MASK                                                                            0x0000000FL
2627 #define SQ_IND_INDEX__SIMD_ID_MASK                                                                            0x00000030L
2628 #define SQ_IND_INDEX__THREAD_ID_MASK                                                                          0x00000FC0L
2629 #define SQ_IND_INDEX__AUTO_INCR_MASK                                                                          0x00001000L
2630 #define SQ_IND_INDEX__FORCE_READ_MASK                                                                         0x00002000L
2631 #define SQ_IND_INDEX__READ_TIMEOUT_MASK                                                                       0x00004000L
2632 #define SQ_IND_INDEX__UNINDEXED_MASK                                                                          0x00008000L
2633 #define SQ_IND_INDEX__INDEX_MASK                                                                              0xFFFF0000L
2634 //SQ_IND_DATA
2635 #define SQ_IND_DATA__DATA__SHIFT                                                                              0x0
2636 #define SQ_IND_DATA__DATA_MASK                                                                                0xFFFFFFFFL
2637 //SQ_CMD
2638 #define SQ_CMD__CMD__SHIFT                                                                                    0x0
2639 #define SQ_CMD__MODE__SHIFT                                                                                   0x4
2640 #define SQ_CMD__CHECK_VMID__SHIFT                                                                             0x7
2641 #define SQ_CMD__DATA__SHIFT                                                                                   0x8
2642 #define SQ_CMD__WAVE_ID__SHIFT                                                                                0x10
2643 #define SQ_CMD__SIMD_ID__SHIFT                                                                                0x14
2644 #define SQ_CMD__QUEUE_ID__SHIFT                                                                               0x18
2645 #define SQ_CMD__VM_ID__SHIFT                                                                                  0x1c
2646 #define SQ_CMD__CMD_MASK                                                                                      0x00000007L
2647 #define SQ_CMD__MODE_MASK                                                                                     0x00000070L
2648 #define SQ_CMD__CHECK_VMID_MASK                                                                               0x00000080L
2649 #define SQ_CMD__DATA_MASK                                                                                     0x00000F00L
2650 #define SQ_CMD__WAVE_ID_MASK                                                                                  0x000F0000L
2651 #define SQ_CMD__SIMD_ID_MASK                                                                                  0x00300000L
2652 #define SQ_CMD__QUEUE_ID_MASK                                                                                 0x07000000L
2653 #define SQ_CMD__VM_ID_MASK                                                                                    0xF0000000L
2654 //SQ_TIME_HI
2655 #define SQ_TIME_HI__TIME__SHIFT                                                                               0x0
2656 #define SQ_TIME_HI__TIME_MASK                                                                                 0xFFFFFFFFL
2657 //SQ_TIME_LO
2658 #define SQ_TIME_LO__TIME__SHIFT                                                                               0x0
2659 #define SQ_TIME_LO__TIME_MASK                                                                                 0xFFFFFFFFL
2660 //SQ_DS_0
2661 #define SQ_DS_0__OFFSET0__SHIFT                                                                               0x0
2662 #define SQ_DS_0__OFFSET1__SHIFT                                                                               0x8
2663 #define SQ_DS_0__GDS__SHIFT                                                                                   0x10
2664 #define SQ_DS_0__OP__SHIFT                                                                                    0x11
2665 #define SQ_DS_0__ENCODING__SHIFT                                                                              0x1a
2666 #define SQ_DS_0__OFFSET0_MASK                                                                                 0x000000FFL
2667 #define SQ_DS_0__OFFSET1_MASK                                                                                 0x0000FF00L
2668 #define SQ_DS_0__GDS_MASK                                                                                     0x00010000L
2669 #define SQ_DS_0__OP_MASK                                                                                      0x01FE0000L
2670 #define SQ_DS_0__ENCODING_MASK                                                                                0xFC000000L
2671 //SQ_DS_1
2672 #define SQ_DS_1__ADDR__SHIFT                                                                                  0x0
2673 #define SQ_DS_1__DATA0__SHIFT                                                                                 0x8
2674 #define SQ_DS_1__DATA1__SHIFT                                                                                 0x10
2675 #define SQ_DS_1__VDST__SHIFT                                                                                  0x18
2676 #define SQ_DS_1__ADDR_MASK                                                                                    0x000000FFL
2677 #define SQ_DS_1__DATA0_MASK                                                                                   0x0000FF00L
2678 #define SQ_DS_1__DATA1_MASK                                                                                   0x00FF0000L
2679 #define SQ_DS_1__VDST_MASK                                                                                    0xFF000000L
2680 //SQ_EXP_0
2681 #define SQ_EXP_0__EN__SHIFT                                                                                   0x0
2682 #define SQ_EXP_0__TGT__SHIFT                                                                                  0x4
2683 #define SQ_EXP_0__COMPR__SHIFT                                                                                0xa
2684 #define SQ_EXP_0__DONE__SHIFT                                                                                 0xb
2685 #define SQ_EXP_0__VM__SHIFT                                                                                   0xc
2686 #define SQ_EXP_0__ENCODING__SHIFT                                                                             0x1a
2687 #define SQ_EXP_0__EN_MASK                                                                                     0x0000000FL
2688 #define SQ_EXP_0__TGT_MASK                                                                                    0x000003F0L
2689 #define SQ_EXP_0__COMPR_MASK                                                                                  0x00000400L
2690 #define SQ_EXP_0__DONE_MASK                                                                                   0x00000800L
2691 #define SQ_EXP_0__VM_MASK                                                                                     0x00001000L
2692 #define SQ_EXP_0__ENCODING_MASK                                                                               0xFC000000L
2693 //SQ_EXP_1
2694 #define SQ_EXP_1__VSRC0__SHIFT                                                                                0x0
2695 #define SQ_EXP_1__VSRC1__SHIFT                                                                                0x8
2696 #define SQ_EXP_1__VSRC2__SHIFT                                                                                0x10
2697 #define SQ_EXP_1__VSRC3__SHIFT                                                                                0x18
2698 #define SQ_EXP_1__VSRC0_MASK                                                                                  0x000000FFL
2699 #define SQ_EXP_1__VSRC1_MASK                                                                                  0x0000FF00L
2700 #define SQ_EXP_1__VSRC2_MASK                                                                                  0x00FF0000L
2701 #define SQ_EXP_1__VSRC3_MASK                                                                                  0xFF000000L
2702 //SQ_FLAT_0
2703 #define SQ_FLAT_0__OFFSET__SHIFT                                                                              0x0
2704 #define SQ_FLAT_0__LDS__SHIFT                                                                                 0xd
2705 #define SQ_FLAT_0__SEG__SHIFT                                                                                 0xe
2706 #define SQ_FLAT_0__GLC__SHIFT                                                                                 0x10
2707 #define SQ_FLAT_0__SLC__SHIFT                                                                                 0x11
2708 #define SQ_FLAT_0__OP__SHIFT                                                                                  0x12
2709 #define SQ_FLAT_0__ENCODING__SHIFT                                                                            0x1a
2710 #define SQ_FLAT_0__OFFSET_MASK                                                                                0x00000FFFL
2711 #define SQ_FLAT_0__LDS_MASK                                                                                   0x00002000L
2712 #define SQ_FLAT_0__SEG_MASK                                                                                   0x0000C000L
2713 #define SQ_FLAT_0__GLC_MASK                                                                                   0x00010000L
2714 #define SQ_FLAT_0__SLC_MASK                                                                                   0x00020000L
2715 #define SQ_FLAT_0__OP_MASK                                                                                    0x01FC0000L
2716 #define SQ_FLAT_0__ENCODING_MASK                                                                              0xFC000000L
2717 //SQ_FLAT_1
2718 #define SQ_FLAT_1__ADDR__SHIFT                                                                                0x0
2719 #define SQ_FLAT_1__DATA__SHIFT                                                                                0x8
2720 #define SQ_FLAT_1__SADDR__SHIFT                                                                               0x10
2721 #define SQ_FLAT_1__NV__SHIFT                                                                                  0x17
2722 #define SQ_FLAT_1__VDST__SHIFT                                                                                0x18
2723 #define SQ_FLAT_1__ADDR_MASK                                                                                  0x000000FFL
2724 #define SQ_FLAT_1__DATA_MASK                                                                                  0x0000FF00L
2725 #define SQ_FLAT_1__SADDR_MASK                                                                                 0x007F0000L
2726 #define SQ_FLAT_1__NV_MASK                                                                                    0x00800000L
2727 #define SQ_FLAT_1__VDST_MASK                                                                                  0xFF000000L
2728 //SQ_GLBL_0
2729 #define SQ_GLBL_0__OFFSET__SHIFT                                                                              0x0
2730 #define SQ_GLBL_0__LDS__SHIFT                                                                                 0xd
2731 #define SQ_GLBL_0__SEG__SHIFT                                                                                 0xe
2732 #define SQ_GLBL_0__GLC__SHIFT                                                                                 0x10
2733 #define SQ_GLBL_0__SLC__SHIFT                                                                                 0x11
2734 #define SQ_GLBL_0__OP__SHIFT                                                                                  0x12
2735 #define SQ_GLBL_0__ENCODING__SHIFT                                                                            0x1a
2736 #define SQ_GLBL_0__OFFSET_MASK                                                                                0x00001FFFL
2737 #define SQ_GLBL_0__LDS_MASK                                                                                   0x00002000L
2738 #define SQ_GLBL_0__SEG_MASK                                                                                   0x0000C000L
2739 #define SQ_GLBL_0__GLC_MASK                                                                                   0x00010000L
2740 #define SQ_GLBL_0__SLC_MASK                                                                                   0x00020000L
2741 #define SQ_GLBL_0__OP_MASK                                                                                    0x01FC0000L
2742 #define SQ_GLBL_0__ENCODING_MASK                                                                              0xFC000000L
2743 //SQ_GLBL_1
2744 #define SQ_GLBL_1__ADDR__SHIFT                                                                                0x0
2745 #define SQ_GLBL_1__DATA__SHIFT                                                                                0x8
2746 #define SQ_GLBL_1__SADDR__SHIFT                                                                               0x10
2747 #define SQ_GLBL_1__NV__SHIFT                                                                                  0x17
2748 #define SQ_GLBL_1__VDST__SHIFT                                                                                0x18
2749 #define SQ_GLBL_1__ADDR_MASK                                                                                  0x000000FFL
2750 #define SQ_GLBL_1__DATA_MASK                                                                                  0x0000FF00L
2751 #define SQ_GLBL_1__SADDR_MASK                                                                                 0x007F0000L
2752 #define SQ_GLBL_1__NV_MASK                                                                                    0x00800000L
2753 #define SQ_GLBL_1__VDST_MASK                                                                                  0xFF000000L
2754 //SQ_INST
2755 #define SQ_INST__ENCODING__SHIFT                                                                              0x0
2756 #define SQ_INST__ENCODING_MASK                                                                                0xFFFFFFFFL
2757 //SQ_MIMG_0
2758 #define SQ_MIMG_0__OPM__SHIFT                                                                                 0x0
2759 #define SQ_MIMG_0__DMASK__SHIFT                                                                               0x8
2760 #define SQ_MIMG_0__UNORM__SHIFT                                                                               0xc
2761 #define SQ_MIMG_0__GLC__SHIFT                                                                                 0xd
2762 #define SQ_MIMG_0__DA__SHIFT                                                                                  0xe
2763 #define SQ_MIMG_0__A16__SHIFT                                                                                 0xf
2764 #define SQ_MIMG_0__TFE__SHIFT                                                                                 0x10
2765 #define SQ_MIMG_0__LWE__SHIFT                                                                                 0x11
2766 #define SQ_MIMG_0__OP__SHIFT                                                                                  0x12
2767 #define SQ_MIMG_0__SLC__SHIFT                                                                                 0x19
2768 #define SQ_MIMG_0__ENCODING__SHIFT                                                                            0x1a
2769 #define SQ_MIMG_0__OPM_MASK                                                                                   0x00000001L
2770 #define SQ_MIMG_0__DMASK_MASK                                                                                 0x00000F00L
2771 #define SQ_MIMG_0__UNORM_MASK                                                                                 0x00001000L
2772 #define SQ_MIMG_0__GLC_MASK                                                                                   0x00002000L
2773 #define SQ_MIMG_0__DA_MASK                                                                                    0x00004000L
2774 #define SQ_MIMG_0__A16_MASK                                                                                   0x00008000L
2775 #define SQ_MIMG_0__TFE_MASK                                                                                   0x00010000L
2776 #define SQ_MIMG_0__LWE_MASK                                                                                   0x00020000L
2777 #define SQ_MIMG_0__OP_MASK                                                                                    0x01FC0000L
2778 #define SQ_MIMG_0__SLC_MASK                                                                                   0x02000000L
2779 #define SQ_MIMG_0__ENCODING_MASK                                                                              0xFC000000L
2780 //SQ_MIMG_1
2781 #define SQ_MIMG_1__VADDR__SHIFT                                                                               0x0
2782 #define SQ_MIMG_1__VDATA__SHIFT                                                                               0x8
2783 #define SQ_MIMG_1__SRSRC__SHIFT                                                                               0x10
2784 #define SQ_MIMG_1__SSAMP__SHIFT                                                                               0x15
2785 #define SQ_MIMG_1__D16__SHIFT                                                                                 0x1f
2786 #define SQ_MIMG_1__VADDR_MASK                                                                                 0x000000FFL
2787 #define SQ_MIMG_1__VDATA_MASK                                                                                 0x0000FF00L
2788 #define SQ_MIMG_1__SRSRC_MASK                                                                                 0x001F0000L
2789 #define SQ_MIMG_1__SSAMP_MASK                                                                                 0x03E00000L
2790 #define SQ_MIMG_1__D16_MASK                                                                                   0x80000000L
2791 //SQ_MTBUF_0
2792 #define SQ_MTBUF_0__OFFSET__SHIFT                                                                             0x0
2793 #define SQ_MTBUF_0__OFFEN__SHIFT                                                                              0xc
2794 #define SQ_MTBUF_0__IDXEN__SHIFT                                                                              0xd
2795 #define SQ_MTBUF_0__GLC__SHIFT                                                                                0xe
2796 #define SQ_MTBUF_0__OP__SHIFT                                                                                 0xf
2797 #define SQ_MTBUF_0__DFMT__SHIFT                                                                               0x13
2798 #define SQ_MTBUF_0__NFMT__SHIFT                                                                               0x17
2799 #define SQ_MTBUF_0__ENCODING__SHIFT                                                                           0x1a
2800 #define SQ_MTBUF_0__OFFSET_MASK                                                                               0x00000FFFL
2801 #define SQ_MTBUF_0__OFFEN_MASK                                                                                0x00001000L
2802 #define SQ_MTBUF_0__IDXEN_MASK                                                                                0x00002000L
2803 #define SQ_MTBUF_0__GLC_MASK                                                                                  0x00004000L
2804 #define SQ_MTBUF_0__OP_MASK                                                                                   0x00078000L
2805 #define SQ_MTBUF_0__DFMT_MASK                                                                                 0x00780000L
2806 #define SQ_MTBUF_0__NFMT_MASK                                                                                 0x03800000L
2807 #define SQ_MTBUF_0__ENCODING_MASK                                                                             0xFC000000L
2808 //SQ_MTBUF_1
2809 #define SQ_MTBUF_1__VADDR__SHIFT                                                                              0x0
2810 #define SQ_MTBUF_1__VDATA__SHIFT                                                                              0x8
2811 #define SQ_MTBUF_1__SRSRC__SHIFT                                                                              0x10
2812 #define SQ_MTBUF_1__SLC__SHIFT                                                                                0x16
2813 #define SQ_MTBUF_1__TFE__SHIFT                                                                                0x17
2814 #define SQ_MTBUF_1__SOFFSET__SHIFT                                                                            0x18
2815 #define SQ_MTBUF_1__VADDR_MASK                                                                                0x000000FFL
2816 #define SQ_MTBUF_1__VDATA_MASK                                                                                0x0000FF00L
2817 #define SQ_MTBUF_1__SRSRC_MASK                                                                                0x001F0000L
2818 #define SQ_MTBUF_1__SLC_MASK                                                                                  0x00400000L
2819 #define SQ_MTBUF_1__TFE_MASK                                                                                  0x00800000L
2820 #define SQ_MTBUF_1__SOFFSET_MASK                                                                              0xFF000000L
2821 //SQ_MUBUF_0
2822 #define SQ_MUBUF_0__OFFSET__SHIFT                                                                             0x0
2823 #define SQ_MUBUF_0__OFFEN__SHIFT                                                                              0xc
2824 #define SQ_MUBUF_0__IDXEN__SHIFT                                                                              0xd
2825 #define SQ_MUBUF_0__GLC__SHIFT                                                                                0xe
2826 #define SQ_MUBUF_0__LDS__SHIFT                                                                                0x10
2827 #define SQ_MUBUF_0__SLC__SHIFT                                                                                0x11
2828 #define SQ_MUBUF_0__OP__SHIFT                                                                                 0x12
2829 #define SQ_MUBUF_0__ENCODING__SHIFT                                                                           0x1a
2830 #define SQ_MUBUF_0__OFFSET_MASK                                                                               0x00000FFFL
2831 #define SQ_MUBUF_0__OFFEN_MASK                                                                                0x00001000L
2832 #define SQ_MUBUF_0__IDXEN_MASK                                                                                0x00002000L
2833 #define SQ_MUBUF_0__GLC_MASK                                                                                  0x00004000L
2834 #define SQ_MUBUF_0__LDS_MASK                                                                                  0x00010000L
2835 #define SQ_MUBUF_0__SLC_MASK                                                                                  0x00020000L
2836 #define SQ_MUBUF_0__OP_MASK                                                                                   0x01FC0000L
2837 #define SQ_MUBUF_0__ENCODING_MASK                                                                             0xFC000000L
2838 //SQ_MUBUF_1
2839 #define SQ_MUBUF_1__VADDR__SHIFT                                                                              0x0
2840 #define SQ_MUBUF_1__VDATA__SHIFT                                                                              0x8
2841 #define SQ_MUBUF_1__SRSRC__SHIFT                                                                              0x10
2842 #define SQ_MUBUF_1__TFE__SHIFT                                                                                0x17
2843 #define SQ_MUBUF_1__SOFFSET__SHIFT                                                                            0x18
2844 #define SQ_MUBUF_1__VADDR_MASK                                                                                0x000000FFL
2845 #define SQ_MUBUF_1__VDATA_MASK                                                                                0x0000FF00L
2846 #define SQ_MUBUF_1__SRSRC_MASK                                                                                0x001F0000L
2847 #define SQ_MUBUF_1__TFE_MASK                                                                                  0x00800000L
2848 #define SQ_MUBUF_1__SOFFSET_MASK                                                                              0xFF000000L
2849 //SQ_SCRATCH_0
2850 #define SQ_SCRATCH_0__OFFSET__SHIFT                                                                           0x0
2851 #define SQ_SCRATCH_0__LDS__SHIFT                                                                              0xd
2852 #define SQ_SCRATCH_0__SEG__SHIFT                                                                              0xe
2853 #define SQ_SCRATCH_0__GLC__SHIFT                                                                              0x10
2854 #define SQ_SCRATCH_0__SLC__SHIFT                                                                              0x11
2855 #define SQ_SCRATCH_0__OP__SHIFT                                                                               0x12
2856 #define SQ_SCRATCH_0__ENCODING__SHIFT                                                                         0x1a
2857 #define SQ_SCRATCH_0__OFFSET_MASK                                                                             0x00001FFFL
2858 #define SQ_SCRATCH_0__LDS_MASK                                                                                0x00002000L
2859 #define SQ_SCRATCH_0__SEG_MASK                                                                                0x0000C000L
2860 #define SQ_SCRATCH_0__GLC_MASK                                                                                0x00010000L
2861 #define SQ_SCRATCH_0__SLC_MASK                                                                                0x00020000L
2862 #define SQ_SCRATCH_0__OP_MASK                                                                                 0x01FC0000L
2863 #define SQ_SCRATCH_0__ENCODING_MASK                                                                           0xFC000000L
2864 //SQ_SCRATCH_1
2865 #define SQ_SCRATCH_1__ADDR__SHIFT                                                                             0x0
2866 #define SQ_SCRATCH_1__DATA__SHIFT                                                                             0x8
2867 #define SQ_SCRATCH_1__SADDR__SHIFT                                                                            0x10
2868 #define SQ_SCRATCH_1__NV__SHIFT                                                                               0x17
2869 #define SQ_SCRATCH_1__VDST__SHIFT                                                                             0x18
2870 #define SQ_SCRATCH_1__ADDR_MASK                                                                               0x000000FFL
2871 #define SQ_SCRATCH_1__DATA_MASK                                                                               0x0000FF00L
2872 #define SQ_SCRATCH_1__SADDR_MASK                                                                              0x007F0000L
2873 #define SQ_SCRATCH_1__NV_MASK                                                                                 0x00800000L
2874 #define SQ_SCRATCH_1__VDST_MASK                                                                               0xFF000000L
2875 //SQ_SMEM_0
2876 #define SQ_SMEM_0__SBASE__SHIFT                                                                               0x0
2877 #define SQ_SMEM_0__SDATA__SHIFT                                                                               0x6
2878 #define SQ_SMEM_0__SOFFSET_EN__SHIFT                                                                          0xe
2879 #define SQ_SMEM_0__NV__SHIFT                                                                                  0xf
2880 #define SQ_SMEM_0__GLC__SHIFT                                                                                 0x10
2881 #define SQ_SMEM_0__IMM__SHIFT                                                                                 0x11
2882 #define SQ_SMEM_0__OP__SHIFT                                                                                  0x12
2883 #define SQ_SMEM_0__ENCODING__SHIFT                                                                            0x1a
2884 #define SQ_SMEM_0__SBASE_MASK                                                                                 0x0000003FL
2885 #define SQ_SMEM_0__SDATA_MASK                                                                                 0x00001FC0L
2886 #define SQ_SMEM_0__SOFFSET_EN_MASK                                                                            0x00004000L
2887 #define SQ_SMEM_0__NV_MASK                                                                                    0x00008000L
2888 #define SQ_SMEM_0__GLC_MASK                                                                                   0x00010000L
2889 #define SQ_SMEM_0__IMM_MASK                                                                                   0x00020000L
2890 #define SQ_SMEM_0__OP_MASK                                                                                    0x03FC0000L
2891 #define SQ_SMEM_0__ENCODING_MASK                                                                              0xFC000000L
2892 //SQ_SMEM_1
2893 #define SQ_SMEM_1__OFFSET__SHIFT                                                                              0x0
2894 #define SQ_SMEM_1__SOFFSET__SHIFT                                                                             0x19
2895 #define SQ_SMEM_1__OFFSET_MASK                                                                                0x001FFFFFL
2896 #define SQ_SMEM_1__SOFFSET_MASK                                                                               0xFE000000L
2897 //SQ_SOP1
2898 #define SQ_SOP1__SSRC0__SHIFT                                                                                 0x0
2899 #define SQ_SOP1__OP__SHIFT                                                                                    0x8
2900 #define SQ_SOP1__SDST__SHIFT                                                                                  0x10
2901 #define SQ_SOP1__ENCODING__SHIFT                                                                              0x17
2902 #define SQ_SOP1__SSRC0_MASK                                                                                   0x000000FFL
2903 #define SQ_SOP1__OP_MASK                                                                                      0x0000FF00L
2904 #define SQ_SOP1__SDST_MASK                                                                                    0x007F0000L
2905 #define SQ_SOP1__ENCODING_MASK                                                                                0xFF800000L
2906 //SQ_SOP2
2907 #define SQ_SOP2__SSRC0__SHIFT                                                                                 0x0
2908 #define SQ_SOP2__SSRC1__SHIFT                                                                                 0x8
2909 #define SQ_SOP2__SDST__SHIFT                                                                                  0x10
2910 #define SQ_SOP2__OP__SHIFT                                                                                    0x17
2911 #define SQ_SOP2__ENCODING__SHIFT                                                                              0x1e
2912 #define SQ_SOP2__SSRC0_MASK                                                                                   0x000000FFL
2913 #define SQ_SOP2__SSRC1_MASK                                                                                   0x0000FF00L
2914 #define SQ_SOP2__SDST_MASK                                                                                    0x007F0000L
2915 #define SQ_SOP2__OP_MASK                                                                                      0x3F800000L
2916 #define SQ_SOP2__ENCODING_MASK                                                                                0xC0000000L
2917 //SQ_SOPC
2918 #define SQ_SOPC__SSRC0__SHIFT                                                                                 0x0
2919 #define SQ_SOPC__SSRC1__SHIFT                                                                                 0x8
2920 #define SQ_SOPC__OP__SHIFT                                                                                    0x10
2921 #define SQ_SOPC__ENCODING__SHIFT                                                                              0x17
2922 #define SQ_SOPC__SSRC0_MASK                                                                                   0x000000FFL
2923 #define SQ_SOPC__SSRC1_MASK                                                                                   0x0000FF00L
2924 #define SQ_SOPC__OP_MASK                                                                                      0x007F0000L
2925 #define SQ_SOPC__ENCODING_MASK                                                                                0xFF800000L
2926 //SQ_SOPK
2927 #define SQ_SOPK__SIMM16__SHIFT                                                                                0x0
2928 #define SQ_SOPK__SDST__SHIFT                                                                                  0x10
2929 #define SQ_SOPK__OP__SHIFT                                                                                    0x17
2930 #define SQ_SOPK__ENCODING__SHIFT                                                                              0x1c
2931 #define SQ_SOPK__SIMM16_MASK                                                                                  0x0000FFFFL
2932 #define SQ_SOPK__SDST_MASK                                                                                    0x007F0000L
2933 #define SQ_SOPK__OP_MASK                                                                                      0x0F800000L
2934 #define SQ_SOPK__ENCODING_MASK                                                                                0xF0000000L
2935 //SQ_SOPP
2936 #define SQ_SOPP__SIMM16__SHIFT                                                                                0x0
2937 #define SQ_SOPP__OP__SHIFT                                                                                    0x10
2938 #define SQ_SOPP__ENCODING__SHIFT                                                                              0x17
2939 #define SQ_SOPP__SIMM16_MASK                                                                                  0x0000FFFFL
2940 #define SQ_SOPP__OP_MASK                                                                                      0x007F0000L
2941 #define SQ_SOPP__ENCODING_MASK                                                                                0xFF800000L
2942 //SQ_VINTRP
2943 #define SQ_VINTRP__VSRC__SHIFT                                                                                0x0
2944 #define SQ_VINTRP__ATTRCHAN__SHIFT                                                                            0x8
2945 #define SQ_VINTRP__ATTR__SHIFT                                                                                0xa
2946 #define SQ_VINTRP__OP__SHIFT                                                                                  0x10
2947 #define SQ_VINTRP__VDST__SHIFT                                                                                0x12
2948 #define SQ_VINTRP__ENCODING__SHIFT                                                                            0x1a
2949 #define SQ_VINTRP__VSRC_MASK                                                                                  0x000000FFL
2950 #define SQ_VINTRP__ATTRCHAN_MASK                                                                              0x00000300L
2951 #define SQ_VINTRP__ATTR_MASK                                                                                  0x0000FC00L
2952 #define SQ_VINTRP__OP_MASK                                                                                    0x00030000L
2953 #define SQ_VINTRP__VDST_MASK                                                                                  0x03FC0000L
2954 #define SQ_VINTRP__ENCODING_MASK                                                                              0xFC000000L
2955 //SQ_VOP1
2956 #define SQ_VOP1__SRC0__SHIFT                                                                                  0x0
2957 #define SQ_VOP1__OP__SHIFT                                                                                    0x9
2958 #define SQ_VOP1__VDST__SHIFT                                                                                  0x11
2959 #define SQ_VOP1__ENCODING__SHIFT                                                                              0x19
2960 #define SQ_VOP1__SRC0_MASK                                                                                    0x000001FFL
2961 #define SQ_VOP1__OP_MASK                                                                                      0x0001FE00L
2962 #define SQ_VOP1__VDST_MASK                                                                                    0x01FE0000L
2963 #define SQ_VOP1__ENCODING_MASK                                                                                0xFE000000L
2964 //SQ_VOP2
2965 #define SQ_VOP2__SRC0__SHIFT                                                                                  0x0
2966 #define SQ_VOP2__VSRC1__SHIFT                                                                                 0x9
2967 #define SQ_VOP2__VDST__SHIFT                                                                                  0x11
2968 #define SQ_VOP2__OP__SHIFT                                                                                    0x19
2969 #define SQ_VOP2__ENCODING__SHIFT                                                                              0x1f
2970 #define SQ_VOP2__SRC0_MASK                                                                                    0x000001FFL
2971 #define SQ_VOP2__VSRC1_MASK                                                                                   0x0001FE00L
2972 #define SQ_VOP2__VDST_MASK                                                                                    0x01FE0000L
2973 #define SQ_VOP2__OP_MASK                                                                                      0x7E000000L
2974 #define SQ_VOP2__ENCODING_MASK                                                                                0x80000000L
2975 //SQ_VOP3P_0
2976 #define SQ_VOP3P_0__VDST__SHIFT                                                                               0x0
2977 #define SQ_VOP3P_0__NEG_HI__SHIFT                                                                             0x8
2978 #define SQ_VOP3P_0__OP_SEL__SHIFT                                                                             0xb
2979 #define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT                                                                        0xe
2980 #define SQ_VOP3P_0__CLAMP__SHIFT                                                                              0xf
2981 #define SQ_VOP3P_0__OP__SHIFT                                                                                 0x10
2982 #define SQ_VOP3P_0__ENCODING__SHIFT                                                                           0x17
2983 #define SQ_VOP3P_0__VDST_MASK                                                                                 0x000000FFL
2984 #define SQ_VOP3P_0__NEG_HI_MASK                                                                               0x00000700L
2985 #define SQ_VOP3P_0__OP_SEL_MASK                                                                               0x00003800L
2986 #define SQ_VOP3P_0__OP_SEL_HI_2_MASK                                                                          0x00004000L
2987 #define SQ_VOP3P_0__CLAMP_MASK                                                                                0x00008000L
2988 #define SQ_VOP3P_0__OP_MASK                                                                                   0x007F0000L
2989 #define SQ_VOP3P_0__ENCODING_MASK                                                                             0xFF800000L
2990 //SQ_VOP3P_1
2991 #define SQ_VOP3P_1__SRC0__SHIFT                                                                               0x0
2992 #define SQ_VOP3P_1__SRC1__SHIFT                                                                               0x9
2993 #define SQ_VOP3P_1__SRC2__SHIFT                                                                               0x12
2994 #define SQ_VOP3P_1__OP_SEL_HI__SHIFT                                                                          0x1b
2995 #define SQ_VOP3P_1__NEG__SHIFT                                                                                0x1d
2996 #define SQ_VOP3P_1__SRC0_MASK                                                                                 0x000001FFL
2997 #define SQ_VOP3P_1__SRC1_MASK                                                                                 0x0003FE00L
2998 #define SQ_VOP3P_1__SRC2_MASK                                                                                 0x07FC0000L
2999 #define SQ_VOP3P_1__OP_SEL_HI_MASK                                                                            0x18000000L
3000 #define SQ_VOP3P_1__NEG_MASK                                                                                  0xE0000000L
3001 //SQ_VOP3_0
3002 #define SQ_VOP3_0__VDST__SHIFT                                                                                0x0
3003 #define SQ_VOP3_0__ABS__SHIFT                                                                                 0x8
3004 #define SQ_VOP3_0__OP_SEL__SHIFT                                                                              0xb
3005 #define SQ_VOP3_0__CLAMP__SHIFT                                                                               0xf
3006 #define SQ_VOP3_0__OP__SHIFT                                                                                  0x10
3007 #define SQ_VOP3_0__ENCODING__SHIFT                                                                            0x1a
3008 #define SQ_VOP3_0__VDST_MASK                                                                                  0x000000FFL
3009 #define SQ_VOP3_0__ABS_MASK                                                                                   0x00000700L
3010 #define SQ_VOP3_0__OP_SEL_MASK                                                                                0x00007800L
3011 #define SQ_VOP3_0__CLAMP_MASK                                                                                 0x00008000L
3012 #define SQ_VOP3_0__OP_MASK                                                                                    0x03FF0000L
3013 #define SQ_VOP3_0__ENCODING_MASK                                                                              0xFC000000L
3014 //SQ_VOP3_0_SDST_ENC
3015 #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT                                                                       0x0
3016 #define SQ_VOP3_0_SDST_ENC__SDST__SHIFT                                                                       0x8
3017 #define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT                                                                      0xf
3018 #define SQ_VOP3_0_SDST_ENC__OP__SHIFT                                                                         0x10
3019 #define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT                                                                   0x1a
3020 #define SQ_VOP3_0_SDST_ENC__VDST_MASK                                                                         0x000000FFL
3021 #define SQ_VOP3_0_SDST_ENC__SDST_MASK                                                                         0x00007F00L
3022 #define SQ_VOP3_0_SDST_ENC__CLAMP_MASK                                                                        0x00008000L
3023 #define SQ_VOP3_0_SDST_ENC__OP_MASK                                                                           0x03FF0000L
3024 #define SQ_VOP3_0_SDST_ENC__ENCODING_MASK                                                                     0xFC000000L
3025 //SQ_VOP3_1
3026 #define SQ_VOP3_1__SRC0__SHIFT                                                                                0x0
3027 #define SQ_VOP3_1__SRC1__SHIFT                                                                                0x9
3028 #define SQ_VOP3_1__SRC2__SHIFT                                                                                0x12
3029 #define SQ_VOP3_1__OMOD__SHIFT                                                                                0x1b
3030 #define SQ_VOP3_1__NEG__SHIFT                                                                                 0x1d
3031 #define SQ_VOP3_1__SRC0_MASK                                                                                  0x000001FFL
3032 #define SQ_VOP3_1__SRC1_MASK                                                                                  0x0003FE00L
3033 #define SQ_VOP3_1__SRC2_MASK                                                                                  0x07FC0000L
3034 #define SQ_VOP3_1__OMOD_MASK                                                                                  0x18000000L
3035 #define SQ_VOP3_1__NEG_MASK                                                                                   0xE0000000L
3036 //SQ_VOPC
3037 #define SQ_VOPC__SRC0__SHIFT                                                                                  0x0
3038 #define SQ_VOPC__VSRC1__SHIFT                                                                                 0x9
3039 #define SQ_VOPC__OP__SHIFT                                                                                    0x11
3040 #define SQ_VOPC__ENCODING__SHIFT                                                                              0x19
3041 #define SQ_VOPC__SRC0_MASK                                                                                    0x000001FFL
3042 #define SQ_VOPC__VSRC1_MASK                                                                                   0x0001FE00L
3043 #define SQ_VOPC__OP_MASK                                                                                      0x01FE0000L
3044 #define SQ_VOPC__ENCODING_MASK                                                                                0xFE000000L
3045 //SQ_VOP_DPP
3046 #define SQ_VOP_DPP__SRC0__SHIFT                                                                               0x0
3047 #define SQ_VOP_DPP__DPP_CTRL__SHIFT                                                                           0x8
3048 #define SQ_VOP_DPP__BOUND_CTRL__SHIFT                                                                         0x13
3049 #define SQ_VOP_DPP__SRC0_NEG__SHIFT                                                                           0x14
3050 #define SQ_VOP_DPP__SRC0_ABS__SHIFT                                                                           0x15
3051 #define SQ_VOP_DPP__SRC1_NEG__SHIFT                                                                           0x16
3052 #define SQ_VOP_DPP__SRC1_ABS__SHIFT                                                                           0x17
3053 #define SQ_VOP_DPP__BANK_MASK__SHIFT                                                                          0x18
3054 #define SQ_VOP_DPP__ROW_MASK__SHIFT                                                                           0x1c
3055 #define SQ_VOP_DPP__SRC0_MASK                                                                                 0x000000FFL
3056 #define SQ_VOP_DPP__DPP_CTRL_MASK                                                                             0x0001FF00L
3057 #define SQ_VOP_DPP__BOUND_CTRL_MASK                                                                           0x00080000L
3058 #define SQ_VOP_DPP__SRC0_NEG_MASK                                                                             0x00100000L
3059 #define SQ_VOP_DPP__SRC0_ABS_MASK                                                                             0x00200000L
3060 #define SQ_VOP_DPP__SRC1_NEG_MASK                                                                             0x00400000L
3061 #define SQ_VOP_DPP__SRC1_ABS_MASK                                                                             0x00800000L
3062 #define SQ_VOP_DPP__BANK_MASK_MASK                                                                            0x0F000000L
3063 #define SQ_VOP_DPP__ROW_MASK_MASK                                                                             0xF0000000L
3064 //SQ_VOP_SDWA
3065 #define SQ_VOP_SDWA__SRC0__SHIFT                                                                              0x0
3066 #define SQ_VOP_SDWA__DST_SEL__SHIFT                                                                           0x8
3067 #define SQ_VOP_SDWA__DST_UNUSED__SHIFT                                                                        0xb
3068 #define SQ_VOP_SDWA__CLAMP__SHIFT                                                                             0xd
3069 #define SQ_VOP_SDWA__OMOD__SHIFT                                                                              0xe
3070 #define SQ_VOP_SDWA__SRC0_SEL__SHIFT                                                                          0x10
3071 #define SQ_VOP_SDWA__SRC0_SEXT__SHIFT                                                                         0x13
3072 #define SQ_VOP_SDWA__SRC0_NEG__SHIFT                                                                          0x14
3073 #define SQ_VOP_SDWA__SRC0_ABS__SHIFT                                                                          0x15
3074 #define SQ_VOP_SDWA__S0__SHIFT                                                                                0x17
3075 #define SQ_VOP_SDWA__SRC1_SEL__SHIFT                                                                          0x18
3076 #define SQ_VOP_SDWA__SRC1_SEXT__SHIFT                                                                         0x1b
3077 #define SQ_VOP_SDWA__SRC1_NEG__SHIFT                                                                          0x1c
3078 #define SQ_VOP_SDWA__SRC1_ABS__SHIFT                                                                          0x1d
3079 #define SQ_VOP_SDWA__S1__SHIFT                                                                                0x1f
3080 #define SQ_VOP_SDWA__SRC0_MASK                                                                                0x000000FFL
3081 #define SQ_VOP_SDWA__DST_SEL_MASK                                                                             0x00000700L
3082 #define SQ_VOP_SDWA__DST_UNUSED_MASK                                                                          0x00001800L
3083 #define SQ_VOP_SDWA__CLAMP_MASK                                                                               0x00002000L
3084 #define SQ_VOP_SDWA__OMOD_MASK                                                                                0x0000C000L
3085 #define SQ_VOP_SDWA__SRC0_SEL_MASK                                                                            0x00070000L
3086 #define SQ_VOP_SDWA__SRC0_SEXT_MASK                                                                           0x00080000L
3087 #define SQ_VOP_SDWA__SRC0_NEG_MASK                                                                            0x00100000L
3088 #define SQ_VOP_SDWA__SRC0_ABS_MASK                                                                            0x00200000L
3089 #define SQ_VOP_SDWA__S0_MASK                                                                                  0x00800000L
3090 #define SQ_VOP_SDWA__SRC1_SEL_MASK                                                                            0x07000000L
3091 #define SQ_VOP_SDWA__SRC1_SEXT_MASK                                                                           0x08000000L
3092 #define SQ_VOP_SDWA__SRC1_NEG_MASK                                                                            0x10000000L
3093 #define SQ_VOP_SDWA__SRC1_ABS_MASK                                                                            0x20000000L
3094 #define SQ_VOP_SDWA__S1_MASK                                                                                  0x80000000L
3095 //SQ_VOP_SDWA_SDST_ENC
3096 #define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT                                                                     0x0
3097 #define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT                                                                     0x8
3098 #define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT                                                                       0xf
3099 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT                                                                 0x10
3100 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT                                                                0x13
3101 #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT                                                                 0x14
3102 #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT                                                                 0x15
3103 #define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT                                                                       0x17
3104 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT                                                                 0x18
3105 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT                                                                0x1b
3106 #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT                                                                 0x1c
3107 #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT                                                                 0x1d
3108 #define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT                                                                       0x1f
3109 #define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK                                                                       0x000000FFL
3110 #define SQ_VOP_SDWA_SDST_ENC__SDST_MASK                                                                       0x00007F00L
3111 #define SQ_VOP_SDWA_SDST_ENC__SD_MASK                                                                         0x00008000L
3112 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK                                                                   0x00070000L
3113 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK                                                                  0x00080000L
3114 #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK                                                                   0x00100000L
3115 #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK                                                                   0x00200000L
3116 #define SQ_VOP_SDWA_SDST_ENC__S0_MASK                                                                         0x00800000L
3117 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK                                                                   0x07000000L
3118 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK                                                                  0x08000000L
3119 #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK                                                                   0x10000000L
3120 #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK                                                                   0x20000000L
3121 #define SQ_VOP_SDWA_SDST_ENC__S1_MASK                                                                         0x80000000L
3122 //SQ_LB_CTR_CTRL
3123 #define SQ_LB_CTR_CTRL__START__SHIFT                                                                          0x0
3124 #define SQ_LB_CTR_CTRL__LOAD__SHIFT                                                                           0x1
3125 #define SQ_LB_CTR_CTRL__CLEAR__SHIFT                                                                          0x2
3126 #define SQ_LB_CTR_CTRL__START_MASK                                                                            0x00000001L
3127 #define SQ_LB_CTR_CTRL__LOAD_MASK                                                                             0x00000002L
3128 #define SQ_LB_CTR_CTRL__CLEAR_MASK                                                                            0x00000004L
3129 //SQ_LB_DATA0
3130 #define SQ_LB_DATA0__DATA__SHIFT                                                                              0x0
3131 #define SQ_LB_DATA0__DATA_MASK                                                                                0xFFFFFFFFL
3132 //SQ_LB_DATA1
3133 #define SQ_LB_DATA1__DATA__SHIFT                                                                              0x0
3134 #define SQ_LB_DATA1__DATA_MASK                                                                                0xFFFFFFFFL
3135 //SQ_LB_DATA2
3136 #define SQ_LB_DATA2__DATA__SHIFT                                                                              0x0
3137 #define SQ_LB_DATA2__DATA_MASK                                                                                0xFFFFFFFFL
3138 //SQ_LB_DATA3
3139 #define SQ_LB_DATA3__DATA__SHIFT                                                                              0x0
3140 #define SQ_LB_DATA3__DATA_MASK                                                                                0xFFFFFFFFL
3141 //SQ_LB_CTR_SEL
3142 #define SQ_LB_CTR_SEL__SEL0__SHIFT                                                                            0x0
3143 #define SQ_LB_CTR_SEL__SEL1__SHIFT                                                                            0x4
3144 #define SQ_LB_CTR_SEL__SEL2__SHIFT                                                                            0x8
3145 #define SQ_LB_CTR_SEL__SEL3__SHIFT                                                                            0xc
3146 #define SQ_LB_CTR_SEL__SEL0_MASK                                                                              0x0000000FL
3147 #define SQ_LB_CTR_SEL__SEL1_MASK                                                                              0x000000F0L
3148 #define SQ_LB_CTR_SEL__SEL2_MASK                                                                              0x00000F00L
3149 #define SQ_LB_CTR_SEL__SEL3_MASK                                                                              0x0000F000L
3150 //SQ_LB_CTR0_CU
3151 #define SQ_LB_CTR0_CU__SH0_MASK__SHIFT                                                                        0x0
3152 #define SQ_LB_CTR0_CU__SH1_MASK__SHIFT                                                                        0x10
3153 #define SQ_LB_CTR0_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3154 #define SQ_LB_CTR0_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3155 //SQ_LB_CTR1_CU
3156 #define SQ_LB_CTR1_CU__SH0_MASK__SHIFT                                                                        0x0
3157 #define SQ_LB_CTR1_CU__SH1_MASK__SHIFT                                                                        0x10
3158 #define SQ_LB_CTR1_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3159 #define SQ_LB_CTR1_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3160 //SQ_LB_CTR2_CU
3161 #define SQ_LB_CTR2_CU__SH0_MASK__SHIFT                                                                        0x0
3162 #define SQ_LB_CTR2_CU__SH1_MASK__SHIFT                                                                        0x10
3163 #define SQ_LB_CTR2_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3164 #define SQ_LB_CTR2_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3165 //SQ_LB_CTR3_CU
3166 #define SQ_LB_CTR3_CU__SH0_MASK__SHIFT                                                                        0x0
3167 #define SQ_LB_CTR3_CU__SH1_MASK__SHIFT                                                                        0x10
3168 #define SQ_LB_CTR3_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3169 #define SQ_LB_CTR3_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3170 //SQC_EDC_CNT
3171 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x0
3172 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0x2
3173 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0x4
3174 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0x6
3175 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x8
3176 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0xa
3177 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0xc
3178 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0xe
3179 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x10
3180 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0x12
3181 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0x14
3182 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0x16
3183 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x18
3184 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0x1a
3185 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0x1c
3186 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0x1e
3187 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x00000003L
3188 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x0000000CL
3189 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x00000030L
3190 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK                                                      0x000000C0L
3191 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x00000300L
3192 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x00000C00L
3193 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x00003000L
3194 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK                                                      0x0000C000L
3195 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x00030000L
3196 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x000C0000L
3197 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x00300000L
3198 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK                                                      0x00C00000L
3199 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x03000000L
3200 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x0C000000L
3201 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x30000000L
3202 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK                                                      0xC0000000L
3203 //SQ_EDC_SEC_CNT
3204 #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT                                                                        0x0
3205 #define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT                                                                       0x8
3206 #define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT                                                                       0x10
3207 #define SQ_EDC_SEC_CNT__LDS_SEC_MASK                                                                          0x000000FFL
3208 #define SQ_EDC_SEC_CNT__SGPR_SEC_MASK                                                                         0x0000FF00L
3209 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK                                                                         0x00FF0000L
3210 //SQ_EDC_DED_CNT
3211 #define SQ_EDC_DED_CNT__LDS_DED__SHIFT                                                                        0x0
3212 #define SQ_EDC_DED_CNT__SGPR_DED__SHIFT                                                                       0x8
3213 #define SQ_EDC_DED_CNT__VGPR_DED__SHIFT                                                                       0x10
3214 #define SQ_EDC_DED_CNT__LDS_DED_MASK                                                                          0x000000FFL
3215 #define SQ_EDC_DED_CNT__SGPR_DED_MASK                                                                         0x0000FF00L
3216 #define SQ_EDC_DED_CNT__VGPR_DED_MASK                                                                         0x00FF0000L
3217 //SQ_EDC_INFO
3218 #define SQ_EDC_INFO__WAVE_ID__SHIFT                                                                           0x0
3219 #define SQ_EDC_INFO__SIMD_ID__SHIFT                                                                           0x4
3220 #define SQ_EDC_INFO__SOURCE__SHIFT                                                                            0x6
3221 #define SQ_EDC_INFO__VM_ID__SHIFT                                                                             0x9
3222 #define SQ_EDC_INFO__WAVE_ID_MASK                                                                             0x0000000FL
3223 #define SQ_EDC_INFO__SIMD_ID_MASK                                                                             0x00000030L
3224 #define SQ_EDC_INFO__SOURCE_MASK                                                                              0x000001C0L
3225 #define SQ_EDC_INFO__VM_ID_MASK                                                                               0x00001E00L
3226 //SQ_EDC_CNT
3227 #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT                                                                    0x0
3228 #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT                                                                    0x2
3229 #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT                                                                    0x4
3230 #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT                                                                    0x6
3231 #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT                                                                     0x8
3232 #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT                                                                     0xa
3233 #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT                                                                    0xc
3234 #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT                                                                    0xe
3235 #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT                                                                    0x10
3236 #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT                                                                    0x12
3237 #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT                                                                    0x14
3238 #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT                                                                    0x16
3239 #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT                                                                    0x18
3240 #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT                                                                    0x1a
3241 #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK                                                                      0x00000003L
3242 #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK                                                                      0x0000000CL
3243 #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK                                                                      0x00000030L
3244 #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK                                                                      0x000000C0L
3245 #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK                                                                       0x00000300L
3246 #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK                                                                       0x00000C00L
3247 #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK                                                                      0x00003000L
3248 #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK                                                                      0x0000C000L
3249 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK                                                                      0x00030000L
3250 #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK                                                                      0x000C0000L
3251 #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK                                                                      0x00300000L
3252 #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK                                                                      0x00C00000L
3253 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK                                                                      0x03000000L
3254 #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK                                                                      0x0C000000L
3255 //SQ_EDC_FUE_CNTL
3256 #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT                                                               0x0
3257 #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT                                                         0x10
3258 #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK                                                                 0x0000FFFFL
3259 #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK                                                           0xFFFF0000L
3260 //SQ_THREAD_TRACE_WORD_CMN
3261 #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT                                                           0x0
3262 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT                                                           0x4
3263 #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK                                                             0x000FL
3264 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK                                                             0x0010L
3265 //SQ_THREAD_TRACE_WORD_EVENT
3266 #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT                                                         0x0
3267 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT                                                         0x4
3268 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT                                                              0x5
3269 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT                                                              0x6
3270 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT                                                         0xa
3271 #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK                                                           0x000FL
3272 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK                                                           0x0010L
3273 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK                                                                0x0020L
3274 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK                                                                0x01C0L
3275 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK                                                           0xFC00L
3276 //SQ_THREAD_TRACE_WORD_INST
3277 #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT                                                          0x0
3278 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT                                                          0x4
3279 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT                                                             0x5
3280 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT                                                             0x9
3281 #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT                                                           0xb
3282 #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK                                                            0x000FL
3283 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK                                                            0x0010L
3284 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK                                                               0x01E0L
3285 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK                                                               0x0600L
3286 #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK                                                             0xF800L
3287 //SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
3288 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT                                                0x0
3289 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT                                                0x4
3290 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT                                                   0x5
3291 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT                                                   0x9
3292 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT                                                0xf
3293 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT                                                     0x10
3294 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK                                                  0x0000000FL
3295 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK                                                  0x00000010L
3296 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK                                                     0x000001E0L
3297 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK                                                     0x00000600L
3298 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK                                                  0x00008000L
3299 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK                                                       0xFFFF0000L
3300 //SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
3301 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT                                          0x0
3302 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT                                          0x4
3303 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT                                               0x5
3304 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT                                               0x6
3305 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT                                             0xa
3306 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT                                             0xe
3307 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT                                             0x10
3308 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK                                            0x0000000FL
3309 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK                                            0x00000010L
3310 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK                                                 0x00000020L
3311 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK                                                 0x000003C0L
3312 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK                                               0x00003C00L
3313 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK                                               0x0000C000L
3314 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK                                               0xFFFF0000L
3315 //SQ_THREAD_TRACE_WORD_ISSUE
3316 #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT                                                         0x0
3317 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT                                                         0x4
3318 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT                                                            0x5
3319 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT                                                              0x8
3320 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT                                                              0xa
3321 #define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT                                                              0xc
3322 #define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT                                                              0xe
3323 #define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT                                                              0x10
3324 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT                                                              0x12
3325 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT                                                              0x14
3326 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT                                                              0x16
3327 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT                                                              0x18
3328 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT                                                              0x1a
3329 #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK                                                           0x0000000FL
3330 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK                                                           0x00000010L
3331 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK                                                              0x00000060L
3332 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK                                                                0x00000300L
3333 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK                                                                0x00000C00L
3334 #define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK                                                                0x00003000L
3335 #define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK                                                                0x0000C000L
3336 #define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK                                                                0x00030000L
3337 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK                                                                0x000C0000L
3338 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK                                                                0x00300000L
3339 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK                                                                0x00C00000L
3340 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK                                                                0x03000000L
3341 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK                                                                0x0C000000L
3342 //SQ_THREAD_TRACE_WORD_MISC
3343 #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT                                                          0x0
3344 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT                                                          0x4
3345 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT                                                               0xc
3346 #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT                                                     0xd
3347 #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK                                                            0x000FL
3348 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK                                                            0x0FF0L
3349 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK                                                                 0x1000L
3350 #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK                                                       0xE000L
3351 //SQ_THREAD_TRACE_WORD_PERF_1_OF_2
3352 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT                                                   0x0
3353 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT                                                   0x4
3354 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT                                                        0x5
3355 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT                                                        0x6
3356 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT                                                    0xa
3357 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT                                                        0xc
3358 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT                                                     0x19
3359 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK                                                     0x0000000FL
3360 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK                                                     0x00000010L
3361 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK                                                          0x00000020L
3362 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK                                                          0x000003C0L
3363 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK                                                      0x00000C00L
3364 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK                                                          0x01FFF000L
3365 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK                                                       0xFE000000L
3366 //SQ_THREAD_TRACE_WORD_REG_1_OF_2
3367 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT                                                    0x0
3368 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT                                                    0x4
3369 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT                                                       0x5
3370 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT                                                         0x7
3371 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT                                              0x9
3372 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT                                                      0xa
3373 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT                                                      0xe
3374 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT                                                        0xf
3375 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT                                                      0x10
3376 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK                                                      0x0000000FL
3377 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK                                                      0x00000010L
3378 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK                                                         0x00000060L
3379 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK                                                           0x00000180L
3380 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK                                                0x00000200L
3381 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK                                                        0x00001C00L
3382 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK                                                        0x00004000L
3383 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK                                                          0x00008000L
3384 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK                                                        0xFFFF0000L
3385 //SQ_THREAD_TRACE_WORD_REG_2_OF_2
3386 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT                                                          0x0
3387 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK                                                            0xFFFFFFFFL
3388 //SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
3389 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT                                                 0x0
3390 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT                                                 0x4
3391 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT                                                    0x5
3392 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT                                                      0x7
3393 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT                                                   0x9
3394 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT                                                    0x10
3395 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK                                                   0x0000000FL
3396 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK                                                   0x00000010L
3397 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK                                                      0x00000060L
3398 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK                                                        0x00000180L
3399 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK                                                     0x0000FE00L
3400 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK                                                      0xFFFF0000L
3401 //SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
3402 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT                                                    0x0
3403 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK                                                      0x0000FFFFL
3404 //SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
3405 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT                                              0x0
3406 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT                                                 0x10
3407 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK                                                0x0000000FL
3408 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK                                                   0xFFFF0000L
3409 //SQ_THREAD_TRACE_WORD_WAVE
3410 #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT                                                          0x0
3411 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT                                                          0x4
3412 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT                                                               0x5
3413 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT                                                               0x6
3414 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT                                                             0xa
3415 #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT                                                             0xe
3416 #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK                                                            0x000FL
3417 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK                                                            0x0010L
3418 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK                                                                 0x0020L
3419 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK                                                                 0x03C0L
3420 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK                                                               0x3C00L
3421 #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK                                                               0xC000L
3422 //SQ_THREAD_TRACE_WORD_WAVE_START
3423 #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT                                                    0x0
3424 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT                                                    0x4
3425 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT                                                         0x5
3426 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT                                                         0x6
3427 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT                                                       0xa
3428 #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT                                                       0xe
3429 #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT                                                    0x10
3430 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT                                        0x15
3431 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT                                                         0x16
3432 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT                                                         0x1d
3433 #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK                                                      0x0000000FL
3434 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK                                                      0x00000010L
3435 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK                                                           0x00000020L
3436 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK                                                           0x000003C0L
3437 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK                                                         0x00003C00L
3438 #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK                                                         0x0000C000L
3439 #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK                                                      0x001F0000L
3440 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK                                          0x00200000L
3441 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK                                                           0x1FC00000L
3442 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK                                                           0xE0000000L
3443 //SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
3444 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT                                                     0x0
3445 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK                                                       0x00FFFFFFL
3446 //SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
3447 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT                                             0x0
3448 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK                                               0xFFFFL
3449 //SQ_THREAD_TRACE_WORD_PERF_2_OF_2
3450 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT                                                     0x0
3451 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT                                                        0x6
3452 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT                                                        0x13
3453 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK                                                       0x0000003FL
3454 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK                                                          0x0007FFC0L
3455 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK                                                          0xFFF80000L
3456 //SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
3457 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT                                                 0x0
3458 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK                                                   0xFFFFFFFFL
3459 //SQ_WREXEC_EXEC_HI
3460 #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT                                                                     0x0
3461 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT                                                                  0x1a
3462 #define SQ_WREXEC_EXEC_HI__ATC__SHIFT                                                                         0x1b
3463 #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT                                                                       0x1c
3464 #define SQ_WREXEC_EXEC_HI__MSB__SHIFT                                                                         0x1f
3465 #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK                                                                       0x0000FFFFL
3466 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK                                                                    0x04000000L
3467 #define SQ_WREXEC_EXEC_HI__ATC_MASK                                                                           0x08000000L
3468 #define SQ_WREXEC_EXEC_HI__MTYPE_MASK                                                                         0x70000000L
3469 #define SQ_WREXEC_EXEC_HI__MSB_MASK                                                                           0x80000000L
3470 //SQ_WREXEC_EXEC_LO
3471 #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT                                                                     0x0
3472 #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK                                                                       0xFFFFFFFFL
3473 //SQ_BUF_RSRC_WORD0
3474 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT                                                                0x0
3475 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK                                                                  0xFFFFFFFFL
3476 //SQ_BUF_RSRC_WORD1
3477 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT                                                             0x0
3478 #define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT                                                                      0x10
3479 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT                                                               0x1e
3480 #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT                                                              0x1f
3481 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK                                                               0x0000FFFFL
3482 #define SQ_BUF_RSRC_WORD1__STRIDE_MASK                                                                        0x3FFF0000L
3483 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK                                                                 0x40000000L
3484 #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK                                                                0x80000000L
3485 //SQ_BUF_RSRC_WORD2
3486 #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT                                                                 0x0
3487 #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK                                                                   0xFFFFFFFFL
3488 //SQ_BUF_RSRC_WORD3
3489 #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT                                                                   0x0
3490 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT                                                                   0x3
3491 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT                                                                   0x6
3492 #define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT                                                                   0x9
3493 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT                                                                  0xc
3494 #define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT                                                                 0xf
3495 #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT                                                              0x13
3496 #define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT                                                                0x14
3497 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT                                                                0x15
3498 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT                                                              0x17
3499 #define SQ_BUF_RSRC_WORD3__NV__SHIFT                                                                          0x1b
3500 #define SQ_BUF_RSRC_WORD3__TYPE__SHIFT                                                                        0x1e
3501 #define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK                                                                     0x00000007L
3502 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK                                                                     0x00000038L
3503 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK                                                                     0x000001C0L
3504 #define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK                                                                     0x00000E00L
3505 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK                                                                    0x00007000L
3506 #define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK                                                                   0x00078000L
3507 #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK                                                                0x00080000L
3508 #define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK                                                                  0x00100000L
3509 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK                                                                  0x00600000L
3510 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK                                                                0x00800000L
3511 #define SQ_BUF_RSRC_WORD3__NV_MASK                                                                            0x08000000L
3512 #define SQ_BUF_RSRC_WORD3__TYPE_MASK                                                                          0xC0000000L
3513 //SQ_IMG_RSRC_WORD0
3514 #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT                                                                0x0
3515 #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK                                                                  0xFFFFFFFFL
3516 //SQ_IMG_RSRC_WORD1
3517 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT                                                             0x0
3518 #define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT                                                                     0x8
3519 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT                                                                 0x14
3520 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT                                                                  0x1a
3521 #define SQ_IMG_RSRC_WORD1__NV__SHIFT                                                                          0x1e
3522 #define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT                                                                 0x1f
3523 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK                                                               0x000000FFL
3524 #define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK                                                                       0x000FFF00L
3525 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK                                                                   0x03F00000L
3526 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK                                                                    0x3C000000L
3527 #define SQ_IMG_RSRC_WORD1__NV_MASK                                                                            0x40000000L
3528 #define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK                                                                   0x80000000L
3529 //SQ_IMG_RSRC_WORD2
3530 #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT                                                                       0x0
3531 #define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT                                                                      0xe
3532 #define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT                                                                    0x1c
3533 #define SQ_IMG_RSRC_WORD2__WIDTH_MASK                                                                         0x00003FFFL
3534 #define SQ_IMG_RSRC_WORD2__HEIGHT_MASK                                                                        0x0FFFC000L
3535 #define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK                                                                      0x70000000L
3536 //SQ_IMG_RSRC_WORD3
3537 #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT                                                                   0x0
3538 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT                                                                   0x3
3539 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT                                                                   0x6
3540 #define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT                                                                   0x9
3541 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT                                                                  0xc
3542 #define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT                                                                  0x10
3543 #define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT                                                                     0x14
3544 #define SQ_IMG_RSRC_WORD3__TYPE__SHIFT                                                                        0x1c
3545 #define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK                                                                     0x00000007L
3546 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK                                                                     0x00000038L
3547 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK                                                                     0x000001C0L
3548 #define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK                                                                     0x00000E00L
3549 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK                                                                    0x0000F000L
3550 #define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK                                                                    0x000F0000L
3551 #define SQ_IMG_RSRC_WORD3__SW_MODE_MASK                                                                       0x01F00000L
3552 #define SQ_IMG_RSRC_WORD3__TYPE_MASK                                                                          0xF0000000L
3553 //SQ_IMG_RSRC_WORD4
3554 #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT                                                                       0x0
3555 #define SQ_IMG_RSRC_WORD4__PITCH__SHIFT                                                                       0xd
3556 #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT                                                                  0x1d
3557 #define SQ_IMG_RSRC_WORD4__DEPTH_MASK                                                                         0x00001FFFL
3558 #define SQ_IMG_RSRC_WORD4__PITCH_MASK                                                                         0x1FFFE000L
3559 #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK                                                                    0xE0000000L
3560 //SQ_IMG_RSRC_WORD5
3561 #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT                                                                  0x0
3562 #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT                                                                 0xd
3563 #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT                                                           0x11
3564 #define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT                                                                 0x19
3565 #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT                                                           0x1a
3566 #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT                                                             0x1b
3567 #define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT                                                                     0x1c
3568 #define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK                                                                    0x00001FFFL
3569 #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK                                                                   0x0001E000L
3570 #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK                                                             0x01FE0000L
3571 #define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK                                                                   0x02000000L
3572 #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK                                                             0x04000000L
3573 #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK                                                               0x08000000L
3574 #define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK                                                                       0xF0000000L
3575 //SQ_IMG_RSRC_WORD6
3576 #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT                                                                0x0
3577 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT                                                             0xc
3578 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT                                                              0x14
3579 #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT                                                              0x15
3580 #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT                                                             0x16
3581 #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT                                                             0x17
3582 #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT                                                             0x18
3583 #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT                                                             0x1c
3584 #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK                                                                  0x00000FFFL
3585 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK                                                               0x000FF000L
3586 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK                                                                0x00100000L
3587 #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK                                                                0x00200000L
3588 #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK                                                               0x00400000L
3589 #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK                                                               0x00800000L
3590 #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK                                                               0x0F000000L
3591 #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK                                                               0xF0000000L
3592 //SQ_IMG_RSRC_WORD7
3593 #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT                                                           0x0
3594 #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK                                                             0xFFFFFFFFL
3595 //SQ_IMG_SAMP_WORD0
3596 #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT                                                                     0x0
3597 #define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT                                                                     0x3
3598 #define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT                                                                     0x6
3599 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT                                                             0x9
3600 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT                                                          0xc
3601 #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT                                                          0xf
3602 #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT                                                             0x10
3603 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT                                                              0x13
3604 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT                                                               0x14
3605 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT                                                                  0x15
3606 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT                                                                 0x1b
3607 #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT                                                           0x1c
3608 #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT                                                                 0x1d
3609 #define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT                                                                 0x1f
3610 #define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK                                                                       0x00000007L
3611 #define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK                                                                       0x00000038L
3612 #define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK                                                                       0x000001C0L
3613 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK                                                               0x00000E00L
3614 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK                                                            0x00007000L
3615 #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK                                                            0x00008000L
3616 #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK                                                               0x00070000L
3617 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK                                                                0x00080000L
3618 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK                                                                 0x00100000L
3619 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK                                                                    0x07E00000L
3620 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK                                                                   0x08000000L
3621 #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK                                                             0x10000000L
3622 #define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK                                                                   0x60000000L
3623 #define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK                                                                   0x80000000L
3624 //SQ_IMG_SAMP_WORD1
3625 #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT                                                                     0x0
3626 #define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT                                                                     0xc
3627 #define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT                                                                    0x18
3628 #define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT                                                                      0x1c
3629 #define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK                                                                       0x00000FFFL
3630 #define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK                                                                       0x00FFF000L
3631 #define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK                                                                      0x0F000000L
3632 #define SQ_IMG_SAMP_WORD1__PERF_Z_MASK                                                                        0xF0000000L
3633 //SQ_IMG_SAMP_WORD2
3634 #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT                                                                    0x0
3635 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT                                                                0xe
3636 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT                                                               0x14
3637 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT                                                               0x16
3638 #define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT                                                                    0x18
3639 #define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT                                                                  0x1a
3640 #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT                                                          0x1c
3641 #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT                                                              0x1d
3642 #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT                                                             0x1e
3643 #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT                                                              0x1f
3644 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK                                                                      0x00003FFFL
3645 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK                                                                  0x000FC000L
3646 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK                                                                 0x00300000L
3647 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK                                                                 0x00C00000L
3648 #define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK                                                                      0x03000000L
3649 #define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK                                                                    0x0C000000L
3650 #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK                                                            0x10000000L
3651 #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK                                                                0x20000000L
3652 #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK                                                               0x40000000L
3653 #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK                                                                0x80000000L
3654 //SQ_IMG_SAMP_WORD3
3655 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT                                                            0x0
3656 #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT                                                                0xc
3657 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT                                                           0x1e
3658 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK                                                              0x00000FFFL
3659 #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK                                                                  0x00001000L
3660 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK                                                             0xC0000000L
3661 //SQ_FLAT_SCRATCH_WORD0
3662 #define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT                                                                    0x0
3663 #define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK                                                                      0x0007FFFFL
3664 //SQ_FLAT_SCRATCH_WORD1
3665 #define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT                                                                  0x0
3666 #define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK                                                                    0x00FFFFFFL
3667 //SQ_M0_GPR_IDX_WORD
3668 #define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT                                                                      0x0
3669 #define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT                                                                  0xc
3670 #define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT                                                                  0xd
3671 #define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT                                                                  0xe
3672 #define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT                                                                   0xf
3673 #define SQ_M0_GPR_IDX_WORD__INDEX_MASK                                                                        0x000000FFL
3674 #define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK                                                                    0x00001000L
3675 #define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK                                                                    0x00002000L
3676 #define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK                                                                    0x00004000L
3677 #define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK                                                                     0x00008000L
3678 //SQC_ICACHE_UTCL1_CNTL1
3679 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
3680 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
3681 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
3682 #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT                                                              0x3
3683 #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
3684 #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT                                                               0x7
3685 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
3686 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
3687 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT                                                    0x13
3688 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT                                                0x17
3689 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT                                                  0x18
3690 #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
3691 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
3692 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
3693 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
3694 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
3695 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
3696 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
3697 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
3698 #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK                                                                0x00000018L
3699 #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
3700 #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
3701 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
3702 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
3703 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK                                                      0x00780000L
3704 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK                                                  0x00800000L
3705 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK                                                    0x01000000L
3706 #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
3707 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
3708 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
3709 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
3710 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
3711 //SQC_ICACHE_UTCL1_CNTL2
3712 #define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT                                                                  0x0
3713 #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
3714 #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
3715 #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT                                                             0xa
3716 #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                0xb
3717 #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
3718 #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
3719 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
3720 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
3721 #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
3722 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
3723 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
3724 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
3725 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
3726 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
3727 #define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK                                                                    0x000000FFL
3728 #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
3729 #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
3730 #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK                                                               0x00000400L
3731 #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
3732 #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
3733 #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
3734 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
3735 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
3736 #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
3737 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
3738 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
3739 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
3740 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
3741 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
3742 //SQC_DCACHE_UTCL1_CNTL1
3743 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
3744 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
3745 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
3746 #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT                                                              0x3
3747 #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
3748 #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT                                                               0x7
3749 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
3750 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
3751 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT                                                    0x13
3752 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT                                                0x17
3753 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT                                                  0x18
3754 #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
3755 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
3756 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
3757 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
3758 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
3759 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
3760 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
3761 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
3762 #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK                                                                0x00000018L
3763 #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
3764 #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
3765 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
3766 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
3767 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK                                                      0x00780000L
3768 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK                                                  0x00800000L
3769 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK                                                    0x01000000L
3770 #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
3771 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
3772 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
3773 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
3774 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
3775 //SQC_DCACHE_UTCL1_CNTL2
3776 #define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT                                                                  0x0
3777 #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
3778 #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
3779 #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT                                                             0xa
3780 #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                0xb
3781 #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
3782 #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
3783 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
3784 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
3785 #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
3786 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
3787 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
3788 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
3789 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
3790 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
3791 #define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK                                                                    0x000000FFL
3792 #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
3793 #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
3794 #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK                                                               0x00000400L
3795 #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
3796 #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
3797 #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
3798 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
3799 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
3800 #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
3801 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
3802 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
3803 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
3804 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
3805 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
3806 //SQC_ICACHE_UTCL1_STATUS
3807 #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
3808 #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
3809 #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                          0x2
3810 #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
3811 #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
3812 #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK                                                            0x00000004L
3813 //SQC_DCACHE_UTCL1_STATUS
3814 #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
3815 #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
3816 #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                          0x2
3817 #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
3818 #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
3819 #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK                                                            0x00000004L
3820 
3821 
3822 // addressBlock: gc_shsdec
3823 //SX_DEBUG_BUSY
3824 #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT                                                              0x0
3825 #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT                                                              0x1
3826 #define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT                                                                      0x2
3827 #define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT                                                                   0x3
3828 #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT                                                              0x4
3829 #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT                                                              0x5
3830 #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT                                                              0x6
3831 #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT                                                              0x7
3832 #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT                                                              0x8
3833 #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT                                                              0x9
3834 #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT                                                              0xa
3835 #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT                                                              0xb
3836 #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT                                                              0xc
3837 #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT                                                              0xd
3838 #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT                                                              0xe
3839 #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT                                                              0xf
3840 #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT                                                              0x10
3841 #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT                                                              0x11
3842 #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT                                                              0x12
3843 #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT                                                              0x13
3844 #define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT                                                                 0x14
3845 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT                                                                 0x15
3846 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT                                                                 0x16
3847 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT                                                                 0x17
3848 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT                                                                 0x18
3849 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT                                                                 0x19
3850 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT                                                                 0x1a
3851 #define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT                                                                     0x1b
3852 #define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT                                                                    0x1c
3853 #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT                                                                    0x1d
3854 #define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT                                                                   0x1e
3855 #define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT                                                                  0x1f
3856 #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK                                                                0x00000001L
3857 #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK                                                                0x00000002L
3858 #define SX_DEBUG_BUSY__PA_SX_BUSY_MASK                                                                        0x00000004L
3859 #define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK                                                                     0x00000008L
3860 #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK                                                                0x00000010L
3861 #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK                                                                0x00000020L
3862 #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK                                                                0x00000040L
3863 #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK                                                                0x00000080L
3864 #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK                                                                0x00000100L
3865 #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK                                                                0x00000200L
3866 #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK                                                                0x00000400L
3867 #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK                                                                0x00000800L
3868 #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK                                                                0x00001000L
3869 #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK                                                                0x00002000L
3870 #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK                                                                0x00004000L
3871 #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK                                                                0x00008000L
3872 #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK                                                                0x00010000L
3873 #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK                                                                0x00020000L
3874 #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK                                                                0x00040000L
3875 #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK                                                                0x00080000L
3876 #define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK                                                                   0x00100000L
3877 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK                                                                   0x00200000L
3878 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK                                                                   0x00400000L
3879 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK                                                                   0x00800000L
3880 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK                                                                   0x01000000L
3881 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK                                                                   0x02000000L
3882 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK                                                                   0x04000000L
3883 #define SX_DEBUG_BUSY__PCCMD_VALID_MASK                                                                       0x08000000L
3884 #define SX_DEBUG_BUSY__VDATA1_VALID_MASK                                                                      0x10000000L
3885 #define SX_DEBUG_BUSY__VDATA0_VALID_MASK                                                                      0x20000000L
3886 #define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK                                                                     0x40000000L
3887 #define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK                                                                    0x80000000L
3888 //SX_DEBUG_BUSY_2
3889 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT                                                     0x0
3890 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT                                                     0x1
3891 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT                                                     0x2
3892 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT                                                     0x3
3893 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT                                                     0x4
3894 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT                                                     0x5
3895 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT                                                     0x6
3896 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT                                                     0x7
3897 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT                                                     0x8
3898 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT                                                     0x9
3899 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT                                                     0xa
3900 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT                                                     0xb
3901 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT                                                     0xc
3902 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT                                                     0xd
3903 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT                                                     0xe
3904 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT                                                     0xf
3905 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT                                                     0x10
3906 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT                                                     0x11
3907 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT                                                     0x12
3908 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT                                                     0x13
3909 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT                                                     0x14
3910 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT                                                     0x15
3911 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT                                                     0x16
3912 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT                                                     0x17
3913 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT                                                     0x18
3914 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT                                                     0x19
3915 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT                                                     0x1a
3916 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT                                                     0x1b
3917 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT                                                     0x1c
3918 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT                                                     0x1d
3919 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT                                                     0x1e
3920 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT                                                     0x1f
3921 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK                                                       0x00000001L
3922 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK                                                       0x00000002L
3923 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK                                                       0x00000004L
3924 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK                                                       0x00000008L
3925 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK                                                       0x00000010L
3926 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK                                                       0x00000020L
3927 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK                                                       0x00000040L
3928 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY_MASK                                                       0x00000080L
3929 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY_MASK                                                       0x00000100L
3930 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY_MASK                                                       0x00000200L
3931 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY_MASK                                                       0x00000400L
3932 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY_MASK                                                       0x00000800L
3933 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY_MASK                                                       0x00001000L
3934 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY_MASK                                                       0x00002000L
3935 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY_MASK                                                       0x00004000L
3936 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY_MASK                                                       0x00008000L
3937 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY_MASK                                                       0x00010000L
3938 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY_MASK                                                       0x00020000L
3939 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY_MASK                                                       0x00040000L
3940 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY_MASK                                                       0x00080000L
3941 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY_MASK                                                       0x00100000L
3942 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY_MASK                                                       0x00200000L
3943 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY_MASK                                                       0x00400000L
3944 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY_MASK                                                       0x00800000L
3945 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY_MASK                                                       0x01000000L
3946 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY_MASK                                                       0x02000000L
3947 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY_MASK                                                       0x04000000L
3948 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY_MASK                                                       0x08000000L
3949 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY_MASK                                                       0x10000000L
3950 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY_MASK                                                       0x20000000L
3951 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY_MASK                                                       0x40000000L
3952 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY_MASK                                                       0x80000000L
3953 //SX_DEBUG_BUSY_3
3954 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT                                                     0x0
3955 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT                                                     0x1
3956 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT                                                     0x2
3957 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT                                                     0x3
3958 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT                                                     0x4
3959 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT                                                     0x5
3960 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT                                                     0x6
3961 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT                                                     0x7
3962 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT                                                     0x8
3963 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT                                                     0x9
3964 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT                                                     0xa
3965 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT                                                     0xb
3966 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT                                                     0xc
3967 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT                                                     0xd
3968 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT                                                     0xe
3969 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT                                                     0xf
3970 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT                                                     0x10
3971 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT                                                     0x11
3972 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT                                                     0x12
3973 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT                                                     0x13
3974 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT                                                     0x14
3975 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT                                                     0x15
3976 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT                                                     0x16
3977 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT                                                     0x17
3978 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT                                                     0x18
3979 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT                                                     0x19
3980 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT                                                     0x1a
3981 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT                                                     0x1b
3982 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT                                                     0x1c
3983 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT                                                     0x1d
3984 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT                                                     0x1e
3985 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT                                                     0x1f
3986 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK                                                       0x00000001L
3987 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK                                                       0x00000002L
3988 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK                                                       0x00000004L
3989 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK                                                       0x00000008L
3990 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK                                                       0x00000010L
3991 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK                                                       0x00000020L
3992 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK                                                       0x00000040L
3993 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY_MASK                                                       0x00000080L
3994 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY_MASK                                                       0x00000100L
3995 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY_MASK                                                       0x00000200L
3996 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY_MASK                                                       0x00000400L
3997 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY_MASK                                                       0x00000800L
3998 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY_MASK                                                       0x00001000L
3999 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY_MASK                                                       0x00002000L
4000 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY_MASK                                                       0x00004000L
4001 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY_MASK                                                       0x00008000L
4002 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY_MASK                                                       0x00010000L
4003 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY_MASK                                                       0x00020000L
4004 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY_MASK                                                       0x00040000L
4005 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY_MASK                                                       0x00080000L
4006 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY_MASK                                                       0x00100000L
4007 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY_MASK                                                       0x00200000L
4008 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY_MASK                                                       0x00400000L
4009 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY_MASK                                                       0x00800000L
4010 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY_MASK                                                       0x01000000L
4011 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY_MASK                                                       0x02000000L
4012 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY_MASK                                                       0x04000000L
4013 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY_MASK                                                       0x08000000L
4014 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY_MASK                                                       0x10000000L
4015 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY_MASK                                                       0x20000000L
4016 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY_MASK                                                       0x40000000L
4017 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY_MASK                                                       0x80000000L
4018 //SX_DEBUG_BUSY_4
4019 #define SX_DEBUG_BUSY_4__COL_SCBD_BUSY__SHIFT                                                                 0x0
4020 #define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0__SHIFT                                                          0x1
4021 #define SX_DEBUG_BUSY_4__COL_REQ3_IDLE__SHIFT                                                                 0x2
4022 #define SX_DEBUG_BUSY_4__COL_REQ3_BUSY__SHIFT                                                                 0x3
4023 #define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY__SHIFT                                                          0x4
4024 #define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0__SHIFT                                                          0x5
4025 #define SX_DEBUG_BUSY_4__COL_REQ2_IDLE__SHIFT                                                                 0x6
4026 #define SX_DEBUG_BUSY_4__COL_REQ2_BUSY__SHIFT                                                                 0x7
4027 #define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY__SHIFT                                                          0x8
4028 #define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0__SHIFT                                                          0x9
4029 #define SX_DEBUG_BUSY_4__COL_REQ1_IDLE__SHIFT                                                                 0xa
4030 #define SX_DEBUG_BUSY_4__COL_REQ1_BUSY__SHIFT                                                                 0xb
4031 #define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY__SHIFT                                                          0xc
4032 #define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0__SHIFT                                                          0xd
4033 #define SX_DEBUG_BUSY_4__COL_REQ0_IDLE__SHIFT                                                                 0xe
4034 #define SX_DEBUG_BUSY_4__COL_REQ0_BUSY__SHIFT                                                                 0xf
4035 #define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY__SHIFT                                                          0x10
4036 #define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY__SHIFT                                                       0x11
4037 #define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY__SHIFT                                                           0x12
4038 #define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE__SHIFT                                                           0x13
4039 #define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY__SHIFT                                                       0x14
4040 #define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY__SHIFT                                                           0x15
4041 #define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE__SHIFT                                                           0x16
4042 #define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY__SHIFT                                                       0x17
4043 #define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY__SHIFT                                                           0x18
4044 #define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE__SHIFT                                                           0x19
4045 #define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY__SHIFT                                                       0x1a
4046 #define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY__SHIFT                                                           0x1b
4047 #define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE__SHIFT                                                           0x1c
4048 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1__SHIFT                                                       0x1d
4049 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT                                                   0x1e
4050 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2__SHIFT                                                       0x1f
4051 #define SX_DEBUG_BUSY_4__COL_SCBD_BUSY_MASK                                                                   0x00000001L
4052 #define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0_MASK                                                            0x00000002L
4053 #define SX_DEBUG_BUSY_4__COL_REQ3_IDLE_MASK                                                                   0x00000004L
4054 #define SX_DEBUG_BUSY_4__COL_REQ3_BUSY_MASK                                                                   0x00000008L
4055 #define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY_MASK                                                            0x00000010L
4056 #define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0_MASK                                                            0x00000020L
4057 #define SX_DEBUG_BUSY_4__COL_REQ2_IDLE_MASK                                                                   0x00000040L
4058 #define SX_DEBUG_BUSY_4__COL_REQ2_BUSY_MASK                                                                   0x00000080L
4059 #define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY_MASK                                                            0x00000100L
4060 #define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0_MASK                                                            0x00000200L
4061 #define SX_DEBUG_BUSY_4__COL_REQ1_IDLE_MASK                                                                   0x00000400L
4062 #define SX_DEBUG_BUSY_4__COL_REQ1_BUSY_MASK                                                                   0x00000800L
4063 #define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY_MASK                                                            0x00001000L
4064 #define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0_MASK                                                            0x00002000L
4065 #define SX_DEBUG_BUSY_4__COL_REQ0_IDLE_MASK                                                                   0x00004000L
4066 #define SX_DEBUG_BUSY_4__COL_REQ0_BUSY_MASK                                                                   0x00008000L
4067 #define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY_MASK                                                            0x00010000L
4068 #define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY_MASK                                                         0x00020000L
4069 #define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY_MASK                                                             0x00040000L
4070 #define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE_MASK                                                             0x00080000L
4071 #define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY_MASK                                                         0x00100000L
4072 #define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY_MASK                                                             0x00200000L
4073 #define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE_MASK                                                             0x00400000L
4074 #define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY_MASK                                                         0x00800000L
4075 #define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY_MASK                                                             0x01000000L
4076 #define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE_MASK                                                             0x02000000L
4077 #define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY_MASK                                                         0x04000000L
4078 #define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY_MASK                                                             0x08000000L
4079 #define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE_MASK                                                             0x10000000L
4080 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_MASK                                                         0x20000000L
4081 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK                                                     0x40000000L
4082 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2_MASK                                                         0x80000000L
4083 //SX_DEBUG_BUSY_5
4084 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3__SHIFT                                                       0x0
4085 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4__SHIFT                                                       0x1
4086 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5__SHIFT                                                       0x2
4087 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O__SHIFT                                                       0x3
4088 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1__SHIFT                                                       0x4
4089 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT                                                   0x5
4090 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2__SHIFT                                                       0x6
4091 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3__SHIFT                                                       0x7
4092 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4__SHIFT                                                       0x8
4093 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5__SHIFT                                                       0x9
4094 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O__SHIFT                                                       0xa
4095 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1__SHIFT                                                       0xb
4096 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT                                                   0xc
4097 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2__SHIFT                                                       0xd
4098 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3__SHIFT                                                       0xe
4099 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4__SHIFT                                                       0xf
4100 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5__SHIFT                                                       0x10
4101 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O__SHIFT                                                       0x11
4102 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1__SHIFT                                                       0x12
4103 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT                                                   0x13
4104 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2__SHIFT                                                       0x14
4105 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3__SHIFT                                                       0x15
4106 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4__SHIFT                                                       0x16
4107 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5__SHIFT                                                       0x17
4108 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O__SHIFT                                                       0x18
4109 #define SX_DEBUG_BUSY_5__RESERVED__SHIFT                                                                      0x19
4110 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3_MASK                                                         0x00000001L
4111 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4_MASK                                                         0x00000002L
4112 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5_MASK                                                         0x00000004L
4113 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O_MASK                                                         0x00000008L
4114 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_MASK                                                         0x00000010L
4115 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK                                                     0x00000020L
4116 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2_MASK                                                         0x00000040L
4117 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3_MASK                                                         0x00000080L
4118 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4_MASK                                                         0x00000100L
4119 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5_MASK                                                         0x00000200L
4120 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O_MASK                                                         0x00000400L
4121 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_MASK                                                         0x00000800L
4122 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK                                                     0x00001000L
4123 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2_MASK                                                         0x00002000L
4124 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3_MASK                                                         0x00004000L
4125 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4_MASK                                                         0x00008000L
4126 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5_MASK                                                         0x00010000L
4127 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O_MASK                                                         0x00020000L
4128 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_MASK                                                         0x00040000L
4129 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK                                                     0x00080000L
4130 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2_MASK                                                         0x00100000L
4131 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3_MASK                                                         0x00200000L
4132 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4_MASK                                                         0x00400000L
4133 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5_MASK                                                         0x00800000L
4134 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O_MASK                                                         0x01000000L
4135 #define SX_DEBUG_BUSY_5__RESERVED_MASK                                                                        0xFE000000L
4136 //SX_DEBUG_1
4137 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT                                                                  0x0
4138 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT                                                      0x8
4139 #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT                                                           0x9
4140 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT                                                    0xa
4141 #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT                                                              0xb
4142 #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT                                                            0xc
4143 #define SX_DEBUG_1__PC_CFG__SHIFT                                                                             0xd
4144 #define SX_DEBUG_1__DEBUG_DATA__SHIFT                                                                         0xe
4145 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK                                                                    0x0000007FL
4146 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK                                                        0x00000100L
4147 #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK                                                             0x00000200L
4148 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK                                                      0x00000400L
4149 #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK                                                                0x00000800L
4150 #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK                                                              0x00001000L
4151 #define SX_DEBUG_1__PC_CFG_MASK                                                                               0x00002000L
4152 #define SX_DEBUG_1__DEBUG_DATA_MASK                                                                           0xFFFFC000L
4153 //SPI_PS_MAX_WAVE_ID
4154 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
4155 #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT                                                      0x10
4156 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
4157 #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK                                                        0x03FF0000L
4158 //SPI_START_PHASE
4159 #define SPI_START_PHASE__VGPR_START_PHASE__SHIFT                                                              0x0
4160 #define SPI_START_PHASE__SGPR_START_PHASE__SHIFT                                                              0x2
4161 #define SPI_START_PHASE__WAVE_START_PHASE__SHIFT                                                              0x4
4162 #define SPI_START_PHASE__VGPR_START_PHASE_MASK                                                                0x00000003L
4163 #define SPI_START_PHASE__SGPR_START_PHASE_MASK                                                                0x0000000CL
4164 #define SPI_START_PHASE__WAVE_START_PHASE_MASK                                                                0x00000030L
4165 //SPI_GFX_CNTL
4166 #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT                                                                     0x0
4167 #define SPI_GFX_CNTL__RESET_COUNTS_MASK                                                                       0x00000001L
4168 //SPI_DEBUG_READ
4169 #define SPI_DEBUG_READ__DATA__SHIFT                                                                           0x0
4170 #define SPI_DEBUG_READ__DATA_MASK                                                                             0xFFFFFFFFL
4171 //SPI_DSM_CNTL
4172 #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT                                                    0x0
4173 #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                   0x2
4174 #define SPI_DSM_CNTL__UNUSED__SHIFT                                                                           0x3
4175 #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK                                                      0x00000003L
4176 #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK                                                     0x00000004L
4177 #define SPI_DSM_CNTL__UNUSED_MASK                                                                             0xFFFFFFF8L
4178 //SPI_DSM_CNTL2
4179 #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT                                                  0x0
4180 #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT                                                  0x2
4181 #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT                                                         0x4
4182 #define SPI_DSM_CNTL2__UNUSED__SHIFT                                                                          0xa
4183 #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK                                                    0x00000003L
4184 #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK                                                    0x00000004L
4185 #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK                                                           0x000003F0L
4186 #define SPI_DSM_CNTL2__UNUSED_MASK                                                                            0xFFFFFC00L
4187 //SPI_EDC_CNT
4188 #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT                                                              0x0
4189 #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK                                                                0x00000003L
4190 //SPI_DEBUG_BUSY
4191 #define SPI_DEBUG_BUSY__LS_BUSY__SHIFT                                                                        0x0
4192 #define SPI_DEBUG_BUSY__HS_BUSY__SHIFT                                                                        0x1
4193 #define SPI_DEBUG_BUSY__ES_BUSY__SHIFT                                                                        0x2
4194 #define SPI_DEBUG_BUSY__GS_BUSY__SHIFT                                                                        0x3
4195 #define SPI_DEBUG_BUSY__VS_BUSY__SHIFT                                                                        0x4
4196 #define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT                                                                       0x5
4197 #define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT                                                                       0x6
4198 #define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT                                                                       0x7
4199 #define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT                                                                       0x8
4200 #define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT                                                                       0x9
4201 #define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT                                                                       0xa
4202 #define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT                                                                       0xb
4203 #define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT                                                                       0xc
4204 #define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT                                                                       0xd
4205 #define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT                                                                       0xe
4206 #define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT                                                                       0xf
4207 #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT                                                               0x10
4208 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT                                                               0x11
4209 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT                                                               0x12
4210 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT                                                               0x13
4211 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT                                                                0x14
4212 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT                                                               0x15
4213 #define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT                                                                      0x16
4214 #define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT                                                                      0x17
4215 #define SPI_DEBUG_BUSY__LS_BUSY_MASK                                                                          0x00000001L
4216 #define SPI_DEBUG_BUSY__HS_BUSY_MASK                                                                          0x00000002L
4217 #define SPI_DEBUG_BUSY__ES_BUSY_MASK                                                                          0x00000004L
4218 #define SPI_DEBUG_BUSY__GS_BUSY_MASK                                                                          0x00000008L
4219 #define SPI_DEBUG_BUSY__VS_BUSY_MASK                                                                          0x00000010L
4220 #define SPI_DEBUG_BUSY__PS0_BUSY_MASK                                                                         0x00000020L
4221 #define SPI_DEBUG_BUSY__PS1_BUSY_MASK                                                                         0x00000040L
4222 #define SPI_DEBUG_BUSY__CSG_BUSY_MASK                                                                         0x00000080L
4223 #define SPI_DEBUG_BUSY__CS0_BUSY_MASK                                                                         0x00000100L
4224 #define SPI_DEBUG_BUSY__CS1_BUSY_MASK                                                                         0x00000200L
4225 #define SPI_DEBUG_BUSY__CS2_BUSY_MASK                                                                         0x00000400L
4226 #define SPI_DEBUG_BUSY__CS3_BUSY_MASK                                                                         0x00000800L
4227 #define SPI_DEBUG_BUSY__CS4_BUSY_MASK                                                                         0x00001000L
4228 #define SPI_DEBUG_BUSY__CS5_BUSY_MASK                                                                         0x00002000L
4229 #define SPI_DEBUG_BUSY__CS6_BUSY_MASK                                                                         0x00004000L
4230 #define SPI_DEBUG_BUSY__CS7_BUSY_MASK                                                                         0x00008000L
4231 #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK                                                                 0x00010000L
4232 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK                                                                 0x00020000L
4233 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK                                                                 0x00040000L
4234 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK                                                                 0x00080000L
4235 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK                                                                  0x00100000L
4236 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK                                                                 0x00200000L
4237 #define SPI_DEBUG_BUSY__GRBM_BUSY_MASK                                                                        0x00400000L
4238 #define SPI_DEBUG_BUSY__SPIS_BUSY_MASK                                                                        0x00800000L
4239 //SPI_CONFIG_PS_CU_EN
4240 #define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT                                                                    0x0
4241 #define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT                                                                0x1
4242 #define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT                                                                0x10
4243 #define SPI_CONFIG_PS_CU_EN__ENABLE_MASK                                                                      0x00000001L
4244 #define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK                                                                  0x0000FFFEL
4245 #define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK                                                                  0xFFFF0000L
4246 //SPI_WF_LIFETIME_CNTL
4247 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT                                                            0x0
4248 #define SPI_WF_LIFETIME_CNTL__EN__SHIFT                                                                       0x4
4249 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK                                                              0x0000000FL
4250 #define SPI_WF_LIFETIME_CNTL__EN_MASK                                                                         0x00000010L
4251 //SPI_WF_LIFETIME_LIMIT_0
4252 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT                                                               0x0
4253 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT                                                               0x1f
4254 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4255 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK                                                                 0x80000000L
4256 //SPI_WF_LIFETIME_LIMIT_1
4257 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT                                                               0x0
4258 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT                                                               0x1f
4259 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4260 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK                                                                 0x80000000L
4261 //SPI_WF_LIFETIME_LIMIT_2
4262 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT                                                               0x0
4263 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT                                                               0x1f
4264 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4265 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK                                                                 0x80000000L
4266 //SPI_WF_LIFETIME_LIMIT_3
4267 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT                                                               0x0
4268 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT                                                               0x1f
4269 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4270 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK                                                                 0x80000000L
4271 //SPI_WF_LIFETIME_LIMIT_4
4272 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT                                                               0x0
4273 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT                                                               0x1f
4274 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4275 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK                                                                 0x80000000L
4276 //SPI_WF_LIFETIME_LIMIT_5
4277 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT                                                               0x0
4278 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT                                                               0x1f
4279 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4280 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK                                                                 0x80000000L
4281 //SPI_WF_LIFETIME_LIMIT_6
4282 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT                                                               0x0
4283 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT                                                               0x1f
4284 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4285 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK                                                                 0x80000000L
4286 //SPI_WF_LIFETIME_LIMIT_7
4287 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT                                                               0x0
4288 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT                                                               0x1f
4289 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4290 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK                                                                 0x80000000L
4291 //SPI_WF_LIFETIME_LIMIT_8
4292 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT                                                               0x0
4293 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT                                                               0x1f
4294 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4295 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK                                                                 0x80000000L
4296 //SPI_WF_LIFETIME_LIMIT_9
4297 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT                                                               0x0
4298 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT                                                               0x1f
4299 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4300 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK                                                                 0x80000000L
4301 //SPI_WF_LIFETIME_STATUS_0
4302 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT                                                              0x0
4303 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT                                                             0x1f
4304 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK                                                                0x7FFFFFFFL
4305 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK                                                               0x80000000L
4306 //SPI_WF_LIFETIME_STATUS_1
4307 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT                                                              0x0
4308 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT                                                             0x1f
4309 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK                                                                0x7FFFFFFFL
4310 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK                                                               0x80000000L
4311 //SPI_WF_LIFETIME_STATUS_2
4312 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT                                                              0x0
4313 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT                                                             0x1f
4314 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK                                                                0x7FFFFFFFL
4315 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK                                                               0x80000000L
4316 //SPI_WF_LIFETIME_STATUS_3
4317 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT                                                              0x0
4318 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT                                                             0x1f
4319 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK                                                                0x7FFFFFFFL
4320 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK                                                               0x80000000L
4321 //SPI_WF_LIFETIME_STATUS_4
4322 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT                                                              0x0
4323 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT                                                             0x1f
4324 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK                                                                0x7FFFFFFFL
4325 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK                                                               0x80000000L
4326 //SPI_WF_LIFETIME_STATUS_5
4327 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT                                                              0x0
4328 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT                                                             0x1f
4329 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK                                                                0x7FFFFFFFL
4330 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK                                                               0x80000000L
4331 //SPI_WF_LIFETIME_STATUS_6
4332 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT                                                              0x0
4333 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT                                                             0x1f
4334 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK                                                                0x7FFFFFFFL
4335 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK                                                               0x80000000L
4336 //SPI_WF_LIFETIME_STATUS_7
4337 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT                                                              0x0
4338 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT                                                             0x1f
4339 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK                                                                0x7FFFFFFFL
4340 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK                                                               0x80000000L
4341 //SPI_WF_LIFETIME_STATUS_8
4342 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT                                                              0x0
4343 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT                                                             0x1f
4344 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK                                                                0x7FFFFFFFL
4345 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK                                                               0x80000000L
4346 //SPI_WF_LIFETIME_STATUS_9
4347 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT                                                              0x0
4348 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT                                                             0x1f
4349 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK                                                                0x7FFFFFFFL
4350 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK                                                               0x80000000L
4351 //SPI_WF_LIFETIME_STATUS_10
4352 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT                                                             0x0
4353 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT                                                            0x1f
4354 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK                                                               0x7FFFFFFFL
4355 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK                                                              0x80000000L
4356 //SPI_WF_LIFETIME_STATUS_11
4357 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT                                                             0x0
4358 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT                                                            0x1f
4359 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK                                                               0x7FFFFFFFL
4360 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK                                                              0x80000000L
4361 //SPI_WF_LIFETIME_STATUS_12
4362 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT                                                             0x0
4363 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT                                                            0x1f
4364 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK                                                               0x7FFFFFFFL
4365 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK                                                              0x80000000L
4366 //SPI_WF_LIFETIME_STATUS_13
4367 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT                                                             0x0
4368 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT                                                            0x1f
4369 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK                                                               0x7FFFFFFFL
4370 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK                                                              0x80000000L
4371 //SPI_WF_LIFETIME_STATUS_14
4372 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT                                                             0x0
4373 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT                                                            0x1f
4374 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK                                                               0x7FFFFFFFL
4375 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK                                                              0x80000000L
4376 //SPI_WF_LIFETIME_STATUS_15
4377 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT                                                             0x0
4378 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT                                                            0x1f
4379 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK                                                               0x7FFFFFFFL
4380 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK                                                              0x80000000L
4381 //SPI_WF_LIFETIME_STATUS_16
4382 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT                                                             0x0
4383 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT                                                            0x1f
4384 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK                                                               0x7FFFFFFFL
4385 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK                                                              0x80000000L
4386 //SPI_WF_LIFETIME_STATUS_17
4387 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT                                                             0x0
4388 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT                                                            0x1f
4389 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK                                                               0x7FFFFFFFL
4390 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK                                                              0x80000000L
4391 //SPI_WF_LIFETIME_STATUS_18
4392 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT                                                             0x0
4393 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT                                                            0x1f
4394 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK                                                               0x7FFFFFFFL
4395 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK                                                              0x80000000L
4396 //SPI_WF_LIFETIME_STATUS_19
4397 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT                                                             0x0
4398 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT                                                            0x1f
4399 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK                                                               0x7FFFFFFFL
4400 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK                                                              0x80000000L
4401 //SPI_WF_LIFETIME_STATUS_20
4402 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT                                                             0x0
4403 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT                                                            0x1f
4404 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK                                                               0x7FFFFFFFL
4405 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK                                                              0x80000000L
4406 //SPI_WF_LIFETIME_DEBUG
4407 #define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT                                                             0x0
4408 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT                                                             0x1f
4409 #define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK                                                               0x7FFFFFFFL
4410 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK                                                               0x80000000L
4411 //SPI_LB_CTR_CTRL
4412 #define SPI_LB_CTR_CTRL__LOAD__SHIFT                                                                          0x0
4413 #define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT                                                                  0x1
4414 #define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT                                                                 0x3
4415 #define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT                                                                  0x4
4416 #define SPI_LB_CTR_CTRL__LOAD_MASK                                                                            0x00000001L
4417 #define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK                                                                    0x00000006L
4418 #define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK                                                                   0x00000008L
4419 #define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK                                                                    0x00000010L
4420 //SPI_LB_CU_MASK
4421 #define SPI_LB_CU_MASK__CU_MASK__SHIFT                                                                        0x0
4422 #define SPI_LB_CU_MASK__CU_MASK_MASK                                                                          0xFFFFL
4423 //SPI_LB_DATA_REG
4424 #define SPI_LB_DATA_REG__CNT_DATA__SHIFT                                                                      0x0
4425 #define SPI_LB_DATA_REG__CNT_DATA_MASK                                                                        0xFFFFFFFFL
4426 //SPI_PG_ENABLE_STATIC_CU_MASK
4427 #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT                                                          0x0
4428 #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK                                                            0xFFFFL
4429 //SPI_GDS_CREDITS
4430 #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT                                                               0x0
4431 #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT                                                                0x8
4432 #define SPI_GDS_CREDITS__UNUSED__SHIFT                                                                        0x10
4433 #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK                                                                 0x000000FFL
4434 #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK                                                                  0x0000FF00L
4435 #define SPI_GDS_CREDITS__UNUSED_MASK                                                                          0xFFFF0000L
4436 //SPI_SX_EXPORT_BUFFER_SIZES
4437 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT                                                  0x0
4438 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT                                               0x10
4439 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK                                                    0x0000FFFFL
4440 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK                                                 0xFFFF0000L
4441 //SPI_SX_SCOREBOARD_BUFFER_SIZES
4442 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT                                          0x0
4443 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT                                       0x10
4444 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK                                            0x0000FFFFL
4445 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK                                         0xFFFF0000L
4446 //SPI_CSQ_WF_ACTIVE_STATUS
4447 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT                                                               0x0
4448 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK                                                                 0xFFFFFFFFL
4449 //SPI_CSQ_WF_ACTIVE_COUNT_0
4450 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT                                                               0x0
4451 #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT                                                              0x10
4452 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK                                                                 0x000007FFL
4453 #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK                                                                0x07FF0000L
4454 //SPI_CSQ_WF_ACTIVE_COUNT_1
4455 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT                                                               0x0
4456 #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT                                                              0x10
4457 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK                                                                 0x000007FFL
4458 #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK                                                                0x07FF0000L
4459 //SPI_CSQ_WF_ACTIVE_COUNT_2
4460 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT                                                               0x0
4461 #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT                                                              0x10
4462 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK                                                                 0x000007FFL
4463 #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK                                                                0x07FF0000L
4464 //SPI_CSQ_WF_ACTIVE_COUNT_3
4465 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT                                                               0x0
4466 #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT                                                              0x10
4467 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK                                                                 0x000007FFL
4468 #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK                                                                0x07FF0000L
4469 //SPI_CSQ_WF_ACTIVE_COUNT_4
4470 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT                                                               0x0
4471 #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT                                                              0x10
4472 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK                                                                 0x000007FFL
4473 #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK                                                                0x07FF0000L
4474 //SPI_CSQ_WF_ACTIVE_COUNT_5
4475 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT                                                               0x0
4476 #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT                                                              0x10
4477 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK                                                                 0x000007FFL
4478 #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK                                                                0x07FF0000L
4479 //SPI_CSQ_WF_ACTIVE_COUNT_6
4480 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT                                                               0x0
4481 #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT                                                              0x10
4482 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK                                                                 0x000007FFL
4483 #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK                                                                0x07FF0000L
4484 //SPI_CSQ_WF_ACTIVE_COUNT_7
4485 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT                                                               0x0
4486 #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT                                                              0x10
4487 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK                                                                 0x000007FFL
4488 #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK                                                                0x07FF0000L
4489 //SPI_LB_DATA_WAVES
4490 #define SPI_LB_DATA_WAVES__COUNT0__SHIFT                                                                      0x0
4491 #define SPI_LB_DATA_WAVES__COUNT1__SHIFT                                                                      0x10
4492 #define SPI_LB_DATA_WAVES__COUNT0_MASK                                                                        0x0000FFFFL
4493 #define SPI_LB_DATA_WAVES__COUNT1_MASK                                                                        0xFFFF0000L
4494 //SPI_LB_DATA_PERCU_WAVE_HSGS
4495 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT                                                        0x0
4496 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT                                                        0x10
4497 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK                                                          0x0000FFFFL
4498 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK                                                          0xFFFF0000L
4499 //SPI_LB_DATA_PERCU_WAVE_VSPS
4500 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT                                                        0x0
4501 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT                                                        0x10
4502 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK                                                          0x0000FFFFL
4503 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK                                                          0xFFFF0000L
4504 //SPI_LB_DATA_PERCU_WAVE_CS
4505 #define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT                                                              0x0
4506 #define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK                                                                0xFFFFL
4507 //SPIS_DEBUG_READ
4508 #define SPIS_DEBUG_READ__DATA__SHIFT                                                                          0x0
4509 #define SPIS_DEBUG_READ__DATA_MASK                                                                            0xFFFFFFFFL
4510 //BCI_DEBUG_READ
4511 #define BCI_DEBUG_READ__DATA__SHIFT                                                                           0x0
4512 #define BCI_DEBUG_READ__DATA_MASK                                                                             0xFFFFFFL
4513 //SPI_P0_TRAP_SCREEN_PSBA_LO
4514 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
4515 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4516 //SPI_P0_TRAP_SCREEN_PSBA_HI
4517 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
4518 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
4519 //SPI_P0_TRAP_SCREEN_PSMA_LO
4520 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
4521 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4522 //SPI_P0_TRAP_SCREEN_PSMA_HI
4523 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
4524 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
4525 //SPI_P0_TRAP_SCREEN_GPR_MIN
4526 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
4527 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
4528 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
4529 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L
4530 //SPI_P1_TRAP_SCREEN_PSBA_LO
4531 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
4532 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4533 //SPI_P1_TRAP_SCREEN_PSBA_HI
4534 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
4535 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
4536 //SPI_P1_TRAP_SCREEN_PSMA_LO
4537 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
4538 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4539 //SPI_P1_TRAP_SCREEN_PSMA_HI
4540 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
4541 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
4542 //SPI_P1_TRAP_SCREEN_GPR_MIN
4543 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
4544 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
4545 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
4546 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L
4547 
4548 
4549 // addressBlock: gc_tpdec
4550 //TD_CNTL
4551 #define TD_CNTL__SYNC_PHASE_SH__SHIFT                                                                         0x0
4552 #define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT                                                                     0x4
4553 #define TD_CNTL__PAD_STALL_EN__SHIFT                                                                          0x8
4554 #define TD_CNTL__EXTEND_LDS_STALL__SHIFT                                                                      0x9
4555 #define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT                                                                0xb
4556 #define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT                                                               0xf
4557 #define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT                                                                    0x10
4558 #define TD_CNTL__LD_FLOAT_MODE__SHIFT                                                                         0x12
4559 #define TD_CNTL__GATHER4_DX9_MODE__SHIFT                                                                      0x13
4560 #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT                                                                0x14
4561 #define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT                                                                  0x15
4562 #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT                                                            0x17
4563 #define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT                                                        0x18
4564 #define TD_CNTL__SYNC_PHASE_SH_MASK                                                                           0x00000003L
4565 #define TD_CNTL__SYNC_PHASE_VC_SMX_MASK                                                                       0x00000030L
4566 #define TD_CNTL__PAD_STALL_EN_MASK                                                                            0x00000100L
4567 #define TD_CNTL__EXTEND_LDS_STALL_MASK                                                                        0x00000600L
4568 #define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK                                                                  0x00001800L
4569 #define TD_CNTL__PRECISION_COMPATIBILITY_MASK                                                                 0x00008000L
4570 #define TD_CNTL__GATHER4_FLOAT_MODE_MASK                                                                      0x00010000L
4571 #define TD_CNTL__LD_FLOAT_MODE_MASK                                                                           0x00040000L
4572 #define TD_CNTL__GATHER4_DX9_MODE_MASK                                                                        0x00080000L
4573 #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK                                                                  0x00100000L
4574 #define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK                                                                    0x00200000L
4575 #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK                                                              0x00800000L
4576 #define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK                                                          0x01000000L
4577 //TD_STATUS
4578 #define TD_STATUS__BUSY__SHIFT                                                                                0x1f
4579 #define TD_STATUS__BUSY_MASK                                                                                  0x80000000L
4580 //TD_DSM_CNTL
4581 #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT                                                  0x0
4582 #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT                                                 0x2
4583 #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT                                                  0x3
4584 #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT                                                 0x5
4585 #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                     0x6
4586 #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                                    0x8
4587 #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK                                                    0x00000003L
4588 #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK                                                   0x00000004L
4589 #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK                                                    0x00000018L
4590 #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK                                                   0x00000020L
4591 #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK                                                       0x000000C0L
4592 #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                      0x00000100L
4593 //TD_DSM_CNTL2
4594 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT                                                0x0
4595 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT                                                0x2
4596 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT                                                0x3
4597 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT                                                0x5
4598 #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                   0x6
4599 #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT                                                   0x8
4600 #define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT                                                                  0x1a
4601 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK                                                  0x00000003L
4602 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK                                                  0x00000004L
4603 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK                                                  0x00000018L
4604 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK                                                  0x00000020L
4605 #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK                                                     0x000000C0L
4606 #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK                                                     0x00000100L
4607 #define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK                                                                    0xFC000000L
4608 //TD_SCRATCH
4609 #define TD_SCRATCH__SCRATCH__SHIFT                                                                            0x0
4610 #define TD_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL
4611 //TA_CNTL
4612 #define TA_CNTL__FX_XNACK_CREDIT__SHIFT                                                                       0x0
4613 #define TA_CNTL__SQ_XNACK_CREDIT__SHIFT                                                                       0x9
4614 #define TA_CNTL__TC_DATA_CREDIT__SHIFT                                                                        0xd
4615 #define TA_CNTL__ALIGNER_CREDIT__SHIFT                                                                        0x10
4616 #define TA_CNTL__TD_FIFO_CREDIT__SHIFT                                                                        0x16
4617 #define TA_CNTL__FX_XNACK_CREDIT_MASK                                                                         0x0000007FL
4618 #define TA_CNTL__SQ_XNACK_CREDIT_MASK                                                                         0x00001E00L
4619 #define TA_CNTL__TC_DATA_CREDIT_MASK                                                                          0x0000E000L
4620 #define TA_CNTL__ALIGNER_CREDIT_MASK                                                                          0x001F0000L
4621 #define TA_CNTL__TD_FIFO_CREDIT_MASK                                                                          0xFFC00000L
4622 //TA_CNTL_AUX
4623 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT                                                                  0x0
4624 #define TA_CNTL_AUX__RESERVED__SHIFT                                                                          0x1
4625 #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT                                                                0x5
4626 #define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT                                                                   0x6
4627 #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT                                                        0x7
4628 #define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT                                                               0x9
4629 #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT                                                                 0xa
4630 #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT                                                              0xc
4631 #define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT                                                                  0xd
4632 #define TA_CNTL_AUX__ANISO_STEP__SHIFT                                                                        0xe
4633 #define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT                                                                     0xf
4634 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT                                                                 0x10
4635 #define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT                                                                   0x11
4636 #define TA_CNTL_AUX__ANISO_TAP__SHIFT                                                                         0x12
4637 #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT                                                                0x13
4638 #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT                                                      0x14
4639 #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT                                                 0x15
4640 #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT                                                          0x16
4641 #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT                                                 0x17
4642 #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT                                                  0x18
4643 #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT                                               0x19
4644 #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT                                                     0x1a
4645 #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT                                                         0x1b
4646 #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT                                                               0x1c
4647 #define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT                                                                   0x1d
4648 #define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT                                                                  0x1e
4649 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK                                                                    0x00000001L
4650 #define TA_CNTL_AUX__RESERVED_MASK                                                                            0x0000000EL
4651 #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK                                                                  0x00000020L
4652 #define TA_CNTL_AUX__GATHERH_DST_SEL_MASK                                                                     0x00000040L
4653 #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK                                                          0x00000080L
4654 #define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK                                                                 0x00000200L
4655 #define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK                                                                   0x00000C00L
4656 #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK                                                                0x00001000L
4657 #define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK                                                                    0x00002000L
4658 #define TA_CNTL_AUX__ANISO_STEP_MASK                                                                          0x00004000L
4659 #define TA_CNTL_AUX__MINMAG_UNNORM_MASK                                                                       0x00008000L
4660 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK                                                                   0x00010000L
4661 #define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK                                                                     0x00020000L
4662 #define TA_CNTL_AUX__ANISO_TAP_MASK                                                                           0x00040000L
4663 #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK                                                                  0x00080000L
4664 #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK                                                        0x00100000L
4665 #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK                                                   0x00200000L
4666 #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK                                                            0x00400000L
4667 #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK                                                   0x00800000L
4668 #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK                                                    0x01000000L
4669 #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK                                                 0x02000000L
4670 #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK                                                       0x04000000L
4671 #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK                                                           0x08000000L
4672 #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK                                                                 0x10000000L
4673 #define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK                                                                     0x20000000L
4674 #define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK                                                                    0xC0000000L
4675 //TA_RESERVED_010C
4676 #define TA_RESERVED_010C__Unused__SHIFT                                                                       0x0
4677 #define TA_RESERVED_010C__Unused_MASK                                                                         0xFFFFFFFFL
4678 //TA_STATUS
4679 #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT                                                                     0xc
4680 #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT                                                                     0xd
4681 #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT                                                                     0xe
4682 #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT                                                                     0x10
4683 #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT                                                                     0x11
4684 #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT                                                                     0x12
4685 #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT                                                                     0x14
4686 #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT                                                                     0x15
4687 #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT                                                                     0x16
4688 #define TA_STATUS__IN_BUSY__SHIFT                                                                             0x18
4689 #define TA_STATUS__FG_BUSY__SHIFT                                                                             0x19
4690 #define TA_STATUS__LA_BUSY__SHIFT                                                                             0x1a
4691 #define TA_STATUS__FL_BUSY__SHIFT                                                                             0x1b
4692 #define TA_STATUS__TA_BUSY__SHIFT                                                                             0x1c
4693 #define TA_STATUS__FA_BUSY__SHIFT                                                                             0x1d
4694 #define TA_STATUS__AL_BUSY__SHIFT                                                                             0x1e
4695 #define TA_STATUS__BUSY__SHIFT                                                                                0x1f
4696 #define TA_STATUS__FG_PFIFO_EMPTYB_MASK                                                                       0x00001000L
4697 #define TA_STATUS__FG_LFIFO_EMPTYB_MASK                                                                       0x00002000L
4698 #define TA_STATUS__FG_SFIFO_EMPTYB_MASK                                                                       0x00004000L
4699 #define TA_STATUS__FL_PFIFO_EMPTYB_MASK                                                                       0x00010000L
4700 #define TA_STATUS__FL_LFIFO_EMPTYB_MASK                                                                       0x00020000L
4701 #define TA_STATUS__FL_SFIFO_EMPTYB_MASK                                                                       0x00040000L
4702 #define TA_STATUS__FA_PFIFO_EMPTYB_MASK                                                                       0x00100000L
4703 #define TA_STATUS__FA_LFIFO_EMPTYB_MASK                                                                       0x00200000L
4704 #define TA_STATUS__FA_SFIFO_EMPTYB_MASK                                                                       0x00400000L
4705 #define TA_STATUS__IN_BUSY_MASK                                                                               0x01000000L
4706 #define TA_STATUS__FG_BUSY_MASK                                                                               0x02000000L
4707 #define TA_STATUS__LA_BUSY_MASK                                                                               0x04000000L
4708 #define TA_STATUS__FL_BUSY_MASK                                                                               0x08000000L
4709 #define TA_STATUS__TA_BUSY_MASK                                                                               0x10000000L
4710 #define TA_STATUS__FA_BUSY_MASK                                                                               0x20000000L
4711 #define TA_STATUS__AL_BUSY_MASK                                                                               0x40000000L
4712 #define TA_STATUS__BUSY_MASK                                                                                  0x80000000L
4713 //TA_SCRATCH
4714 #define TA_SCRATCH__SCRATCH__SHIFT                                                                            0x0
4715 #define TA_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL
4716 
4717 
4718 // addressBlock: gc_gdsdec
4719 //GDS_CONFIG
4720 #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT                                                                  0x1
4721 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT                                                                  0x3
4722 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT                                                                  0x5
4723 #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT                                                                  0x7
4724 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK                                                                    0x00000006L
4725 #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK                                                                    0x00000018L
4726 #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK                                                                    0x00000060L
4727 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK                                                                    0x00000180L
4728 //GDS_CNTL_STATUS
4729 #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT                                                                      0x0
4730 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT                                                                0x1
4731 #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT                                                                  0x2
4732 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT                                                              0x3
4733 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT                                                              0x4
4734 #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT                                                                   0x5
4735 #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT                                                                   0x6
4736 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT                                                                0x7
4737 #define GDS_CNTL_STATUS__DS_BUSY__SHIFT                                                                       0x8
4738 #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT                                                                      0x9
4739 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT                                                                 0xa
4740 #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT                                                                  0xb
4741 #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT                                                                  0xc
4742 #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT                                                                  0xd
4743 #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT                                                                  0xe
4744 #define GDS_CNTL_STATUS__GDS_BUSY_MASK                                                                        0x00000001L
4745 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK                                                                  0x00000002L
4746 #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK                                                                    0x00000004L
4747 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK                                                                0x00000008L
4748 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK                                                                0x00000010L
4749 #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK                                                                     0x00000020L
4750 #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK                                                                     0x00000040L
4751 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK                                                                  0x00000080L
4752 #define GDS_CNTL_STATUS__DS_BUSY_MASK                                                                         0x00000100L
4753 #define GDS_CNTL_STATUS__GWS_BUSY_MASK                                                                        0x00000200L
4754 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK                                                                   0x00000400L
4755 #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK                                                                    0x00000800L
4756 #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK                                                                    0x00001000L
4757 #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK                                                                    0x00002000L
4758 #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK                                                                    0x00004000L
4759 //GDS_ENHANCE2
4760 #define GDS_ENHANCE2__MISC__SHIFT                                                                             0x0
4761 #define GDS_ENHANCE2__UNUSED__SHIFT                                                                           0x10
4762 #define GDS_ENHANCE2__MISC_MASK                                                                               0x0000FFFFL
4763 #define GDS_ENHANCE2__UNUSED_MASK                                                                             0xFFFF0000L
4764 //GDS_PROTECTION_FAULT
4765 #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                                0x0
4766 #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                           0x1
4767 #define GDS_PROTECTION_FAULT__GRBM__SHIFT                                                                     0x2
4768 #define GDS_PROTECTION_FAULT__SH_ID__SHIFT                                                                    0x3
4769 #define GDS_PROTECTION_FAULT__CU_ID__SHIFT                                                                    0x6
4770 #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT                                                                  0xa
4771 #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT                                                                  0xc
4772 #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT                                                                  0x10
4773 #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK                                                                  0x00000001L
4774 #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                             0x00000002L
4775 #define GDS_PROTECTION_FAULT__GRBM_MASK                                                                       0x00000004L
4776 #define GDS_PROTECTION_FAULT__SH_ID_MASK                                                                      0x00000038L
4777 #define GDS_PROTECTION_FAULT__CU_ID_MASK                                                                      0x000003C0L
4778 #define GDS_PROTECTION_FAULT__SIMD_ID_MASK                                                                    0x00000C00L
4779 #define GDS_PROTECTION_FAULT__WAVE_ID_MASK                                                                    0x0000F000L
4780 #define GDS_PROTECTION_FAULT__ADDRESS_MASK                                                                    0xFFFF0000L
4781 //GDS_VM_PROTECTION_FAULT
4782 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                             0x0
4783 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                        0x1
4784 #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT                                                                   0x2
4785 #define GDS_VM_PROTECTION_FAULT__OA__SHIFT                                                                    0x3
4786 #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT                                                                  0x4
4787 #define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT                                                                   0x5
4788 #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT                                                                  0x8
4789 #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT                                                               0x10
4790 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK                                                               0x00000001L
4791 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                          0x00000002L
4792 #define GDS_VM_PROTECTION_FAULT__GWS_MASK                                                                     0x00000004L
4793 #define GDS_VM_PROTECTION_FAULT__OA_MASK                                                                      0x00000008L
4794 #define GDS_VM_PROTECTION_FAULT__GRBM_MASK                                                                    0x00000010L
4795 #define GDS_VM_PROTECTION_FAULT__TMZ_MASK                                                                     0x00000020L
4796 #define GDS_VM_PROTECTION_FAULT__VMID_MASK                                                                    0x00000F00L
4797 #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK                                                                 0xFFFF0000L
4798 //GDS_EDC_CNT
4799 #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT                                                                       0x0
4800 #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT                                                               0x2
4801 #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT                                                                       0x4
4802 #define GDS_EDC_CNT__UNUSED__SHIFT                                                                            0x6
4803 #define GDS_EDC_CNT__GDS_MEM_DED_MASK                                                                         0x00000003L
4804 #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK                                                                 0x0000000CL
4805 #define GDS_EDC_CNT__GDS_MEM_SEC_MASK                                                                         0x00000030L
4806 #define GDS_EDC_CNT__UNUSED_MASK                                                                              0xFFFFFFC0L
4807 //GDS_EDC_GRBM_CNT
4808 #define GDS_EDC_GRBM_CNT__DED__SHIFT                                                                          0x0
4809 #define GDS_EDC_GRBM_CNT__SEC__SHIFT                                                                          0x2
4810 #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT                                                                       0x4
4811 #define GDS_EDC_GRBM_CNT__DED_MASK                                                                            0x00000003L
4812 #define GDS_EDC_GRBM_CNT__SEC_MASK                                                                            0x0000000CL
4813 #define GDS_EDC_GRBM_CNT__UNUSED_MASK                                                                         0xFFFFFFF0L
4814 //GDS_EDC_OA_DED
4815 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT                                                            0x0
4816 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT                                                            0x1
4817 #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT                                                                     0x2
4818 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT                                                             0x3
4819 #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT                                                                  0x4
4820 #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT                                                                  0x5
4821 #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT                                                                  0x6
4822 #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT                                                                  0x7
4823 #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT                                                                  0x8
4824 #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT                                                                  0x9
4825 #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT                                                                  0xa
4826 #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT                                                                  0xb
4827 #define GDS_EDC_OA_DED__UNUSED1__SHIFT                                                                        0xc
4828 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK                                                              0x00000001L
4829 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK                                                              0x00000002L
4830 #define GDS_EDC_OA_DED__ME0_CS_DED_MASK                                                                       0x00000004L
4831 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK                                                               0x00000008L
4832 #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK                                                                    0x00000010L
4833 #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK                                                                    0x00000020L
4834 #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK                                                                    0x00000040L
4835 #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK                                                                    0x00000080L
4836 #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK                                                                    0x00000100L
4837 #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK                                                                    0x00000200L
4838 #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK                                                                    0x00000400L
4839 #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK                                                                    0x00000800L
4840 #define GDS_EDC_OA_DED__UNUSED1_MASK                                                                          0xFFFFF000L
4841 //GDS_DSM_CNTL
4842 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT                                                 0x0
4843 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT                                                 0x1
4844 #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                      0x2
4845 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT                                         0x3
4846 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT                                         0x4
4847 #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
4848 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT                                         0x6
4849 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT                                         0x7
4850 #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
4851 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT                                        0x9
4852 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT                                        0xa
4853 #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT                                             0xb
4854 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT                                            0xc
4855 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT                                            0xd
4856 #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xe
4857 #define GDS_DSM_CNTL__UNUSED__SHIFT                                                                           0xf
4858 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK                                                   0x00000001L
4859 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK                                                   0x00000002L
4860 #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK                                                        0x00000004L
4861 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK                                           0x00000008L
4862 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK                                           0x00000010L
4863 #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
4864 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK                                           0x00000040L
4865 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK                                           0x00000080L
4866 #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
4867 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK                                          0x00000200L
4868 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK                                          0x00000400L
4869 #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK                                               0x00000800L
4870 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK                                              0x00001000L
4871 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK                                              0x00002000L
4872 #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00004000L
4873 #define GDS_DSM_CNTL__UNUSED_MASK                                                                             0xFFFF8000L
4874 //GDS_EDC_OA_PHY_CNT
4875 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT                                                        0x0
4876 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT                                                        0x2
4877 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT                                                        0x4
4878 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT                                                        0x6
4879 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT                                                       0x8
4880 #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT                                                                    0xa
4881 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK                                                          0x00000003L
4882 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK                                                          0x0000000CL
4883 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK                                                          0x00000030L
4884 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK                                                          0x000000C0L
4885 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK                                                         0x00000300L
4886 #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK                                                                      0xFFFFFC00L
4887 //GDS_EDC_OA_PIPE_CNT
4888 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT                                                    0x0
4889 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT                                                    0x2
4890 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT                                                    0x4
4891 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT                                                    0x6
4892 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT                                                    0x8
4893 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT                                                    0xa
4894 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT                                                    0xc
4895 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT                                                    0xe
4896 #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT                                                                    0x10
4897 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK                                                      0x00000003L
4898 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK                                                      0x0000000CL
4899 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK                                                      0x00000030L
4900 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK                                                      0x000000C0L
4901 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK                                                      0x00000300L
4902 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK                                                      0x00000C00L
4903 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK                                                      0x00003000L
4904 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK                                                      0x0000C000L
4905 #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK                                                                      0xFFFF0000L
4906 //GDS_DSM_CNTL2
4907 #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT                                                     0x0
4908 #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT                                                     0x2
4909 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT                                             0x3
4910 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT                                             0x5
4911 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT                                             0x6
4912 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT                                             0x8
4913 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT                                            0x9
4914 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT                                            0xb
4915 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT                                                0xc
4916 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT                                                0xe
4917 #define GDS_DSM_CNTL2__UNUSED__SHIFT                                                                          0xf
4918 #define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT                                                                0x1a
4919 #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK                                                       0x00000003L
4920 #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK                                                       0x00000004L
4921 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
4922 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK                                               0x00000020L
4923 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
4924 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK                                               0x00000100L
4925 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK                                              0x00000600L
4926 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK                                              0x00000800L
4927 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK                                                  0x00003000L
4928 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK                                                  0x00004000L
4929 #define GDS_DSM_CNTL2__UNUSED_MASK                                                                            0x03FF8000L
4930 #define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK                                                                  0xFC000000L
4931 //GDS_WD_GDS_CSB
4932 #define GDS_WD_GDS_CSB__COUNTER__SHIFT                                                                        0x0
4933 #define GDS_WD_GDS_CSB__UNUSED__SHIFT                                                                         0xd
4934 #define GDS_WD_GDS_CSB__COUNTER_MASK                                                                          0x00001FFFL
4935 #define GDS_WD_GDS_CSB__UNUSED_MASK                                                                           0xFFFFE000L
4936 
4937 
4938 // addressBlock: gc_rbdec
4939 //DB_DEBUG
4940 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT                                                       0x0
4941 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT                                                         0x1
4942 #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT                                                                    0x2
4943 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT                                                              0x3
4944 #define DB_DEBUG__FORCE_Z_MODE__SHIFT                                                                         0x4
4945 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT                                                               0x6
4946 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT                                                             0x7
4947 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT                                                               0x8
4948 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT                                                              0xa
4949 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT                                                              0xc
4950 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT                                                                 0xe
4951 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT                                                           0xf
4952 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT                                                              0x10
4953 #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT                                                                  0x11
4954 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT                                                               0x12
4955 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT                                                             0x13
4956 #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT                                                                    0x15
4957 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT                                                0x16
4958 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT                                                    0x17
4959 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT                                                           0x18
4960 #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT                                                                   0x1c
4961 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT                                                           0x1d
4962 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT                                                           0x1e
4963 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT                                                           0x1f
4964 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK                                                         0x00000001L
4965 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK                                                           0x00000002L
4966 #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK                                                                      0x00000004L
4967 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK                                                                0x00000008L
4968 #define DB_DEBUG__FORCE_Z_MODE_MASK                                                                           0x00000030L
4969 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK                                                                 0x00000040L
4970 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK                                                               0x00000080L
4971 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK                                                                 0x00000300L
4972 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK                                                                0x00000C00L
4973 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK                                                                0x00003000L
4974 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK                                                                   0x00004000L
4975 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK                                                             0x00008000L
4976 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK                                                                0x00010000L
4977 #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK                                                                    0x00020000L
4978 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK                                                                 0x00040000L
4979 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK                                                               0x00180000L
4980 #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK                                                                      0x00200000L
4981 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK                                                  0x00400000L
4982 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK                                                      0x00800000L
4983 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK                                                             0x0F000000L
4984 #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK                                                                     0x10000000L
4985 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK                                                             0x20000000L
4986 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK                                                             0x40000000L
4987 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK                                                             0x80000000L
4988 //DB_DEBUG2
4989 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT                                                            0x0
4990 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT                                                          0x1
4991 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT                                                            0x2
4992 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT                                                                 0x3
4993 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT                                                        0x4
4994 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT                                                            0x5
4995 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT                                                        0x6
4996 #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT                                                        0x7
4997 #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT                                                     0x8
4998 #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT                                                                       0x9
4999 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT                                                    0xe
5000 #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT                                                             0xf
5001 #define DB_DEBUG2__RESERVED__SHIFT                                                                            0x10
5002 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT                                                         0x11
5003 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT                                                         0x12
5004 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT                                                        0x13
5005 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT                                                             0x1c
5006 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT                                                        0x1d
5007 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT                                                    0x1e
5008 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT                                                0x1f
5009 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK                                                              0x00000001L
5010 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK                                                            0x00000002L
5011 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK                                                              0x00000004L
5012 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK                                                                   0x00000008L
5013 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK                                                          0x00000010L
5014 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK                                                              0x00000020L
5015 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK                                                          0x00000040L
5016 #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK                                                          0x00000080L
5017 #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK                                                       0x00000100L
5018 #define DB_DEBUG2__CLK_OFF_DELAY_MASK                                                                         0x00003E00L
5019 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK                                                      0x00004000L
5020 #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK                                                               0x00008000L
5021 #define DB_DEBUG2__RESERVED_MASK                                                                              0x00010000L
5022 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK                                                           0x00020000L
5023 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK                                                           0x00040000L
5024 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK                                                          0x00080000L
5025 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK                                                               0x10000000L
5026 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK                                                          0x20000000L
5027 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK                                                      0x40000000L
5028 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK                                                  0x80000000L
5029 //DB_DEBUG3
5030 #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT                                                     0x0
5031 #define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT                                                             0x1
5032 #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT                                                                    0x2
5033 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT                                                     0x3
5034 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT                                                          0x4
5035 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT                                                             0x5
5036 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT                                                              0x6
5037 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT                                                              0x7
5038 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT                                                      0x8
5039 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT                                                 0x9
5040 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT                                            0xa
5041 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT                                                        0xb
5042 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT                                                        0xc
5043 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT                                                                0xd
5044 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT                                                         0xe
5045 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT                                                       0xf
5046 #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT                                                             0x10
5047 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT                                                         0x11
5048 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT                                                        0x12
5049 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT                                                     0x13
5050 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT                                                         0x14
5051 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT                                                0x15
5052 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT                                                        0x16
5053 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT                                                  0x17
5054 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT                                                           0x18
5055 #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT                                                                 0x19
5056 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT                                                             0x1a
5057 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT                                                       0x1b
5058 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT                                                         0x1c
5059 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT                                                         0x1d
5060 #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT                                                       0x1e
5061 #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT                                                   0x1f
5062 #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK                                                       0x00000001L
5063 #define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK                                                               0x00000002L
5064 #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK                                                                      0x00000004L
5065 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK                                                       0x00000008L
5066 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK                                                            0x00000010L
5067 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK                                                               0x00000020L
5068 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK                                                                0x00000040L
5069 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK                                                                0x00000080L
5070 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK                                                        0x00000100L
5071 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK                                                   0x00000200L
5072 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK                                              0x00000400L
5073 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK                                                          0x00000800L
5074 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK                                                          0x00001000L
5075 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK                                                                  0x00002000L
5076 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK                                                           0x00004000L
5077 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK                                                         0x00008000L
5078 #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK                                                               0x00010000L
5079 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK                                                           0x00020000L
5080 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK                                                          0x00040000L
5081 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK                                                       0x00080000L
5082 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK                                                           0x00100000L
5083 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK                                                  0x00200000L
5084 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK                                                          0x00400000L
5085 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK                                                    0x00800000L
5086 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK                                                             0x01000000L
5087 #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK                                                                   0x02000000L
5088 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK                                                               0x04000000L
5089 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK                                                         0x08000000L
5090 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK                                                           0x10000000L
5091 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK                                                           0x20000000L
5092 #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK                                                         0x40000000L
5093 #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK                                                     0x80000000L
5094 //DB_DEBUG4
5095 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT                                                         0x0
5096 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT                                                   0x1
5097 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT                                                    0x2
5098 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT                                             0x3
5099 #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT                                                          0x4
5100 #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT                                                       0x5
5101 #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT                                                    0x6
5102 #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT                                                                0x7
5103 #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT                                                  0x8
5104 #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT                                                        0x9
5105 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT                                                        0xa
5106 #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT                                                        0xb
5107 #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT                                                           0xc
5108 #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT                                                   0xd
5109 #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT                                              0xe
5110 #define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT                                                                 0xf
5111 #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT                                                0x10
5112 #define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT                                                  0x11
5113 #define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT                                                  0x12
5114 #define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT                                                                     0x13
5115 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK                                                           0x00000001L
5116 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK                                                     0x00000002L
5117 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK                                                      0x00000004L
5118 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK                                               0x00000008L
5119 #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK                                                            0x00000010L
5120 #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK                                                         0x00000020L
5121 #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK                                                      0x00000040L
5122 #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK                                                                  0x00000080L
5123 #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK                                                    0x00000100L
5124 #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK                                                          0x00000200L
5125 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK                                                          0x00000400L
5126 #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK                                                          0x00000800L
5127 #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK                                                             0x00001000L
5128 #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK                                                     0x00002000L
5129 #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK                                                0x00004000L
5130 #define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK                                                                   0x00008000L
5131 #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK                                                  0x00010000L
5132 #define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK                                                    0x00020000L
5133 #define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK                                                    0x00040000L
5134 #define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK                                                                       0xFFF80000L
5135 //DB_CREDIT_LIMIT
5136 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT                                                            0x0
5137 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT                                                            0x5
5138 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT                                                           0xa
5139 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT                                                            0x18
5140 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK                                                              0x0000001FL
5141 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK                                                              0x000003E0L
5142 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK                                                             0x00001C00L
5143 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK                                                              0x7F000000L
5144 //DB_WATERMARKS
5145 #define DB_WATERMARKS__DEPTH_FREE__SHIFT                                                                      0x0
5146 #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT                                                                     0x5
5147 #define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT                                                                 0xb
5148 #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT                                                              0xf
5149 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT                                                            0x14
5150 #define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT                                                                0x1e
5151 #define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT                                                                 0x1f
5152 #define DB_WATERMARKS__DEPTH_FREE_MASK                                                                        0x0000001FL
5153 #define DB_WATERMARKS__DEPTH_FLUSH_MASK                                                                       0x000007E0L
5154 #define DB_WATERMARKS__FORCE_SUMMARIZE_MASK                                                                   0x00007800L
5155 #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK                                                                0x000F8000L
5156 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK                                                              0x0FF00000L
5157 #define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK                                                                  0x40000000L
5158 #define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK                                                                   0x80000000L
5159 //DB_SUBTILE_CONTROL
5160 #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT                                                                    0x0
5161 #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT                                                                    0x2
5162 #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT                                                                    0x4
5163 #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT                                                                    0x6
5164 #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT                                                                    0x8
5165 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT                                                                    0xa
5166 #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT                                                                    0xc
5167 #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT                                                                    0xe
5168 #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT                                                                   0x10
5169 #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT                                                                   0x12
5170 #define DB_SUBTILE_CONTROL__MSAA1_X_MASK                                                                      0x00000003L
5171 #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK                                                                      0x0000000CL
5172 #define DB_SUBTILE_CONTROL__MSAA2_X_MASK                                                                      0x00000030L
5173 #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK                                                                      0x000000C0L
5174 #define DB_SUBTILE_CONTROL__MSAA4_X_MASK                                                                      0x00000300L
5175 #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK                                                                      0x00000C00L
5176 #define DB_SUBTILE_CONTROL__MSAA8_X_MASK                                                                      0x00003000L
5177 #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK                                                                      0x0000C000L
5178 #define DB_SUBTILE_CONTROL__MSAA16_X_MASK                                                                     0x00030000L
5179 #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK                                                                     0x000C0000L
5180 //DB_FREE_CACHELINES
5181 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT                                                           0x0
5182 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT                                                           0x7
5183 #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT                                                               0xe
5184 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT                                                           0x14
5185 #define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT                                                             0x18
5186 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK                                                             0x0000007FL
5187 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK                                                             0x00003F80L
5188 #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK                                                                 0x000FC000L
5189 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK                                                             0x00F00000L
5190 #define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK                                                               0xFF000000L
5191 //DB_FIFO_DEPTH1
5192 #define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT                                                           0x0
5193 #define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT                                                           0x5
5194 #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT                                                                      0xa
5195 #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT                                                                       0x10
5196 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT                                                         0x15
5197 #define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK                                                             0x0000001FL
5198 #define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK                                                             0x000003E0L
5199 #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK                                                                        0x0000FC00L
5200 #define DB_FIFO_DEPTH1__QC_DEPTH_MASK                                                                         0x001F0000L
5201 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK                                                           0x1FE00000L
5202 //DB_FIFO_DEPTH2
5203 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT                                                               0x0
5204 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT                                                            0x8
5205 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT                                                               0xf
5206 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT                                                            0x19
5207 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK                                                                 0x000000FFL
5208 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK                                                              0x00007F00L
5209 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK                                                                 0x01FF8000L
5210 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK                                                              0xFE000000L
5211 //DB_EXCEPTION_CONTROL
5212 #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT                                                    0x0
5213 #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT                                                     0x1
5214 #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT                                                       0x2
5215 #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK                                                      0x00000001L
5216 #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK                                                       0x00000002L
5217 #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK                                                         0x00000004L
5218 //DB_RING_CONTROL
5219 #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT                                                               0x0
5220 #define DB_RING_CONTROL__COUNTER_CONTROL_MASK                                                                 0x00000003L
5221 //DB_MEM_ARB_WATERMARKS
5222 #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT                                                       0x0
5223 #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT                                                       0x8
5224 #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT                                                       0x10
5225 #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT                                                       0x18
5226 #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK                                                         0x00000007L
5227 #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK                                                         0x00000700L
5228 #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK                                                         0x00070000L
5229 #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK                                                         0x07000000L
5230 //DB_RMI_CACHE_POLICY
5231 #define DB_RMI_CACHE_POLICY__Z_RD__SHIFT                                                                      0x0
5232 #define DB_RMI_CACHE_POLICY__S_RD__SHIFT                                                                      0x1
5233 #define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT                                                                  0x2
5234 #define DB_RMI_CACHE_POLICY__Z_WR__SHIFT                                                                      0x8
5235 #define DB_RMI_CACHE_POLICY__S_WR__SHIFT                                                                      0x9
5236 #define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT                                                                  0xa
5237 #define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT                                                                 0xb
5238 #define DB_RMI_CACHE_POLICY__CC_RD__SHIFT                                                                     0x10
5239 #define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT                                                                  0x11
5240 #define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT                                                                  0x12
5241 #define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT                                                                    0x13
5242 #define DB_RMI_CACHE_POLICY__CC_WR__SHIFT                                                                     0x18
5243 #define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT                                                                  0x19
5244 #define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT                                                                  0x1a
5245 #define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT                                                                    0x1b
5246 #define DB_RMI_CACHE_POLICY__Z_RD_MASK                                                                        0x00000001L
5247 #define DB_RMI_CACHE_POLICY__S_RD_MASK                                                                        0x00000002L
5248 #define DB_RMI_CACHE_POLICY__HTILE_RD_MASK                                                                    0x00000004L
5249 #define DB_RMI_CACHE_POLICY__Z_WR_MASK                                                                        0x00000100L
5250 #define DB_RMI_CACHE_POLICY__S_WR_MASK                                                                        0x00000200L
5251 #define DB_RMI_CACHE_POLICY__HTILE_WR_MASK                                                                    0x00000400L
5252 #define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK                                                                   0x00000800L
5253 #define DB_RMI_CACHE_POLICY__CC_RD_MASK                                                                       0x00010000L
5254 #define DB_RMI_CACHE_POLICY__FMASK_RD_MASK                                                                    0x00020000L
5255 #define DB_RMI_CACHE_POLICY__CMASK_RD_MASK                                                                    0x00040000L
5256 #define DB_RMI_CACHE_POLICY__DCC_RD_MASK                                                                      0x00080000L
5257 #define DB_RMI_CACHE_POLICY__CC_WR_MASK                                                                       0x01000000L
5258 #define DB_RMI_CACHE_POLICY__FMASK_WR_MASK                                                                    0x02000000L
5259 #define DB_RMI_CACHE_POLICY__CMASK_WR_MASK                                                                    0x04000000L
5260 #define DB_RMI_CACHE_POLICY__DCC_WR_MASK                                                                      0x08000000L
5261 //DB_DFSM_CONFIG
5262 #define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT                                                                    0x0
5263 #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT                                                               0x1
5264 #define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT                                                                   0x2
5265 #define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT                                                                    0x3
5266 #define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT                                                          0x8
5267 #define DB_DFSM_CONFIG__BYPASS_DFSM_MASK                                                                      0x00000001L
5268 #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK                                                                 0x00000002L
5269 #define DB_DFSM_CONFIG__DISABLE_POPS_MASK                                                                     0x00000004L
5270 #define DB_DFSM_CONFIG__FORCE_FLUSH_MASK                                                                      0x00000008L
5271 #define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK                                                            0x00007F00L
5272 //DB_DFSM_WATERMARK
5273 #define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT                                                         0x0
5274 #define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT                                                         0x10
5275 #define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK                                                           0x0000FFFFL
5276 #define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK                                                           0xFFFF0000L
5277 //DB_DFSM_TILES_IN_FLIGHT
5278 #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
5279 #define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT                                                            0x10
5280 #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
5281 #define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK                                                              0xFFFF0000L
5282 //DB_DFSM_PRIMS_IN_FLIGHT
5283 #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
5284 #define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT                                                            0x10
5285 #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
5286 #define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK                                                              0xFFFF0000L
5287 //DB_DFSM_WATCHDOG
5288 #define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT                                                                 0x0
5289 #define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK                                                                   0xFFFFFFFFL
5290 //DB_DFSM_FLUSH_ENABLE
5291 #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT                                                           0x0
5292 #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT                                                       0x18
5293 #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT                                                               0x1c
5294 #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK                                                             0x000003FFL
5295 #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK                                                         0x0F000000L
5296 #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK                                                                 0xF0000000L
5297 //DB_DFSM_FLUSH_AUX_EVENT
5298 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT                                                               0x0
5299 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT                                                               0x8
5300 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT                                                               0x10
5301 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT                                                               0x18
5302 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK                                                                 0x000000FFL
5303 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK                                                                 0x0000FF00L
5304 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK                                                                 0x00FF0000L
5305 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK                                                                 0xFF000000L
5306 //CC_RB_REDUNDANCY
5307 #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                                   0x8
5308 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                               0xc
5309 #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                                   0x10
5310 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                               0x14
5311 #define CC_RB_REDUNDANCY__FAILED_RB0_MASK                                                                     0x00000F00L
5312 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                                 0x00001000L
5313 #define CC_RB_REDUNDANCY__FAILED_RB1_MASK                                                                     0x000F0000L
5314 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                                 0x00100000L
5315 //CC_RB_BACKEND_DISABLE
5316 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                         0x10
5317 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                           0x00FF0000L
5318 //GB_ADDR_CONFIG
5319 #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                      0x0
5320 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                           0x3
5321 #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                           0x6
5322 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                           0x8
5323 #define GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                      0xc
5324 #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                                        0x10
5325 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                             0x13
5326 #define GB_ADDR_CONFIG__NUM_GPUS__SHIFT                                                                       0x15
5327 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                            0x18
5328 #define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                                  0x1a
5329 #define GB_ADDR_CONFIG__ROW_SIZE__SHIFT                                                                       0x1c
5330 #define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                                0x1e
5331 #define GB_ADDR_CONFIG__SE_ENABLE__SHIFT                                                                      0x1f
5332 #define GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                        0x00000007L
5333 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                             0x00000038L
5334 #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                             0x000000C0L
5335 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                             0x00000700L
5336 #define GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                        0x00007000L
5337 #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                          0x00070000L
5338 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                               0x00180000L
5339 #define GB_ADDR_CONFIG__NUM_GPUS_MASK                                                                         0x00E00000L
5340 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                              0x03000000L
5341 #define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                                    0x0C000000L
5342 #define GB_ADDR_CONFIG__ROW_SIZE_MASK                                                                         0x30000000L
5343 #define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                                  0x40000000L
5344 #define GB_ADDR_CONFIG__SE_ENABLE_MASK                                                                        0x80000000L
5345 //GB_BACKEND_MAP
5346 #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT                                                                    0x0
5347 #define GB_BACKEND_MAP__BACKEND_MAP_MASK                                                                      0xFFFFFFFFL
5348 //GB_GPU_ID
5349 #define GB_GPU_ID__GPU_ID__SHIFT                                                                              0x0
5350 #define GB_GPU_ID__GPU_ID_MASK                                                                                0x0000000FL
5351 //CC_RB_DAISY_CHAIN
5352 #define CC_RB_DAISY_CHAIN__RB_0__SHIFT                                                                        0x0
5353 #define CC_RB_DAISY_CHAIN__RB_1__SHIFT                                                                        0x4
5354 #define CC_RB_DAISY_CHAIN__RB_2__SHIFT                                                                        0x8
5355 #define CC_RB_DAISY_CHAIN__RB_3__SHIFT                                                                        0xc
5356 #define CC_RB_DAISY_CHAIN__RB_4__SHIFT                                                                        0x10
5357 #define CC_RB_DAISY_CHAIN__RB_5__SHIFT                                                                        0x14
5358 #define CC_RB_DAISY_CHAIN__RB_6__SHIFT                                                                        0x18
5359 #define CC_RB_DAISY_CHAIN__RB_7__SHIFT                                                                        0x1c
5360 #define CC_RB_DAISY_CHAIN__RB_0_MASK                                                                          0x0000000FL
5361 #define CC_RB_DAISY_CHAIN__RB_1_MASK                                                                          0x000000F0L
5362 #define CC_RB_DAISY_CHAIN__RB_2_MASK                                                                          0x00000F00L
5363 #define CC_RB_DAISY_CHAIN__RB_3_MASK                                                                          0x0000F000L
5364 #define CC_RB_DAISY_CHAIN__RB_4_MASK                                                                          0x000F0000L
5365 #define CC_RB_DAISY_CHAIN__RB_5_MASK                                                                          0x00F00000L
5366 #define CC_RB_DAISY_CHAIN__RB_6_MASK                                                                          0x0F000000L
5367 #define CC_RB_DAISY_CHAIN__RB_7_MASK                                                                          0xF0000000L
5368 //GB_ADDR_CONFIG_READ
5369 #define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                                 0x0
5370 #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x3
5371 #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                      0x6
5372 #define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                      0x8
5373 #define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                                 0xc
5374 #define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT                                                   0x10
5375 #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                        0x13
5376 #define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT                                                                  0x15
5377 #define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT                                                       0x18
5378 #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT                                                             0x1a
5379 #define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT                                                                  0x1c
5380 #define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT                                                           0x1e
5381 #define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT                                                                 0x1f
5382 #define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                                   0x00000007L
5383 #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000038L
5384 #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                        0x000000C0L
5385 #define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                        0x00000700L
5386 #define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                                   0x00007000L
5387 #define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK                                                     0x00070000L
5388 #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                          0x00180000L
5389 #define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK                                                                    0x00E00000L
5390 #define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK                                                         0x03000000L
5391 #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK                                                               0x0C000000L
5392 #define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK                                                                    0x30000000L
5393 #define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK                                                             0x40000000L
5394 #define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK                                                                   0x80000000L
5395 //GB_TILE_MODE0
5396 #define GB_TILE_MODE0__ARRAY_MODE__SHIFT                                                                      0x2
5397 #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT                                                                     0x6
5398 #define GB_TILE_MODE0__TILE_SPLIT__SHIFT                                                                      0xb
5399 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5400 #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT                                                                    0x19
5401 #define GB_TILE_MODE0__ARRAY_MODE_MASK                                                                        0x0000003CL
5402 #define GB_TILE_MODE0__PIPE_CONFIG_MASK                                                                       0x000007C0L
5403 #define GB_TILE_MODE0__TILE_SPLIT_MASK                                                                        0x00003800L
5404 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5405 #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5406 //GB_TILE_MODE1
5407 #define GB_TILE_MODE1__ARRAY_MODE__SHIFT                                                                      0x2
5408 #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT                                                                     0x6
5409 #define GB_TILE_MODE1__TILE_SPLIT__SHIFT                                                                      0xb
5410 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5411 #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT                                                                    0x19
5412 #define GB_TILE_MODE1__ARRAY_MODE_MASK                                                                        0x0000003CL
5413 #define GB_TILE_MODE1__PIPE_CONFIG_MASK                                                                       0x000007C0L
5414 #define GB_TILE_MODE1__TILE_SPLIT_MASK                                                                        0x00003800L
5415 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5416 #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5417 //GB_TILE_MODE2
5418 #define GB_TILE_MODE2__ARRAY_MODE__SHIFT                                                                      0x2
5419 #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT                                                                     0x6
5420 #define GB_TILE_MODE2__TILE_SPLIT__SHIFT                                                                      0xb
5421 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5422 #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT                                                                    0x19
5423 #define GB_TILE_MODE2__ARRAY_MODE_MASK                                                                        0x0000003CL
5424 #define GB_TILE_MODE2__PIPE_CONFIG_MASK                                                                       0x000007C0L
5425 #define GB_TILE_MODE2__TILE_SPLIT_MASK                                                                        0x00003800L
5426 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5427 #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5428 //GB_TILE_MODE3
5429 #define GB_TILE_MODE3__ARRAY_MODE__SHIFT                                                                      0x2
5430 #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT                                                                     0x6
5431 #define GB_TILE_MODE3__TILE_SPLIT__SHIFT                                                                      0xb
5432 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5433 #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT                                                                    0x19
5434 #define GB_TILE_MODE3__ARRAY_MODE_MASK                                                                        0x0000003CL
5435 #define GB_TILE_MODE3__PIPE_CONFIG_MASK                                                                       0x000007C0L
5436 #define GB_TILE_MODE3__TILE_SPLIT_MASK                                                                        0x00003800L
5437 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5438 #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5439 //GB_TILE_MODE4
5440 #define GB_TILE_MODE4__ARRAY_MODE__SHIFT                                                                      0x2
5441 #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT                                                                     0x6
5442 #define GB_TILE_MODE4__TILE_SPLIT__SHIFT                                                                      0xb
5443 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5444 #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT                                                                    0x19
5445 #define GB_TILE_MODE4__ARRAY_MODE_MASK                                                                        0x0000003CL
5446 #define GB_TILE_MODE4__PIPE_CONFIG_MASK                                                                       0x000007C0L
5447 #define GB_TILE_MODE4__TILE_SPLIT_MASK                                                                        0x00003800L
5448 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5449 #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5450 //GB_TILE_MODE5
5451 #define GB_TILE_MODE5__ARRAY_MODE__SHIFT                                                                      0x2
5452 #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT                                                                     0x6
5453 #define GB_TILE_MODE5__TILE_SPLIT__SHIFT                                                                      0xb
5454 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5455 #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT                                                                    0x19
5456 #define GB_TILE_MODE5__ARRAY_MODE_MASK                                                                        0x0000003CL
5457 #define GB_TILE_MODE5__PIPE_CONFIG_MASK                                                                       0x000007C0L
5458 #define GB_TILE_MODE5__TILE_SPLIT_MASK                                                                        0x00003800L
5459 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5460 #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5461 //GB_TILE_MODE6
5462 #define GB_TILE_MODE6__ARRAY_MODE__SHIFT                                                                      0x2
5463 #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT                                                                     0x6
5464 #define GB_TILE_MODE6__TILE_SPLIT__SHIFT                                                                      0xb
5465 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5466 #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT                                                                    0x19
5467 #define GB_TILE_MODE6__ARRAY_MODE_MASK                                                                        0x0000003CL
5468 #define GB_TILE_MODE6__PIPE_CONFIG_MASK                                                                       0x000007C0L
5469 #define GB_TILE_MODE6__TILE_SPLIT_MASK                                                                        0x00003800L
5470 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5471 #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5472 //GB_TILE_MODE7
5473 #define GB_TILE_MODE7__ARRAY_MODE__SHIFT                                                                      0x2
5474 #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT                                                                     0x6
5475 #define GB_TILE_MODE7__TILE_SPLIT__SHIFT                                                                      0xb
5476 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5477 #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT                                                                    0x19
5478 #define GB_TILE_MODE7__ARRAY_MODE_MASK                                                                        0x0000003CL
5479 #define GB_TILE_MODE7__PIPE_CONFIG_MASK                                                                       0x000007C0L
5480 #define GB_TILE_MODE7__TILE_SPLIT_MASK                                                                        0x00003800L
5481 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5482 #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5483 //GB_TILE_MODE8
5484 #define GB_TILE_MODE8__ARRAY_MODE__SHIFT                                                                      0x2
5485 #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT                                                                     0x6
5486 #define GB_TILE_MODE8__TILE_SPLIT__SHIFT                                                                      0xb
5487 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5488 #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT                                                                    0x19
5489 #define GB_TILE_MODE8__ARRAY_MODE_MASK                                                                        0x0000003CL
5490 #define GB_TILE_MODE8__PIPE_CONFIG_MASK                                                                       0x000007C0L
5491 #define GB_TILE_MODE8__TILE_SPLIT_MASK                                                                        0x00003800L
5492 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5493 #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5494 //GB_TILE_MODE9
5495 #define GB_TILE_MODE9__ARRAY_MODE__SHIFT                                                                      0x2
5496 #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT                                                                     0x6
5497 #define GB_TILE_MODE9__TILE_SPLIT__SHIFT                                                                      0xb
5498 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5499 #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT                                                                    0x19
5500 #define GB_TILE_MODE9__ARRAY_MODE_MASK                                                                        0x0000003CL
5501 #define GB_TILE_MODE9__PIPE_CONFIG_MASK                                                                       0x000007C0L
5502 #define GB_TILE_MODE9__TILE_SPLIT_MASK                                                                        0x00003800L
5503 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5504 #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5505 //GB_TILE_MODE10
5506 #define GB_TILE_MODE10__ARRAY_MODE__SHIFT                                                                     0x2
5507 #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT                                                                    0x6
5508 #define GB_TILE_MODE10__TILE_SPLIT__SHIFT                                                                     0xb
5509 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5510 #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT                                                                   0x19
5511 #define GB_TILE_MODE10__ARRAY_MODE_MASK                                                                       0x0000003CL
5512 #define GB_TILE_MODE10__PIPE_CONFIG_MASK                                                                      0x000007C0L
5513 #define GB_TILE_MODE10__TILE_SPLIT_MASK                                                                       0x00003800L
5514 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5515 #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5516 //GB_TILE_MODE11
5517 #define GB_TILE_MODE11__ARRAY_MODE__SHIFT                                                                     0x2
5518 #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT                                                                    0x6
5519 #define GB_TILE_MODE11__TILE_SPLIT__SHIFT                                                                     0xb
5520 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5521 #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT                                                                   0x19
5522 #define GB_TILE_MODE11__ARRAY_MODE_MASK                                                                       0x0000003CL
5523 #define GB_TILE_MODE11__PIPE_CONFIG_MASK                                                                      0x000007C0L
5524 #define GB_TILE_MODE11__TILE_SPLIT_MASK                                                                       0x00003800L
5525 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5526 #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5527 //GB_TILE_MODE12
5528 #define GB_TILE_MODE12__ARRAY_MODE__SHIFT                                                                     0x2
5529 #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT                                                                    0x6
5530 #define GB_TILE_MODE12__TILE_SPLIT__SHIFT                                                                     0xb
5531 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5532 #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT                                                                   0x19
5533 #define GB_TILE_MODE12__ARRAY_MODE_MASK                                                                       0x0000003CL
5534 #define GB_TILE_MODE12__PIPE_CONFIG_MASK                                                                      0x000007C0L
5535 #define GB_TILE_MODE12__TILE_SPLIT_MASK                                                                       0x00003800L
5536 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5537 #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5538 //GB_TILE_MODE13
5539 #define GB_TILE_MODE13__ARRAY_MODE__SHIFT                                                                     0x2
5540 #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT                                                                    0x6
5541 #define GB_TILE_MODE13__TILE_SPLIT__SHIFT                                                                     0xb
5542 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5543 #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT                                                                   0x19
5544 #define GB_TILE_MODE13__ARRAY_MODE_MASK                                                                       0x0000003CL
5545 #define GB_TILE_MODE13__PIPE_CONFIG_MASK                                                                      0x000007C0L
5546 #define GB_TILE_MODE13__TILE_SPLIT_MASK                                                                       0x00003800L
5547 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5548 #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5549 //GB_TILE_MODE14
5550 #define GB_TILE_MODE14__ARRAY_MODE__SHIFT                                                                     0x2
5551 #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT                                                                    0x6
5552 #define GB_TILE_MODE14__TILE_SPLIT__SHIFT                                                                     0xb
5553 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5554 #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT                                                                   0x19
5555 #define GB_TILE_MODE14__ARRAY_MODE_MASK                                                                       0x0000003CL
5556 #define GB_TILE_MODE14__PIPE_CONFIG_MASK                                                                      0x000007C0L
5557 #define GB_TILE_MODE14__TILE_SPLIT_MASK                                                                       0x00003800L
5558 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5559 #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5560 //GB_TILE_MODE15
5561 #define GB_TILE_MODE15__ARRAY_MODE__SHIFT                                                                     0x2
5562 #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT                                                                    0x6
5563 #define GB_TILE_MODE15__TILE_SPLIT__SHIFT                                                                     0xb
5564 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5565 #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT                                                                   0x19
5566 #define GB_TILE_MODE15__ARRAY_MODE_MASK                                                                       0x0000003CL
5567 #define GB_TILE_MODE15__PIPE_CONFIG_MASK                                                                      0x000007C0L
5568 #define GB_TILE_MODE15__TILE_SPLIT_MASK                                                                       0x00003800L
5569 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5570 #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5571 //GB_TILE_MODE16
5572 #define GB_TILE_MODE16__ARRAY_MODE__SHIFT                                                                     0x2
5573 #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT                                                                    0x6
5574 #define GB_TILE_MODE16__TILE_SPLIT__SHIFT                                                                     0xb
5575 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5576 #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT                                                                   0x19
5577 #define GB_TILE_MODE16__ARRAY_MODE_MASK                                                                       0x0000003CL
5578 #define GB_TILE_MODE16__PIPE_CONFIG_MASK                                                                      0x000007C0L
5579 #define GB_TILE_MODE16__TILE_SPLIT_MASK                                                                       0x00003800L
5580 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5581 #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5582 //GB_TILE_MODE17
5583 #define GB_TILE_MODE17__ARRAY_MODE__SHIFT                                                                     0x2
5584 #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT                                                                    0x6
5585 #define GB_TILE_MODE17__TILE_SPLIT__SHIFT                                                                     0xb
5586 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5587 #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT                                                                   0x19
5588 #define GB_TILE_MODE17__ARRAY_MODE_MASK                                                                       0x0000003CL
5589 #define GB_TILE_MODE17__PIPE_CONFIG_MASK                                                                      0x000007C0L
5590 #define GB_TILE_MODE17__TILE_SPLIT_MASK                                                                       0x00003800L
5591 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5592 #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5593 //GB_TILE_MODE18
5594 #define GB_TILE_MODE18__ARRAY_MODE__SHIFT                                                                     0x2
5595 #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT                                                                    0x6
5596 #define GB_TILE_MODE18__TILE_SPLIT__SHIFT                                                                     0xb
5597 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5598 #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT                                                                   0x19
5599 #define GB_TILE_MODE18__ARRAY_MODE_MASK                                                                       0x0000003CL
5600 #define GB_TILE_MODE18__PIPE_CONFIG_MASK                                                                      0x000007C0L
5601 #define GB_TILE_MODE18__TILE_SPLIT_MASK                                                                       0x00003800L
5602 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5603 #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5604 //GB_TILE_MODE19
5605 #define GB_TILE_MODE19__ARRAY_MODE__SHIFT                                                                     0x2
5606 #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT                                                                    0x6
5607 #define GB_TILE_MODE19__TILE_SPLIT__SHIFT                                                                     0xb
5608 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5609 #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT                                                                   0x19
5610 #define GB_TILE_MODE19__ARRAY_MODE_MASK                                                                       0x0000003CL
5611 #define GB_TILE_MODE19__PIPE_CONFIG_MASK                                                                      0x000007C0L
5612 #define GB_TILE_MODE19__TILE_SPLIT_MASK                                                                       0x00003800L
5613 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5614 #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5615 //GB_TILE_MODE20
5616 #define GB_TILE_MODE20__ARRAY_MODE__SHIFT                                                                     0x2
5617 #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT                                                                    0x6
5618 #define GB_TILE_MODE20__TILE_SPLIT__SHIFT                                                                     0xb
5619 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5620 #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT                                                                   0x19
5621 #define GB_TILE_MODE20__ARRAY_MODE_MASK                                                                       0x0000003CL
5622 #define GB_TILE_MODE20__PIPE_CONFIG_MASK                                                                      0x000007C0L
5623 #define GB_TILE_MODE20__TILE_SPLIT_MASK                                                                       0x00003800L
5624 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5625 #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5626 //GB_TILE_MODE21
5627 #define GB_TILE_MODE21__ARRAY_MODE__SHIFT                                                                     0x2
5628 #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT                                                                    0x6
5629 #define GB_TILE_MODE21__TILE_SPLIT__SHIFT                                                                     0xb
5630 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5631 #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT                                                                   0x19
5632 #define GB_TILE_MODE21__ARRAY_MODE_MASK                                                                       0x0000003CL
5633 #define GB_TILE_MODE21__PIPE_CONFIG_MASK                                                                      0x000007C0L
5634 #define GB_TILE_MODE21__TILE_SPLIT_MASK                                                                       0x00003800L
5635 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5636 #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5637 //GB_TILE_MODE22
5638 #define GB_TILE_MODE22__ARRAY_MODE__SHIFT                                                                     0x2
5639 #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT                                                                    0x6
5640 #define GB_TILE_MODE22__TILE_SPLIT__SHIFT                                                                     0xb
5641 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5642 #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT                                                                   0x19
5643 #define GB_TILE_MODE22__ARRAY_MODE_MASK                                                                       0x0000003CL
5644 #define GB_TILE_MODE22__PIPE_CONFIG_MASK                                                                      0x000007C0L
5645 #define GB_TILE_MODE22__TILE_SPLIT_MASK                                                                       0x00003800L
5646 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5647 #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5648 //GB_TILE_MODE23
5649 #define GB_TILE_MODE23__ARRAY_MODE__SHIFT                                                                     0x2
5650 #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT                                                                    0x6
5651 #define GB_TILE_MODE23__TILE_SPLIT__SHIFT                                                                     0xb
5652 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5653 #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT                                                                   0x19
5654 #define GB_TILE_MODE23__ARRAY_MODE_MASK                                                                       0x0000003CL
5655 #define GB_TILE_MODE23__PIPE_CONFIG_MASK                                                                      0x000007C0L
5656 #define GB_TILE_MODE23__TILE_SPLIT_MASK                                                                       0x00003800L
5657 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5658 #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5659 //GB_TILE_MODE24
5660 #define GB_TILE_MODE24__ARRAY_MODE__SHIFT                                                                     0x2
5661 #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT                                                                    0x6
5662 #define GB_TILE_MODE24__TILE_SPLIT__SHIFT                                                                     0xb
5663 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5664 #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT                                                                   0x19
5665 #define GB_TILE_MODE24__ARRAY_MODE_MASK                                                                       0x0000003CL
5666 #define GB_TILE_MODE24__PIPE_CONFIG_MASK                                                                      0x000007C0L
5667 #define GB_TILE_MODE24__TILE_SPLIT_MASK                                                                       0x00003800L
5668 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5669 #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5670 //GB_TILE_MODE25
5671 #define GB_TILE_MODE25__ARRAY_MODE__SHIFT                                                                     0x2
5672 #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT                                                                    0x6
5673 #define GB_TILE_MODE25__TILE_SPLIT__SHIFT                                                                     0xb
5674 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5675 #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT                                                                   0x19
5676 #define GB_TILE_MODE25__ARRAY_MODE_MASK                                                                       0x0000003CL
5677 #define GB_TILE_MODE25__PIPE_CONFIG_MASK                                                                      0x000007C0L
5678 #define GB_TILE_MODE25__TILE_SPLIT_MASK                                                                       0x00003800L
5679 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5680 #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5681 //GB_TILE_MODE26
5682 #define GB_TILE_MODE26__ARRAY_MODE__SHIFT                                                                     0x2
5683 #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT                                                                    0x6
5684 #define GB_TILE_MODE26__TILE_SPLIT__SHIFT                                                                     0xb
5685 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5686 #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT                                                                   0x19
5687 #define GB_TILE_MODE26__ARRAY_MODE_MASK                                                                       0x0000003CL
5688 #define GB_TILE_MODE26__PIPE_CONFIG_MASK                                                                      0x000007C0L
5689 #define GB_TILE_MODE26__TILE_SPLIT_MASK                                                                       0x00003800L
5690 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5691 #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5692 //GB_TILE_MODE27
5693 #define GB_TILE_MODE27__ARRAY_MODE__SHIFT                                                                     0x2
5694 #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT                                                                    0x6
5695 #define GB_TILE_MODE27__TILE_SPLIT__SHIFT                                                                     0xb
5696 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5697 #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT                                                                   0x19
5698 #define GB_TILE_MODE27__ARRAY_MODE_MASK                                                                       0x0000003CL
5699 #define GB_TILE_MODE27__PIPE_CONFIG_MASK                                                                      0x000007C0L
5700 #define GB_TILE_MODE27__TILE_SPLIT_MASK                                                                       0x00003800L
5701 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5702 #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5703 //GB_TILE_MODE28
5704 #define GB_TILE_MODE28__ARRAY_MODE__SHIFT                                                                     0x2
5705 #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT                                                                    0x6
5706 #define GB_TILE_MODE28__TILE_SPLIT__SHIFT                                                                     0xb
5707 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5708 #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT                                                                   0x19
5709 #define GB_TILE_MODE28__ARRAY_MODE_MASK                                                                       0x0000003CL
5710 #define GB_TILE_MODE28__PIPE_CONFIG_MASK                                                                      0x000007C0L
5711 #define GB_TILE_MODE28__TILE_SPLIT_MASK                                                                       0x00003800L
5712 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5713 #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5714 //GB_TILE_MODE29
5715 #define GB_TILE_MODE29__ARRAY_MODE__SHIFT                                                                     0x2
5716 #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT                                                                    0x6
5717 #define GB_TILE_MODE29__TILE_SPLIT__SHIFT                                                                     0xb
5718 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5719 #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT                                                                   0x19
5720 #define GB_TILE_MODE29__ARRAY_MODE_MASK                                                                       0x0000003CL
5721 #define GB_TILE_MODE29__PIPE_CONFIG_MASK                                                                      0x000007C0L
5722 #define GB_TILE_MODE29__TILE_SPLIT_MASK                                                                       0x00003800L
5723 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5724 #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5725 //GB_TILE_MODE30
5726 #define GB_TILE_MODE30__ARRAY_MODE__SHIFT                                                                     0x2
5727 #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT                                                                    0x6
5728 #define GB_TILE_MODE30__TILE_SPLIT__SHIFT                                                                     0xb
5729 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5730 #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT                                                                   0x19
5731 #define GB_TILE_MODE30__ARRAY_MODE_MASK                                                                       0x0000003CL
5732 #define GB_TILE_MODE30__PIPE_CONFIG_MASK                                                                      0x000007C0L
5733 #define GB_TILE_MODE30__TILE_SPLIT_MASK                                                                       0x00003800L
5734 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5735 #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5736 //GB_TILE_MODE31
5737 #define GB_TILE_MODE31__ARRAY_MODE__SHIFT                                                                     0x2
5738 #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT                                                                    0x6
5739 #define GB_TILE_MODE31__TILE_SPLIT__SHIFT                                                                     0xb
5740 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5741 #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT                                                                   0x19
5742 #define GB_TILE_MODE31__ARRAY_MODE_MASK                                                                       0x0000003CL
5743 #define GB_TILE_MODE31__PIPE_CONFIG_MASK                                                                      0x000007C0L
5744 #define GB_TILE_MODE31__TILE_SPLIT_MASK                                                                       0x00003800L
5745 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5746 #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5747 //GB_MACROTILE_MODE0
5748 #define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT                                                                 0x0
5749 #define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT                                                                0x2
5750 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5751 #define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT                                                                  0x6
5752 #define GB_MACROTILE_MODE0__BANK_WIDTH_MASK                                                                   0x00000003L
5753 #define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK                                                                  0x0000000CL
5754 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5755 #define GB_MACROTILE_MODE0__NUM_BANKS_MASK                                                                    0x000000C0L
5756 //GB_MACROTILE_MODE1
5757 #define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT                                                                 0x0
5758 #define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT                                                                0x2
5759 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5760 #define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT                                                                  0x6
5761 #define GB_MACROTILE_MODE1__BANK_WIDTH_MASK                                                                   0x00000003L
5762 #define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK                                                                  0x0000000CL
5763 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5764 #define GB_MACROTILE_MODE1__NUM_BANKS_MASK                                                                    0x000000C0L
5765 //GB_MACROTILE_MODE2
5766 #define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT                                                                 0x0
5767 #define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT                                                                0x2
5768 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5769 #define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT                                                                  0x6
5770 #define GB_MACROTILE_MODE2__BANK_WIDTH_MASK                                                                   0x00000003L
5771 #define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK                                                                  0x0000000CL
5772 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5773 #define GB_MACROTILE_MODE2__NUM_BANKS_MASK                                                                    0x000000C0L
5774 //GB_MACROTILE_MODE3
5775 #define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT                                                                 0x0
5776 #define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT                                                                0x2
5777 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5778 #define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT                                                                  0x6
5779 #define GB_MACROTILE_MODE3__BANK_WIDTH_MASK                                                                   0x00000003L
5780 #define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK                                                                  0x0000000CL
5781 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5782 #define GB_MACROTILE_MODE3__NUM_BANKS_MASK                                                                    0x000000C0L
5783 //GB_MACROTILE_MODE4
5784 #define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT                                                                 0x0
5785 #define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT                                                                0x2
5786 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5787 #define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT                                                                  0x6
5788 #define GB_MACROTILE_MODE4__BANK_WIDTH_MASK                                                                   0x00000003L
5789 #define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK                                                                  0x0000000CL
5790 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5791 #define GB_MACROTILE_MODE4__NUM_BANKS_MASK                                                                    0x000000C0L
5792 //GB_MACROTILE_MODE5
5793 #define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT                                                                 0x0
5794 #define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT                                                                0x2
5795 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5796 #define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT                                                                  0x6
5797 #define GB_MACROTILE_MODE5__BANK_WIDTH_MASK                                                                   0x00000003L
5798 #define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK                                                                  0x0000000CL
5799 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5800 #define GB_MACROTILE_MODE5__NUM_BANKS_MASK                                                                    0x000000C0L
5801 //GB_MACROTILE_MODE6
5802 #define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT                                                                 0x0
5803 #define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT                                                                0x2
5804 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5805 #define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT                                                                  0x6
5806 #define GB_MACROTILE_MODE6__BANK_WIDTH_MASK                                                                   0x00000003L
5807 #define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK                                                                  0x0000000CL
5808 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5809 #define GB_MACROTILE_MODE6__NUM_BANKS_MASK                                                                    0x000000C0L
5810 //GB_MACROTILE_MODE7
5811 #define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT                                                                 0x0
5812 #define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT                                                                0x2
5813 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5814 #define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT                                                                  0x6
5815 #define GB_MACROTILE_MODE7__BANK_WIDTH_MASK                                                                   0x00000003L
5816 #define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK                                                                  0x0000000CL
5817 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5818 #define GB_MACROTILE_MODE7__NUM_BANKS_MASK                                                                    0x000000C0L
5819 //GB_MACROTILE_MODE8
5820 #define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT                                                                 0x0
5821 #define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT                                                                0x2
5822 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5823 #define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT                                                                  0x6
5824 #define GB_MACROTILE_MODE8__BANK_WIDTH_MASK                                                                   0x00000003L
5825 #define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK                                                                  0x0000000CL
5826 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5827 #define GB_MACROTILE_MODE8__NUM_BANKS_MASK                                                                    0x000000C0L
5828 //GB_MACROTILE_MODE9
5829 #define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT                                                                 0x0
5830 #define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT                                                                0x2
5831 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5832 #define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT                                                                  0x6
5833 #define GB_MACROTILE_MODE9__BANK_WIDTH_MASK                                                                   0x00000003L
5834 #define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK                                                                  0x0000000CL
5835 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5836 #define GB_MACROTILE_MODE9__NUM_BANKS_MASK                                                                    0x000000C0L
5837 //GB_MACROTILE_MODE10
5838 #define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT                                                                0x0
5839 #define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT                                                               0x2
5840 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5841 #define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT                                                                 0x6
5842 #define GB_MACROTILE_MODE10__BANK_WIDTH_MASK                                                                  0x00000003L
5843 #define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK                                                                 0x0000000CL
5844 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5845 #define GB_MACROTILE_MODE10__NUM_BANKS_MASK                                                                   0x000000C0L
5846 //GB_MACROTILE_MODE11
5847 #define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT                                                                0x0
5848 #define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT                                                               0x2
5849 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5850 #define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT                                                                 0x6
5851 #define GB_MACROTILE_MODE11__BANK_WIDTH_MASK                                                                  0x00000003L
5852 #define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK                                                                 0x0000000CL
5853 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5854 #define GB_MACROTILE_MODE11__NUM_BANKS_MASK                                                                   0x000000C0L
5855 //GB_MACROTILE_MODE12
5856 #define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT                                                                0x0
5857 #define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT                                                               0x2
5858 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5859 #define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT                                                                 0x6
5860 #define GB_MACROTILE_MODE12__BANK_WIDTH_MASK                                                                  0x00000003L
5861 #define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK                                                                 0x0000000CL
5862 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5863 #define GB_MACROTILE_MODE12__NUM_BANKS_MASK                                                                   0x000000C0L
5864 //GB_MACROTILE_MODE13
5865 #define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT                                                                0x0
5866 #define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT                                                               0x2
5867 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5868 #define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT                                                                 0x6
5869 #define GB_MACROTILE_MODE13__BANK_WIDTH_MASK                                                                  0x00000003L
5870 #define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK                                                                 0x0000000CL
5871 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5872 #define GB_MACROTILE_MODE13__NUM_BANKS_MASK                                                                   0x000000C0L
5873 //GB_MACROTILE_MODE14
5874 #define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT                                                                0x0
5875 #define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT                                                               0x2
5876 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5877 #define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT                                                                 0x6
5878 #define GB_MACROTILE_MODE14__BANK_WIDTH_MASK                                                                  0x00000003L
5879 #define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK                                                                 0x0000000CL
5880 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5881 #define GB_MACROTILE_MODE14__NUM_BANKS_MASK                                                                   0x000000C0L
5882 //GB_MACROTILE_MODE15
5883 #define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT                                                                0x0
5884 #define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT                                                               0x2
5885 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5886 #define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT                                                                 0x6
5887 #define GB_MACROTILE_MODE15__BANK_WIDTH_MASK                                                                  0x00000003L
5888 #define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK                                                                 0x0000000CL
5889 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5890 #define GB_MACROTILE_MODE15__NUM_BANKS_MASK                                                                   0x000000C0L
5891 //CB_HW_CONTROL
5892 #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT                                                            0x0
5893 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT                                                            0x6
5894 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT                                                            0xc
5895 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT                                                      0x10
5896 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT                                                0x12
5897 #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT                                                                 0x13
5898 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT                                                             0x14
5899 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT                                                0x15
5900 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT                                                         0x16
5901 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT                                             0x17
5902 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT                                                   0x18
5903 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT                                                        0x19
5904 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT                                                 0x1a
5905 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT                                0x1b
5906 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT                                   0x1c
5907 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT                                0x1d
5908 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT                                              0x1e
5909 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT                                    0x1f
5910 #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK                                                              0x0000000FL
5911 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK                                                              0x000003C0L
5912 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK                                                              0x0000F000L
5913 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK                                                        0x00010000L
5914 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK                                                  0x00040000L
5915 #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK                                                                   0x00080000L
5916 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK                                                               0x00100000L
5917 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK                                                  0x00200000L
5918 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK                                                           0x00400000L
5919 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK                                               0x00800000L
5920 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK                                                     0x01000000L
5921 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK                                                          0x02000000L
5922 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK                                                   0x04000000L
5923 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK                                  0x08000000L
5924 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK                                     0x10000000L
5925 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK                                  0x20000000L
5926 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK                                                0x40000000L
5927 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK                                      0x80000000L
5928 //CB_HW_CONTROL_1
5929 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT                                                             0x0
5930 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT                                                             0x5
5931 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT                                                             0xb
5932 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT                                                            0x11
5933 #define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT                                                                   0x1a
5934 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK                                                               0x0000001FL
5935 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK                                                               0x000007E0L
5936 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK                                                               0x0001F800L
5937 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK                                                              0x03FE0000L
5938 #define CB_HW_CONTROL_1__RMI_CREDITS_MASK                                                                     0xFC000000L
5939 //CB_HW_CONTROL_2
5940 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT                                                        0x0
5941 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT                                                      0x8
5942 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT                                                      0xf
5943 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT                                                   0x18
5944 #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT                                                                  0x1c
5945 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK                                                          0x000000FFL
5946 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK                                                        0x00007F00L
5947 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK                                                        0x007F8000L
5948 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK                                                     0x0F000000L
5949 #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK                                                                    0xF0000000L
5950 //CB_HW_CONTROL_3
5951 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT                                        0x0
5952 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT                                              0x1
5953 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT                                                  0x2
5954 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT                                                 0x3
5955 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT                                            0x4
5956 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT                                            0x5
5957 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT                                                 0x6
5958 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT                                                 0x7
5959 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT                             0x8
5960 #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT                                                 0x9
5961 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT                                                     0xa
5962 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT                                             0xb
5963 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT                                              0xc
5964 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT                                              0xd
5965 #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT                                                0xe
5966 #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT                                                           0xf
5967 #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT                                                          0x10
5968 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT                                                       0x11
5969 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT                                                       0x12
5970 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT                                                       0x13
5971 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT                                                       0x14
5972 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT                                                    0x15
5973 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT                                                    0x16
5974 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT                                                    0x17
5975 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT                                                    0x18
5976 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT                                                  0x19
5977 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT                                                  0x1a
5978 #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT                                            0x1b
5979 #define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT                                                  0x1c
5980 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK                                          0x00000001L
5981 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK                                                0x00000002L
5982 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK                                                    0x00000004L
5983 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK                                                   0x00000008L
5984 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK                                              0x00000010L
5985 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK                                              0x00000020L
5986 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK                                                   0x00000040L
5987 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK                                                   0x00000080L
5988 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK                               0x00000100L
5989 #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK                                                   0x00000200L
5990 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK                                                       0x00000400L
5991 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK                                               0x00000800L
5992 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK                                                0x00001000L
5993 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK                                                0x00002000L
5994 #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK                                                  0x00004000L
5995 #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK                                                             0x00008000L
5996 #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK                                                            0x00010000L
5997 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK                                                         0x00020000L
5998 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK                                                         0x00040000L
5999 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK                                                         0x00080000L
6000 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK                                                         0x00100000L
6001 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK                                                      0x00200000L
6002 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK                                                      0x00400000L
6003 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK                                                      0x00800000L
6004 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK                                                      0x01000000L
6005 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK                                                    0x02000000L
6006 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK                                                    0x04000000L
6007 #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK                                              0x08000000L
6008 #define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK                                                    0x30000000L
6009 //CB_HW_MEM_ARBITER_RD
6010 #define CB_HW_MEM_ARBITER_RD__MODE__SHIFT                                                                     0x0
6011 #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT                                                        0x2
6012 #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT                                                          0x6
6013 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT                                                                0xa
6014 #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT                                                                0xc
6015 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT                                                                0xe
6016 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT                                                                0x10
6017 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
6018 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
6019 #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT                                                   0x16
6020 #define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT                                                                0x17
6021 #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT                                                             0x1a
6022 #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
6023 #define CB_HW_MEM_ARBITER_RD__MODE_MASK                                                                       0x00000003L
6024 #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
6025 #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
6026 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK                                                                  0x00000C00L
6027 #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK                                                                  0x00003000L
6028 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK                                                                  0x0000C000L
6029 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK                                                                  0x00030000L
6030 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
6031 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
6032 #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK                                                     0x00400000L
6033 #define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK                                                                  0x03800000L
6034 #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK                                                               0x1C000000L
6035 #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
6036 //CB_HW_MEM_ARBITER_WR
6037 #define CB_HW_MEM_ARBITER_WR__MODE__SHIFT                                                                     0x0
6038 #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT                                                        0x2
6039 #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT                                                          0x6
6040 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT                                                                0xa
6041 #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT                                                                0xc
6042 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT                                                                0xe
6043 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT                                                                0x10
6044 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
6045 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
6046 #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT                                                  0x16
6047 #define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT                                                                0x17
6048 #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT                                                             0x1a
6049 #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
6050 #define CB_HW_MEM_ARBITER_WR__MODE_MASK                                                                       0x00000003L
6051 #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
6052 #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
6053 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK                                                                  0x00000C00L
6054 #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK                                                                  0x00003000L
6055 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK                                                                  0x0000C000L
6056 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK                                                                  0x00030000L
6057 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
6058 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
6059 #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK                                                    0x00400000L
6060 #define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK                                                                  0x03800000L
6061 #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK                                                               0x1C000000L
6062 #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
6063 //CB_DCC_CONFIG
6064 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT                                                        0x0
6065 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT                                                      0x5
6066 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT                                               0x6
6067 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT                                                       0x8
6068 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT                                                     0x10
6069 #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT                                                           0x18
6070 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT                                                              0x1c
6071 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK                                                          0x0000001FL
6072 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK                                                        0x00000020L
6073 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK                                                 0x00000040L
6074 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK                                                         0x0000FF00L
6075 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK                                                       0x007F0000L
6076 #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK                                                             0x0F000000L
6077 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK                                                                0xF0000000L
6078 //GC_USER_RB_REDUNDANCY
6079 #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                              0x8
6080 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                          0xc
6081 #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                              0x10
6082 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                          0x14
6083 #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK                                                                0x00000F00L
6084 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                            0x00001000L
6085 #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK                                                                0x000F0000L
6086 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                            0x00100000L
6087 //GC_USER_RB_BACKEND_DISABLE
6088 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                    0x10
6089 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                      0x00FF0000L
6090 
6091 
6092 // addressBlock: gc_rmi_rmidec
6093 //RMI_GENERAL_CNTL
6094 #define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT                                                                0x0
6095 #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT                                                           0x1
6096 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT                                                              0x11
6097 #define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT                                                               0x13
6098 #define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT                                                               0x14
6099 #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT                                                     0x15
6100 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT                                                       0x19
6101 #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT                                              0x1a
6102 #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1b
6103 #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT                                              0x1c
6104 #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1d
6105 #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT                                       0x1e
6106 #define RMI_GENERAL_CNTL__BURST_DISABLE_MASK                                                                  0x00000001L
6107 #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK                                                             0x0001FFFEL
6108 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK                                                                0x00060000L
6109 #define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK                                                                 0x00080000L
6110 #define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK                                                                 0x00100000L
6111 #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK                                                       0x01E00000L
6112 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK                                                         0x02000000L
6113 #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK                                                0x04000000L
6114 #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK                                               0x08000000L
6115 #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK                                                0x10000000L
6116 #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK                                               0x20000000L
6117 #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK                                         0x40000000L
6118 //RMI_GENERAL_CNTL1
6119 #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT                                                0x0
6120 #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT                                                     0x4
6121 #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT                                                     0x6
6122 #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT                                            0x8
6123 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT                                                       0x9
6124 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT                                                             0xa
6125 #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT                                           0xb
6126 #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT                                           0xc
6127 #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK                                                  0x0000000FL
6128 #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK                                                       0x00000030L
6129 #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK                                                       0x000000C0L
6130 #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK                                              0x00000100L
6131 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK                                                         0x00000200L
6132 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK                                                               0x00000400L
6133 #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK                                             0x00000800L
6134 #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK                                             0x00001000L
6135 //RMI_GENERAL_STATUS
6136 #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT                                                0x0
6137 #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT                                                 0x1
6138 #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT                                                0x2
6139 #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT                                                 0x3
6140 #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT                                                0x4
6141 #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT                                                              0x5
6142 #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT                                                             0x6
6143 #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT                                                        0x7
6144 #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT                                                        0x8
6145 #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT                                                           0x9
6146 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT                                                       0xa
6147 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xb
6148 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xc
6149 #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT                                                        0xd
6150 #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT                                                           0xe
6151 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT                                                       0xf
6152 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT                                                 0x10
6153 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT                                                 0x11
6154 #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT                                                            0x12
6155 #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT                                                            0x13
6156 #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT                                                             0x14
6157 #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT                                                        0x15
6158 #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT                                                           0x1d
6159 #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT                                                            0x1e
6160 #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT                                          0x1f
6161 #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK                                                  0x00000001L
6162 #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK                                                   0x00000002L
6163 #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK                                                  0x00000004L
6164 #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK                                                   0x00000008L
6165 #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK                                                  0x00000010L
6166 #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK                                                                0x00000020L
6167 #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK                                                               0x00000040L
6168 #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK                                                          0x00000080L
6169 #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK                                                          0x00000100L
6170 #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK                                                             0x00000200L
6171 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK                                                         0x00000400L
6172 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00000800L
6173 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00001000L
6174 #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK                                                          0x00002000L
6175 #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK                                                             0x00004000L
6176 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK                                                         0x00008000L
6177 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK                                                   0x00010000L
6178 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK                                                   0x00020000L
6179 #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK                                                              0x00040000L
6180 #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK                                                              0x00080000L
6181 #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK                                                               0x00100000L
6182 #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK                                                          0x1FE00000L
6183 #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK                                                             0x20000000L
6184 #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK                                                              0x40000000L
6185 #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK                                            0x80000000L
6186 //RMI_SUBBLOCK_STATUS0
6187 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT                                     0x0
6188 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT                                         0x7
6189 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT                                        0x8
6190 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT                                     0x9
6191 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT                                         0x10
6192 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT                                        0x11
6193 #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT                                                       0x12
6194 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK                                       0x0000007FL
6195 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK                                           0x00000080L
6196 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK                                          0x00000100L
6197 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK                                       0x0000FE00L
6198 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK                                           0x00010000L
6199 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK                                          0x00020000L
6200 #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK                                                         0x0FFC0000L
6201 //RMI_SUBBLOCK_STATUS1
6202 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT                                                   0x0
6203 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT                                                   0xa
6204 #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT                                                       0x14
6205 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK                                                     0x000003FFL
6206 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK                                                     0x000FFC00L
6207 #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK                                                         0x3FF00000L
6208 //RMI_SUBBLOCK_STATUS2
6209 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT                                                      0x0
6210 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT                                                      0x9
6211 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK                                                        0x000001FFL
6212 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK                                                        0x0003FE00L
6213 //RMI_SUBBLOCK_STATUS3
6214 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT                                             0x0
6215 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT                                             0xa
6216 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK                                               0x000003FFL
6217 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK                                               0x000FFC00L
6218 //RMI_XBAR_CONFIG
6219 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT                                                      0x0
6220 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT                                             0x2
6221 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT                                                0x6
6222 #define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT                                                                   0x7
6223 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT                                                                0x8
6224 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT                                                       0xc
6225 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT                                                                0xd
6226 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT                                                                0xe
6227 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK                                                        0x00000003L
6228 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK                                               0x0000003CL
6229 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK                                                  0x00000040L
6230 #define RMI_XBAR_CONFIG__ARBITER_DIS_MASK                                                                     0x00000080L
6231 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK                                                                  0x00000F00L
6232 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK                                                         0x00001000L
6233 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK                                                                  0x00002000L
6234 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK                                                                  0x00004000L
6235 //RMI_PROBE_POP_LOGIC_CNTL
6236 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT                                             0x0
6237 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT                                                    0x7
6238 #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT                                      0x8
6239 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT                                             0xa
6240 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT                                                    0x11
6241 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK                                               0x0000007FL
6242 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK                                                      0x00000080L
6243 #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK                                        0x00000300L
6244 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK                                               0x0001FC00L
6245 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK                                                      0x00020000L
6246 //RMI_UTC_XNACK_N_MISC_CNTL
6247 #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT                                              0x0
6248 #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT                                         0x8
6249 #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT                                                     0xc
6250 #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT                                       0xd
6251 #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK                                                0x000000FFL
6252 #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK                                           0x00000F00L
6253 #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK                                                       0x00001000L
6254 #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK                                         0x00002000L
6255 //RMI_DEMUX_CNTL
6256 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT                                                               0x0
6257 #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x1
6258 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                                0x4
6259 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT                                             0x6
6260 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT                                                                0xe
6261 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT                                                               0x10
6262 #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x11
6263 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                                0x14
6264 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT                                             0x16
6265 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT                                                                0x1e
6266 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK                                                                 0x00000001L
6267 #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00000002L
6268 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK                                                  0x00000030L
6269 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK                                               0x00003FC0L
6270 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK                                                                  0x0000C000L
6271 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK                                                                 0x00010000L
6272 #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00020000L
6273 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK                                                  0x00300000L
6274 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK                                               0x3FC00000L
6275 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK                                                                  0xC0000000L
6276 //RMI_UTCL1_CNTL1
6277 #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
6278 #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                                 0x1
6279 #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
6280 #define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                     0x3
6281 #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
6282 #define RMI_UTCL1_CNTL1__CLIENTID__SHIFT                                                                      0x7
6283 #define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT                                                                    0x10
6284 #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                             0x11
6285 #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                          0x12
6286 #define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
6287 #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
6288 #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
6289 #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
6290 #define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
6291 #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                0x1b
6292 #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
6293 #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
6294 #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
6295 #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                                   0x00000002L
6296 #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
6297 #define RMI_UTCL1_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
6298 #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
6299 #define RMI_UTCL1_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
6300 #define RMI_UTCL1_CNTL1__USERVM_DIS_MASK                                                                      0x00010000L
6301 #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                               0x00020000L
6302 #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                            0x00040000L
6303 #define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
6304 #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
6305 #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
6306 #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
6307 #define RMI_UTCL1_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
6308 #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                  0x08000000L
6309 #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
6310 #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
6311 //RMI_UTCL1_CNTL2
6312 #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT                                                                     0x0
6313 #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
6314 #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                    0xa
6315 #define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                       0xb
6316 #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
6317 #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                 0xd
6318 #define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
6319 #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
6320 #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT                                                          0x10
6321 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT                                                 0x12
6322 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT                                                        0x13
6323 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT                                                  0x14
6324 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT                                                         0x15
6325 #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT                                                         0x19
6326 #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT                                                    0x1a
6327 #define RMI_UTCL1_CNTL2__UTC_SPARE_MASK                                                                       0x000000FFL
6328 #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
6329 #define RMI_UTCL1_CNTL2__LINE_VALID_MASK                                                                      0x00000400L
6330 #define RMI_UTCL1_CNTL2__DIS_EDC_MASK                                                                         0x00000800L
6331 #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
6332 #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                                   0x00002000L
6333 #define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
6334 #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
6335 #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK                                                            0x00030000L
6336 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK                                                   0x00040000L
6337 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK                                                          0x00080000L
6338 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK                                                    0x00100000L
6339 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK                                                           0x01E00000L
6340 #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK                                                           0x02000000L
6341 #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK                                                      0x04000000L
6342 //RMI_UTC_UNIT_CONFIG
6343 //RMI_TCIW_FORMATTER0_CNTL
6344 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT                                             0x0
6345 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT                                          0x1
6346 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
6347 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT                                         0x13
6348 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
6349 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT                                                  0x1c
6350 #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT                                                  0x1d
6351 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
6352 #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT                                                  0x1f
6353 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK                                               0x00000001L
6354 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK                                            0x000001FEL
6355 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
6356 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK                                           0x07F80000L
6357 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
6358 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK                                                    0x10000000L
6359 #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK                                                    0x20000000L
6360 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
6361 #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK                                                    0x80000000L
6362 //RMI_TCIW_FORMATTER1_CNTL
6363 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT                                             0x0
6364 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT                                          0x1
6365 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
6366 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT                                         0x13
6367 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
6368 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT                                                  0x1c
6369 #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT                                                  0x1d
6370 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
6371 #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT                                                  0x1f
6372 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK                                               0x00000001L
6373 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK                                            0x000001FEL
6374 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
6375 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK                                           0x07F80000L
6376 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
6377 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK                                                    0x10000000L
6378 #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK                                                    0x20000000L
6379 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
6380 #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK                                                    0x80000000L
6381 //RMI_SCOREBOARD_CNTL
6382 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT                                                        0x0
6383 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT                                              0x1
6384 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT                                                        0x2
6385 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT                                              0x3
6386 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT                                                      0x4
6387 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT                                         0x5
6388 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT                                      0x6
6389 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT                                                      0x7
6390 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT                                                  0x8
6391 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT                                   0x9
6392 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK                                                          0x00000001L
6393 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK                                                0x00000002L
6394 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK                                                          0x00000004L
6395 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK                                                0x00000008L
6396 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK                                                        0x00000010L
6397 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK                                           0x00000020L
6398 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK                                        0x00000040L
6399 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK                                                        0x00000080L
6400 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK                                                    0x00000100L
6401 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK                                     0x001FFE00L
6402 //RMI_SCOREBOARD_STATUS0
6403 #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT                                                     0x0
6404 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT                                                    0x1
6405 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT                                                   0x2
6406 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT                                                   0x12
6407 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT                                                       0x13
6408 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT                                                 0x14
6409 #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT                                                    0x15
6410 #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK                                                       0x00000001L
6411 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK                                                      0x00000002L
6412 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK                                                     0x0003FFFCL
6413 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK                                                     0x00040000L
6414 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK                                                         0x00080000L
6415 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK                                                   0x00100000L
6416 #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK                                                      0x00200000L
6417 //RMI_SCOREBOARD_STATUS1
6418 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT                                                        0x0
6419 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT                                              0xc
6420 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT                                               0xd
6421 #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT                                      0xe
6422 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT                                                        0xf
6423 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT                                              0x1b
6424 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT                                               0x1c
6425 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT                                                  0x1d
6426 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT                                                  0x1e
6427 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK                                                          0x00000FFFL
6428 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK                                                0x00001000L
6429 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK                                                 0x00002000L
6430 #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK                                        0x00004000L
6431 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK                                                          0x07FF8000L
6432 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK                                                0x08000000L
6433 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK                                                 0x10000000L
6434 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK                                                    0x20000000L
6435 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK                                                    0x40000000L
6436 //RMI_SCOREBOARD_STATUS2
6437 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT                                                       0x0
6438 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT                                             0xc
6439 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT                                                       0xd
6440 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT                                             0x19
6441 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT                                                     0x1a
6442 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT                                                     0x1b
6443 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT                                           0x1c
6444 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT                                           0x1d
6445 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT                                              0x1e
6446 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT                                              0x1f
6447 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK                                                         0x00000FFFL
6448 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK                                               0x00001000L
6449 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK                                                         0x01FFE000L
6450 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK                                               0x02000000L
6451 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK                                                       0x04000000L
6452 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK                                                       0x08000000L
6453 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK                                             0x10000000L
6454 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK                                             0x20000000L
6455 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK                                                0x40000000L
6456 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK                                                0x80000000L
6457 //RMI_XBAR_ARBITER_CONFIG
6458 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT                                                        0x0
6459 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x2
6460 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT                                                       0x3
6461 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x4
6462 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                        0x6
6463 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT                                     0x8
6464 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT                                                        0x10
6465 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x12
6466 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT                                                       0x13
6467 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x14
6468 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                        0x16
6469 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT                                     0x18
6470 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK                                                          0x00000003L
6471 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00000004L
6472 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK                                                         0x00000008L
6473 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                           0x00000010L
6474 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK                                          0x000000C0L
6475 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK                                       0x0000FF00L
6476 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK                                                          0x00030000L
6477 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00040000L
6478 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK                                                         0x00080000L
6479 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                           0x00100000L
6480 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK                                          0x00C00000L
6481 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK                                       0xFF000000L
6482 //RMI_XBAR_ARBITER_CONFIG_1
6483 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT                                  0x0
6484 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT                                  0x8
6485 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT                                  0x10
6486 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT                                  0x18
6487 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK                                    0x000000FFL
6488 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK                                    0x0000FF00L
6489 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK                                    0x00FF0000L
6490 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK                                    0xFF000000L
6491 //RMI_CLOCK_CNTRL
6492 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT                                                         0x0
6493 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT                                                         0x5
6494 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT                                                       0xa
6495 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT                                                       0xf
6496 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT                                                         0x14
6497 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT                                                       0x19
6498 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK                                                           0x0000001FL
6499 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK                                                           0x000003E0L
6500 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK                                                         0x00007C00L
6501 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK                                                         0x000F8000L
6502 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK                                                           0x01F00000L
6503 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK                                                         0x3E000000L
6504 //RMI_UTCL1_STATUS
6505 #define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
6506 #define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
6507 #define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
6508 #define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
6509 #define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
6510 #define RMI_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
6511 //RMI_XNACK_DEBUG
6512 #define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT                                                                0x0
6513 #define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK                                                                  0x0000FFFFL
6514 //RMI_SPARE
6515 #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT                                     0x0
6516 #define RMI_SPARE__SPARE_BIT_1__SHIFT                                                                         0x1
6517 #define RMI_SPARE__SPARE_BIT_2__SHIFT                                                                         0x2
6518 #define RMI_SPARE__SPARE_BIT_3__SHIFT                                                                         0x3
6519 #define RMI_SPARE__SPARE_BIT_4__SHIFT                                                                         0x4
6520 #define RMI_SPARE__SPARE_BIT_5__SHIFT                                                                         0x5
6521 #define RMI_SPARE__SPARE_BIT_6__SHIFT                                                                         0x6
6522 #define RMI_SPARE__SPARE_BIT_7__SHIFT                                                                         0x7
6523 #define RMI_SPARE__SPARE_BIT_8_0__SHIFT                                                                       0x8
6524 #define RMI_SPARE__SPARE_BIT_16_0__SHIFT                                                                      0x10
6525 #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK                                       0x00000001L
6526 #define RMI_SPARE__SPARE_BIT_1_MASK                                                                           0x00000002L
6527 #define RMI_SPARE__SPARE_BIT_2_MASK                                                                           0x00000004L
6528 #define RMI_SPARE__SPARE_BIT_3_MASK                                                                           0x00000008L
6529 #define RMI_SPARE__SPARE_BIT_4_MASK                                                                           0x00000010L
6530 #define RMI_SPARE__SPARE_BIT_5_MASK                                                                           0x00000020L
6531 #define RMI_SPARE__SPARE_BIT_6_MASK                                                                           0x00000040L
6532 #define RMI_SPARE__SPARE_BIT_7_MASK                                                                           0x00000080L
6533 #define RMI_SPARE__SPARE_BIT_8_0_MASK                                                                         0x0000FF00L
6534 #define RMI_SPARE__SPARE_BIT_16_0_MASK                                                                        0xFFFF0000L
6535 //RMI_SPARE_1
6536 #define RMI_SPARE_1__SPARE_BIT_8__SHIFT                                                                       0x0
6537 #define RMI_SPARE_1__SPARE_BIT_9__SHIFT                                                                       0x1
6538 #define RMI_SPARE_1__SPARE_BIT_10__SHIFT                                                                      0x2
6539 #define RMI_SPARE_1__SPARE_BIT_11__SHIFT                                                                      0x3
6540 #define RMI_SPARE_1__SPARE_BIT_12__SHIFT                                                                      0x4
6541 #define RMI_SPARE_1__SPARE_BIT_13__SHIFT                                                                      0x5
6542 #define RMI_SPARE_1__SPARE_BIT_14__SHIFT                                                                      0x6
6543 #define RMI_SPARE_1__SPARE_BIT_15__SHIFT                                                                      0x7
6544 #define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT                                                                     0x8
6545 #define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT                                                                    0x10
6546 #define RMI_SPARE_1__SPARE_BIT_8_MASK                                                                         0x00000001L
6547 #define RMI_SPARE_1__SPARE_BIT_9_MASK                                                                         0x00000002L
6548 #define RMI_SPARE_1__SPARE_BIT_10_MASK                                                                        0x00000004L
6549 #define RMI_SPARE_1__SPARE_BIT_11_MASK                                                                        0x00000008L
6550 #define RMI_SPARE_1__SPARE_BIT_12_MASK                                                                        0x00000010L
6551 #define RMI_SPARE_1__SPARE_BIT_13_MASK                                                                        0x00000020L
6552 #define RMI_SPARE_1__SPARE_BIT_14_MASK                                                                        0x00000040L
6553 #define RMI_SPARE_1__SPARE_BIT_15_MASK                                                                        0x00000080L
6554 #define RMI_SPARE_1__SPARE_BIT_8_1_MASK                                                                       0x0000FF00L
6555 #define RMI_SPARE_1__SPARE_BIT_16_1_MASK                                                                      0xFFFF0000L
6556 //RMI_SPARE_2
6557 #define RMI_SPARE_2__SPARE_BIT_16__SHIFT                                                                      0x0
6558 #define RMI_SPARE_2__SPARE_BIT_17__SHIFT                                                                      0x1
6559 #define RMI_SPARE_2__SPARE_BIT_18__SHIFT                                                                      0x2
6560 #define RMI_SPARE_2__SPARE_BIT_19__SHIFT                                                                      0x3
6561 #define RMI_SPARE_2__SPARE_BIT_20__SHIFT                                                                      0x4
6562 #define RMI_SPARE_2__SPARE_BIT_21__SHIFT                                                                      0x5
6563 #define RMI_SPARE_2__SPARE_BIT_22__SHIFT                                                                      0x6
6564 #define RMI_SPARE_2__SPARE_BIT_23__SHIFT                                                                      0x7
6565 #define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT                                                                     0x8
6566 #define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT                                                                     0xc
6567 #define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT                                                                     0x10
6568 #define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT                                                                     0x18
6569 #define RMI_SPARE_2__SPARE_BIT_16_MASK                                                                        0x00000001L
6570 #define RMI_SPARE_2__SPARE_BIT_17_MASK                                                                        0x00000002L
6571 #define RMI_SPARE_2__SPARE_BIT_18_MASK                                                                        0x00000004L
6572 #define RMI_SPARE_2__SPARE_BIT_19_MASK                                                                        0x00000008L
6573 #define RMI_SPARE_2__SPARE_BIT_20_MASK                                                                        0x00000010L
6574 #define RMI_SPARE_2__SPARE_BIT_21_MASK                                                                        0x00000020L
6575 #define RMI_SPARE_2__SPARE_BIT_22_MASK                                                                        0x00000040L
6576 #define RMI_SPARE_2__SPARE_BIT_23_MASK                                                                        0x00000080L
6577 #define RMI_SPARE_2__SPARE_BIT_4_0_MASK                                                                       0x00000F00L
6578 #define RMI_SPARE_2__SPARE_BIT_4_1_MASK                                                                       0x0000F000L
6579 #define RMI_SPARE_2__SPARE_BIT_8_2_MASK                                                                       0x00FF0000L
6580 #define RMI_SPARE_2__SPARE_BIT_8_3_MASK                                                                       0xFF000000L
6581 
6582 
6583 // addressBlock: gc_utcl2_atcl2dec
6584 //ATC_L2_CNTL
6585 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                               0x0
6586 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                              0x3
6587 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                                   0x6
6588 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                                  0x7
6589 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                             0x8
6590 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                          0xb
6591 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                                 0x00000003L
6592 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                                0x00000018L
6593 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                     0x00000040L
6594 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                                    0x00000080L
6595 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                               0x00000700L
6596 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                            0x00000800L
6597 //ATC_L2_CNTL2
6598 #define ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                                      0x0
6599 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                             0x6
6600 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                              0x8
6601 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                                     0x9
6602 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                               0xc
6603 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                         0xf
6604 #define ATC_L2_CNTL2__BANK_SELECT_MASK                                                                        0x0000003FL
6605 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                               0x000000C0L
6606 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                                0x00000100L
6607 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                                       0x00000E00L
6608 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                                 0x00007000L
6609 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                           0x001F8000L
6610 //ATC_L2_CACHE_DATA0
6611 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                        0x0
6612 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                          0x1
6613 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                          0x2
6614 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                                  0x17
6615 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                          0x00000001L
6616 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                            0x00000002L
6617 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                            0x007FFFFCL
6618 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                                    0x07800000L
6619 //ATC_L2_CACHE_DATA1
6620 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                                   0x0
6621 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                                     0xFFFFFFFFL
6622 //ATC_L2_CACHE_DATA2
6623 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                                      0x0
6624 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                        0xFFFFFFFFL
6625 //ATC_L2_CNTL3
6626 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                                  0x0
6627 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                        0x3
6628 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                                    0x00000007L
6629 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                          0x000001F8L
6630 //ATC_L2_STATUS
6631 #define ATC_L2_STATUS__BUSY__SHIFT                                                                            0x0
6632 #define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT                                                               0x1
6633 #define ATC_L2_STATUS__BUSY_MASK                                                                              0x00000001L
6634 #define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK                                                                 0x3FFFFFFEL
6635 //ATC_L2_STATUS2
6636 #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                              0x0
6637 #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                                  0x8
6638 #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                                0x000000FFL
6639 #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                                    0x0000FF00L
6640 //ATC_L2_MISC_CG
6641 #define ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                         0x6
6642 #define ATC_L2_MISC_CG__ENABLE__SHIFT                                                                         0x12
6643 #define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                                  0x13
6644 #define ATC_L2_MISC_CG__OFFDLY_MASK                                                                           0x00000FC0L
6645 #define ATC_L2_MISC_CG__ENABLE_MASK                                                                           0x00040000L
6646 #define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                                    0x00080000L
6647 //ATC_L2_MEM_POWER_LS
6648 #define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                                  0x0
6649 #define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                                   0x6
6650 #define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                                    0x0000003FL
6651 #define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                                     0x00000FC0L
6652 //ATC_L2_CGTT_CLK_CTRL
6653 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
6654 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
6655 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                            0xf
6656 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                      0x10
6657 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                            0x18
6658 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
6659 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
6660 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                              0x00008000L
6661 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                        0x00FF0000L
6662 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                              0xFF000000L
6663 
6664 
6665 // addressBlock: gc_utcl2_vml2pfdec
6666 //VM_L2_CNTL
6667 #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                    0x0
6668 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                      0x1
6669 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                      0x2
6670 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                      0x4
6671 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                                  0x8
6672 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                            0x9
6673 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                           0xa
6674 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                           0xb
6675 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                           0xc
6676 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                            0xf
6677 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                           0x12
6678 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                      0x13
6679 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                        0x15
6680 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                             0x1a
6681 #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                                      0x00000001L
6682 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                        0x00000002L
6683 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                        0x0000000CL
6684 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                        0x00000030L
6685 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                                    0x00000100L
6686 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                              0x00000200L
6687 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                             0x00000400L
6688 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                             0x00000800L
6689 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                             0x00007000L
6690 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                              0x00038000L
6691 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                             0x00040000L
6692 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                        0x00180000L
6693 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                          0x03E00000L
6694 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                               0x0C000000L
6695 //VM_L2_CNTL2
6696 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                            0x0
6697 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                               0x1
6698 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                                     0x15
6699 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                                   0x16
6700 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                            0x17
6701 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                             0x1a
6702 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c
6703 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                              0x00000001L
6704 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                                 0x00000002L
6705 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                       0x00200000L
6706 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                                     0x00400000L
6707 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                              0x03800000L
6708 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                               0x0C000000L
6709 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                            0x70000000L
6710 //VM_L2_CNTL3
6711 #define VM_L2_CNTL3__BANK_SELECT__SHIFT                                                                       0x0
6712 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                              0x6
6713 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                          0x8
6714 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                       0xf
6715 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                       0x14
6716 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15
6717 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                      0x18
6718 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                            0x1c
6719 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                          0x1d
6720 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                              0x1e
6721 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                         0x1f
6722 #define VM_L2_CNTL3__BANK_SELECT_MASK                                                                         0x0000003FL
6723 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                                0x000000C0L
6724 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                            0x00001F00L
6725 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                         0x000F8000L
6726 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                         0x00100000L
6727 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L
6728 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L
6729 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                              0x10000000L
6730 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                            0x20000000L
6731 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                                0x40000000L
6732 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                           0x80000000L
6733 //VM_L2_STATUS
6734 #define VM_L2_STATUS__L2_BUSY__SHIFT                                                                          0x0
6735 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                              0x1
6736 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                                 0x11
6737 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                               0x12
6738 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                                   0x13
6739 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                                   0x14
6740 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                                   0x15
6741 #define VM_L2_STATUS__L2_BUSY_MASK                                                                            0x00000001L
6742 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                                0x0001FFFEL
6743 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                                   0x00020000L
6744 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                                 0x00040000L
6745 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                                     0x00080000L
6746 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                                     0x00100000L
6747 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                                     0x00200000L
6748 //VM_DUMMY_PAGE_FAULT_CNTL
6749 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                              0x0
6750 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                           0x1
6751 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                              0x2
6752 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                                0x00000001L
6753 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                             0x00000002L
6754 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                                0x000000FCL
6755 //VM_DUMMY_PAGE_FAULT_ADDR_LO32
6756 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                            0x0
6757 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                              0xFFFFFFFFL
6758 //VM_DUMMY_PAGE_FAULT_ADDR_HI32
6759 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                             0x0
6760 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                               0x0000000FL
6761 //VM_L2_PROTECTION_FAULT_CNTL
6762 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                0x0
6763 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT             0x1
6764 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x2
6765 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x3
6766 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x4
6767 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x5
6768 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                 0x6
6769 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x7
6770 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                        0x8
6771 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x9
6772 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0xa
6773 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0xb
6774 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
6775 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                                0xd
6776 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                          0x1d
6777 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                           0x1e
6778 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                              0x1f
6779 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                  0x00000001L
6780 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK               0x00000002L
6781 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000004L
6782 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000008L
6783 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000010L
6784 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000020L
6785 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                   0x00000040L
6786 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000080L
6787 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                          0x00000100L
6788 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000200L
6789 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000400L
6790 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000800L
6791 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
6792 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                                  0x1FFFE000L
6793 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                            0x20000000L
6794 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                             0x40000000L
6795 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                                0x80000000L
6796 //VM_L2_PROTECTION_FAULT_CNTL2
6797 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                                    0x0
6798 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                              0x10
6799 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                        0x11
6800 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                             0x12
6801 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                                     0x13
6802 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                      0x0000FFFFL
6803 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                0x00010000L
6804 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                          0x00020000L
6805 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                               0x00040000L
6806 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                                       0x00080000L
6807 //VM_L2_PROTECTION_FAULT_MM_CNTL3
6808 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                  0x0
6809 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                    0xFFFFFFFFL
6810 //VM_L2_PROTECTION_FAULT_MM_CNTL4
6811 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                 0x0
6812 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                   0xFFFFFFFFL
6813 //VM_L2_PROTECTION_FAULT_STATUS
6814 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                                     0x0
6815 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                                    0x1
6816 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                               0x4
6817 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                                   0x8
6818 #define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                             0x9
6819 #define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                              0x12
6820 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                          0x13
6821 #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                            0x14
6822 #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                              0x18
6823 #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                            0x19
6824 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                                       0x00000001L
6825 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                                      0x0000000EL
6826 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                                 0x000000F0L
6827 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                                     0x00000100L
6828 #define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                               0x0003FE00L
6829 #define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                                0x00040000L
6830 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                            0x00080000L
6831 #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                              0x00F00000L
6832 #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                                0x01000000L
6833 #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                              0x1E000000L
6834 //VM_L2_PROTECTION_FAULT_ADDR_LO32
6835 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                                       0x0
6836 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                         0xFFFFFFFFL
6837 //VM_L2_PROTECTION_FAULT_ADDR_HI32
6838 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                        0x0
6839 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                          0x0000000FL
6840 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
6841 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                              0x0
6842 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                                0xFFFFFFFFL
6843 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
6844 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                               0x0
6845 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                                 0x0000000FL
6846 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
6847 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
6848 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
6849 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
6850 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
6851 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
6852 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
6853 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
6854 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
6855 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
6856 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
6857 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
6858 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
6859 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                         0x0
6860 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                           0xFFFFFFFFL
6861 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
6862 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                          0x0
6863 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                            0x0000000FL
6864 //VM_L2_CNTL4
6865 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                       0x0
6866 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                                      0x6
6867 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                                      0x7
6868 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                           0x8
6869 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                          0x12
6870 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                               0x1c
6871 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                         0x0000003FL
6872 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                        0x00000040L
6873 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                        0x00000080L
6874 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                             0x0003FF00L
6875 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                            0x0FFC0000L
6876 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                                 0x10000000L
6877 //VM_L2_MM_GROUP_RT_CLASSES
6878 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                                    0x0
6879 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                                    0x1
6880 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                                    0x2
6881 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                                    0x3
6882 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                                    0x4
6883 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                                    0x5
6884 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                                    0x6
6885 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                                    0x7
6886 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                                    0x8
6887 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                                    0x9
6888 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                                   0xa
6889 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                                   0xb
6890 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                                   0xc
6891 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                                   0xd
6892 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                                   0xe
6893 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                                   0xf
6894 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                                   0x10
6895 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                                   0x11
6896 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                                   0x12
6897 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                                   0x13
6898 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                                   0x14
6899 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                                   0x15
6900 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                                   0x16
6901 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                                   0x17
6902 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                                   0x18
6903 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                                   0x19
6904 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                                   0x1a
6905 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                                   0x1b
6906 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                                   0x1c
6907 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                                   0x1d
6908 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                                   0x1e
6909 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                                   0x1f
6910 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                                      0x00000001L
6911 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                                      0x00000002L
6912 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                                      0x00000004L
6913 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                                      0x00000008L
6914 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                                      0x00000010L
6915 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                                      0x00000020L
6916 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                                      0x00000040L
6917 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                                      0x00000080L
6918 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                                      0x00000100L
6919 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                                      0x00000200L
6920 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                                     0x00000400L
6921 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                                     0x00000800L
6922 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                                     0x00001000L
6923 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                                     0x00002000L
6924 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                                     0x00004000L
6925 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                                     0x00008000L
6926 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                                     0x00010000L
6927 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                                     0x00020000L
6928 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                                     0x00040000L
6929 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                                     0x00080000L
6930 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                                     0x00100000L
6931 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                                     0x00200000L
6932 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                                     0x00400000L
6933 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                                     0x00800000L
6934 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                                     0x01000000L
6935 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                                     0x02000000L
6936 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                                     0x04000000L
6937 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                                     0x08000000L
6938 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                                     0x10000000L
6939 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                                     0x20000000L
6940 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                                     0x40000000L
6941 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                                     0x80000000L
6942 //VM_L2_BANK_SELECT_RESERVED_CID
6943 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                        0x0
6944 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                                       0xa
6945 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                         0x14
6946 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                               0x18
6947 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                            0x19
6948 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                          0x000001FFL
6949 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                         0x0007FC00L
6950 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                           0x00100000L
6951 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                                 0x01000000L
6952 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                              0x02000000L
6953 //VM_L2_BANK_SELECT_RESERVED_CID2
6954 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                                       0x0
6955 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                                      0xa
6956 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                        0x14
6957 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                              0x18
6958 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                           0x19
6959 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                         0x000001FFL
6960 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                        0x0007FC00L
6961 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                          0x00100000L
6962 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                                0x01000000L
6963 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                             0x02000000L
6964 //VM_L2_CACHE_PARITY_CNTL
6965 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                                 0x0
6966 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                               0x1
6967 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                                    0x2
6968 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                                 0x3
6969 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                               0x4
6970 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                                    0x5
6971 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                                      0x6
6972 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                                    0x9
6973 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                                     0xc
6974 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                                   0x00000001L
6975 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                                 0x00000002L
6976 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                                      0x00000004L
6977 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                                   0x00000008L
6978 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                                 0x00000010L
6979 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                                      0x00000020L
6980 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                        0x000001C0L
6981 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                                      0x00000E00L
6982 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                                       0x0000F000L
6983 //VM_L2_CGTT_CLK_CTRL
6984 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
6985 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
6986 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                             0xf
6987 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                       0x10
6988 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                             0x18
6989 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
6990 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
6991 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                               0x00008000L
6992 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                         0x00FF0000L
6993 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                               0xFF000000L
6994 
6995 
6996 // addressBlock: gc_utcl2_vml2vcdec
6997 //VM_CONTEXT0_CNTL
6998 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
6999 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7000 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7001 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7002 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7003 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7004 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7005 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7006 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7007 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7008 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7009 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7010 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7011 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7012 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7013 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7014 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7015 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7016 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7017 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7018 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7019 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7020 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7021 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7022 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7023 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7024 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7025 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7026 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7027 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7028 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7029 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7030 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7031 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7032 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7033 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7034 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7035 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7036 //VM_CONTEXT1_CNTL
7037 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7038 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7039 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7040 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7041 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7042 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7043 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7044 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7045 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7046 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7047 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7048 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7049 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7050 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7051 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7052 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7053 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7054 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7055 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7056 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7057 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7058 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7059 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7060 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7061 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7062 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7063 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7064 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7065 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7066 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7067 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7068 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7069 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7070 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7071 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7072 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7073 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7074 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7075 //VM_CONTEXT2_CNTL
7076 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7077 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7078 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7079 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7080 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7081 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7082 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7083 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7084 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7085 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7086 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7087 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7088 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7089 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7090 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7091 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7092 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7093 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7094 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7095 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7096 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7097 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7098 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7099 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7100 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7101 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7102 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7103 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7104 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7105 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7106 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7107 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7108 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7109 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7110 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7111 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7112 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7113 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7114 //VM_CONTEXT3_CNTL
7115 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7116 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7117 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7118 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7119 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7120 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7121 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7122 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7123 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7124 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7125 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7126 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7127 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7128 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7129 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7130 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7131 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7132 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7133 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7134 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7135 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7136 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7137 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7138 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7139 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7140 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7141 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7142 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7143 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7144 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7145 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7146 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7147 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7148 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7149 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7150 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7151 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7152 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7153 //VM_CONTEXT4_CNTL
7154 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7155 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7156 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7157 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7158 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7159 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7160 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7161 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7162 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7163 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7164 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7165 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7166 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7167 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7168 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7169 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7170 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7171 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7172 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7173 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7174 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7175 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7176 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7177 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7178 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7179 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7180 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7181 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7182 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7183 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7184 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7185 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7186 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7187 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7188 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7189 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7190 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7191 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7192 //VM_CONTEXT5_CNTL
7193 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7194 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7195 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7196 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7197 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7198 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7199 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7200 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7201 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7202 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7203 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7204 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7205 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7206 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7207 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7208 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7209 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7210 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7211 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7212 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7213 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7214 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7215 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7216 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7217 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7218 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7219 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7220 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7221 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7222 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7223 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7224 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7225 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7226 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7227 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7228 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7229 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7230 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7231 //VM_CONTEXT6_CNTL
7232 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7233 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7234 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7235 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7236 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7237 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7238 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7239 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7240 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7241 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7242 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7243 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7244 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7245 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7246 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7247 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7248 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7249 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7250 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7251 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7252 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7253 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7254 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7255 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7256 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7257 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7258 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7259 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7260 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7261 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7262 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7263 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7264 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7265 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7266 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7267 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7268 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7269 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7270 //VM_CONTEXT7_CNTL
7271 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7272 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7273 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7274 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7275 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7276 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7277 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7278 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7279 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7280 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7281 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7282 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7283 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7284 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7285 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7286 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7287 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7288 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7289 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7290 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7291 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7292 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7293 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7294 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7295 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7296 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7297 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7298 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7299 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7300 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7301 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7302 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7303 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7304 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7305 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7306 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7307 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7308 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7309 //VM_CONTEXT8_CNTL
7310 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7311 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7312 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7313 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7314 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7315 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7316 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7317 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7318 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7319 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7320 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7321 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7322 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7323 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7324 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7325 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7326 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7327 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7328 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7329 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7330 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7331 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7332 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7333 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7334 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7335 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7336 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7337 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7338 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7339 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7340 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7341 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7342 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7343 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7344 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7345 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7346 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7347 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7348 //VM_CONTEXT9_CNTL
7349 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7350 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7351 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7352 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7353 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7354 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7355 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7356 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7357 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7358 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7359 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7360 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7361 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7362 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7363 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7364 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7365 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7366 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7367 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7368 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7369 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7370 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7371 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7372 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7373 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7374 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7375 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7376 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7377 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7378 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7379 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7380 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7381 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7382 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7383 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7384 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7385 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7386 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7387 //VM_CONTEXT10_CNTL
7388 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7389 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7390 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7391 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7392 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7393 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7394 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7395 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7396 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7397 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7398 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7399 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7400 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7401 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7402 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7403 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7404 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7405 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7406 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7407 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7408 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7409 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7410 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7411 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7412 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7413 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7414 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7415 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7416 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7417 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7418 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7419 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7420 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7421 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7422 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7423 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7424 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7425 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7426 //VM_CONTEXT11_CNTL
7427 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7428 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7429 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7430 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7431 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7432 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7433 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7434 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7435 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7436 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7437 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7438 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7439 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7440 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7441 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7442 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7443 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7444 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7445 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7446 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7447 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7448 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7449 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7450 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7451 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7452 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7453 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7454 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7455 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7456 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7457 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7458 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7459 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7460 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7461 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7462 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7463 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7464 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7465 //VM_CONTEXT12_CNTL
7466 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7467 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7468 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7469 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7470 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7471 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7472 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7473 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7474 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7475 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7476 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7477 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7478 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7479 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7480 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7481 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7482 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7483 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7484 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7485 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7486 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7487 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7488 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7489 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7490 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7491 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7492 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7493 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7494 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7495 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7496 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7497 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7498 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7499 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7500 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7501 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7502 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7503 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7504 //VM_CONTEXT13_CNTL
7505 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7506 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7507 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7508 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7509 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7510 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7511 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7512 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7513 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7514 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7515 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7516 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7517 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7518 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7519 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7520 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7521 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7522 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7523 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7524 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7525 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7526 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7527 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7528 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7529 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7530 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7531 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7532 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7533 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7534 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7535 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7536 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7537 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7538 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7539 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7540 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7541 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7542 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7543 //VM_CONTEXT14_CNTL
7544 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7545 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7546 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7547 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7548 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7549 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7550 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7551 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7552 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7553 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7554 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7555 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7556 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7557 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7558 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7559 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7560 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7561 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7562 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7563 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7564 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7565 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7566 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7567 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7568 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7569 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7570 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7571 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7572 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7573 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7574 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7575 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7576 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7577 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7578 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7579 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7580 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7581 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7582 //VM_CONTEXT15_CNTL
7583 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7584 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7585 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7586 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7587 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7588 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7589 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7590 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7591 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7592 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7593 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7594 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7595 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7596 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7597 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7598 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7599 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7600 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7601 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7602 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7603 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7604 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7605 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7606 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7607 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7608 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7609 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7610 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7611 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7612 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7613 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7614 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7615 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7616 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7617 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7618 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7619 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7620 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7621 //VM_CONTEXTS_DISABLE
7622 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                         0x0
7623 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                         0x1
7624 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                         0x2
7625 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                         0x3
7626 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                         0x4
7627 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                         0x5
7628 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                         0x6
7629 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                         0x7
7630 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                         0x8
7631 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                         0x9
7632 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                        0xa
7633 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                        0xb
7634 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                        0xc
7635 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                        0xd
7636 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                        0xe
7637 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                        0xf
7638 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                           0x00000001L
7639 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                           0x00000002L
7640 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                           0x00000004L
7641 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                           0x00000008L
7642 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                           0x00000010L
7643 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                           0x00000020L
7644 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                           0x00000040L
7645 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                           0x00000080L
7646 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                           0x00000100L
7647 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                           0x00000200L
7648 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                          0x00000400L
7649 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                          0x00000800L
7650 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                          0x00001000L
7651 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                          0x00002000L
7652 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                          0x00004000L
7653 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                          0x00008000L
7654 //VM_INVALIDATE_ENG0_SEM
7655 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                              0x0
7656 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                                0x00000001L
7657 //VM_INVALIDATE_ENG1_SEM
7658 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                              0x0
7659 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                                0x00000001L
7660 //VM_INVALIDATE_ENG2_SEM
7661 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                              0x0
7662 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                                0x00000001L
7663 //VM_INVALIDATE_ENG3_SEM
7664 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                              0x0
7665 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                                0x00000001L
7666 //VM_INVALIDATE_ENG4_SEM
7667 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                              0x0
7668 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                                0x00000001L
7669 //VM_INVALIDATE_ENG5_SEM
7670 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                              0x0
7671 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                                0x00000001L
7672 //VM_INVALIDATE_ENG6_SEM
7673 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                              0x0
7674 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                                0x00000001L
7675 //VM_INVALIDATE_ENG7_SEM
7676 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                              0x0
7677 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                                0x00000001L
7678 //VM_INVALIDATE_ENG8_SEM
7679 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                              0x0
7680 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                                0x00000001L
7681 //VM_INVALIDATE_ENG9_SEM
7682 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                              0x0
7683 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                                0x00000001L
7684 //VM_INVALIDATE_ENG10_SEM
7685 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                             0x0
7686 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                               0x00000001L
7687 //VM_INVALIDATE_ENG11_SEM
7688 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                             0x0
7689 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                               0x00000001L
7690 //VM_INVALIDATE_ENG12_SEM
7691 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                             0x0
7692 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                               0x00000001L
7693 //VM_INVALIDATE_ENG13_SEM
7694 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                             0x0
7695 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                               0x00000001L
7696 //VM_INVALIDATE_ENG14_SEM
7697 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                             0x0
7698 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                               0x00000001L
7699 //VM_INVALIDATE_ENG15_SEM
7700 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                             0x0
7701 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                               0x00000001L
7702 //VM_INVALIDATE_ENG16_SEM
7703 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                             0x0
7704 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                               0x00000001L
7705 //VM_INVALIDATE_ENG17_SEM
7706 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                             0x0
7707 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                               0x00000001L
7708 //VM_INVALIDATE_ENG0_REQ
7709 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7710 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7711 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7712 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7713 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7714 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7715 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7716 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7717 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7718 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7719 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7720 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7721 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7722 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7723 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7724 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7725 //VM_INVALIDATE_ENG1_REQ
7726 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7727 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7728 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7729 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7730 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7731 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7732 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7733 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7734 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7735 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7736 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7737 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7738 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7739 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7740 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7741 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7742 //VM_INVALIDATE_ENG2_REQ
7743 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7744 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7745 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7746 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7747 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7748 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7749 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7750 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7751 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7752 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7753 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7754 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7755 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7756 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7757 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7758 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7759 //VM_INVALIDATE_ENG3_REQ
7760 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7761 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7762 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7763 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7764 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7765 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7766 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7767 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7768 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7769 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7770 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7771 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7772 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7773 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7774 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7775 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7776 //VM_INVALIDATE_ENG4_REQ
7777 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7778 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7779 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7780 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7781 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7782 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7783 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7784 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7785 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7786 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7787 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7788 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7789 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7790 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7791 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7792 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7793 //VM_INVALIDATE_ENG5_REQ
7794 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7795 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7796 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7797 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7798 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7799 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7800 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7801 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7802 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7803 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7804 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7805 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7806 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7807 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7808 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7809 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7810 //VM_INVALIDATE_ENG6_REQ
7811 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7812 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7813 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7814 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7815 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7816 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7817 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7818 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7819 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7820 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7821 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7822 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7823 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7824 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7825 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7826 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7827 //VM_INVALIDATE_ENG7_REQ
7828 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7829 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7830 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7831 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7832 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7833 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7834 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7835 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7836 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7837 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7838 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7839 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7840 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7841 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7842 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7843 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7844 //VM_INVALIDATE_ENG8_REQ
7845 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7846 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7847 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7848 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7849 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7850 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7851 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7852 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7853 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7854 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7855 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7856 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7857 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7858 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7859 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7860 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7861 //VM_INVALIDATE_ENG9_REQ
7862 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7863 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7864 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7865 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7866 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7867 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7868 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7869 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7870 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7871 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7872 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7873 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7874 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7875 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7876 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7877 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7878 //VM_INVALIDATE_ENG10_REQ
7879 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7880 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7881 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7882 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7883 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7884 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7885 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7886 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7887 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7888 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7889 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7890 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7891 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7892 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7893 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7894 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7895 //VM_INVALIDATE_ENG11_REQ
7896 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7897 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7898 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7899 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7900 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7901 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7902 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7903 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7904 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7905 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7906 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7907 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7908 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7909 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7910 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7911 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7912 //VM_INVALIDATE_ENG12_REQ
7913 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7914 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7915 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7916 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7917 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7918 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7919 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7920 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7921 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7922 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7923 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7924 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7925 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7926 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7927 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7928 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7929 //VM_INVALIDATE_ENG13_REQ
7930 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7931 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7932 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7933 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7934 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7935 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7936 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7937 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7938 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7939 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7940 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7941 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7942 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7943 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7944 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7945 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7946 //VM_INVALIDATE_ENG14_REQ
7947 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7948 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7949 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7950 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7951 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7952 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7953 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7954 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7955 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7956 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7957 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7958 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7959 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7960 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7961 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7962 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7963 //VM_INVALIDATE_ENG15_REQ
7964 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7965 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7966 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7967 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7968 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7969 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7970 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7971 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7972 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7973 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7974 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7975 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7976 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7977 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7978 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7979 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7980 //VM_INVALIDATE_ENG16_REQ
7981 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7982 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7983 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7984 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7985 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7986 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7987 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7988 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7989 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7990 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7991 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7992 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7993 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7994 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7995 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7996 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7997 //VM_INVALIDATE_ENG17_REQ
7998 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7999 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                            0x10
8000 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
8001 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
8002 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
8003 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
8004 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
8005 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
8006 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
8007 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
8008 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
8009 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
8010 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
8011 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
8012 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
8013 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
8014 //VM_INVALIDATE_ENG0_ACK
8015 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8016 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                              0x10
8017 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8018 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                                0x00010000L
8019 //VM_INVALIDATE_ENG1_ACK
8020 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8021 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                              0x10
8022 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8023 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                                0x00010000L
8024 //VM_INVALIDATE_ENG2_ACK
8025 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8026 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                              0x10
8027 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8028 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                                0x00010000L
8029 //VM_INVALIDATE_ENG3_ACK
8030 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8031 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                              0x10
8032 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8033 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                                0x00010000L
8034 //VM_INVALIDATE_ENG4_ACK
8035 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8036 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                              0x10
8037 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8038 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                                0x00010000L
8039 //VM_INVALIDATE_ENG5_ACK
8040 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8041 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                              0x10
8042 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8043 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                                0x00010000L
8044 //VM_INVALIDATE_ENG6_ACK
8045 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8046 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                              0x10
8047 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8048 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                                0x00010000L
8049 //VM_INVALIDATE_ENG7_ACK
8050 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8051 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                              0x10
8052 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8053 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                                0x00010000L
8054 //VM_INVALIDATE_ENG8_ACK
8055 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8056 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                              0x10
8057 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8058 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                                0x00010000L
8059 //VM_INVALIDATE_ENG9_ACK
8060 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8061 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                              0x10
8062 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8063 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                                0x00010000L
8064 //VM_INVALIDATE_ENG10_ACK
8065 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8066 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                             0x10
8067 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8068 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                               0x00010000L
8069 //VM_INVALIDATE_ENG11_ACK
8070 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8071 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                             0x10
8072 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8073 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                               0x00010000L
8074 //VM_INVALIDATE_ENG12_ACK
8075 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8076 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                             0x10
8077 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8078 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                               0x00010000L
8079 //VM_INVALIDATE_ENG13_ACK
8080 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8081 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                             0x10
8082 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8083 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                               0x00010000L
8084 //VM_INVALIDATE_ENG14_ACK
8085 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8086 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                             0x10
8087 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8088 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                               0x00010000L
8089 //VM_INVALIDATE_ENG15_ACK
8090 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8091 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                             0x10
8092 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8093 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                               0x00010000L
8094 //VM_INVALIDATE_ENG16_ACK
8095 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8096 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                             0x10
8097 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8098 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                               0x00010000L
8099 //VM_INVALIDATE_ENG17_ACK
8100 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8101 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                             0x10
8102 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8103 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                               0x00010000L
8104 //VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
8105 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8106 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8107 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8108 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8109 //VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
8110 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8111 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8112 //VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
8113 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8114 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8115 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8116 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8117 //VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
8118 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8119 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8120 //VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
8121 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8122 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8123 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8124 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8125 //VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
8126 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8127 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8128 //VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
8129 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8130 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8131 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8132 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8133 //VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
8134 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8135 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8136 //VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
8137 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8138 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8139 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8140 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8141 //VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
8142 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8143 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8144 //VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
8145 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8146 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8147 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8148 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8149 //VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
8150 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8151 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8152 //VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
8153 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8154 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8155 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8156 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8157 //VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
8158 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8159 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8160 //VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
8161 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8162 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8163 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8164 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8165 //VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
8166 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8167 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8168 //VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
8169 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8170 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8171 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8172 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8173 //VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
8174 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8175 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8176 //VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
8177 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8178 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8179 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8180 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8181 //VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
8182 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8183 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8184 //VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
8185 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8186 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8187 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8188 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8189 //VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
8190 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8191 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8192 //VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
8193 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8194 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8195 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8196 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8197 //VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
8198 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8199 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8200 //VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
8201 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8202 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8203 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8204 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8205 //VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
8206 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8207 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8208 //VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
8209 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8210 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8211 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8212 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8213 //VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
8214 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8215 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8216 //VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
8217 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8218 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8219 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8220 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8221 //VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
8222 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8223 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8224 //VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
8225 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8226 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8227 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8228 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8229 //VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
8230 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8231 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8232 //VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
8233 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8234 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8235 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8236 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8237 //VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
8238 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8239 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8240 //VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
8241 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8242 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8243 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8244 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8245 //VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
8246 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8247 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8248 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
8249 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8250 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8251 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
8252 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8253 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8254 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
8255 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8256 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8257 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
8258 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8259 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8260 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
8261 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8262 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8263 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
8264 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8265 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8266 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
8267 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8268 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8269 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
8270 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8271 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8272 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
8273 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8274 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8275 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
8276 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8277 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8278 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
8279 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8280 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8281 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
8282 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8283 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8284 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
8285 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8286 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8287 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
8288 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8289 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8290 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
8291 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8292 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8293 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
8294 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8295 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8296 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
8297 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8298 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8299 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
8300 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8301 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8302 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
8303 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8304 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8305 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
8306 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8307 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8308 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
8309 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8310 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8311 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
8312 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8313 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8314 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
8315 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8316 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8317 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
8318 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8319 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8320 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
8321 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8322 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8323 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
8324 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8325 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8326 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
8327 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8328 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8329 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
8330 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8331 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8332 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
8333 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8334 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8335 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
8336 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8337 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8338 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
8339 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8340 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8341 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
8342 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8343 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8344 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
8345 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8346 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8347 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
8348 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8349 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8350 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
8351 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8352 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8353 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
8354 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8355 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8356 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
8357 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8358 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8359 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
8360 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8361 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8362 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
8363 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8364 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8365 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
8366 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8367 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8368 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
8369 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8370 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8371 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
8372 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8373 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8374 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
8375 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8376 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8377 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
8378 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8379 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8380 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
8381 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8382 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8383 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
8384 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8385 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8386 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
8387 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8388 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8389 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
8390 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8391 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8392 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
8393 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8394 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8395 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
8396 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8397 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8398 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
8399 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8400 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8401 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
8402 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8403 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8404 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
8405 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8406 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8407 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
8408 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8409 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8410 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
8411 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8412 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8413 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
8414 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8415 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8416 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
8417 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8418 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8419 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
8420 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8421 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8422 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
8423 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8424 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8425 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
8426 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8427 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8428 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
8429 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8430 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8431 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
8432 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8433 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8434 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
8435 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8436 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8437 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
8438 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8439 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8440 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
8441 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8442 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8443 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
8444 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8445 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8446 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
8447 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8448 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8449 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
8450 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8451 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8452 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
8453 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8454 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8455 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
8456 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8457 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8458 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
8459 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8460 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8461 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
8462 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8463 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8464 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
8465 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8466 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8467 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
8468 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8469 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8470 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
8471 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8472 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8473 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
8474 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8475 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8476 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
8477 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8478 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8479 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
8480 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8481 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8482 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
8483 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8484 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8485 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
8486 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8487 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8488 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
8489 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8490 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8491 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
8492 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8493 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8494 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
8495 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8496 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8497 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
8498 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8499 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8500 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
8501 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8502 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8503 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
8504 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8505 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8506 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
8507 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8508 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8509 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
8510 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8511 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8512 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
8513 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8514 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8515 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
8516 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8517 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8518 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
8519 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8520 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8521 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
8522 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8523 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8524 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
8525 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8526 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8527 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
8528 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8529 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8530 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
8531 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8532 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8533 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
8534 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8535 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8536 
8537 
8538 // addressBlock: gc_utcl2_vmsharedpfdec
8539 //MC_VM_NB_MMIOBASE
8540 #define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                                    0x0
8541 #define MC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                                      0xFFFFFFFFL
8542 //MC_VM_NB_MMIOLIMIT
8543 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                                  0x0
8544 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                                    0xFFFFFFFFL
8545 //MC_VM_NB_PCI_CTRL
8546 #define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                                  0x17
8547 #define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                                    0x00800000L
8548 //MC_VM_NB_PCI_ARB
8549 #define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                                     0x3
8550 #define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                                       0x00000008L
8551 //MC_VM_NB_TOP_OF_DRAM_SLOT1
8552 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                                        0x17
8553 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                                          0xFF800000L
8554 //MC_VM_NB_LOWER_TOP_OF_DRAM2
8555 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                            0x0
8556 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                                        0x17
8557 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                              0x00000001L
8558 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                                          0xFF800000L
8559 //MC_VM_NB_UPPER_TOP_OF_DRAM2
8560 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                                        0x0
8561 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                                          0x00000FFFL
8562 //MC_VM_FB_OFFSET
8563 #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                     0x0
8564 #define MC_VM_FB_OFFSET__FB_OFFSET_MASK                                                                       0x00FFFFFFL
8565 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
8566 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                               0x0
8567 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                                 0xFFFFFFFFL
8568 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
8569 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                               0x0
8570 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                                 0x0000000FL
8571 //MC_VM_STEERING
8572 #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                               0x0
8573 #define MC_VM_STEERING__DEFAULT_STEERING_MASK                                                                 0x00000003L
8574 //MC_SHARED_VIRT_RESET_REQ
8575 #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                                   0x0
8576 #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                                   0x1f
8577 #define MC_SHARED_VIRT_RESET_REQ__VF_MASK                                                                     0x0000FFFFL
8578 #define MC_SHARED_VIRT_RESET_REQ__PF_MASK                                                                     0x80000000L
8579 //MC_MEM_POWER_LS
8580 #define MC_MEM_POWER_LS__LS_SETUP__SHIFT                                                                      0x0
8581 #define MC_MEM_POWER_LS__LS_HOLD__SHIFT                                                                       0x6
8582 #define MC_MEM_POWER_LS__LS_SETUP_MASK                                                                        0x0000003FL
8583 #define MC_MEM_POWER_LS__LS_HOLD_MASK                                                                         0x00000FC0L
8584 //MC_VM_CACHEABLE_DRAM_ADDRESS_START
8585 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                                    0x0
8586 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                                      0x000FFFFFL
8587 //MC_VM_CACHEABLE_DRAM_ADDRESS_END
8588 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                                      0x0
8589 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                                        0x000FFFFFL
8590 //MC_VM_APT_CNTL
8591 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                                 0x0
8592 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                               0x1
8593 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                                   0x00000001L
8594 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                                 0x00000002L
8595 //MC_VM_LOCAL_HBM_ADDRESS_START
8596 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                                         0x0
8597 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                                           0x000FFFFFL
8598 //MC_VM_LOCAL_HBM_ADDRESS_END
8599 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                                           0x0
8600 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                             0x000FFFFFL
8601 //MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
8602 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                        0x0
8603 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                          0x00000001L
8604 
8605 
8606 // addressBlock: gc_utcl2_vmsharedvcdec
8607 //MC_VM_FB_LOCATION_BASE
8608 #define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                                0x0
8609 #define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                  0x00FFFFFFL
8610 //MC_VM_FB_LOCATION_TOP
8611 #define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                  0x0
8612 #define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                    0x00FFFFFFL
8613 //MC_VM_AGP_TOP
8614 #define MC_VM_AGP_TOP__AGP_TOP__SHIFT                                                                         0x0
8615 #define MC_VM_AGP_TOP__AGP_TOP_MASK                                                                           0x00FFFFFFL
8616 //MC_VM_AGP_BOT
8617 #define MC_VM_AGP_BOT__AGP_BOT__SHIFT                                                                         0x0
8618 #define MC_VM_AGP_BOT__AGP_BOT_MASK                                                                           0x00FFFFFFL
8619 //MC_VM_AGP_BASE
8620 #define MC_VM_AGP_BASE__AGP_BASE__SHIFT                                                                       0x0
8621 #define MC_VM_AGP_BASE__AGP_BASE_MASK                                                                         0x00FFFFFFL
8622 //MC_VM_SYSTEM_APERTURE_LOW_ADDR
8623 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                                   0x0
8624 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                                     0x3FFFFFFFL
8625 //MC_VM_SYSTEM_APERTURE_HIGH_ADDR
8626 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                                  0x0
8627 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                                    0x3FFFFFFFL
8628 //MC_VM_MX_L1_TLB_CNTL
8629 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                            0x0
8630 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                                       0x3
8631 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                          0x5
8632 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                             0x6
8633 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                                 0x7
8634 #define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                                    0xb
8635 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT                                                                   0xd
8636 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                              0x00000001L
8637 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                                         0x00000018L
8638 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                            0x00000020L
8639 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                               0x00000040L
8640 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                                   0x00000780L
8641 #define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                                      0x00001800L
8642 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK                                                                     0x00002000L
8643 
8644 
8645 // addressBlock: gc_tcdec
8646 //TCP_INVALIDATE
8647 #define TCP_INVALIDATE__START__SHIFT                                                                          0x0
8648 #define TCP_INVALIDATE__START_MASK                                                                            0x00000001L
8649 //TCP_STATUS
8650 #define TCP_STATUS__TCP_BUSY__SHIFT                                                                           0x0
8651 #define TCP_STATUS__INPUT_BUSY__SHIFT                                                                         0x1
8652 #define TCP_STATUS__ADRS_BUSY__SHIFT                                                                          0x2
8653 #define TCP_STATUS__TAGRAMS_BUSY__SHIFT                                                                       0x3
8654 #define TCP_STATUS__CNTRL_BUSY__SHIFT                                                                         0x4
8655 #define TCP_STATUS__LFIFO_BUSY__SHIFT                                                                         0x5
8656 #define TCP_STATUS__READ_BUSY__SHIFT                                                                          0x6
8657 #define TCP_STATUS__FORMAT_BUSY__SHIFT                                                                        0x7
8658 #define TCP_STATUS__VM_BUSY__SHIFT                                                                            0x8
8659 #define TCP_STATUS__TCP_BUSY_MASK                                                                             0x00000001L
8660 #define TCP_STATUS__INPUT_BUSY_MASK                                                                           0x00000002L
8661 #define TCP_STATUS__ADRS_BUSY_MASK                                                                            0x00000004L
8662 #define TCP_STATUS__TAGRAMS_BUSY_MASK                                                                         0x00000008L
8663 #define TCP_STATUS__CNTRL_BUSY_MASK                                                                           0x00000010L
8664 #define TCP_STATUS__LFIFO_BUSY_MASK                                                                           0x00000020L
8665 #define TCP_STATUS__READ_BUSY_MASK                                                                            0x00000040L
8666 #define TCP_STATUS__FORMAT_BUSY_MASK                                                                          0x00000080L
8667 #define TCP_STATUS__VM_BUSY_MASK                                                                              0x00000100L
8668 //TCP_CNTL
8669 #define TCP_CNTL__FORCE_HIT__SHIFT                                                                            0x0
8670 #define TCP_CNTL__FORCE_MISS__SHIFT                                                                           0x1
8671 #define TCP_CNTL__L1_SIZE__SHIFT                                                                              0x2
8672 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT                                                                 0x4
8673 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT                                                               0x5
8674 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT                                                                  0xf
8675 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT                                                                 0x16
8676 #define TCP_CNTL__DISABLE_Z_MAP__SHIFT                                                                        0x1c
8677 #define TCP_CNTL__INV_ALL_VMIDS__SHIFT                                                                        0x1d
8678 #define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT                                                                 0x1e
8679 #define TCP_CNTL__FORCE_HIT_MASK                                                                              0x00000001L
8680 #define TCP_CNTL__FORCE_MISS_MASK                                                                             0x00000002L
8681 #define TCP_CNTL__L1_SIZE_MASK                                                                                0x0000000CL
8682 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK                                                                   0x00000010L
8683 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK                                                                 0x00000020L
8684 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK                                                                    0x001F8000L
8685 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK                                                                   0x0FC00000L
8686 #define TCP_CNTL__DISABLE_Z_MAP_MASK                                                                          0x10000000L
8687 #define TCP_CNTL__INV_ALL_VMIDS_MASK                                                                          0x20000000L
8688 #define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK                                                                   0x40000000L
8689 //TCP_CHAN_STEER_LO
8690 #define TCP_CHAN_STEER_LO__CHAN0__SHIFT                                                                       0x0
8691 #define TCP_CHAN_STEER_LO__CHAN1__SHIFT                                                                       0x4
8692 #define TCP_CHAN_STEER_LO__CHAN2__SHIFT                                                                       0x8
8693 #define TCP_CHAN_STEER_LO__CHAN3__SHIFT                                                                       0xc
8694 #define TCP_CHAN_STEER_LO__CHAN4__SHIFT                                                                       0x10
8695 #define TCP_CHAN_STEER_LO__CHAN5__SHIFT                                                                       0x14
8696 #define TCP_CHAN_STEER_LO__CHAN6__SHIFT                                                                       0x18
8697 #define TCP_CHAN_STEER_LO__CHAN7__SHIFT                                                                       0x1c
8698 #define TCP_CHAN_STEER_LO__CHAN0_MASK                                                                         0x0000000FL
8699 #define TCP_CHAN_STEER_LO__CHAN1_MASK                                                                         0x000000F0L
8700 #define TCP_CHAN_STEER_LO__CHAN2_MASK                                                                         0x00000F00L
8701 #define TCP_CHAN_STEER_LO__CHAN3_MASK                                                                         0x0000F000L
8702 #define TCP_CHAN_STEER_LO__CHAN4_MASK                                                                         0x000F0000L
8703 #define TCP_CHAN_STEER_LO__CHAN5_MASK                                                                         0x00F00000L
8704 #define TCP_CHAN_STEER_LO__CHAN6_MASK                                                                         0x0F000000L
8705 #define TCP_CHAN_STEER_LO__CHAN7_MASK                                                                         0xF0000000L
8706 //TCP_CHAN_STEER_HI
8707 #define TCP_CHAN_STEER_HI__CHAN8__SHIFT                                                                       0x0
8708 #define TCP_CHAN_STEER_HI__CHAN9__SHIFT                                                                       0x4
8709 #define TCP_CHAN_STEER_HI__CHANA__SHIFT                                                                       0x8
8710 #define TCP_CHAN_STEER_HI__CHANB__SHIFT                                                                       0xc
8711 #define TCP_CHAN_STEER_HI__CHANC__SHIFT                                                                       0x10
8712 #define TCP_CHAN_STEER_HI__CHAND__SHIFT                                                                       0x14
8713 #define TCP_CHAN_STEER_HI__CHANE__SHIFT                                                                       0x18
8714 #define TCP_CHAN_STEER_HI__CHANF__SHIFT                                                                       0x1c
8715 #define TCP_CHAN_STEER_HI__CHAN8_MASK                                                                         0x0000000FL
8716 #define TCP_CHAN_STEER_HI__CHAN9_MASK                                                                         0x000000F0L
8717 #define TCP_CHAN_STEER_HI__CHANA_MASK                                                                         0x00000F00L
8718 #define TCP_CHAN_STEER_HI__CHANB_MASK                                                                         0x0000F000L
8719 #define TCP_CHAN_STEER_HI__CHANC_MASK                                                                         0x000F0000L
8720 #define TCP_CHAN_STEER_HI__CHAND_MASK                                                                         0x00F00000L
8721 #define TCP_CHAN_STEER_HI__CHANE_MASK                                                                         0x0F000000L
8722 #define TCP_CHAN_STEER_HI__CHANF_MASK                                                                         0xF0000000L
8723 //TCP_ADDR_CONFIG
8724 #define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT                                                                 0x0
8725 #define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                     0x4
8726 #define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT                                                                   0x6
8727 #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT                                                                0x9
8728 #define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK                                                                   0x0000000FL
8729 #define TCP_ADDR_CONFIG__NUM_BANKS_MASK                                                                       0x00000030L
8730 #define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK                                                                     0x000001C0L
8731 #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK                                                                  0x00000200L
8732 //TCP_CREDIT
8733 #define TCP_CREDIT__LFIFO_CREDIT__SHIFT                                                                       0x0
8734 #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT                                                                    0x10
8735 #define TCP_CREDIT__TD_CREDIT__SHIFT                                                                          0x1d
8736 #define TCP_CREDIT__LFIFO_CREDIT_MASK                                                                         0x000003FFL
8737 #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK                                                                      0x007F0000L
8738 #define TCP_CREDIT__TD_CREDIT_MASK                                                                            0xE0000000L
8739 //TCP_BUFFER_ADDR_HASH_CNTL
8740 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT                                                        0x0
8741 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT                                                           0x8
8742 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT                                                   0x10
8743 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT                                                      0x18
8744 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK                                                          0x00000007L
8745 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK                                                             0x00000700L
8746 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK                                                     0x00070000L
8747 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK                                                        0x07000000L
8748 //TCP_EDC_CNT
8749 #define TCP_EDC_CNT__SEC_COUNT__SHIFT                                                                         0x0
8750 #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT                                                                   0x8
8751 #define TCP_EDC_CNT__DED_COUNT__SHIFT                                                                         0x10
8752 #define TCP_EDC_CNT__SEC_COUNT_MASK                                                                           0x000000FFL
8753 #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK                                                                     0x0000FF00L
8754 #define TCP_EDC_CNT__DED_COUNT_MASK                                                                           0x00FF0000L
8755 //TC_CFG_L1_LOAD_POLICY0
8756 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT                                                               0x0
8757 #define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT                                                               0x2
8758 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT                                                               0x4
8759 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT                                                               0x6
8760 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT                                                               0x8
8761 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT                                                               0xa
8762 #define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT                                                               0xc
8763 #define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT                                                               0xe
8764 #define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT                                                               0x10
8765 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT                                                               0x12
8766 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT                                                              0x14
8767 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT                                                              0x16
8768 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT                                                              0x18
8769 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT                                                              0x1a
8770 #define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT                                                              0x1c
8771 #define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT                                                              0x1e
8772 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK                                                                 0x00000003L
8773 #define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK                                                                 0x0000000CL
8774 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK                                                                 0x00000030L
8775 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK                                                                 0x000000C0L
8776 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK                                                                 0x00000300L
8777 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK                                                                 0x00000C00L
8778 #define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK                                                                 0x00003000L
8779 #define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK                                                                 0x0000C000L
8780 #define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK                                                                 0x00030000L
8781 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK                                                                 0x000C0000L
8782 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK                                                                0x00300000L
8783 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK                                                                0x00C00000L
8784 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK                                                                0x03000000L
8785 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK                                                                0x0C000000L
8786 #define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK                                                                0x30000000L
8787 #define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK                                                                0xC0000000L
8788 //TC_CFG_L1_LOAD_POLICY1
8789 #define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT                                                              0x0
8790 #define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT                                                              0x2
8791 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT                                                              0x4
8792 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT                                                              0x6
8793 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT                                                              0x8
8794 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT                                                              0xa
8795 #define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT                                                              0xc
8796 #define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT                                                              0xe
8797 #define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT                                                              0x10
8798 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT                                                              0x12
8799 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT                                                              0x14
8800 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT                                                              0x16
8801 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT                                                              0x18
8802 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT                                                              0x1a
8803 #define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT                                                              0x1c
8804 #define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT                                                              0x1e
8805 #define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK                                                                0x00000003L
8806 #define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK                                                                0x0000000CL
8807 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK                                                                0x00000030L
8808 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK                                                                0x000000C0L
8809 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK                                                                0x00000300L
8810 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK                                                                0x00000C00L
8811 #define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK                                                                0x00003000L
8812 #define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK                                                                0x0000C000L
8813 #define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK                                                                0x00030000L
8814 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK                                                                0x000C0000L
8815 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK                                                                0x00300000L
8816 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK                                                                0x00C00000L
8817 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK                                                                0x03000000L
8818 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK                                                                0x0C000000L
8819 #define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK                                                                0x30000000L
8820 #define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK                                                                0xC0000000L
8821 //TC_CFG_L1_STORE_POLICY
8822 #define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT                                                               0x0
8823 #define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT                                                               0x1
8824 #define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT                                                               0x2
8825 #define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT                                                               0x3
8826 #define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT                                                               0x4
8827 #define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT                                                               0x5
8828 #define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT                                                               0x6
8829 #define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT                                                               0x7
8830 #define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT                                                               0x8
8831 #define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT                                                               0x9
8832 #define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT                                                              0xa
8833 #define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT                                                              0xb
8834 #define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT                                                              0xc
8835 #define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT                                                              0xd
8836 #define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT                                                              0xe
8837 #define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT                                                              0xf
8838 #define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT                                                              0x10
8839 #define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT                                                              0x11
8840 #define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT                                                              0x12
8841 #define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT                                                              0x13
8842 #define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT                                                              0x14
8843 #define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT                                                              0x15
8844 #define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT                                                              0x16
8845 #define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT                                                              0x17
8846 #define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT                                                              0x18
8847 #define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT                                                              0x19
8848 #define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT                                                              0x1a
8849 #define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT                                                              0x1b
8850 #define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT                                                              0x1c
8851 #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT                                                              0x1d
8852 #define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT                                                              0x1e
8853 #define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT                                                              0x1f
8854 #define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK                                                                 0x00000001L
8855 #define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK                                                                 0x00000002L
8856 #define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK                                                                 0x00000004L
8857 #define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK                                                                 0x00000008L
8858 #define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK                                                                 0x00000010L
8859 #define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK                                                                 0x00000020L
8860 #define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK                                                                 0x00000040L
8861 #define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK                                                                 0x00000080L
8862 #define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK                                                                 0x00000100L
8863 #define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK                                                                 0x00000200L
8864 #define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK                                                                0x00000400L
8865 #define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK                                                                0x00000800L
8866 #define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK                                                                0x00001000L
8867 #define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK                                                                0x00002000L
8868 #define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK                                                                0x00004000L
8869 #define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK                                                                0x00008000L
8870 #define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK                                                                0x00010000L
8871 #define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK                                                                0x00020000L
8872 #define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK                                                                0x00040000L
8873 #define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK                                                                0x00080000L
8874 #define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK                                                                0x00100000L
8875 #define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK                                                                0x00200000L
8876 #define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK                                                                0x00400000L
8877 #define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK                                                                0x00800000L
8878 #define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK                                                                0x01000000L
8879 #define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK                                                                0x02000000L
8880 #define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK                                                                0x04000000L
8881 #define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK                                                                0x08000000L
8882 #define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK                                                                0x10000000L
8883 #define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK                                                                0x20000000L
8884 #define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK                                                                0x40000000L
8885 #define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK                                                                0x80000000L
8886 //TC_CFG_L2_LOAD_POLICY0
8887 #define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT                                                               0x0
8888 #define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT                                                               0x2
8889 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT                                                               0x4
8890 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT                                                               0x6
8891 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT                                                               0x8
8892 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT                                                               0xa
8893 #define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT                                                               0xc
8894 #define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT                                                               0xe
8895 #define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT                                                               0x10
8896 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT                                                               0x12
8897 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT                                                              0x14
8898 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT                                                              0x16
8899 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT                                                              0x18
8900 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT                                                              0x1a
8901 #define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT                                                              0x1c
8902 #define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT                                                              0x1e
8903 #define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK                                                                 0x00000003L
8904 #define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK                                                                 0x0000000CL
8905 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK                                                                 0x00000030L
8906 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK                                                                 0x000000C0L
8907 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK                                                                 0x00000300L
8908 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK                                                                 0x00000C00L
8909 #define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK                                                                 0x00003000L
8910 #define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK                                                                 0x0000C000L
8911 #define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK                                                                 0x00030000L
8912 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK                                                                 0x000C0000L
8913 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK                                                                0x00300000L
8914 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK                                                                0x00C00000L
8915 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK                                                                0x03000000L
8916 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK                                                                0x0C000000L
8917 #define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK                                                                0x30000000L
8918 #define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK                                                                0xC0000000L
8919 //TC_CFG_L2_LOAD_POLICY1
8920 #define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT                                                              0x0
8921 #define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT                                                              0x2
8922 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT                                                              0x4
8923 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT                                                              0x6
8924 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT                                                              0x8
8925 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT                                                              0xa
8926 #define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT                                                              0xc
8927 #define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT                                                              0xe
8928 #define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT                                                              0x10
8929 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT                                                              0x12
8930 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT                                                              0x14
8931 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT                                                              0x16
8932 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT                                                              0x18
8933 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT                                                              0x1a
8934 #define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT                                                              0x1c
8935 #define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT                                                              0x1e
8936 #define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK                                                                0x00000003L
8937 #define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK                                                                0x0000000CL
8938 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK                                                                0x00000030L
8939 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK                                                                0x000000C0L
8940 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK                                                                0x00000300L
8941 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK                                                                0x00000C00L
8942 #define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK                                                                0x00003000L
8943 #define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK                                                                0x0000C000L
8944 #define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK                                                                0x00030000L
8945 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK                                                                0x000C0000L
8946 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK                                                                0x00300000L
8947 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK                                                                0x00C00000L
8948 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK                                                                0x03000000L
8949 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK                                                                0x0C000000L
8950 #define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK                                                                0x30000000L
8951 #define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK                                                                0xC0000000L
8952 //TC_CFG_L2_STORE_POLICY0
8953 #define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT                                                              0x0
8954 #define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT                                                              0x2
8955 #define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT                                                              0x4
8956 #define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT                                                              0x6
8957 #define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT                                                              0x8
8958 #define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT                                                              0xa
8959 #define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT                                                              0xc
8960 #define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT                                                              0xe
8961 #define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT                                                              0x10
8962 #define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT                                                              0x12
8963 #define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT                                                             0x14
8964 #define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT                                                             0x16
8965 #define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT                                                             0x18
8966 #define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT                                                             0x1a
8967 #define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT                                                             0x1c
8968 #define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT                                                             0x1e
8969 #define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK                                                                0x00000003L
8970 #define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK                                                                0x0000000CL
8971 #define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK                                                                0x00000030L
8972 #define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK                                                                0x000000C0L
8973 #define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK                                                                0x00000300L
8974 #define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK                                                                0x00000C00L
8975 #define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK                                                                0x00003000L
8976 #define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK                                                                0x0000C000L
8977 #define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK                                                                0x00030000L
8978 #define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK                                                                0x000C0000L
8979 #define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK                                                               0x00300000L
8980 #define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK                                                               0x00C00000L
8981 #define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK                                                               0x03000000L
8982 #define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK                                                               0x0C000000L
8983 #define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK                                                               0x30000000L
8984 #define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK                                                               0xC0000000L
8985 //TC_CFG_L2_STORE_POLICY1
8986 #define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT                                                             0x0
8987 #define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT                                                             0x2
8988 #define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT                                                             0x4
8989 #define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT                                                             0x6
8990 #define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT                                                             0x8
8991 #define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT                                                             0xa
8992 #define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT                                                             0xc
8993 #define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT                                                             0xe
8994 #define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT                                                             0x10
8995 #define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT                                                             0x12
8996 #define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT                                                             0x14
8997 #define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT                                                             0x16
8998 #define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT                                                             0x18
8999 #define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT                                                             0x1a
9000 #define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT                                                             0x1c
9001 #define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT                                                             0x1e
9002 #define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK                                                               0x00000003L
9003 #define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK                                                               0x0000000CL
9004 #define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK                                                               0x00000030L
9005 #define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK                                                               0x000000C0L
9006 #define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK                                                               0x00000300L
9007 #define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK                                                               0x00000C00L
9008 #define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK                                                               0x00003000L
9009 #define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK                                                               0x0000C000L
9010 #define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK                                                               0x00030000L
9011 #define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK                                                               0x000C0000L
9012 #define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK                                                               0x00300000L
9013 #define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK                                                               0x00C00000L
9014 #define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK                                                               0x03000000L
9015 #define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK                                                               0x0C000000L
9016 #define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK                                                               0x30000000L
9017 #define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK                                                               0xC0000000L
9018 //TC_CFG_L2_ATOMIC_POLICY
9019 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT                                                              0x0
9020 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT                                                              0x2
9021 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT                                                              0x4
9022 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT                                                              0x6
9023 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT                                                              0x8
9024 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT                                                              0xa
9025 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT                                                              0xc
9026 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT                                                              0xe
9027 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT                                                              0x10
9028 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT                                                              0x12
9029 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT                                                             0x14
9030 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT                                                             0x16
9031 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT                                                             0x18
9032 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT                                                             0x1a
9033 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT                                                             0x1c
9034 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT                                                             0x1e
9035 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK                                                                0x00000003L
9036 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK                                                                0x0000000CL
9037 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK                                                                0x00000030L
9038 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK                                                                0x000000C0L
9039 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK                                                                0x00000300L
9040 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK                                                                0x00000C00L
9041 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK                                                                0x00003000L
9042 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK                                                                0x0000C000L
9043 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK                                                                0x00030000L
9044 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK                                                                0x000C0000L
9045 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK                                                               0x00300000L
9046 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK                                                               0x00C00000L
9047 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK                                                               0x03000000L
9048 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK                                                               0x0C000000L
9049 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK                                                               0x30000000L
9050 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK                                                               0xC0000000L
9051 //TC_CFG_L1_VOLATILE
9052 #define TC_CFG_L1_VOLATILE__VOL__SHIFT                                                                        0x0
9053 #define TC_CFG_L1_VOLATILE__VOL_MASK                                                                          0x0000000FL
9054 //TC_CFG_L2_VOLATILE
9055 #define TC_CFG_L2_VOLATILE__VOL__SHIFT                                                                        0x0
9056 #define TC_CFG_L2_VOLATILE__VOL_MASK                                                                          0x0000000FL
9057 //TCI_STATUS
9058 #define TCI_STATUS__TCI_BUSY__SHIFT                                                                           0x0
9059 #define TCI_STATUS__TCI_BUSY_MASK                                                                             0x00000001L
9060 //TCI_CNTL_1
9061 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT                                                                 0x0
9062 #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT                                                                     0x10
9063 #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT                                                                    0x18
9064 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK                                                                   0x0000FFFFL
9065 #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK                                                                       0x00FF0000L
9066 #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK                                                                      0xFF000000L
9067 //TCI_CNTL_2
9068 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT                                                                0x0
9069 #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT                                                                     0x1
9070 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK                                                                  0x00000001L
9071 #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK                                                                       0x000001FEL
9072 //TCC_CTRL
9073 #define TCC_CTRL__CACHE_SIZE__SHIFT                                                                           0x0
9074 #define TCC_CTRL__RATE__SHIFT                                                                                 0x2
9075 #define TCC_CTRL__WRITEBACK_MARGIN__SHIFT                                                                     0x4
9076 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT                                                           0x8
9077 #define TCC_CTRL__SRC_FIFO_SIZE__SHIFT                                                                        0xc
9078 #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT                                                                    0x10
9079 #define TCC_CTRL__LINEAR_SET_HASH__SHIFT                                                                      0x15
9080 #define TCC_CTRL__MDC_SIZE__SHIFT                                                                             0x18
9081 #define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT                                                                      0x1a
9082 #define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT                                                               0x1c
9083 #define TCC_CTRL__CACHE_SIZE_MASK                                                                             0x00000003L
9084 #define TCC_CTRL__RATE_MASK                                                                                   0x0000000CL
9085 #define TCC_CTRL__WRITEBACK_MARGIN_MASK                                                                       0x000000F0L
9086 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK                                                             0x00000F00L
9087 #define TCC_CTRL__SRC_FIFO_SIZE_MASK                                                                          0x0000F000L
9088 #define TCC_CTRL__LATENCY_FIFO_SIZE_MASK                                                                      0x000F0000L
9089 #define TCC_CTRL__LINEAR_SET_HASH_MASK                                                                        0x00200000L
9090 #define TCC_CTRL__MDC_SIZE_MASK                                                                               0x03000000L
9091 #define TCC_CTRL__MDC_SECTOR_SIZE_MASK                                                                        0x0C000000L
9092 #define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK                                                                 0xF0000000L
9093 //TCC_CTRL2
9094 #define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT                                                                     0x0
9095 #define TCC_CTRL2__PROBE_FIFO_SIZE_MASK                                                                       0x0000000FL
9096 //TCC_EDC_CNT
9097 #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT                                                              0x0
9098 #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT                                                              0x2
9099 #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT                                                             0x4
9100 #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT                                                             0x6
9101 #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT                                                           0x8
9102 #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT                                                           0xa
9103 #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT                                                            0xc
9104 #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT                                                            0xe
9105 #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT                                                                0x10
9106 #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT                                                                0x12
9107 #define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT                                                              0x14
9108 #define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT                                                         0x16
9109 #define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT                                                            0x18
9110 #define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT                                                             0x1a
9111 #define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT                                                          0x1c
9112 #define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT                                                          0x1e
9113 #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK                                                                0x00000003L
9114 #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK                                                                0x0000000CL
9115 #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK                                                               0x00000030L
9116 #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK                                                               0x000000C0L
9117 #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK                                                             0x00000300L
9118 #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK                                                             0x00000C00L
9119 #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK                                                              0x00003000L
9120 #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK                                                              0x0000C000L
9121 #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK                                                                  0x00030000L
9122 #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK                                                                  0x000C0000L
9123 #define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK                                                                0x00300000L
9124 #define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK                                                           0x00C00000L
9125 #define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK                                                              0x03000000L
9126 #define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK                                                               0x0C000000L
9127 #define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK                                                            0x30000000L
9128 #define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK                                                            0xC0000000L
9129 //TCC_EDC_CNT2
9130 #define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT                                                           0x0
9131 #define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT                                                       0x2
9132 #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT                                                      0x4
9133 #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT                                                  0x6
9134 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT                                                   0x8
9135 #define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT__SHIFT                                                 0xa
9136 #define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT__SHIFT                                                   0xc
9137 #define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK                                                             0x00000003L
9138 #define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK                                                         0x0000000CL
9139 #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK                                                        0x00000030L
9140 #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK                                                    0x000000C0L
9141 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK                                                     0x00000300L
9142 #define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT_MASK                                                   0x00000C00L
9143 #define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT_MASK                                                     0x00003000L
9144 //TCC_REDUNDANCY
9145 #define TCC_REDUNDANCY__MC_SEL0__SHIFT                                                                        0x0
9146 #define TCC_REDUNDANCY__MC_SEL1__SHIFT                                                                        0x1
9147 #define TCC_REDUNDANCY__MC_SEL0_MASK                                                                          0x00000001L
9148 #define TCC_REDUNDANCY__MC_SEL1_MASK                                                                          0x00000002L
9149 //TCC_EXE_DISABLE
9150 #define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT                                                                   0x1
9151 #define TCC_EXE_DISABLE__EXE_DISABLE_MASK                                                                     0x00000002L
9152 //TCC_DSM_CNTL
9153 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT                                                    0x0
9154 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT                                                0x2
9155 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT                                           0x3
9156 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT                                       0x5
9157 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT                                           0x6
9158 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT                                       0x8
9159 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT                                           0x9
9160 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT                                       0xb
9161 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT                                            0xc
9162 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT                                        0xe
9163 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT                                            0xf
9164 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT                                        0x11
9165 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT                                                 0x12
9166 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x14
9167 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT                                                  0x15
9168 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x17
9169 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT                                                    0x18
9170 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT                                                0x1a
9171 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT                                               0x1b
9172 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT                                           0x1d
9173 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK                                                      0x00000003L
9174 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK                                                  0x00000004L
9175 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK                                             0x00000018L
9176 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK                                         0x00000020L
9177 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK                                             0x000000C0L
9178 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK                                         0x00000100L
9179 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK                                             0x00000600L
9180 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK                                         0x00000800L
9181 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK                                              0x00003000L
9182 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK                                          0x00004000L
9183 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK                                              0x00018000L
9184 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK                                          0x00020000L
9185 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK                                                   0x000C0000L
9186 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK                                               0x00100000L
9187 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK                                                    0x00600000L
9188 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK                                                0x00800000L
9189 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK                                                      0x03000000L
9190 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK                                                  0x04000000L
9191 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK                                                 0x18000000L
9192 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK                                             0x20000000L
9193 //TCC_DSM_CNTLA
9194 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT                                                     0x0
9195 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                                 0x2
9196 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT                                               0x3
9197 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                           0x5
9198 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT                                                 0x6
9199 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x8
9200 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT                                             0x9
9201 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT                                         0xb
9202 #define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT                                            0xc
9203 #define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                        0xe
9204 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT                                        0xf
9205 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                    0x11
9206 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT                                         0x12
9207 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                     0x14
9208 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT                                                 0x15
9209 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x17
9210 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT                                                  0x18
9211 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x1a
9212 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT                                               0x1b
9213 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT                                           0x1d
9214 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK                                                       0x00000003L
9215 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                                   0x00000004L
9216 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK                                                 0x00000018L
9217 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                             0x00000020L
9218 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK                                                   0x000000C0L
9219 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK                                               0x00000100L
9220 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK                                               0x00000600L
9221 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK                                           0x00000800L
9222 #define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK                                              0x00003000L
9223 #define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK                                          0x00004000L
9224 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK                                          0x00018000L
9225 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK                                      0x00020000L
9226 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK                                           0x000C0000L
9227 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                       0x00100000L
9228 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK                                                   0x00600000L
9229 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                               0x00800000L
9230 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK                                                    0x03000000L
9231 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK                                                0x04000000L
9232 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK                                                 0x18000000L
9233 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK                                             0x20000000L
9234 //TCC_DSM_CNTL2
9235 #define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT                                                  0x0
9236 #define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT                                                  0x2
9237 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT                                         0x3
9238 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT                                         0x5
9239 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT                                         0x6
9240 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT                                         0x8
9241 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT                                         0x9
9242 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT                                         0xb
9243 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT                                          0xc
9244 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT                                          0xe
9245 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT                                          0xf
9246 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT                                          0x11
9247 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT                                               0x12
9248 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT                                               0x14
9249 #define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT                                                0x15
9250 #define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT                                                0x17
9251 #define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
9252 #define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK                                                    0x00000003L
9253 #define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK                                                    0x00000004L
9254 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK                                           0x00000018L
9255 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK                                           0x00000020L
9256 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK                                           0x000000C0L
9257 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK                                           0x00000100L
9258 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK                                           0x00000600L
9259 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK                                           0x00000800L
9260 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK                                            0x00003000L
9261 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK                                            0x00004000L
9262 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK                                            0x00018000L
9263 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK                                            0x00020000L
9264 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK                                                 0x000C0000L
9265 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK                                                 0x00100000L
9266 #define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK                                                  0x00600000L
9267 #define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK                                                  0x00800000L
9268 #define TCC_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
9269 //TCC_DSM_CNTL2A
9270 #define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT                                                 0x0
9271 #define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT                                                 0x2
9272 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT                                            0x3
9273 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT                                            0x5
9274 #define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT                                                0x6
9275 #define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT                                                0x8
9276 #define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT                                             0x9
9277 #define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT                                             0xb
9278 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0xc
9279 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0xe
9280 #define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT                                               0xf
9281 #define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT                                               0x11
9282 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT                                           0x12
9283 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT                                           0x14
9284 #define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                   0x15
9285 #define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT                                                   0x17
9286 #define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT                                          0x18
9287 #define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT                                          0x1a
9288 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x1b
9289 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT                                       0x1d
9290 #define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK                                                   0x00000003L
9291 #define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK                                                   0x00000004L
9292 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK                                              0x00000018L
9293 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK                                              0x00000020L
9294 #define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK                                                  0x000000C0L
9295 #define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK                                                  0x00000100L
9296 #define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK                                               0x00000600L
9297 #define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK                                               0x00000800L
9298 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
9299 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00004000L
9300 #define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK                                                 0x00018000L
9301 #define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK                                                 0x00020000L
9302 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK                                             0x000C0000L
9303 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK                                             0x00100000L
9304 #define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK                                                     0x00600000L
9305 #define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK                                                     0x00800000L
9306 #define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK                                            0x03000000L
9307 #define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK                                            0x04000000L
9308 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK                                         0x18000000L
9309 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK                                         0x20000000L
9310 //TCC_DSM_CNTL2B
9311 #define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT                                               0x0
9312 #define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT                                               0x2
9313 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT                                      0x3
9314 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT                                      0x5
9315 #define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
9316 #define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
9317 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK                                        0x00000018L
9318 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK                                        0x00000020L
9319 //TCC_WBINVL2
9320 #define TCC_WBINVL2__DONE__SHIFT                                                                              0x4
9321 #define TCC_WBINVL2__DONE_MASK                                                                                0x00000010L
9322 //TCC_SOFT_RESET
9323 #define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT                                                                 0x0
9324 #define TCC_SOFT_RESET__HALT_FOR_RESET_MASK                                                                   0x00000001L
9325 //TCA_CTRL
9326 #define TCA_CTRL__HOLE_TIMEOUT__SHIFT                                                                         0x0
9327 #define TCA_CTRL__RB_STILL_4_PHASE__SHIFT                                                                     0x4
9328 #define TCA_CTRL__RB_AS_TCI__SHIFT                                                                            0x5
9329 #define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT                                                               0x6
9330 #define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT                                                          0x7
9331 #define TCA_CTRL__HOLE_TIMEOUT_MASK                                                                           0x0000000FL
9332 #define TCA_CTRL__RB_STILL_4_PHASE_MASK                                                                       0x00000010L
9333 #define TCA_CTRL__RB_AS_TCI_MASK                                                                              0x00000020L
9334 #define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK                                                                 0x00000040L
9335 #define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK                                                            0x00000080L
9336 //TCA_BURST_MASK
9337 #define TCA_BURST_MASK__ADDR_MASK__SHIFT                                                                      0x0
9338 #define TCA_BURST_MASK__ADDR_MASK_MASK                                                                        0xFFFFFFFFL
9339 //TCA_BURST_CTRL
9340 #define TCA_BURST_CTRL__MAX_BURST__SHIFT                                                                      0x0
9341 #define TCA_BURST_CTRL__RB_DISABLE__SHIFT                                                                     0x3
9342 #define TCA_BURST_CTRL__TCP_DISABLE__SHIFT                                                                    0x4
9343 #define TCA_BURST_CTRL__SQC_DISABLE__SHIFT                                                                    0x5
9344 #define TCA_BURST_CTRL__CPF_DISABLE__SHIFT                                                                    0x6
9345 #define TCA_BURST_CTRL__CPG_DISABLE__SHIFT                                                                    0x7
9346 #define TCA_BURST_CTRL__IA_DISABLE__SHIFT                                                                     0x8
9347 #define TCA_BURST_CTRL__WD_DISABLE__SHIFT                                                                     0x9
9348 #define TCA_BURST_CTRL__SQG_DISABLE__SHIFT                                                                    0xa
9349 #define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT                                                                  0xb
9350 #define TCA_BURST_CTRL__TPI_DISABLE__SHIFT                                                                    0xc
9351 #define TCA_BURST_CTRL__RLC_DISABLE__SHIFT                                                                    0xd
9352 #define TCA_BURST_CTRL__PA_DISABLE__SHIFT                                                                     0xe
9353 #define TCA_BURST_CTRL__MAX_BURST_MASK                                                                        0x00000007L
9354 #define TCA_BURST_CTRL__RB_DISABLE_MASK                                                                       0x00000008L
9355 #define TCA_BURST_CTRL__TCP_DISABLE_MASK                                                                      0x00000010L
9356 #define TCA_BURST_CTRL__SQC_DISABLE_MASK                                                                      0x00000020L
9357 #define TCA_BURST_CTRL__CPF_DISABLE_MASK                                                                      0x00000040L
9358 #define TCA_BURST_CTRL__CPG_DISABLE_MASK                                                                      0x00000080L
9359 #define TCA_BURST_CTRL__IA_DISABLE_MASK                                                                       0x00000100L
9360 #define TCA_BURST_CTRL__WD_DISABLE_MASK                                                                       0x00000200L
9361 #define TCA_BURST_CTRL__SQG_DISABLE_MASK                                                                      0x00000400L
9362 #define TCA_BURST_CTRL__UTCL2_DISABLE_MASK                                                                    0x00000800L
9363 #define TCA_BURST_CTRL__TPI_DISABLE_MASK                                                                      0x00001000L
9364 #define TCA_BURST_CTRL__RLC_DISABLE_MASK                                                                      0x00002000L
9365 #define TCA_BURST_CTRL__PA_DISABLE_MASK                                                                       0x00004000L
9366 //TCA_DSM_CNTL
9367 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT                                                 0x0
9368 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x2
9369 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT                                                  0x3
9370 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x5
9371 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK                                                   0x00000003L
9372 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK                                               0x00000004L
9373 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK                                                    0x00000018L
9374 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK                                                0x00000020L
9375 //TCA_DSM_CNTL2
9376 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT                                               0x0
9377 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT                                               0x2
9378 #define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT                                                0x3
9379 #define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT                                                0x5
9380 #define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
9381 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
9382 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
9383 #define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK                                                  0x00000018L
9384 #define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK                                                  0x00000020L
9385 #define TCA_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
9386 //TCA_EDC_CNT
9387 #define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT                                                               0x0
9388 #define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT                                                                0x2
9389 #define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK                                                                 0x00000003L
9390 #define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK                                                                  0x0000000CL
9391 
9392 
9393 // addressBlock: gc_shdec
9394 //SPI_SHADER_PGM_RSRC3_PS
9395 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT                                                                 0x0
9396 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT                                                            0x10
9397 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
9398 #define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT                                                          0x1a
9399 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK                                                                   0x0000FFFFL
9400 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK                                                              0x003F0000L
9401 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
9402 #define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK                                                            0x3C000000L
9403 //SPI_SHADER_PGM_LO_PS
9404 #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT                                                                 0x0
9405 #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9406 //SPI_SHADER_PGM_HI_PS
9407 #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT                                                                 0x0
9408 #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK                                                                   0xFFL
9409 //SPI_SHADER_PGM_RSRC1_PS
9410 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT                                                                 0x0
9411 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT                                                                 0x6
9412 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT                                                              0xa
9413 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT                                                            0xc
9414 #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT                                                                  0x14
9415 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT                                                            0x15
9416 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT                                                            0x16
9417 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT                                                             0x17
9418 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT                                                      0x18
9419 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT                                                             0x1c
9420 #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT                                                             0x1d
9421 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK                                                                   0x0000003FL
9422 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK                                                                   0x000003C0L
9423 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK                                                                0x00000C00L
9424 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK                                                              0x000FF000L
9425 #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK                                                                    0x00100000L
9426 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK                                                              0x00200000L
9427 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK                                                              0x00400000L
9428 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK                                                               0x00800000L
9429 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK                                                        0x01000000L
9430 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK                                                               0x10000000L
9431 #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK                                                               0x20000000L
9432 //SPI_SHADER_PGM_RSRC2_PS
9433 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT                                                            0x0
9434 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT                                                             0x1
9435 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT                                                          0x6
9436 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT                                                           0x7
9437 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT                                                        0x8
9438 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT                                                               0x10
9439 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT                                                 0x19
9440 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT                                              0x1a
9441 #define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT                                                           0x1b
9442 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT                                                         0x1c
9443 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK                                                              0x00000001L
9444 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK                                                               0x0000003EL
9445 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK                                                            0x00000040L
9446 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK                                                             0x00000080L
9447 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK                                                          0x0000FF00L
9448 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK                                                                 0x01FF0000L
9449 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK                                                   0x02000000L
9450 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK                                                0x04000000L
9451 #define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK                                                             0x08000000L
9452 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK                                                           0x10000000L
9453 //SPI_SHADER_USER_DATA_PS_0
9454 #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT                                                                0x0
9455 #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK                                                                  0xFFFFFFFFL
9456 //SPI_SHADER_USER_DATA_PS_1
9457 #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT                                                                0x0
9458 #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK                                                                  0xFFFFFFFFL
9459 //SPI_SHADER_USER_DATA_PS_2
9460 #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT                                                                0x0
9461 #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK                                                                  0xFFFFFFFFL
9462 //SPI_SHADER_USER_DATA_PS_3
9463 #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT                                                                0x0
9464 #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK                                                                  0xFFFFFFFFL
9465 //SPI_SHADER_USER_DATA_PS_4
9466 #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT                                                                0x0
9467 #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK                                                                  0xFFFFFFFFL
9468 //SPI_SHADER_USER_DATA_PS_5
9469 #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT                                                                0x0
9470 #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK                                                                  0xFFFFFFFFL
9471 //SPI_SHADER_USER_DATA_PS_6
9472 #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT                                                                0x0
9473 #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK                                                                  0xFFFFFFFFL
9474 //SPI_SHADER_USER_DATA_PS_7
9475 #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT                                                                0x0
9476 #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK                                                                  0xFFFFFFFFL
9477 //SPI_SHADER_USER_DATA_PS_8
9478 #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT                                                                0x0
9479 #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK                                                                  0xFFFFFFFFL
9480 //SPI_SHADER_USER_DATA_PS_9
9481 #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT                                                                0x0
9482 #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK                                                                  0xFFFFFFFFL
9483 //SPI_SHADER_USER_DATA_PS_10
9484 #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT                                                               0x0
9485 #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK                                                                 0xFFFFFFFFL
9486 //SPI_SHADER_USER_DATA_PS_11
9487 #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT                                                               0x0
9488 #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK                                                                 0xFFFFFFFFL
9489 //SPI_SHADER_USER_DATA_PS_12
9490 #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT                                                               0x0
9491 #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK                                                                 0xFFFFFFFFL
9492 //SPI_SHADER_USER_DATA_PS_13
9493 #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT                                                               0x0
9494 #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK                                                                 0xFFFFFFFFL
9495 //SPI_SHADER_USER_DATA_PS_14
9496 #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT                                                               0x0
9497 #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK                                                                 0xFFFFFFFFL
9498 //SPI_SHADER_USER_DATA_PS_15
9499 #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT                                                               0x0
9500 #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK                                                                 0xFFFFFFFFL
9501 //SPI_SHADER_USER_DATA_PS_16
9502 #define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT                                                               0x0
9503 #define SPI_SHADER_USER_DATA_PS_16__DATA_MASK                                                                 0xFFFFFFFFL
9504 //SPI_SHADER_USER_DATA_PS_17
9505 #define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT                                                               0x0
9506 #define SPI_SHADER_USER_DATA_PS_17__DATA_MASK                                                                 0xFFFFFFFFL
9507 //SPI_SHADER_USER_DATA_PS_18
9508 #define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT                                                               0x0
9509 #define SPI_SHADER_USER_DATA_PS_18__DATA_MASK                                                                 0xFFFFFFFFL
9510 //SPI_SHADER_USER_DATA_PS_19
9511 #define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT                                                               0x0
9512 #define SPI_SHADER_USER_DATA_PS_19__DATA_MASK                                                                 0xFFFFFFFFL
9513 //SPI_SHADER_USER_DATA_PS_20
9514 #define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT                                                               0x0
9515 #define SPI_SHADER_USER_DATA_PS_20__DATA_MASK                                                                 0xFFFFFFFFL
9516 //SPI_SHADER_USER_DATA_PS_21
9517 #define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT                                                               0x0
9518 #define SPI_SHADER_USER_DATA_PS_21__DATA_MASK                                                                 0xFFFFFFFFL
9519 //SPI_SHADER_USER_DATA_PS_22
9520 #define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT                                                               0x0
9521 #define SPI_SHADER_USER_DATA_PS_22__DATA_MASK                                                                 0xFFFFFFFFL
9522 //SPI_SHADER_USER_DATA_PS_23
9523 #define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT                                                               0x0
9524 #define SPI_SHADER_USER_DATA_PS_23__DATA_MASK                                                                 0xFFFFFFFFL
9525 //SPI_SHADER_USER_DATA_PS_24
9526 #define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT                                                               0x0
9527 #define SPI_SHADER_USER_DATA_PS_24__DATA_MASK                                                                 0xFFFFFFFFL
9528 //SPI_SHADER_USER_DATA_PS_25
9529 #define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT                                                               0x0
9530 #define SPI_SHADER_USER_DATA_PS_25__DATA_MASK                                                                 0xFFFFFFFFL
9531 //SPI_SHADER_USER_DATA_PS_26
9532 #define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT                                                               0x0
9533 #define SPI_SHADER_USER_DATA_PS_26__DATA_MASK                                                                 0xFFFFFFFFL
9534 //SPI_SHADER_USER_DATA_PS_27
9535 #define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT                                                               0x0
9536 #define SPI_SHADER_USER_DATA_PS_27__DATA_MASK                                                                 0xFFFFFFFFL
9537 //SPI_SHADER_USER_DATA_PS_28
9538 #define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT                                                               0x0
9539 #define SPI_SHADER_USER_DATA_PS_28__DATA_MASK                                                                 0xFFFFFFFFL
9540 //SPI_SHADER_USER_DATA_PS_29
9541 #define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT                                                               0x0
9542 #define SPI_SHADER_USER_DATA_PS_29__DATA_MASK                                                                 0xFFFFFFFFL
9543 //SPI_SHADER_USER_DATA_PS_30
9544 #define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT                                                               0x0
9545 #define SPI_SHADER_USER_DATA_PS_30__DATA_MASK                                                                 0xFFFFFFFFL
9546 //SPI_SHADER_USER_DATA_PS_31
9547 #define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT                                                               0x0
9548 #define SPI_SHADER_USER_DATA_PS_31__DATA_MASK                                                                 0xFFFFFFFFL
9549 //SPI_SHADER_PGM_RSRC3_VS
9550 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT                                                                 0x0
9551 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT                                                            0x10
9552 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
9553 #define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT                                                          0x1a
9554 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK                                                                   0x0000FFFFL
9555 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK                                                              0x003F0000L
9556 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
9557 #define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK                                                            0x3C000000L
9558 //SPI_SHADER_LATE_ALLOC_VS
9559 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT                                                                0x0
9560 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK                                                                  0x0000003FL
9561 //SPI_SHADER_PGM_LO_VS
9562 #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT                                                                 0x0
9563 #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9564 //SPI_SHADER_PGM_HI_VS
9565 #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT                                                                 0x0
9566 #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK                                                                   0xFFL
9567 //SPI_SHADER_PGM_RSRC1_VS
9568 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT                                                                 0x0
9569 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT                                                                 0x6
9570 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT                                                              0xa
9571 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT                                                            0xc
9572 #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT                                                                  0x14
9573 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT                                                            0x15
9574 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT                                                            0x16
9575 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT                                                             0x17
9576 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT                                                         0x18
9577 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT                                                       0x1a
9578 #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT                                                             0x1e
9579 #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT                                                             0x1f
9580 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK                                                                   0x0000003FL
9581 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK                                                                   0x000003C0L
9582 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK                                                                0x00000C00L
9583 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK                                                              0x000FF000L
9584 #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK                                                                    0x00100000L
9585 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK                                                              0x00200000L
9586 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK                                                              0x00400000L
9587 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK                                                               0x00800000L
9588 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK                                                           0x03000000L
9589 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK                                                         0x04000000L
9590 #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK                                                               0x40000000L
9591 #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK                                                               0x80000000L
9592 //SPI_SHADER_PGM_RSRC2_VS
9593 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT                                                            0x0
9594 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT                                                             0x1
9595 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT                                                          0x6
9596 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT                                                             0x7
9597 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT                                                           0x8
9598 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT                                                           0x9
9599 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT                                                           0xa
9600 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT                                                           0xb
9601 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT                                                                 0xc
9602 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT                                                               0xd
9603 #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT                                                            0x16
9604 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT                                                      0x18
9605 #define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT                                                           0x1b
9606 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT                                                         0x1c
9607 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK                                                              0x00000001L
9608 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK                                                               0x0000003EL
9609 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK                                                            0x00000040L
9610 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK                                                               0x00000080L
9611 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK                                                             0x00000100L
9612 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK                                                             0x00000200L
9613 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK                                                             0x00000400L
9614 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK                                                             0x00000800L
9615 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK                                                                   0x00001000L
9616 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK                                                                 0x003FE000L
9617 #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK                                                              0x00400000L
9618 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK                                                        0x01000000L
9619 #define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK                                                             0x08000000L
9620 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK                                                           0x10000000L
9621 //SPI_SHADER_USER_DATA_VS_0
9622 #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT                                                                0x0
9623 #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK                                                                  0xFFFFFFFFL
9624 //SPI_SHADER_USER_DATA_VS_1
9625 #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT                                                                0x0
9626 #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK                                                                  0xFFFFFFFFL
9627 //SPI_SHADER_USER_DATA_VS_2
9628 #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT                                                                0x0
9629 #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK                                                                  0xFFFFFFFFL
9630 //SPI_SHADER_USER_DATA_VS_3
9631 #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT                                                                0x0
9632 #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK                                                                  0xFFFFFFFFL
9633 //SPI_SHADER_USER_DATA_VS_4
9634 #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT                                                                0x0
9635 #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK                                                                  0xFFFFFFFFL
9636 //SPI_SHADER_USER_DATA_VS_5
9637 #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT                                                                0x0
9638 #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK                                                                  0xFFFFFFFFL
9639 //SPI_SHADER_USER_DATA_VS_6
9640 #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT                                                                0x0
9641 #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK                                                                  0xFFFFFFFFL
9642 //SPI_SHADER_USER_DATA_VS_7
9643 #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT                                                                0x0
9644 #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK                                                                  0xFFFFFFFFL
9645 //SPI_SHADER_USER_DATA_VS_8
9646 #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT                                                                0x0
9647 #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK                                                                  0xFFFFFFFFL
9648 //SPI_SHADER_USER_DATA_VS_9
9649 #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT                                                                0x0
9650 #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK                                                                  0xFFFFFFFFL
9651 //SPI_SHADER_USER_DATA_VS_10
9652 #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT                                                               0x0
9653 #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK                                                                 0xFFFFFFFFL
9654 //SPI_SHADER_USER_DATA_VS_11
9655 #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT                                                               0x0
9656 #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK                                                                 0xFFFFFFFFL
9657 //SPI_SHADER_USER_DATA_VS_12
9658 #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT                                                               0x0
9659 #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK                                                                 0xFFFFFFFFL
9660 //SPI_SHADER_USER_DATA_VS_13
9661 #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT                                                               0x0
9662 #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK                                                                 0xFFFFFFFFL
9663 //SPI_SHADER_USER_DATA_VS_14
9664 #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT                                                               0x0
9665 #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK                                                                 0xFFFFFFFFL
9666 //SPI_SHADER_USER_DATA_VS_15
9667 #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT                                                               0x0
9668 #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK                                                                 0xFFFFFFFFL
9669 //SPI_SHADER_USER_DATA_VS_16
9670 #define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT                                                               0x0
9671 #define SPI_SHADER_USER_DATA_VS_16__DATA_MASK                                                                 0xFFFFFFFFL
9672 //SPI_SHADER_USER_DATA_VS_17
9673 #define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT                                                               0x0
9674 #define SPI_SHADER_USER_DATA_VS_17__DATA_MASK                                                                 0xFFFFFFFFL
9675 //SPI_SHADER_USER_DATA_VS_18
9676 #define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT                                                               0x0
9677 #define SPI_SHADER_USER_DATA_VS_18__DATA_MASK                                                                 0xFFFFFFFFL
9678 //SPI_SHADER_USER_DATA_VS_19
9679 #define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT                                                               0x0
9680 #define SPI_SHADER_USER_DATA_VS_19__DATA_MASK                                                                 0xFFFFFFFFL
9681 //SPI_SHADER_USER_DATA_VS_20
9682 #define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT                                                               0x0
9683 #define SPI_SHADER_USER_DATA_VS_20__DATA_MASK                                                                 0xFFFFFFFFL
9684 //SPI_SHADER_USER_DATA_VS_21
9685 #define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT                                                               0x0
9686 #define SPI_SHADER_USER_DATA_VS_21__DATA_MASK                                                                 0xFFFFFFFFL
9687 //SPI_SHADER_USER_DATA_VS_22
9688 #define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT                                                               0x0
9689 #define SPI_SHADER_USER_DATA_VS_22__DATA_MASK                                                                 0xFFFFFFFFL
9690 //SPI_SHADER_USER_DATA_VS_23
9691 #define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT                                                               0x0
9692 #define SPI_SHADER_USER_DATA_VS_23__DATA_MASK                                                                 0xFFFFFFFFL
9693 //SPI_SHADER_USER_DATA_VS_24
9694 #define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT                                                               0x0
9695 #define SPI_SHADER_USER_DATA_VS_24__DATA_MASK                                                                 0xFFFFFFFFL
9696 //SPI_SHADER_USER_DATA_VS_25
9697 #define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT                                                               0x0
9698 #define SPI_SHADER_USER_DATA_VS_25__DATA_MASK                                                                 0xFFFFFFFFL
9699 //SPI_SHADER_USER_DATA_VS_26
9700 #define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT                                                               0x0
9701 #define SPI_SHADER_USER_DATA_VS_26__DATA_MASK                                                                 0xFFFFFFFFL
9702 //SPI_SHADER_USER_DATA_VS_27
9703 #define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT                                                               0x0
9704 #define SPI_SHADER_USER_DATA_VS_27__DATA_MASK                                                                 0xFFFFFFFFL
9705 //SPI_SHADER_USER_DATA_VS_28
9706 #define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT                                                               0x0
9707 #define SPI_SHADER_USER_DATA_VS_28__DATA_MASK                                                                 0xFFFFFFFFL
9708 //SPI_SHADER_USER_DATA_VS_29
9709 #define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT                                                               0x0
9710 #define SPI_SHADER_USER_DATA_VS_29__DATA_MASK                                                                 0xFFFFFFFFL
9711 //SPI_SHADER_USER_DATA_VS_30
9712 #define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT                                                               0x0
9713 #define SPI_SHADER_USER_DATA_VS_30__DATA_MASK                                                                 0xFFFFFFFFL
9714 //SPI_SHADER_USER_DATA_VS_31
9715 #define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT                                                               0x0
9716 #define SPI_SHADER_USER_DATA_VS_31__DATA_MASK                                                                 0xFFFFFFFFL
9717 //SPI_SHADER_PGM_RSRC2_GS_VS
9718 #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT                                                         0x0
9719 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT                                                          0x1
9720 #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT                                                       0x6
9721 #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT                                                            0x7
9722 #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT                                                      0x10
9723 #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT                                                          0x12
9724 #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT                                                           0x13
9725 #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT                                                        0x1b
9726 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT                                                      0x1c
9727 #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK                                                           0x00000001L
9728 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK                                                            0x0000003EL
9729 #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK                                                         0x00000040L
9730 #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK                                                              0x0000FF80L
9731 #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK                                                        0x00030000L
9732 #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK                                                            0x00040000L
9733 #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK                                                             0x07F80000L
9734 #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK                                                          0x08000000L
9735 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK                                                        0x10000000L
9736 //SPI_SHADER_PGM_RSRC4_GS
9737 #define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT                                                      0x0
9738 #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT                                              0x7
9739 #define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK                                                        0x0000007FL
9740 #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK                                                0x00003F80L
9741 //SPI_SHADER_USER_DATA_ADDR_LO_GS
9742 #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT                                                      0x0
9743 #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
9744 //SPI_SHADER_USER_DATA_ADDR_HI_GS
9745 #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT                                                      0x0
9746 #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
9747 //SPI_SHADER_PGM_LO_ES
9748 #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT                                                                 0x0
9749 #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9750 //SPI_SHADER_PGM_HI_ES
9751 #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT                                                                 0x0
9752 #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK                                                                   0xFFL
9753 //SPI_SHADER_PGM_RSRC3_GS
9754 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT                                                                 0x0
9755 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT                                                            0x10
9756 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
9757 #define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT                                                          0x1a
9758 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK                                                                   0x0000FFFFL
9759 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK                                                              0x003F0000L
9760 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
9761 #define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK                                                            0x3C000000L
9762 //SPI_SHADER_PGM_LO_GS
9763 #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT                                                                 0x0
9764 #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9765 //SPI_SHADER_PGM_HI_GS
9766 #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT                                                                 0x0
9767 #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK                                                                   0xFFL
9768 //SPI_SHADER_PGM_RSRC1_GS
9769 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT                                                                 0x0
9770 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT                                                                 0x6
9771 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT                                                              0xa
9772 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT                                                            0xc
9773 #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT                                                                  0x14
9774 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT                                                            0x15
9775 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT                                                            0x16
9776 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT                                                             0x17
9777 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT                                                       0x18
9778 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT                                                             0x1c
9779 #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT                                                      0x1d
9780 #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT                                                             0x1f
9781 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK                                                                   0x0000003FL
9782 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK                                                                   0x000003C0L
9783 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK                                                                0x00000C00L
9784 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK                                                              0x000FF000L
9785 #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK                                                                    0x00100000L
9786 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK                                                              0x00200000L
9787 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK                                                              0x00400000L
9788 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK                                                               0x00800000L
9789 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK                                                         0x01000000L
9790 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK                                                               0x10000000L
9791 #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK                                                        0x60000000L
9792 #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK                                                               0x80000000L
9793 //SPI_SHADER_PGM_RSRC2_GS
9794 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT                                                            0x0
9795 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT                                                             0x1
9796 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT                                                          0x6
9797 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT                                                               0x7
9798 #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT                                                      0x10
9799 #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT                                                             0x12
9800 #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT                                                              0x13
9801 #define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT                                                           0x1b
9802 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT                                                         0x1c
9803 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK                                                              0x00000001L
9804 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK                                                               0x0000003EL
9805 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK                                                            0x00000040L
9806 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK                                                                 0x0000FF80L
9807 #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK                                                        0x00030000L
9808 #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK                                                               0x00040000L
9809 #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK                                                                0x07F80000L
9810 #define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK                                                             0x08000000L
9811 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK                                                           0x10000000L
9812 //SPI_SHADER_USER_DATA_ES_0
9813 #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT                                                                0x0
9814 #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK                                                                  0xFFFFFFFFL
9815 //SPI_SHADER_USER_DATA_ES_1
9816 #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT                                                                0x0
9817 #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK                                                                  0xFFFFFFFFL
9818 //SPI_SHADER_USER_DATA_ES_2
9819 #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT                                                                0x0
9820 #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK                                                                  0xFFFFFFFFL
9821 //SPI_SHADER_USER_DATA_ES_3
9822 #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT                                                                0x0
9823 #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK                                                                  0xFFFFFFFFL
9824 //SPI_SHADER_USER_DATA_ES_4
9825 #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT                                                                0x0
9826 #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK                                                                  0xFFFFFFFFL
9827 //SPI_SHADER_USER_DATA_ES_5
9828 #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT                                                                0x0
9829 #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK                                                                  0xFFFFFFFFL
9830 //SPI_SHADER_USER_DATA_ES_6
9831 #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT                                                                0x0
9832 #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK                                                                  0xFFFFFFFFL
9833 //SPI_SHADER_USER_DATA_ES_7
9834 #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT                                                                0x0
9835 #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK                                                                  0xFFFFFFFFL
9836 //SPI_SHADER_USER_DATA_ES_8
9837 #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT                                                                0x0
9838 #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK                                                                  0xFFFFFFFFL
9839 //SPI_SHADER_USER_DATA_ES_9
9840 #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT                                                                0x0
9841 #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK                                                                  0xFFFFFFFFL
9842 //SPI_SHADER_USER_DATA_ES_10
9843 #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT                                                               0x0
9844 #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK                                                                 0xFFFFFFFFL
9845 //SPI_SHADER_USER_DATA_ES_11
9846 #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT                                                               0x0
9847 #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK                                                                 0xFFFFFFFFL
9848 //SPI_SHADER_USER_DATA_ES_12
9849 #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT                                                               0x0
9850 #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK                                                                 0xFFFFFFFFL
9851 //SPI_SHADER_USER_DATA_ES_13
9852 #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT                                                               0x0
9853 #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK                                                                 0xFFFFFFFFL
9854 //SPI_SHADER_USER_DATA_ES_14
9855 #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT                                                               0x0
9856 #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK                                                                 0xFFFFFFFFL
9857 //SPI_SHADER_USER_DATA_ES_15
9858 #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT                                                               0x0
9859 #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK                                                                 0xFFFFFFFFL
9860 //SPI_SHADER_USER_DATA_ES_16
9861 #define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT                                                               0x0
9862 #define SPI_SHADER_USER_DATA_ES_16__DATA_MASK                                                                 0xFFFFFFFFL
9863 //SPI_SHADER_USER_DATA_ES_17
9864 #define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT                                                               0x0
9865 #define SPI_SHADER_USER_DATA_ES_17__DATA_MASK                                                                 0xFFFFFFFFL
9866 //SPI_SHADER_USER_DATA_ES_18
9867 #define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT                                                               0x0
9868 #define SPI_SHADER_USER_DATA_ES_18__DATA_MASK                                                                 0xFFFFFFFFL
9869 //SPI_SHADER_USER_DATA_ES_19
9870 #define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT                                                               0x0
9871 #define SPI_SHADER_USER_DATA_ES_19__DATA_MASK                                                                 0xFFFFFFFFL
9872 //SPI_SHADER_USER_DATA_ES_20
9873 #define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT                                                               0x0
9874 #define SPI_SHADER_USER_DATA_ES_20__DATA_MASK                                                                 0xFFFFFFFFL
9875 //SPI_SHADER_USER_DATA_ES_21
9876 #define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT                                                               0x0
9877 #define SPI_SHADER_USER_DATA_ES_21__DATA_MASK                                                                 0xFFFFFFFFL
9878 //SPI_SHADER_USER_DATA_ES_22
9879 #define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT                                                               0x0
9880 #define SPI_SHADER_USER_DATA_ES_22__DATA_MASK                                                                 0xFFFFFFFFL
9881 //SPI_SHADER_USER_DATA_ES_23
9882 #define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT                                                               0x0
9883 #define SPI_SHADER_USER_DATA_ES_23__DATA_MASK                                                                 0xFFFFFFFFL
9884 //SPI_SHADER_USER_DATA_ES_24
9885 #define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT                                                               0x0
9886 #define SPI_SHADER_USER_DATA_ES_24__DATA_MASK                                                                 0xFFFFFFFFL
9887 //SPI_SHADER_USER_DATA_ES_25
9888 #define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT                                                               0x0
9889 #define SPI_SHADER_USER_DATA_ES_25__DATA_MASK                                                                 0xFFFFFFFFL
9890 //SPI_SHADER_USER_DATA_ES_26
9891 #define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT                                                               0x0
9892 #define SPI_SHADER_USER_DATA_ES_26__DATA_MASK                                                                 0xFFFFFFFFL
9893 //SPI_SHADER_USER_DATA_ES_27
9894 #define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT                                                               0x0
9895 #define SPI_SHADER_USER_DATA_ES_27__DATA_MASK                                                                 0xFFFFFFFFL
9896 //SPI_SHADER_USER_DATA_ES_28
9897 #define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT                                                               0x0
9898 #define SPI_SHADER_USER_DATA_ES_28__DATA_MASK                                                                 0xFFFFFFFFL
9899 //SPI_SHADER_USER_DATA_ES_29
9900 #define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT                                                               0x0
9901 #define SPI_SHADER_USER_DATA_ES_29__DATA_MASK                                                                 0xFFFFFFFFL
9902 //SPI_SHADER_USER_DATA_ES_30
9903 #define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT                                                               0x0
9904 #define SPI_SHADER_USER_DATA_ES_30__DATA_MASK                                                                 0xFFFFFFFFL
9905 //SPI_SHADER_USER_DATA_ES_31
9906 #define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT                                                               0x0
9907 #define SPI_SHADER_USER_DATA_ES_31__DATA_MASK                                                                 0xFFFFFFFFL
9908 //SPI_SHADER_PGM_RSRC4_HS
9909 #define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT                                                      0x0
9910 #define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK                                                        0x0000007FL
9911 //SPI_SHADER_USER_DATA_ADDR_LO_HS
9912 #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT                                                      0x0
9913 #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
9914 //SPI_SHADER_USER_DATA_ADDR_HI_HS
9915 #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT                                                      0x0
9916 #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
9917 //SPI_SHADER_PGM_LO_LS
9918 #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT                                                                 0x0
9919 #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9920 //SPI_SHADER_PGM_HI_LS
9921 #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT                                                                 0x0
9922 #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK                                                                   0xFFL
9923 //SPI_SHADER_PGM_RSRC3_HS
9924 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT                                                            0x0
9925 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x6
9926 #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT                                                          0xa
9927 #define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT                                                                 0x10
9928 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK                                                              0x0000003FL
9929 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK                                                      0x000003C0L
9930 #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK                                                            0x00003C00L
9931 #define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK                                                                   0xFFFF0000L
9932 //SPI_SHADER_PGM_LO_HS
9933 #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT                                                                 0x0
9934 #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9935 //SPI_SHADER_PGM_HI_HS
9936 #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT                                                                 0x0
9937 #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK                                                                   0xFFL
9938 //SPI_SHADER_PGM_RSRC1_HS
9939 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT                                                                 0x0
9940 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT                                                                 0x6
9941 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT                                                              0xa
9942 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT                                                            0xc
9943 #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT                                                                  0x14
9944 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT                                                            0x15
9945 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT                                                            0x16
9946 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT                                                             0x17
9947 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT                                                             0x1b
9948 #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT                                                      0x1c
9949 #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT                                                             0x1e
9950 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK                                                                   0x0000003FL
9951 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK                                                                   0x000003C0L
9952 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK                                                                0x00000C00L
9953 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK                                                              0x000FF000L
9954 #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK                                                                    0x00100000L
9955 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK                                                              0x00200000L
9956 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK                                                              0x00400000L
9957 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK                                                               0x00800000L
9958 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK                                                               0x08000000L
9959 #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK                                                        0x30000000L
9960 #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK                                                               0x40000000L
9961 //SPI_SHADER_PGM_RSRC2_HS
9962 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT                                                            0x0
9963 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT                                                             0x1
9964 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT                                                          0x6
9965 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT                                                               0x7
9966 #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT                                                              0x10
9967 #define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT                                                           0x1b
9968 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT                                                         0x1c
9969 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK                                                              0x00000001L
9970 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK                                                               0x0000003EL
9971 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK                                                            0x00000040L
9972 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK                                                                 0x0000FF80L
9973 #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK                                                                0x01FF0000L
9974 #define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK                                                             0x08000000L
9975 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK                                                           0x10000000L
9976 //SPI_SHADER_USER_DATA_LS_0
9977 #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT                                                                0x0
9978 #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK                                                                  0xFFFFFFFFL
9979 //SPI_SHADER_USER_DATA_LS_1
9980 #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT                                                                0x0
9981 #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK                                                                  0xFFFFFFFFL
9982 //SPI_SHADER_USER_DATA_LS_2
9983 #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT                                                                0x0
9984 #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK                                                                  0xFFFFFFFFL
9985 //SPI_SHADER_USER_DATA_LS_3
9986 #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT                                                                0x0
9987 #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK                                                                  0xFFFFFFFFL
9988 //SPI_SHADER_USER_DATA_LS_4
9989 #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT                                                                0x0
9990 #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK                                                                  0xFFFFFFFFL
9991 //SPI_SHADER_USER_DATA_LS_5
9992 #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT                                                                0x0
9993 #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK                                                                  0xFFFFFFFFL
9994 //SPI_SHADER_USER_DATA_LS_6
9995 #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT                                                                0x0
9996 #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK                                                                  0xFFFFFFFFL
9997 //SPI_SHADER_USER_DATA_LS_7
9998 #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT                                                                0x0
9999 #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK                                                                  0xFFFFFFFFL
10000 //SPI_SHADER_USER_DATA_LS_8
10001 #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT                                                                0x0
10002 #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK                                                                  0xFFFFFFFFL
10003 //SPI_SHADER_USER_DATA_LS_9
10004 #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT                                                                0x0
10005 #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK                                                                  0xFFFFFFFFL
10006 //SPI_SHADER_USER_DATA_LS_10
10007 #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT                                                               0x0
10008 #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK                                                                 0xFFFFFFFFL
10009 //SPI_SHADER_USER_DATA_LS_11
10010 #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT                                                               0x0
10011 #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK                                                                 0xFFFFFFFFL
10012 //SPI_SHADER_USER_DATA_LS_12
10013 #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT                                                               0x0
10014 #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK                                                                 0xFFFFFFFFL
10015 //SPI_SHADER_USER_DATA_LS_13
10016 #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT                                                               0x0
10017 #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK                                                                 0xFFFFFFFFL
10018 //SPI_SHADER_USER_DATA_LS_14
10019 #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT                                                               0x0
10020 #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK                                                                 0xFFFFFFFFL
10021 //SPI_SHADER_USER_DATA_LS_15
10022 #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT                                                               0x0
10023 #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK                                                                 0xFFFFFFFFL
10024 //SPI_SHADER_USER_DATA_LS_16
10025 #define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT                                                               0x0
10026 #define SPI_SHADER_USER_DATA_LS_16__DATA_MASK                                                                 0xFFFFFFFFL
10027 //SPI_SHADER_USER_DATA_LS_17
10028 #define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT                                                               0x0
10029 #define SPI_SHADER_USER_DATA_LS_17__DATA_MASK                                                                 0xFFFFFFFFL
10030 //SPI_SHADER_USER_DATA_LS_18
10031 #define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT                                                               0x0
10032 #define SPI_SHADER_USER_DATA_LS_18__DATA_MASK                                                                 0xFFFFFFFFL
10033 //SPI_SHADER_USER_DATA_LS_19
10034 #define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT                                                               0x0
10035 #define SPI_SHADER_USER_DATA_LS_19__DATA_MASK                                                                 0xFFFFFFFFL
10036 //SPI_SHADER_USER_DATA_LS_20
10037 #define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT                                                               0x0
10038 #define SPI_SHADER_USER_DATA_LS_20__DATA_MASK                                                                 0xFFFFFFFFL
10039 //SPI_SHADER_USER_DATA_LS_21
10040 #define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT                                                               0x0
10041 #define SPI_SHADER_USER_DATA_LS_21__DATA_MASK                                                                 0xFFFFFFFFL
10042 //SPI_SHADER_USER_DATA_LS_22
10043 #define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT                                                               0x0
10044 #define SPI_SHADER_USER_DATA_LS_22__DATA_MASK                                                                 0xFFFFFFFFL
10045 //SPI_SHADER_USER_DATA_LS_23
10046 #define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT                                                               0x0
10047 #define SPI_SHADER_USER_DATA_LS_23__DATA_MASK                                                                 0xFFFFFFFFL
10048 //SPI_SHADER_USER_DATA_LS_24
10049 #define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT                                                               0x0
10050 #define SPI_SHADER_USER_DATA_LS_24__DATA_MASK                                                                 0xFFFFFFFFL
10051 //SPI_SHADER_USER_DATA_LS_25
10052 #define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT                                                               0x0
10053 #define SPI_SHADER_USER_DATA_LS_25__DATA_MASK                                                                 0xFFFFFFFFL
10054 //SPI_SHADER_USER_DATA_LS_26
10055 #define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT                                                               0x0
10056 #define SPI_SHADER_USER_DATA_LS_26__DATA_MASK                                                                 0xFFFFFFFFL
10057 //SPI_SHADER_USER_DATA_LS_27
10058 #define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT                                                               0x0
10059 #define SPI_SHADER_USER_DATA_LS_27__DATA_MASK                                                                 0xFFFFFFFFL
10060 //SPI_SHADER_USER_DATA_LS_28
10061 #define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT                                                               0x0
10062 #define SPI_SHADER_USER_DATA_LS_28__DATA_MASK                                                                 0xFFFFFFFFL
10063 //SPI_SHADER_USER_DATA_LS_29
10064 #define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT                                                               0x0
10065 #define SPI_SHADER_USER_DATA_LS_29__DATA_MASK                                                                 0xFFFFFFFFL
10066 //SPI_SHADER_USER_DATA_LS_30
10067 #define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT                                                               0x0
10068 #define SPI_SHADER_USER_DATA_LS_30__DATA_MASK                                                                 0xFFFFFFFFL
10069 //SPI_SHADER_USER_DATA_LS_31
10070 #define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT                                                               0x0
10071 #define SPI_SHADER_USER_DATA_LS_31__DATA_MASK                                                                 0xFFFFFFFFL
10072 //SPI_SHADER_USER_DATA_COMMON_0
10073 #define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT                                                            0x0
10074 #define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK                                                              0xFFFFFFFFL
10075 //SPI_SHADER_USER_DATA_COMMON_1
10076 #define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT                                                            0x0
10077 #define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK                                                              0xFFFFFFFFL
10078 //SPI_SHADER_USER_DATA_COMMON_2
10079 #define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT                                                            0x0
10080 #define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK                                                              0xFFFFFFFFL
10081 //SPI_SHADER_USER_DATA_COMMON_3
10082 #define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT                                                            0x0
10083 #define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK                                                              0xFFFFFFFFL
10084 //SPI_SHADER_USER_DATA_COMMON_4
10085 #define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT                                                            0x0
10086 #define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK                                                              0xFFFFFFFFL
10087 //SPI_SHADER_USER_DATA_COMMON_5
10088 #define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT                                                            0x0
10089 #define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK                                                              0xFFFFFFFFL
10090 //SPI_SHADER_USER_DATA_COMMON_6
10091 #define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT                                                            0x0
10092 #define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK                                                              0xFFFFFFFFL
10093 //SPI_SHADER_USER_DATA_COMMON_7
10094 #define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT                                                            0x0
10095 #define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK                                                              0xFFFFFFFFL
10096 //SPI_SHADER_USER_DATA_COMMON_8
10097 #define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT                                                            0x0
10098 #define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK                                                              0xFFFFFFFFL
10099 //SPI_SHADER_USER_DATA_COMMON_9
10100 #define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT                                                            0x0
10101 #define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK                                                              0xFFFFFFFFL
10102 //SPI_SHADER_USER_DATA_COMMON_10
10103 #define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT                                                           0x0
10104 #define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK                                                             0xFFFFFFFFL
10105 //SPI_SHADER_USER_DATA_COMMON_11
10106 #define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT                                                           0x0
10107 #define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK                                                             0xFFFFFFFFL
10108 //SPI_SHADER_USER_DATA_COMMON_12
10109 #define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT                                                           0x0
10110 #define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK                                                             0xFFFFFFFFL
10111 //SPI_SHADER_USER_DATA_COMMON_13
10112 #define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT                                                           0x0
10113 #define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK                                                             0xFFFFFFFFL
10114 //SPI_SHADER_USER_DATA_COMMON_14
10115 #define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT                                                           0x0
10116 #define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK                                                             0xFFFFFFFFL
10117 //SPI_SHADER_USER_DATA_COMMON_15
10118 #define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT                                                           0x0
10119 #define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK                                                             0xFFFFFFFFL
10120 //SPI_SHADER_USER_DATA_COMMON_16
10121 #define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT                                                           0x0
10122 #define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK                                                             0xFFFFFFFFL
10123 //SPI_SHADER_USER_DATA_COMMON_17
10124 #define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT                                                           0x0
10125 #define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK                                                             0xFFFFFFFFL
10126 //SPI_SHADER_USER_DATA_COMMON_18
10127 #define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT                                                           0x0
10128 #define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK                                                             0xFFFFFFFFL
10129 //SPI_SHADER_USER_DATA_COMMON_19
10130 #define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT                                                           0x0
10131 #define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK                                                             0xFFFFFFFFL
10132 //SPI_SHADER_USER_DATA_COMMON_20
10133 #define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT                                                           0x0
10134 #define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK                                                             0xFFFFFFFFL
10135 //SPI_SHADER_USER_DATA_COMMON_21
10136 #define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT                                                           0x0
10137 #define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK                                                             0xFFFFFFFFL
10138 //SPI_SHADER_USER_DATA_COMMON_22
10139 #define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT                                                           0x0
10140 #define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK                                                             0xFFFFFFFFL
10141 //SPI_SHADER_USER_DATA_COMMON_23
10142 #define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT                                                           0x0
10143 #define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK                                                             0xFFFFFFFFL
10144 //SPI_SHADER_USER_DATA_COMMON_24
10145 #define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT                                                           0x0
10146 #define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK                                                             0xFFFFFFFFL
10147 //SPI_SHADER_USER_DATA_COMMON_25
10148 #define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT                                                           0x0
10149 #define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK                                                             0xFFFFFFFFL
10150 //SPI_SHADER_USER_DATA_COMMON_26
10151 #define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT                                                           0x0
10152 #define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK                                                             0xFFFFFFFFL
10153 //SPI_SHADER_USER_DATA_COMMON_27
10154 #define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT                                                           0x0
10155 #define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK                                                             0xFFFFFFFFL
10156 //SPI_SHADER_USER_DATA_COMMON_28
10157 #define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT                                                           0x0
10158 #define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK                                                             0xFFFFFFFFL
10159 //SPI_SHADER_USER_DATA_COMMON_29
10160 #define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT                                                           0x0
10161 #define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK                                                             0xFFFFFFFFL
10162 //SPI_SHADER_USER_DATA_COMMON_30
10163 #define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT                                                           0x0
10164 #define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK                                                             0xFFFFFFFFL
10165 //SPI_SHADER_USER_DATA_COMMON_31
10166 #define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT                                                           0x0
10167 #define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK                                                             0xFFFFFFFFL
10168 //COMPUTE_DISPATCH_INITIATOR
10169 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT                                                  0x0
10170 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT                                                      0x1
10171 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT                                                 0x2
10172 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT                                                0x3
10173 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT                                                0x4
10174 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT                                              0x5
10175 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT                                                         0x6
10176 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT                                                  0xa
10177 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT                                                  0xb
10178 #define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT                                                           0xc
10179 #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT                                                            0xe
10180 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK                                                    0x00000001L
10181 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK                                                        0x00000002L
10182 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK                                                   0x00000004L
10183 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK                                                  0x00000008L
10184 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK                                                  0x00000010L
10185 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK                                                0x00000020L
10186 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK                                                           0x00000040L
10187 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK                                                    0x00000400L
10188 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK                                                    0x00000800L
10189 #define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK                                                             0x00001000L
10190 #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK                                                              0x00004000L
10191 //COMPUTE_DIM_X
10192 #define COMPUTE_DIM_X__SIZE__SHIFT                                                                            0x0
10193 #define COMPUTE_DIM_X__SIZE_MASK                                                                              0xFFFFFFFFL
10194 //COMPUTE_DIM_Y
10195 #define COMPUTE_DIM_Y__SIZE__SHIFT                                                                            0x0
10196 #define COMPUTE_DIM_Y__SIZE_MASK                                                                              0xFFFFFFFFL
10197 //COMPUTE_DIM_Z
10198 #define COMPUTE_DIM_Z__SIZE__SHIFT                                                                            0x0
10199 #define COMPUTE_DIM_Z__SIZE_MASK                                                                              0xFFFFFFFFL
10200 //COMPUTE_START_X
10201 #define COMPUTE_START_X__START__SHIFT                                                                         0x0
10202 #define COMPUTE_START_X__START_MASK                                                                           0xFFFFFFFFL
10203 //COMPUTE_START_Y
10204 #define COMPUTE_START_Y__START__SHIFT                                                                         0x0
10205 #define COMPUTE_START_Y__START_MASK                                                                           0xFFFFFFFFL
10206 //COMPUTE_START_Z
10207 #define COMPUTE_START_Z__START__SHIFT                                                                         0x0
10208 #define COMPUTE_START_Z__START_MASK                                                                           0xFFFFFFFFL
10209 //COMPUTE_NUM_THREAD_X
10210 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT                                                          0x0
10211 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
10212 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
10213 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
10214 //COMPUTE_NUM_THREAD_Y
10215 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT                                                          0x0
10216 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
10217 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
10218 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
10219 //COMPUTE_NUM_THREAD_Z
10220 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT                                                          0x0
10221 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
10222 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
10223 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
10224 //COMPUTE_PIPELINESTAT_ENABLE
10225 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT                                               0x0
10226 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK                                                 0x00000001L
10227 //COMPUTE_PERFCOUNT_ENABLE
10228 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT                                                     0x0
10229 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK                                                       0x00000001L
10230 //COMPUTE_PGM_LO
10231 #define COMPUTE_PGM_LO__DATA__SHIFT                                                                           0x0
10232 #define COMPUTE_PGM_LO__DATA_MASK                                                                             0xFFFFFFFFL
10233 //COMPUTE_PGM_HI
10234 #define COMPUTE_PGM_HI__DATA__SHIFT                                                                           0x0
10235 #define COMPUTE_PGM_HI__DATA_MASK                                                                             0x000000FFL
10236 //COMPUTE_DISPATCH_PKT_ADDR_LO
10237 #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT                                                             0x0
10238 #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK                                                               0xFFFFFFFFL
10239 //COMPUTE_DISPATCH_PKT_ADDR_HI
10240 #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT                                                             0x0
10241 #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK                                                               0x000000FFL
10242 //COMPUTE_DISPATCH_SCRATCH_BASE_LO
10243 #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT                                                         0x0
10244 #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK                                                           0xFFFFFFFFL
10245 //COMPUTE_DISPATCH_SCRATCH_BASE_HI
10246 #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT                                                         0x0
10247 #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK                                                           0x000000FFL
10248 //COMPUTE_PGM_RSRC1
10249 #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT                                                                       0x0
10250 #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT                                                                       0x6
10251 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT                                                                    0xa
10252 #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT                                                                  0xc
10253 #define COMPUTE_PGM_RSRC1__PRIV__SHIFT                                                                        0x14
10254 #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT                                                                  0x15
10255 #define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT                                                                  0x16
10256 #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT                                                                   0x17
10257 #define COMPUTE_PGM_RSRC1__BULKY__SHIFT                                                                       0x18
10258 #define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT                                                                   0x19
10259 #define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT                                                                   0x1a
10260 #define COMPUTE_PGM_RSRC1__VGPRS_MASK                                                                         0x0000003FL
10261 #define COMPUTE_PGM_RSRC1__SGPRS_MASK                                                                         0x000003C0L
10262 #define COMPUTE_PGM_RSRC1__PRIORITY_MASK                                                                      0x00000C00L
10263 #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK                                                                    0x000FF000L
10264 #define COMPUTE_PGM_RSRC1__PRIV_MASK                                                                          0x00100000L
10265 #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK                                                                    0x00200000L
10266 #define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK                                                                    0x00400000L
10267 #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK                                                                     0x00800000L
10268 #define COMPUTE_PGM_RSRC1__BULKY_MASK                                                                         0x01000000L
10269 #define COMPUTE_PGM_RSRC1__CDBG_USER_MASK                                                                     0x02000000L
10270 #define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK                                                                     0x04000000L
10271 //COMPUTE_PGM_RSRC2
10272 #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT                                                                  0x0
10273 #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT                                                                   0x1
10274 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT                                                                0x6
10275 #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT                                                                   0x7
10276 #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT                                                                   0x8
10277 #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT                                                                   0x9
10278 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT                                                                  0xa
10279 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT                                                              0xb
10280 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT                                                                 0xd
10281 #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT                                                                    0xf
10282 #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT                                                                     0x18
10283 #define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT                                                                 0x1f
10284 #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK                                                                    0x00000001L
10285 #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK                                                                     0x0000003EL
10286 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK                                                                  0x00000040L
10287 #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK                                                                     0x00000080L
10288 #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK                                                                     0x00000100L
10289 #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK                                                                     0x00000200L
10290 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK                                                                    0x00000400L
10291 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK                                                                0x00001800L
10292 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK                                                                   0x00006000L
10293 #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK                                                                      0x00FF8000L
10294 #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK                                                                       0x7F000000L
10295 #define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK                                                                   0x80000000L
10296 //COMPUTE_VMID
10297 #define COMPUTE_VMID__DATA__SHIFT                                                                             0x0
10298 #define COMPUTE_VMID__DATA_MASK                                                                               0x0000000FL
10299 //COMPUTE_RESOURCE_LIMITS
10300 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT                                                          0x0
10301 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT                                                             0xc
10302 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT                                                        0x10
10303 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT                                                        0x16
10304 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT                                                       0x17
10305 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT                                                        0x18
10306 #define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT                                                          0x1b
10307 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK                                                            0x000003FFL
10308 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK                                                               0x0000F000L
10309 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK                                                          0x003F0000L
10310 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK                                                          0x00400000L
10311 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK                                                         0x00800000L
10312 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK                                                          0x07000000L
10313 #define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK                                                            0x78000000L
10314 //COMPUTE_STATIC_THREAD_MGMT_SE0
10315 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT                                                      0x0
10316 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT                                                      0x10
10317 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK                                                        0x0000FFFFL
10318 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK                                                        0xFFFF0000L
10319 //COMPUTE_STATIC_THREAD_MGMT_SE1
10320 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT                                                      0x0
10321 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT                                                      0x10
10322 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK                                                        0x0000FFFFL
10323 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK                                                        0xFFFF0000L
10324 //COMPUTE_TMPRING_SIZE
10325 #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT                                                                    0x0
10326 #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT                                                                 0xc
10327 #define COMPUTE_TMPRING_SIZE__WAVES_MASK                                                                      0x00000FFFL
10328 #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK                                                                   0x01FFF000L
10329 //COMPUTE_STATIC_THREAD_MGMT_SE2
10330 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT                                                      0x0
10331 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT                                                      0x10
10332 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK                                                        0x0000FFFFL
10333 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK                                                        0xFFFF0000L
10334 //COMPUTE_STATIC_THREAD_MGMT_SE3
10335 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT                                                      0x0
10336 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT                                                      0x10
10337 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK                                                        0x0000FFFFL
10338 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK                                                        0xFFFF0000L
10339 //COMPUTE_RESTART_X
10340 #define COMPUTE_RESTART_X__RESTART__SHIFT                                                                     0x0
10341 #define COMPUTE_RESTART_X__RESTART_MASK                                                                       0xFFFFFFFFL
10342 //COMPUTE_RESTART_Y
10343 #define COMPUTE_RESTART_Y__RESTART__SHIFT                                                                     0x0
10344 #define COMPUTE_RESTART_Y__RESTART_MASK                                                                       0xFFFFFFFFL
10345 //COMPUTE_RESTART_Z
10346 #define COMPUTE_RESTART_Z__RESTART__SHIFT                                                                     0x0
10347 #define COMPUTE_RESTART_Z__RESTART_MASK                                                                       0xFFFFFFFFL
10348 //COMPUTE_THREAD_TRACE_ENABLE
10349 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT                                               0x0
10350 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK                                                 0x00000001L
10351 //COMPUTE_MISC_RESERVED
10352 #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT                                                               0x0
10353 #define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT                                                               0x2
10354 #define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT                                                               0x3
10355 #define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT                                                               0x4
10356 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT                                                            0x5
10357 #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK                                                                 0x00000003L
10358 #define COMPUTE_MISC_RESERVED__RESERVED2_MASK                                                                 0x00000004L
10359 #define COMPUTE_MISC_RESERVED__RESERVED3_MASK                                                                 0x00000008L
10360 #define COMPUTE_MISC_RESERVED__RESERVED4_MASK                                                                 0x00000010L
10361 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK                                                              0x0001FFE0L
10362 //COMPUTE_DISPATCH_ID
10363 #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT                                                               0x0
10364 #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK                                                                 0xFFFFFFFFL
10365 //COMPUTE_THREADGROUP_ID
10366 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT                                                         0x0
10367 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK                                                           0xFFFFFFFFL
10368 //COMPUTE_RELAUNCH
10369 #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT                                                                      0x0
10370 #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT                                                                     0x1e
10371 #define COMPUTE_RELAUNCH__IS_STATE__SHIFT                                                                     0x1f
10372 #define COMPUTE_RELAUNCH__PAYLOAD_MASK                                                                        0x3FFFFFFFL
10373 #define COMPUTE_RELAUNCH__IS_EVENT_MASK                                                                       0x40000000L
10374 #define COMPUTE_RELAUNCH__IS_STATE_MASK                                                                       0x80000000L
10375 //COMPUTE_WAVE_RESTORE_ADDR_LO
10376 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT                                                             0x0
10377 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK                                                               0xFFFFFFFFL
10378 //COMPUTE_WAVE_RESTORE_ADDR_HI
10379 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT                                                             0x0
10380 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK                                                               0xFFFFL
10381 //COMPUTE_USER_DATA_0
10382 #define COMPUTE_USER_DATA_0__DATA__SHIFT                                                                      0x0
10383 #define COMPUTE_USER_DATA_0__DATA_MASK                                                                        0xFFFFFFFFL
10384 //COMPUTE_USER_DATA_1
10385 #define COMPUTE_USER_DATA_1__DATA__SHIFT                                                                      0x0
10386 #define COMPUTE_USER_DATA_1__DATA_MASK                                                                        0xFFFFFFFFL
10387 //COMPUTE_USER_DATA_2
10388 #define COMPUTE_USER_DATA_2__DATA__SHIFT                                                                      0x0
10389 #define COMPUTE_USER_DATA_2__DATA_MASK                                                                        0xFFFFFFFFL
10390 //COMPUTE_USER_DATA_3
10391 #define COMPUTE_USER_DATA_3__DATA__SHIFT                                                                      0x0
10392 #define COMPUTE_USER_DATA_3__DATA_MASK                                                                        0xFFFFFFFFL
10393 //COMPUTE_USER_DATA_4
10394 #define COMPUTE_USER_DATA_4__DATA__SHIFT                                                                      0x0
10395 #define COMPUTE_USER_DATA_4__DATA_MASK                                                                        0xFFFFFFFFL
10396 //COMPUTE_USER_DATA_5
10397 #define COMPUTE_USER_DATA_5__DATA__SHIFT                                                                      0x0
10398 #define COMPUTE_USER_DATA_5__DATA_MASK                                                                        0xFFFFFFFFL
10399 //COMPUTE_USER_DATA_6
10400 #define COMPUTE_USER_DATA_6__DATA__SHIFT                                                                      0x0
10401 #define COMPUTE_USER_DATA_6__DATA_MASK                                                                        0xFFFFFFFFL
10402 //COMPUTE_USER_DATA_7
10403 #define COMPUTE_USER_DATA_7__DATA__SHIFT                                                                      0x0
10404 #define COMPUTE_USER_DATA_7__DATA_MASK                                                                        0xFFFFFFFFL
10405 //COMPUTE_USER_DATA_8
10406 #define COMPUTE_USER_DATA_8__DATA__SHIFT                                                                      0x0
10407 #define COMPUTE_USER_DATA_8__DATA_MASK                                                                        0xFFFFFFFFL
10408 //COMPUTE_USER_DATA_9
10409 #define COMPUTE_USER_DATA_9__DATA__SHIFT                                                                      0x0
10410 #define COMPUTE_USER_DATA_9__DATA_MASK                                                                        0xFFFFFFFFL
10411 //COMPUTE_USER_DATA_10
10412 #define COMPUTE_USER_DATA_10__DATA__SHIFT                                                                     0x0
10413 #define COMPUTE_USER_DATA_10__DATA_MASK                                                                       0xFFFFFFFFL
10414 //COMPUTE_USER_DATA_11
10415 #define COMPUTE_USER_DATA_11__DATA__SHIFT                                                                     0x0
10416 #define COMPUTE_USER_DATA_11__DATA_MASK                                                                       0xFFFFFFFFL
10417 //COMPUTE_USER_DATA_12
10418 #define COMPUTE_USER_DATA_12__DATA__SHIFT                                                                     0x0
10419 #define COMPUTE_USER_DATA_12__DATA_MASK                                                                       0xFFFFFFFFL
10420 //COMPUTE_USER_DATA_13
10421 #define COMPUTE_USER_DATA_13__DATA__SHIFT                                                                     0x0
10422 #define COMPUTE_USER_DATA_13__DATA_MASK                                                                       0xFFFFFFFFL
10423 //COMPUTE_USER_DATA_14
10424 #define COMPUTE_USER_DATA_14__DATA__SHIFT                                                                     0x0
10425 #define COMPUTE_USER_DATA_14__DATA_MASK                                                                       0xFFFFFFFFL
10426 //COMPUTE_USER_DATA_15
10427 #define COMPUTE_USER_DATA_15__DATA__SHIFT                                                                     0x0
10428 #define COMPUTE_USER_DATA_15__DATA_MASK                                                                       0xFFFFFFFFL
10429 //COMPUTE_NOWHERE
10430 #define COMPUTE_NOWHERE__DATA__SHIFT                                                                          0x0
10431 #define COMPUTE_NOWHERE__DATA_MASK                                                                            0xFFFFFFFFL
10432 
10433 
10434 // addressBlock: gc_cppdec
10435 //CP_DFY_CNTL
10436 #define CP_DFY_CNTL__POLICY__SHIFT                                                                            0x0
10437 #define CP_DFY_CNTL__MTYPE__SHIFT                                                                             0x2
10438 #define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT                                                                       0x1a
10439 #define CP_DFY_CNTL__LFSR_RESET__SHIFT                                                                        0x1c
10440 #define CP_DFY_CNTL__MODE__SHIFT                                                                              0x1d
10441 #define CP_DFY_CNTL__ENABLE__SHIFT                                                                            0x1f
10442 #define CP_DFY_CNTL__POLICY_MASK                                                                              0x00000001L
10443 #define CP_DFY_CNTL__MTYPE_MASK                                                                               0x0000000CL
10444 #define CP_DFY_CNTL__TPI_SDP_SEL_MASK                                                                         0x04000000L
10445 #define CP_DFY_CNTL__LFSR_RESET_MASK                                                                          0x10000000L
10446 #define CP_DFY_CNTL__MODE_MASK                                                                                0x60000000L
10447 #define CP_DFY_CNTL__ENABLE_MASK                                                                              0x80000000L
10448 //CP_DFY_STAT
10449 #define CP_DFY_STAT__BURST_COUNT__SHIFT                                                                       0x0
10450 #define CP_DFY_STAT__TAGS_PENDING__SHIFT                                                                      0x10
10451 #define CP_DFY_STAT__BUSY__SHIFT                                                                              0x1f
10452 #define CP_DFY_STAT__BURST_COUNT_MASK                                                                         0x0000FFFFL
10453 #define CP_DFY_STAT__TAGS_PENDING_MASK                                                                        0x07FF0000L
10454 #define CP_DFY_STAT__BUSY_MASK                                                                                0x80000000L
10455 //CP_DFY_ADDR_HI
10456 #define CP_DFY_ADDR_HI__ADDR_HI__SHIFT                                                                        0x0
10457 #define CP_DFY_ADDR_HI__ADDR_HI_MASK                                                                          0xFFFFFFFFL
10458 //CP_DFY_ADDR_LO
10459 #define CP_DFY_ADDR_LO__ADDR_LO__SHIFT                                                                        0x5
10460 #define CP_DFY_ADDR_LO__ADDR_LO_MASK                                                                          0xFFFFFFE0L
10461 //CP_DFY_DATA_0
10462 #define CP_DFY_DATA_0__DATA__SHIFT                                                                            0x0
10463 #define CP_DFY_DATA_0__DATA_MASK                                                                              0xFFFFFFFFL
10464 //CP_DFY_DATA_1
10465 #define CP_DFY_DATA_1__DATA__SHIFT                                                                            0x0
10466 #define CP_DFY_DATA_1__DATA_MASK                                                                              0xFFFFFFFFL
10467 //CP_DFY_DATA_2
10468 #define CP_DFY_DATA_2__DATA__SHIFT                                                                            0x0
10469 #define CP_DFY_DATA_2__DATA_MASK                                                                              0xFFFFFFFFL
10470 //CP_DFY_DATA_3
10471 #define CP_DFY_DATA_3__DATA__SHIFT                                                                            0x0
10472 #define CP_DFY_DATA_3__DATA_MASK                                                                              0xFFFFFFFFL
10473 //CP_DFY_DATA_4
10474 #define CP_DFY_DATA_4__DATA__SHIFT                                                                            0x0
10475 #define CP_DFY_DATA_4__DATA_MASK                                                                              0xFFFFFFFFL
10476 //CP_DFY_DATA_5
10477 #define CP_DFY_DATA_5__DATA__SHIFT                                                                            0x0
10478 #define CP_DFY_DATA_5__DATA_MASK                                                                              0xFFFFFFFFL
10479 //CP_DFY_DATA_6
10480 #define CP_DFY_DATA_6__DATA__SHIFT                                                                            0x0
10481 #define CP_DFY_DATA_6__DATA_MASK                                                                              0xFFFFFFFFL
10482 //CP_DFY_DATA_7
10483 #define CP_DFY_DATA_7__DATA__SHIFT                                                                            0x0
10484 #define CP_DFY_DATA_7__DATA_MASK                                                                              0xFFFFFFFFL
10485 //CP_DFY_DATA_8
10486 #define CP_DFY_DATA_8__DATA__SHIFT                                                                            0x0
10487 #define CP_DFY_DATA_8__DATA_MASK                                                                              0xFFFFFFFFL
10488 //CP_DFY_DATA_9
10489 #define CP_DFY_DATA_9__DATA__SHIFT                                                                            0x0
10490 #define CP_DFY_DATA_9__DATA_MASK                                                                              0xFFFFFFFFL
10491 //CP_DFY_DATA_10
10492 #define CP_DFY_DATA_10__DATA__SHIFT                                                                           0x0
10493 #define CP_DFY_DATA_10__DATA_MASK                                                                             0xFFFFFFFFL
10494 //CP_DFY_DATA_11
10495 #define CP_DFY_DATA_11__DATA__SHIFT                                                                           0x0
10496 #define CP_DFY_DATA_11__DATA_MASK                                                                             0xFFFFFFFFL
10497 //CP_DFY_DATA_12
10498 #define CP_DFY_DATA_12__DATA__SHIFT                                                                           0x0
10499 #define CP_DFY_DATA_12__DATA_MASK                                                                             0xFFFFFFFFL
10500 //CP_DFY_DATA_13
10501 #define CP_DFY_DATA_13__DATA__SHIFT                                                                           0x0
10502 #define CP_DFY_DATA_13__DATA_MASK                                                                             0xFFFFFFFFL
10503 //CP_DFY_DATA_14
10504 #define CP_DFY_DATA_14__DATA__SHIFT                                                                           0x0
10505 #define CP_DFY_DATA_14__DATA_MASK                                                                             0xFFFFFFFFL
10506 //CP_DFY_DATA_15
10507 #define CP_DFY_DATA_15__DATA__SHIFT                                                                           0x0
10508 #define CP_DFY_DATA_15__DATA_MASK                                                                             0xFFFFFFFFL
10509 //CP_DFY_CMD
10510 #define CP_DFY_CMD__OFFSET__SHIFT                                                                             0x0
10511 #define CP_DFY_CMD__SIZE__SHIFT                                                                               0x10
10512 #define CP_DFY_CMD__OFFSET_MASK                                                                               0x000001FFL
10513 #define CP_DFY_CMD__SIZE_MASK                                                                                 0xFFFF0000L
10514 //CP_EOPQ_WAIT_TIME
10515 #define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT                                                                   0x0
10516 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT                                                                 0xa
10517 #define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK                                                                     0x000003FFL
10518 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK                                                                   0x0003FC00L
10519 //CP_CPC_MGCG_SYNC_CNTL
10520 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT                                                         0x0
10521 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT                                                           0x8
10522 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK                                                           0x000000FFL
10523 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK                                                             0x0000FF00L
10524 //CPC_INT_INFO
10525 #define CPC_INT_INFO__ADDR_HI__SHIFT                                                                          0x0
10526 #define CPC_INT_INFO__TYPE__SHIFT                                                                             0x10
10527 #define CPC_INT_INFO__VMID__SHIFT                                                                             0x14
10528 #define CPC_INT_INFO__QUEUE_ID__SHIFT                                                                         0x1c
10529 #define CPC_INT_INFO__ADDR_HI_MASK                                                                            0x0000FFFFL
10530 #define CPC_INT_INFO__TYPE_MASK                                                                               0x00010000L
10531 #define CPC_INT_INFO__VMID_MASK                                                                               0x00F00000L
10532 #define CPC_INT_INFO__QUEUE_ID_MASK                                                                           0x70000000L
10533 //CP_VIRT_STATUS
10534 #define CP_VIRT_STATUS__VIRT_STATUS__SHIFT                                                                    0x0
10535 #define CP_VIRT_STATUS__VIRT_STATUS_MASK                                                                      0xFFFFFFFFL
10536 //CPC_INT_ADDR
10537 #define CPC_INT_ADDR__ADDR__SHIFT                                                                             0x0
10538 #define CPC_INT_ADDR__ADDR_MASK                                                                               0xFFFFFFFFL
10539 //CPC_INT_PASID
10540 #define CPC_INT_PASID__PASID__SHIFT                                                                           0x0
10541 #define CPC_INT_PASID__PASID_MASK                                                                             0x0000FFFFL
10542 //CP_GFX_ERROR
10543 #define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
10544 #define CP_GFX_ERROR__SUA_ERROR__SHIFT                                                                        0x4
10545 #define CP_GFX_ERROR__RSVD1_ERROR__SHIFT                                                                      0x5
10546 #define CP_GFX_ERROR__RSVD2_ERROR__SHIFT                                                                      0x6
10547 #define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0x7
10548 #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT                                                              0x8
10549 #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT                                                               0x9
10550 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT                                                              0xa
10551 #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT                                                              0xb
10552 #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT                                                           0xc
10553 #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT                                                           0xd
10554 #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT                                                               0xe
10555 #define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT                                                               0xf
10556 #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT                                                               0x10
10557 #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT                                                           0x11
10558 #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0x12
10559 #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x13
10560 #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT                                                               0x14
10561 #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT                                                                0x15
10562 #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT                                                                0x16
10563 #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT                                                              0x17
10564 #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT                                                            0x18
10565 #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT                                                           0x19
10566 #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1a
10567 #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1b
10568 #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1c
10569 #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1d
10570 #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1e
10571 #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT                                                              0x1f
10572 #define CP_GFX_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
10573 #define CP_GFX_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
10574 #define CP_GFX_ERROR__RSVD1_ERROR_MASK                                                                        0x00000020L
10575 #define CP_GFX_ERROR__RSVD2_ERROR_MASK                                                                        0x00000040L
10576 #define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00000080L
10577 #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK                                                                0x00000100L
10578 #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK                                                                 0x00000200L
10579 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK                                                                0x00000400L
10580 #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK                                                                0x00000800L
10581 #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK                                                             0x00001000L
10582 #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK                                                             0x00002000L
10583 #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK                                                                 0x00004000L
10584 #define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK                                                                 0x00008000L
10585 #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK                                                                 0x00010000L
10586 #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK                                                             0x00020000L
10587 #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00040000L
10588 #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00080000L
10589 #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK                                                                 0x00100000L
10590 #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK                                                                  0x00200000L
10591 #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK                                                                  0x00400000L
10592 #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK                                                                0x00800000L
10593 #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK                                                              0x01000000L
10594 #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK                                                             0x02000000L
10595 #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK                                                             0x04000000L
10596 #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK                                                             0x08000000L
10597 #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK                                                             0x10000000L
10598 #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK                                                             0x20000000L
10599 #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK                                                             0x40000000L
10600 #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK                                                                0x80000000L
10601 //CPG_UTCL1_CNTL
10602 #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
10603 #define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
10604 #define CPG_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
10605 #define CPG_UTCL1_CNTL__BYPASS__SHIFT                                                                         0x19
10606 #define CPG_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
10607 #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
10608 #define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
10609 #define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                            0x1d
10610 #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
10611 #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
10612 #define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
10613 #define CPG_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
10614 #define CPG_UTCL1_CNTL__BYPASS_MASK                                                                           0x02000000L
10615 #define CPG_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
10616 #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
10617 #define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
10618 #define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                              0x20000000L
10619 #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
10620 //CPC_UTCL1_CNTL
10621 #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
10622 #define CPC_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
10623 #define CPC_UTCL1_CNTL__BYPASS__SHIFT                                                                         0x19
10624 #define CPC_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
10625 #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
10626 #define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
10627 #define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                            0x1d
10628 #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
10629 #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
10630 #define CPC_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
10631 #define CPC_UTCL1_CNTL__BYPASS_MASK                                                                           0x02000000L
10632 #define CPC_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
10633 #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
10634 #define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
10635 #define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                              0x20000000L
10636 #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
10637 //CPF_UTCL1_CNTL
10638 #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
10639 #define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
10640 #define CPF_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
10641 #define CPF_UTCL1_CNTL__BYPASS__SHIFT                                                                         0x19
10642 #define CPF_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
10643 #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
10644 #define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
10645 #define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                            0x1d
10646 #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
10647 #define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT                                                                   0x1f
10648 #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
10649 #define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
10650 #define CPF_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
10651 #define CPF_UTCL1_CNTL__BYPASS_MASK                                                                           0x02000000L
10652 #define CPF_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
10653 #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
10654 #define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
10655 #define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                              0x20000000L
10656 #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
10657 #define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK                                                                     0x80000000L
10658 //CP_AQL_SMM_STATUS
10659 #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT                                                               0x0
10660 #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK                                                                 0xFFFFFFFFL
10661 //CP_RB0_BASE
10662 #define CP_RB0_BASE__RB_BASE__SHIFT                                                                           0x0
10663 #define CP_RB0_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
10664 //CP_RB_BASE
10665 #define CP_RB_BASE__RB_BASE__SHIFT                                                                            0x0
10666 #define CP_RB_BASE__RB_BASE_MASK                                                                              0xFFFFFFFFL
10667 //CP_RB0_CNTL
10668 #define CP_RB0_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
10669 #define CP_RB0_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
10670 #define CP_RB0_CNTL__BUF_SWAP__SHIFT                                                                          0x11
10671 #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
10672 #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
10673 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
10674 #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
10675 #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
10676 #define CP_RB0_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
10677 #define CP_RB0_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
10678 #define CP_RB0_CNTL__BUF_SWAP_MASK                                                                            0x00060000L
10679 #define CP_RB0_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
10680 #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
10681 #define CP_RB0_CNTL__CACHE_POLICY_MASK                                                                        0x01000000L
10682 #define CP_RB0_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
10683 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
10684 //CP_RB_CNTL
10685 #define CP_RB_CNTL__RB_BUFSZ__SHIFT                                                                           0x0
10686 #define CP_RB_CNTL__RB_BLKSZ__SHIFT                                                                           0x8
10687 #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT                                                                        0x14
10688 #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                     0x16
10689 #define CP_RB_CNTL__CACHE_POLICY__SHIFT                                                                       0x18
10690 #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                                                                       0x1b
10691 #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                     0x1f
10692 #define CP_RB_CNTL__RB_BUFSZ_MASK                                                                             0x0000003FL
10693 #define CP_RB_CNTL__RB_BLKSZ_MASK                                                                             0x00003F00L
10694 #define CP_RB_CNTL__MIN_AVAILSZ_MASK                                                                          0x00300000L
10695 #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK                                                                       0x00C00000L
10696 #define CP_RB_CNTL__CACHE_POLICY_MASK                                                                         0x01000000L
10697 #define CP_RB_CNTL__RB_NO_UPDATE_MASK                                                                         0x08000000L
10698 #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                                                                       0x80000000L
10699 //CP_RB_RPTR_WR
10700 #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                                                                      0x0
10701 #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                                                                        0x000FFFFFL
10702 //CP_RB0_RPTR_ADDR
10703 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
10704 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
10705 //CP_RB_RPTR_ADDR
10706 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                  0x2
10707 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                    0xFFFFFFFCL
10708 //CP_RB0_RPTR_ADDR_HI
10709 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
10710 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
10711 //CP_RB_RPTR_ADDR_HI
10712 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                            0x0
10713 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                              0x0000FFFFL
10714 //CP_RB0_BUFSZ_MASK
10715 #define CP_RB0_BUFSZ_MASK__DATA__SHIFT                                                                        0x0
10716 #define CP_RB0_BUFSZ_MASK__DATA_MASK                                                                          0x000FFFFFL
10717 //CP_RB_BUFSZ_MASK
10718 #define CP_RB_BUFSZ_MASK__DATA__SHIFT                                                                         0x0
10719 #define CP_RB_BUFSZ_MASK__DATA_MASK                                                                           0x000FFFFFL
10720 //CP_RB_WPTR_POLL_ADDR_LO
10721 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT                                                  0x2
10722 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK                                                    0xFFFFFFFCL
10723 //CP_RB_WPTR_POLL_ADDR_HI
10724 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT                                                  0x0
10725 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK                                                    0x0000FFFFL
10726 //GC_PRIV_MODE
10727 //CP_INT_CNTL
10728 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                      0xb
10729 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                           0xe
10730 #define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                    0x10
10731 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                       0x11
10732 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT                                                               0x12
10733 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT                                                              0x13
10734 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT                                                             0x14
10735 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT                                                               0x15
10736 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT                                                             0x16
10737 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                               0x17
10738 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                           0x18
10739 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                             0x1a
10740 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                     0x1b
10741 #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                               0x1d
10742 #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                               0x1e
10743 #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                               0x1f
10744 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                        0x00000800L
10745 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                             0x00004000L
10746 #define CP_INT_CNTL__GPF_INT_ENABLE_MASK                                                                      0x00010000L
10747 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                         0x00020000L
10748 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK                                                                 0x00040000L
10749 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK                                                                0x00080000L
10750 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK                                                               0x00100000L
10751 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK                                                                 0x00200000L
10752 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK                                                               0x00400000L
10753 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                 0x00800000L
10754 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                             0x01000000L
10755 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                               0x04000000L
10756 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                       0x08000000L
10757 #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                 0x20000000L
10758 #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                 0x40000000L
10759 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                 0x80000000L
10760 //CP_INT_STATUS
10761 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                      0xb
10762 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT                                                           0xe
10763 #define CP_INT_STATUS__GPF_INT_STAT__SHIFT                                                                    0x10
10764 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                       0x11
10765 #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT                                                               0x12
10766 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT                                                              0x13
10767 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT                                                             0x14
10768 #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT                                                               0x15
10769 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT                                                             0x16
10770 #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT                                                               0x17
10771 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT                                                           0x18
10772 #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT                                                             0x1a
10773 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                                     0x1b
10774 #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT                                                               0x1d
10775 #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT                                                               0x1e
10776 #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT                                                               0x1f
10777 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                        0x00000800L
10778 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK                                                             0x00004000L
10779 #define CP_INT_STATUS__GPF_INT_STAT_MASK                                                                      0x00010000L
10780 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                         0x00020000L
10781 #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK                                                                 0x00040000L
10782 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK                                                                0x00080000L
10783 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK                                                               0x00100000L
10784 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK                                                                 0x00200000L
10785 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK                                                               0x00400000L
10786 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK                                                                 0x00800000L
10787 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK                                                             0x01000000L
10788 #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK                                                               0x04000000L
10789 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK                                                       0x08000000L
10790 #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK                                                                 0x20000000L
10791 #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK                                                                 0x40000000L
10792 #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK                                                                 0x80000000L
10793 //CP_DEVICE_ID
10794 #define CP_DEVICE_ID__DEVICE_ID__SHIFT                                                                        0x0
10795 #define CP_DEVICE_ID__DEVICE_ID_MASK                                                                          0x000000FFL
10796 //CP_ME0_PIPE_PRIORITY_CNTS
10797 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
10798 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
10799 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
10800 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
10801 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
10802 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
10803 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
10804 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
10805 //CP_RING_PRIORITY_CNTS
10806 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                           0x0
10807 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                          0x8
10808 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                          0x10
10809 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                           0x18
10810 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                             0x000000FFL
10811 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                            0x0000FF00L
10812 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                            0x00FF0000L
10813 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                             0xFF000000L
10814 //CP_ME0_PIPE0_PRIORITY
10815 #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
10816 #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
10817 //CP_RING0_PRIORITY
10818 #define CP_RING0_PRIORITY__PRIORITY__SHIFT                                                                    0x0
10819 #define CP_RING0_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
10820 //CP_ME0_PIPE1_PRIORITY
10821 #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
10822 #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
10823 //CP_RING1_PRIORITY
10824 #define CP_RING1_PRIORITY__PRIORITY__SHIFT                                                                    0x0
10825 #define CP_RING1_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
10826 //CP_ME0_PIPE2_PRIORITY
10827 #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
10828 #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
10829 //CP_RING2_PRIORITY
10830 #define CP_RING2_PRIORITY__PRIORITY__SHIFT                                                                    0x0
10831 #define CP_RING2_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
10832 //CP_FATAL_ERROR
10833 #define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT                                                                0x0
10834 #define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT                                                                0x1
10835 #define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT                                                                  0x2
10836 #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT                                                            0x3
10837 #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT                                                         0x4
10838 #define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK                                                                  0x00000001L
10839 #define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK                                                                  0x00000002L
10840 #define CP_FATAL_ERROR__GFX_HALT_PROC_MASK                                                                    0x00000004L
10841 #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK                                                              0x00000008L
10842 #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK                                                           0x00000010L
10843 //CP_RB_VMID
10844 #define CP_RB_VMID__RB0_VMID__SHIFT                                                                           0x0
10845 #define CP_RB_VMID__RB1_VMID__SHIFT                                                                           0x8
10846 #define CP_RB_VMID__RB2_VMID__SHIFT                                                                           0x10
10847 #define CP_RB_VMID__RB0_VMID_MASK                                                                             0x0000000FL
10848 #define CP_RB_VMID__RB1_VMID_MASK                                                                             0x00000F00L
10849 #define CP_RB_VMID__RB2_VMID_MASK                                                                             0x000F0000L
10850 //CP_ME0_PIPE0_VMID
10851 #define CP_ME0_PIPE0_VMID__VMID__SHIFT                                                                        0x0
10852 #define CP_ME0_PIPE0_VMID__VMID_MASK                                                                          0x0000000FL
10853 //CP_ME0_PIPE1_VMID
10854 #define CP_ME0_PIPE1_VMID__VMID__SHIFT                                                                        0x0
10855 #define CP_ME0_PIPE1_VMID__VMID_MASK                                                                          0x0000000FL
10856 //CP_RB0_WPTR
10857 #define CP_RB0_WPTR__RB_WPTR__SHIFT                                                                           0x0
10858 #define CP_RB0_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
10859 //CP_RB_WPTR
10860 #define CP_RB_WPTR__RB_WPTR__SHIFT                                                                            0x0
10861 #define CP_RB_WPTR__RB_WPTR_MASK                                                                              0xFFFFFFFFL
10862 //CP_RB0_WPTR_HI
10863 #define CP_RB0_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
10864 #define CP_RB0_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
10865 //CP_RB_WPTR_HI
10866 #define CP_RB_WPTR_HI__RB_WPTR__SHIFT                                                                         0x0
10867 #define CP_RB_WPTR_HI__RB_WPTR_MASK                                                                           0xFFFFFFFFL
10868 //CP_RB1_WPTR
10869 #define CP_RB1_WPTR__RB_WPTR__SHIFT                                                                           0x0
10870 #define CP_RB1_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
10871 //CP_RB1_WPTR_HI
10872 #define CP_RB1_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
10873 #define CP_RB1_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
10874 //CP_RB2_WPTR
10875 #define CP_RB2_WPTR__RB_WPTR__SHIFT                                                                           0x0
10876 #define CP_RB2_WPTR__RB_WPTR_MASK                                                                             0x000FFFFFL
10877 //CP_RB_DOORBELL_CONTROL
10878 #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                      0x1
10879 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                        0x2
10880 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                            0x1e
10881 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                           0x1f
10882 #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                        0x00000002L
10883 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                          0x0FFFFFFCL
10884 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                              0x40000000L
10885 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                             0x80000000L
10886 //CP_RB_DOORBELL_RANGE_LOWER
10887 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                               0x2
10888 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                 0x0FFFFFFCL
10889 //CP_RB_DOORBELL_RANGE_UPPER
10890 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                               0x2
10891 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                 0x0FFFFFFCL
10892 //CP_MEC_DOORBELL_RANGE_LOWER
10893 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                              0x2
10894 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                0x0FFFFFFCL
10895 //CP_MEC_DOORBELL_RANGE_UPPER
10896 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                              0x2
10897 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                0x0FFFFFFCL
10898 //CPG_UTCL1_ERROR
10899 #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
10900 #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
10901 //CPC_UTCL1_ERROR
10902 #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
10903 #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
10904 //CP_RB1_BASE
10905 #define CP_RB1_BASE__RB_BASE__SHIFT                                                                           0x0
10906 #define CP_RB1_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
10907 //CP_RB1_CNTL
10908 #define CP_RB1_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
10909 #define CP_RB1_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
10910 #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
10911 #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
10912 #define CP_RB1_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
10913 #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
10914 #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
10915 #define CP_RB1_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
10916 #define CP_RB1_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
10917 #define CP_RB1_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
10918 #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
10919 #define CP_RB1_CNTL__CACHE_POLICY_MASK                                                                        0x01000000L
10920 #define CP_RB1_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
10921 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
10922 //CP_RB1_RPTR_ADDR
10923 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
10924 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
10925 //CP_RB1_RPTR_ADDR_HI
10926 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
10927 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
10928 //CP_RB2_BASE
10929 #define CP_RB2_BASE__RB_BASE__SHIFT                                                                           0x0
10930 #define CP_RB2_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
10931 //CP_RB2_CNTL
10932 #define CP_RB2_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
10933 #define CP_RB2_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
10934 #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
10935 #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
10936 #define CP_RB2_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
10937 #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
10938 #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
10939 #define CP_RB2_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
10940 #define CP_RB2_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
10941 #define CP_RB2_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
10942 #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
10943 #define CP_RB2_CNTL__CACHE_POLICY_MASK                                                                        0x01000000L
10944 #define CP_RB2_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
10945 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
10946 //CP_RB2_RPTR_ADDR
10947 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
10948 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
10949 //CP_RB2_RPTR_ADDR_HI
10950 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
10951 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
10952 //CP_RB0_ACTIVE
10953 #define CP_RB0_ACTIVE__ACTIVE__SHIFT                                                                          0x0
10954 #define CP_RB0_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
10955 //CP_RB_ACTIVE
10956 #define CP_RB_ACTIVE__ACTIVE__SHIFT                                                                           0x0
10957 #define CP_RB_ACTIVE__ACTIVE_MASK                                                                             0x00000001L
10958 //CP_INT_CNTL_RING0
10959 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
10960 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
10961 #define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT                                                              0x10
10962 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
10963 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
10964 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
10965 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
10966 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
10967 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
10968 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
10969 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
10970 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
10971 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
10972 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
10973 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
10974 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
10975 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
10976 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
10977 #define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK                                                                0x00010000L
10978 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
10979 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
10980 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
10981 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
10982 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
10983 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
10984 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
10985 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
10986 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
10987 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
10988 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
10989 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
10990 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
10991 //CP_INT_CNTL_RING1
10992 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
10993 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
10994 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT                                                              0x10
10995 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
10996 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
10997 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
10998 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
10999 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
11000 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
11001 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
11002 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
11003 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
11004 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
11005 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
11006 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
11007 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
11008 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
11009 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
11010 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK                                                                0x00010000L
11011 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
11012 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
11013 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
11014 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
11015 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
11016 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
11017 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
11018 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
11019 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
11020 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
11021 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
11022 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
11023 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
11024 //CP_INT_CNTL_RING2
11025 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
11026 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
11027 #define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT                                                              0x10
11028 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
11029 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
11030 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
11031 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
11032 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
11033 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
11034 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
11035 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
11036 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
11037 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
11038 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
11039 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
11040 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
11041 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
11042 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
11043 #define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK                                                                0x00010000L
11044 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
11045 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
11046 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
11047 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
11048 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
11049 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
11050 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
11051 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
11052 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
11053 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
11054 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
11055 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
11056 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
11057 //CP_INT_STATUS_RING0
11058 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
11059 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
11060 #define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT                                                              0x10
11061 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
11062 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
11063 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT                                                       0x13
11064 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
11065 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
11066 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
11067 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT                                                         0x17
11068 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
11069 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
11070 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
11071 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT                                                         0x1d
11072 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT                                                         0x1e
11073 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT                                                         0x1f
11074 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
11075 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
11076 #define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK                                                                0x00010000L
11077 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
11078 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
11079 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK                                                         0x00080000L
11080 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
11081 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
11082 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
11083 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
11084 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
11085 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
11086 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
11087 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK                                                           0x20000000L
11088 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK                                                           0x40000000L
11089 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK                                                           0x80000000L
11090 //CP_INT_STATUS_RING1
11091 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
11092 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
11093 #define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT                                                              0x10
11094 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
11095 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
11096 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
11097 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
11098 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
11099 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
11100 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT                                                         0x17
11101 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
11102 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
11103 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
11104 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT                                                         0x1d
11105 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT                                                         0x1e
11106 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT                                                         0x1f
11107 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
11108 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
11109 #define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK                                                                0x00010000L
11110 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
11111 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
11112 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
11113 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
11114 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
11115 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
11116 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
11117 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
11118 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
11119 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
11120 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK                                                           0x20000000L
11121 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK                                                           0x40000000L
11122 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK                                                           0x80000000L
11123 //CP_INT_STATUS_RING2
11124 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
11125 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
11126 #define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT                                                              0x10
11127 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
11128 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
11129 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
11130 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
11131 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
11132 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
11133 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT                                                         0x17
11134 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
11135 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
11136 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
11137 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT                                                         0x1d
11138 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT                                                         0x1e
11139 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT                                                         0x1f
11140 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
11141 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
11142 #define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK                                                                0x00010000L
11143 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
11144 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
11145 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
11146 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
11147 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
11148 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
11149 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
11150 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
11151 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
11152 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
11153 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK                                                           0x20000000L
11154 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK                                                           0x40000000L
11155 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK                                                           0x80000000L
11156 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                             0x1
11157 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK                                                               0x00000002L
11158 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
11159 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
11160 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
11161 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
11162 //CP_PWR_CNTL
11163 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT                                                            0x0
11164 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT                                                            0x1
11165 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT                                                            0x8
11166 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT                                                            0x9
11167 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT                                                            0xa
11168 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT                                                            0xb
11169 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT                                                            0x10
11170 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT                                                            0x11
11171 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT                                                            0x12
11172 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT                                                            0x13
11173 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK                                                              0x00000001L
11174 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK                                                              0x00000002L
11175 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK                                                              0x00000100L
11176 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK                                                              0x00000200L
11177 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK                                                              0x00000400L
11178 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK                                                              0x00000800L
11179 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK                                                              0x00010000L
11180 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK                                                              0x00020000L
11181 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK                                                              0x00040000L
11182 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK                                                              0x00080000L
11183 //CP_MEM_SLP_CNTL
11184 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT                                                                  0x0
11185 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT                                                                  0x1
11186 #define CP_MEM_SLP_CNTL__RESERVED__SHIFT                                                                      0x2
11187 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT                                                        0x7
11188 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT                                                            0x8
11189 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT                                                           0x10
11190 #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                     0x18
11191 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK                                                                    0x00000001L
11192 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK                                                                    0x00000002L
11193 #define CP_MEM_SLP_CNTL__RESERVED_MASK                                                                        0x0000007CL
11194 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK                                                          0x00000080L
11195 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK                                                              0x0000FF00L
11196 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK                                                             0x00FF0000L
11197 #define CP_MEM_SLP_CNTL__RESERVED1_MASK                                                                       0xFF000000L
11198 //CP_ECC_FIRSTOCCURRENCE
11199 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT                                                              0x0
11200 #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT                                                                 0x4
11201 #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT                                                                     0x8
11202 #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT                                                                   0xa
11203 #define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT                                                                  0xc
11204 #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT                                                                   0x10
11205 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK                                                                0x00000003L
11206 #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK                                                                   0x000000F0L
11207 #define CP_ECC_FIRSTOCCURRENCE__ME_MASK                                                                       0x00000300L
11208 #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK                                                                     0x00000C00L
11209 #define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK                                                                    0x00007000L
11210 #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK                                                                     0x000F0000L
11211 //CP_ECC_FIRSTOCCURRENCE_RING0
11212 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT                                                         0x0
11213 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK                                                           0xFFFFFFFFL
11214 //CP_ECC_FIRSTOCCURRENCE_RING1
11215 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT                                                         0x0
11216 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK                                                           0xFFFFFFFFL
11217 //CP_ECC_FIRSTOCCURRENCE_RING2
11218 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT                                                         0x0
11219 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK                                                           0xFFFFFFFFL
11220 //GB_EDC_MODE
11221 #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT                                                                  0xf
11222 #define GB_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                     0x10
11223 #define GB_EDC_MODE__GATE_FUE__SHIFT                                                                          0x11
11224 #define GB_EDC_MODE__DED_MODE__SHIFT                                                                          0x14
11225 #define GB_EDC_MODE__PROP_FED__SHIFT                                                                          0x1d
11226 #define GB_EDC_MODE__BYPASS__SHIFT                                                                            0x1f
11227 #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK                                                                    0x00008000L
11228 #define GB_EDC_MODE__COUNT_FED_OUT_MASK                                                                       0x00010000L
11229 #define GB_EDC_MODE__GATE_FUE_MASK                                                                            0x00020000L
11230 #define GB_EDC_MODE__DED_MODE_MASK                                                                            0x00300000L
11231 #define GB_EDC_MODE__PROP_FED_MASK                                                                            0x20000000L
11232 #define GB_EDC_MODE__BYPASS_MASK                                                                              0x80000000L
11233 //CP_CPF_DEBUG
11234 //CP_PQ_WPTR_POLL_CNTL
11235 #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT                                                                   0x0
11236 #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT                                                0x1d
11237 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT                                                              0x1e
11238 #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT                                                                       0x1f
11239 #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK                                                                     0x000000FFL
11240 #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK                                                  0x20000000L
11241 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK                                                                0x40000000L
11242 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK                                                                         0x80000000L
11243 //CP_PQ_WPTR_POLL_CNTL1
11244 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT                                                              0x0
11245 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK                                                                0xFFFFFFFFL
11246 //CP_ME1_PIPE0_INT_CNTL
11247 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11248 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11249 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11250 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11251 #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11252 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11253 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11254 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11255 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11256 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11257 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11258 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11259 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11260 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11261 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11262 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11263 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11264 #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11265 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11266 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11267 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11268 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11269 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11270 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11271 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11272 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11273 //CP_ME1_PIPE1_INT_CNTL
11274 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11275 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11276 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11277 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11278 #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11279 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11280 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11281 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11282 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11283 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11284 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11285 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11286 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11287 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11288 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11289 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11290 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11291 #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11292 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11293 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11294 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11295 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11296 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11297 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11298 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11299 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11300 //CP_ME1_PIPE2_INT_CNTL
11301 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11302 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11303 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11304 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11305 #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11306 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11307 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11308 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11309 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11310 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11311 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11312 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11313 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11314 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11315 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11316 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11317 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11318 #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11319 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11320 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11321 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11322 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11323 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11324 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11325 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11326 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11327 //CP_ME1_PIPE3_INT_CNTL
11328 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11329 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11330 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11331 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11332 #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11333 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11334 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11335 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11336 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11337 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11338 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11339 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11340 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11341 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11342 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11343 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11344 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11345 #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11346 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11347 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11348 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11349 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11350 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11351 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11352 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11353 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11354 //CP_ME2_PIPE0_INT_CNTL
11355 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11356 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11357 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11358 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11359 #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11360 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11361 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11362 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11363 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11364 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11365 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11366 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11367 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11368 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11369 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11370 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11371 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11372 #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11373 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11374 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11375 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11376 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11377 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11378 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11379 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11380 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11381 //CP_ME2_PIPE1_INT_CNTL
11382 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11383 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11384 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11385 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11386 #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11387 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11388 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11389 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11390 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11391 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11392 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11393 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11394 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11395 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11396 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11397 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11398 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11399 #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11400 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11401 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11402 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11403 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11404 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11405 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11406 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11407 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11408 //CP_ME2_PIPE2_INT_CNTL
11409 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11410 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11411 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11412 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11413 #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11414 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11415 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11416 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11417 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11418 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11419 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11420 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11421 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11422 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11423 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11424 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11425 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11426 #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11427 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11428 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11429 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11430 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11431 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11432 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11433 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11434 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11435 //CP_ME2_PIPE3_INT_CNTL
11436 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11437 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11438 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11439 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11440 #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11441 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11442 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11443 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11444 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11445 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11446 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11447 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11448 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11449 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11450 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11451 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11452 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11453 #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11454 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11455 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11456 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11457 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11458 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11459 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11460 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11461 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11462 //CP_ME1_PIPE0_INT_STATUS
11463 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11464 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11465 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11466 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11467 #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11468 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11469 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11470 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11471 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11472 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11473 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11474 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11475 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11476 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11477 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11478 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11479 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11480 #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11481 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11482 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11483 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11484 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11485 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11486 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11487 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11488 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11489 //CP_ME1_PIPE1_INT_STATUS
11490 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11491 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11492 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11493 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11494 #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11495 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11496 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11497 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11498 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11499 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11500 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11501 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11502 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11503 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11504 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11505 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11506 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11507 #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11508 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11509 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11510 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11511 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11512 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11513 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11514 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11515 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11516 //CP_ME1_PIPE2_INT_STATUS
11517 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11518 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11519 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11520 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11521 #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11522 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11523 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11524 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11525 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11526 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11527 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11528 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11529 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11530 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11531 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11532 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11533 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11534 #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11535 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11536 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11537 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11538 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11539 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11540 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11541 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11542 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11543 //CP_ME1_PIPE3_INT_STATUS
11544 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11545 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11546 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11547 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11548 #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11549 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11550 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11551 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11552 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11553 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11554 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11555 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11556 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11557 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11558 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11559 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11560 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11561 #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11562 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11563 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11564 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11565 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11566 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11567 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11568 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11569 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11570 //CP_ME2_PIPE0_INT_STATUS
11571 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11572 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11573 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11574 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11575 #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11576 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11577 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11578 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11579 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11580 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11581 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11582 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11583 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11584 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11585 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11586 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11587 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11588 #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11589 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11590 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11591 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11592 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11593 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11594 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11595 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11596 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11597 //CP_ME2_PIPE1_INT_STATUS
11598 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11599 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11600 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11601 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11602 #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11603 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11604 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11605 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11606 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11607 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11608 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11609 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11610 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11611 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11612 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11613 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11614 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11615 #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11616 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11617 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11618 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11619 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11620 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11621 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11622 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11623 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11624 //CP_ME2_PIPE2_INT_STATUS
11625 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11626 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11627 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11628 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11629 #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11630 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11631 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11632 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11633 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11634 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11635 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11636 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11637 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11638 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11639 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11640 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11641 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11642 #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11643 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11644 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11645 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11646 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11647 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11648 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11649 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11650 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11651 //CP_ME2_PIPE3_INT_STATUS
11652 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11653 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11654 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11655 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11656 #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11657 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11658 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11659 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11660 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11661 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11662 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11663 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11664 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11665 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11666 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11667 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11668 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11669 #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11670 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11671 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11672 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11673 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11674 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11675 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11676 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11677 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11678 //CP_ME1_INT_STAT_DEBUG
11679 #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT                                           0xc
11680 #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT                                            0xd
11681 #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT                                               0xe
11682 #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT                                                0xf
11683 #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT                                                        0x10
11684 #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT                                           0x11
11685 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
11686 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT                                               0x18
11687 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT                                                 0x1a
11688 #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT                                         0x1b
11689 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT                                                   0x1d
11690 #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT                                                   0x1e
11691 #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT                                                   0x1f
11692 #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK                                             0x00001000L
11693 #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK                                              0x00002000L
11694 #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK                                                 0x00004000L
11695 #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK                                                  0x00008000L
11696 #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK                                                          0x00010000L
11697 #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK                                             0x00020000L
11698 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
11699 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK                                                 0x01000000L
11700 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK                                                   0x04000000L
11701 #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK                                           0x08000000L
11702 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK                                                     0x20000000L
11703 #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK                                                     0x40000000L
11704 #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK                                                     0x80000000L
11705 //CP_ME2_INT_STAT_DEBUG
11706 #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT                                           0xc
11707 #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT                                            0xd
11708 #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT                                               0xe
11709 #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT                                                0xf
11710 #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT                                                        0x10
11711 #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT                                           0x11
11712 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
11713 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT                                               0x18
11714 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT                                                 0x1a
11715 #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT                                         0x1b
11716 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT                                                   0x1d
11717 #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT                                                   0x1e
11718 #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT                                                   0x1f
11719 #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK                                             0x00001000L
11720 #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK                                              0x00002000L
11721 #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK                                                 0x00004000L
11722 #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK                                                  0x00008000L
11723 #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK                                                          0x00010000L
11724 #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK                                             0x00020000L
11725 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
11726 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK                                                 0x01000000L
11727 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK                                                   0x04000000L
11728 #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK                                           0x08000000L
11729 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK                                                     0x20000000L
11730 #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK                                                     0x40000000L
11731 #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK                                                     0x80000000L
11732 //CC_GC_EDC_CONFIG
11733 #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
11734 #define CC_GC_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
11735 //CP_ME1_PIPE_PRIORITY_CNTS
11736 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
11737 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
11738 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
11739 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
11740 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
11741 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
11742 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
11743 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
11744 //CP_ME1_PIPE0_PRIORITY
11745 #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
11746 #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11747 //CP_ME1_PIPE1_PRIORITY
11748 #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
11749 #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11750 //CP_ME1_PIPE2_PRIORITY
11751 #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
11752 #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11753 //CP_ME1_PIPE3_PRIORITY
11754 #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
11755 #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11756 //CP_ME2_PIPE_PRIORITY_CNTS
11757 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
11758 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
11759 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
11760 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
11761 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
11762 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
11763 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
11764 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
11765 //CP_ME2_PIPE0_PRIORITY
11766 #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
11767 #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11768 //CP_ME2_PIPE1_PRIORITY
11769 #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
11770 #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11771 //CP_ME2_PIPE2_PRIORITY
11772 #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
11773 #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11774 //CP_ME2_PIPE3_PRIORITY
11775 #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
11776 #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11777 //CP_CE_PRGRM_CNTR_START
11778 #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
11779 #define CP_CE_PRGRM_CNTR_START__IP_START_MASK                                                                 0x000007FFL
11780 //CP_PFP_PRGRM_CNTR_START
11781 #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT                                                              0x0
11782 #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK                                                                0x00001FFFL
11783 //CP_ME_PRGRM_CNTR_START
11784 #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
11785 #define CP_ME_PRGRM_CNTR_START__IP_START_MASK                                                                 0x00000FFFL
11786 //CP_MEC1_PRGRM_CNTR_START
11787 #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
11788 #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK                                                               0x0000FFFFL
11789 //CP_MEC2_PRGRM_CNTR_START
11790 #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
11791 #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK                                                               0x0000FFFFL
11792 //CP_CE_INTR_ROUTINE_START
11793 #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
11794 #define CP_CE_INTR_ROUTINE_START__IR_START_MASK                                                               0x000007FFL
11795 //CP_PFP_INTR_ROUTINE_START
11796 #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT                                                            0x0
11797 #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK                                                              0x00001FFFL
11798 //CP_ME_INTR_ROUTINE_START
11799 #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
11800 #define CP_ME_INTR_ROUTINE_START__IR_START_MASK                                                               0x00000FFFL
11801 //CP_MEC1_INTR_ROUTINE_START
11802 #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
11803 #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK                                                             0x0000FFFFL
11804 //CP_MEC2_INTR_ROUTINE_START
11805 #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
11806 #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK                                                             0x0000FFFFL
11807 //CP_CONTEXT_CNTL
11808 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT                                                          0x0
11809 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT                                                        0x4
11810 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT                                                          0x10
11811 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT                                                        0x14
11812 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK                                                            0x00000007L
11813 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK                                                          0x00000070L
11814 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK                                                            0x00070000L
11815 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK                                                          0x00700000L
11816 //CP_MAX_CONTEXT
11817 #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT                                                                    0x0
11818 #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK                                                                      0x00000007L
11819 //CP_IQ_WAIT_TIME1
11820 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT                                                                   0x0
11821 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT                                                               0x8
11822 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT                                                                  0x10
11823 #define CP_IQ_WAIT_TIME1__GWS__SHIFT                                                                          0x18
11824 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK                                                                     0x000000FFL
11825 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK                                                                 0x0000FF00L
11826 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK                                                                    0x00FF0000L
11827 #define CP_IQ_WAIT_TIME1__GWS_MASK                                                                            0xFF000000L
11828 //CP_IQ_WAIT_TIME2
11829 #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT                                                                    0x0
11830 #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT                                                                     0x8
11831 #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT                                                                    0x10
11832 #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT                                                                    0x18
11833 #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK                                                                      0x000000FFL
11834 #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK                                                                       0x0000FF00L
11835 #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK                                                                      0x00FF0000L
11836 #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK                                                                      0xFF000000L
11837 //CP_RB0_BASE_HI
11838 #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
11839 #define CP_RB0_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
11840 //CP_RB1_BASE_HI
11841 #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
11842 #define CP_RB1_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
11843 //CP_VMID_RESET
11844 #define CP_VMID_RESET__RESET_REQUEST__SHIFT                                                                   0x0
11845 #define CP_VMID_RESET__RESET_REQUEST_MASK                                                                     0x0000FFFFL
11846 //CPC_INT_CNTL
11847 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                                      0xc
11848 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                                       0xd
11849 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                          0xe
11850 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                         0xf
11851 #define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                   0x10
11852 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                      0x11
11853 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                              0x17
11854 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                          0x18
11855 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                            0x1a
11856 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                    0x1b
11857 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                              0x1d
11858 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                              0x1e
11859 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                              0x1f
11860 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                                        0x00001000L
11861 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                         0x00002000L
11862 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                            0x00004000L
11863 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                           0x00008000L
11864 #define CPC_INT_CNTL__GPF_INT_ENABLE_MASK                                                                     0x00010000L
11865 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                        0x00020000L
11866 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                0x00800000L
11867 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                            0x01000000L
11868 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                              0x04000000L
11869 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                      0x08000000L
11870 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                0x20000000L
11871 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                0x40000000L
11872 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                0x80000000L
11873 //CPC_INT_STATUS
11874 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                                    0xc
11875 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                                     0xd
11876 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                                        0xe
11877 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                                       0xf
11878 #define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT                                                                 0x10
11879 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                                    0x11
11880 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                            0x17
11881 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                                        0x18
11882 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                          0x1a
11883 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                                  0x1b
11884 #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                            0x1d
11885 #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                            0x1e
11886 #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                            0x1f
11887 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                                      0x00001000L
11888 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                                       0x00002000L
11889 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                          0x00004000L
11890 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                         0x00008000L
11891 #define CPC_INT_STATUS__GPF_INT_STATUS_MASK                                                                   0x00010000L
11892 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                                      0x00020000L
11893 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                              0x00800000L
11894 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                          0x01000000L
11895 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                            0x04000000L
11896 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                                    0x08000000L
11897 #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                              0x20000000L
11898 #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                              0x40000000L
11899 #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                              0x80000000L
11900 //CP_VMID_PREEMPT
11901 #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT                                                               0x0
11902 #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT                                                                  0x10
11903 #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK                                                                 0x0000FFFFL
11904 #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK                                                                    0x000F0000L
11905 //CPC_INT_CNTX_ID
11906 #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT                                                                       0x0
11907 #define CPC_INT_CNTX_ID__CNTX_ID_MASK                                                                         0xFFFFFFFFL
11908 //CP_PQ_STATUS
11909 #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
11910 #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
11911 #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
11912 #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
11913 //CP_CPC_IC_BASE_LO
11914 #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                  0xc
11915 #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK                                                                    0xFFFFF000L
11916 //CP_CPC_IC_BASE_HI
11917 #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                  0x0
11918 #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK                                                                    0x0000FFFFL
11919 //CP_CPC_IC_BASE_CNTL
11920 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT                                                                      0x0
11921 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
11922 #define CP_CPC_IC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
11923 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x01000000L
11924 //CP_CPC_IC_OP_CNTL
11925 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                            0x0
11926 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                0x4
11927 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                               0x5
11928 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                              0x00000001L
11929 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                  0x00000010L
11930 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                 0x00000020L
11931 //CP_MEC1_F32_INT_DIS
11932 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
11933 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
11934 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
11935 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
11936 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
11937 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
11938 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
11939 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
11940 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
11941 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
11942 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
11943 #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
11944 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
11945 #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
11946 #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
11947 #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
11948 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
11949 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
11950 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
11951 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
11952 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
11953 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
11954 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
11955 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
11956 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
11957 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
11958 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
11959 #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
11960 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
11961 #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
11962 #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
11963 #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
11964 //CP_MEC2_F32_INT_DIS
11965 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
11966 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
11967 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
11968 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
11969 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
11970 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
11971 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
11972 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
11973 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
11974 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
11975 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
11976 #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
11977 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
11978 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
11979 #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
11980 #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
11981 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
11982 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
11983 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
11984 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
11985 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
11986 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
11987 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
11988 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
11989 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
11990 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
11991 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
11992 #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
11993 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
11994 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
11995 #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
11996 #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
11997 //CP_VMID_STATUS
11998 #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT                                                              0x0
11999 #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT                                                              0x10
12000 #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK                                                                0x0000FFFFL
12001 #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK                                                                0xFFFF0000L
12002 
12003 
12004 // addressBlock: gc_cppdec2
12005 //CP_RB_DOORBELL_CONTROL_SCH_0
12006 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT                                                  0x2
12007 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT                                                      0x1e
12008 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT                                                     0x1f
12009 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12010 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK                                                        0x40000000L
12011 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK                                                       0x80000000L
12012 //CP_RB_DOORBELL_CONTROL_SCH_1
12013 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT                                                  0x2
12014 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT                                                      0x1e
12015 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT                                                     0x1f
12016 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12017 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK                                                        0x40000000L
12018 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK                                                       0x80000000L
12019 //CP_RB_DOORBELL_CONTROL_SCH_2
12020 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT                                                  0x2
12021 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT                                                      0x1e
12022 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT                                                     0x1f
12023 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12024 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK                                                        0x40000000L
12025 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK                                                       0x80000000L
12026 //CP_RB_DOORBELL_CONTROL_SCH_3
12027 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT                                                  0x2
12028 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT                                                      0x1e
12029 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT                                                     0x1f
12030 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12031 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK                                                        0x40000000L
12032 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK                                                       0x80000000L
12033 //CP_RB_DOORBELL_CONTROL_SCH_4
12034 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT                                                  0x2
12035 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT                                                      0x1e
12036 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT                                                     0x1f
12037 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12038 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK                                                        0x40000000L
12039 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK                                                       0x80000000L
12040 //CP_RB_DOORBELL_CONTROL_SCH_5
12041 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT                                                  0x2
12042 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT                                                      0x1e
12043 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT                                                     0x1f
12044 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12045 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK                                                        0x40000000L
12046 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK                                                       0x80000000L
12047 //CP_RB_DOORBELL_CONTROL_SCH_6
12048 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT                                                  0x2
12049 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT                                                      0x1e
12050 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT                                                     0x1f
12051 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12052 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK                                                        0x40000000L
12053 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK                                                       0x80000000L
12054 //CP_RB_DOORBELL_CONTROL_SCH_7
12055 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT                                                  0x2
12056 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT                                                      0x1e
12057 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT                                                     0x1f
12058 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12059 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK                                                        0x40000000L
12060 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK                                                       0x80000000L
12061 //CP_RB_DOORBELL_CLEAR
12062 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT                                                             0x0
12063 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT                                             0x8
12064 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT                                            0x9
12065 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT                                                 0xa
12066 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT                                                0xb
12067 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT                                                 0xc
12068 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT                                                0xd
12069 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK                                                               0x00000007L
12070 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK                                               0x00000100L
12071 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK                                              0x00000200L
12072 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK                                                   0x00000400L
12073 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK                                                  0x00000800L
12074 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK                                                   0x00001000L
12075 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK                                                  0x00002000L
12076 //CP_GFX_MQD_CONTROL
12077 #define CP_GFX_MQD_CONTROL__VMID__SHIFT                                                                       0x0
12078 #define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
12079 #define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
12080 #define CP_GFX_MQD_CONTROL__VMID_MASK                                                                         0x0000000FL
12081 #define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
12082 #define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK                                                                 0x01000000L
12083 //CP_GFX_MQD_BASE_ADDR
12084 #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x2
12085 #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFCL
12086 //CP_GFX_MQD_BASE_ADDR_HI
12087 #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
12088 #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x0000FFFFL
12089 //CP_RB_STATUS
12090 #define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
12091 #define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
12092 #define CP_RB_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
12093 #define CP_RB_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
12094 //CPG_UTCL1_STATUS
12095 #define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
12096 #define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
12097 #define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
12098 #define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
12099 #define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
12100 #define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
12101 #define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
12102 #define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
12103 #define CPG_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
12104 #define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
12105 #define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
12106 #define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
12107 //CPC_UTCL1_STATUS
12108 #define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
12109 #define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
12110 #define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
12111 #define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
12112 #define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
12113 #define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
12114 #define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
12115 #define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
12116 #define CPC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
12117 #define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
12118 #define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
12119 #define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
12120 //CPF_UTCL1_STATUS
12121 #define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
12122 #define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
12123 #define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
12124 #define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
12125 #define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
12126 #define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
12127 #define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
12128 #define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
12129 #define CPF_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
12130 #define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
12131 #define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
12132 #define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
12133 //CP_SD_CNTL
12134 #define CP_SD_CNTL__CPF_EN__SHIFT                                                                             0x0
12135 #define CP_SD_CNTL__CPG_EN__SHIFT                                                                             0x1
12136 #define CP_SD_CNTL__CPC_EN__SHIFT                                                                             0x2
12137 #define CP_SD_CNTL__RLC_EN__SHIFT                                                                             0x3
12138 #define CP_SD_CNTL__SPI_EN__SHIFT                                                                             0x4
12139 #define CP_SD_CNTL__WD_EN__SHIFT                                                                              0x5
12140 #define CP_SD_CNTL__IA_EN__SHIFT                                                                              0x6
12141 #define CP_SD_CNTL__PA_EN__SHIFT                                                                              0x7
12142 #define CP_SD_CNTL__RMI_EN__SHIFT                                                                             0x8
12143 #define CP_SD_CNTL__EA_EN__SHIFT                                                                              0x9
12144 #define CP_SD_CNTL__CPF_EN_MASK                                                                               0x00000001L
12145 #define CP_SD_CNTL__CPG_EN_MASK                                                                               0x00000002L
12146 #define CP_SD_CNTL__CPC_EN_MASK                                                                               0x00000004L
12147 #define CP_SD_CNTL__RLC_EN_MASK                                                                               0x00000008L
12148 #define CP_SD_CNTL__SPI_EN_MASK                                                                               0x00000010L
12149 #define CP_SD_CNTL__WD_EN_MASK                                                                                0x00000020L
12150 #define CP_SD_CNTL__IA_EN_MASK                                                                                0x00000040L
12151 #define CP_SD_CNTL__PA_EN_MASK                                                                                0x00000080L
12152 #define CP_SD_CNTL__RMI_EN_MASK                                                                               0x00000100L
12153 #define CP_SD_CNTL__EA_EN_MASK                                                                                0x00000200L
12154 //CP_SOFT_RESET_CNTL
12155 #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT                                                        0x0
12156 #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT                                                        0x1
12157 #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT                                                          0x2
12158 #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT                                                         0x3
12159 #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT                                               0x4
12160 #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT                                                      0x5
12161 #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT                                                         0x6
12162 #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK                                                          0x00000001L
12163 #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK                                                          0x00000002L
12164 #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK                                                            0x00000004L
12165 #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK                                                           0x00000008L
12166 #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK                                                 0x00000010L
12167 #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK                                                        0x00000020L
12168 #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK                                                           0x00000040L
12169 //CP_CPC_GFX_CNTL
12170 #define CP_CPC_GFX_CNTL__QUEUEID__SHIFT                                                                       0x0
12171 #define CP_CPC_GFX_CNTL__PIPEID__SHIFT                                                                        0x3
12172 #define CP_CPC_GFX_CNTL__MEID__SHIFT                                                                          0x5
12173 #define CP_CPC_GFX_CNTL__VALID__SHIFT                                                                         0x7
12174 #define CP_CPC_GFX_CNTL__QUEUEID_MASK                                                                         0x00000007L
12175 #define CP_CPC_GFX_CNTL__PIPEID_MASK                                                                          0x00000018L
12176 #define CP_CPC_GFX_CNTL__MEID_MASK                                                                            0x00000060L
12177 #define CP_CPC_GFX_CNTL__VALID_MASK                                                                           0x00000080L
12178 
12179 
12180 // addressBlock: gc_spipdec
12181 //SPI_ARB_PRIORITY
12182 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT                                                               0x0
12183 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT                                                               0x3
12184 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT                                                               0x6
12185 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT                                                               0x9
12186 #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT                                                                 0xc
12187 #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT                                                                 0xe
12188 #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT                                                                 0x10
12189 #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT                                                                 0x12
12190 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK                                                                 0x00000007L
12191 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK                                                                 0x00000038L
12192 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK                                                                 0x000001C0L
12193 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK                                                                 0x00000E00L
12194 #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK                                                                   0x00003000L
12195 #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK                                                                   0x0000C000L
12196 #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK                                                                   0x00030000L
12197 #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK                                                                   0x000C0000L
12198 //SPI_ARB_CYCLES_0
12199 #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT                                                                 0x0
12200 #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT                                                                 0x10
12201 #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK                                                                   0x0000FFFFL
12202 #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK                                                                   0xFFFF0000L
12203 //SPI_ARB_CYCLES_1
12204 #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT                                                                 0x0
12205 #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT                                                                 0x10
12206 #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK                                                                   0x0000FFFFL
12207 #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK                                                                   0xFFFF0000L
12208 //SPI_CDBG_SYS_GFX
12209 #define SPI_CDBG_SYS_GFX__PS_EN__SHIFT                                                                        0x0
12210 #define SPI_CDBG_SYS_GFX__VS_EN__SHIFT                                                                        0x1
12211 #define SPI_CDBG_SYS_GFX__GS_EN__SHIFT                                                                        0x2
12212 #define SPI_CDBG_SYS_GFX__ES_EN__SHIFT                                                                        0x3
12213 #define SPI_CDBG_SYS_GFX__HS_EN__SHIFT                                                                        0x4
12214 #define SPI_CDBG_SYS_GFX__LS_EN__SHIFT                                                                        0x5
12215 #define SPI_CDBG_SYS_GFX__CS_EN__SHIFT                                                                        0x6
12216 #define SPI_CDBG_SYS_GFX__PS_EN_MASK                                                                          0x0001L
12217 #define SPI_CDBG_SYS_GFX__VS_EN_MASK                                                                          0x0002L
12218 #define SPI_CDBG_SYS_GFX__GS_EN_MASK                                                                          0x0004L
12219 #define SPI_CDBG_SYS_GFX__ES_EN_MASK                                                                          0x0008L
12220 #define SPI_CDBG_SYS_GFX__HS_EN_MASK                                                                          0x0010L
12221 #define SPI_CDBG_SYS_GFX__LS_EN_MASK                                                                          0x0020L
12222 #define SPI_CDBG_SYS_GFX__CS_EN_MASK                                                                          0x0040L
12223 //SPI_CDBG_SYS_HP3D
12224 #define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT                                                                       0x0
12225 #define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT                                                                       0x1
12226 #define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT                                                                       0x2
12227 #define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT                                                                       0x3
12228 #define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT                                                                       0x4
12229 #define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT                                                                       0x5
12230 #define SPI_CDBG_SYS_HP3D__PS_EN_MASK                                                                         0x0001L
12231 #define SPI_CDBG_SYS_HP3D__VS_EN_MASK                                                                         0x0002L
12232 #define SPI_CDBG_SYS_HP3D__GS_EN_MASK                                                                         0x0004L
12233 #define SPI_CDBG_SYS_HP3D__ES_EN_MASK                                                                         0x0008L
12234 #define SPI_CDBG_SYS_HP3D__HS_EN_MASK                                                                         0x0010L
12235 #define SPI_CDBG_SYS_HP3D__LS_EN_MASK                                                                         0x0020L
12236 //SPI_CDBG_SYS_CS0
12237 #define SPI_CDBG_SYS_CS0__PIPE0__SHIFT                                                                        0x0
12238 #define SPI_CDBG_SYS_CS0__PIPE1__SHIFT                                                                        0x8
12239 #define SPI_CDBG_SYS_CS0__PIPE2__SHIFT                                                                        0x10
12240 #define SPI_CDBG_SYS_CS0__PIPE3__SHIFT                                                                        0x18
12241 #define SPI_CDBG_SYS_CS0__PIPE0_MASK                                                                          0x000000FFL
12242 #define SPI_CDBG_SYS_CS0__PIPE1_MASK                                                                          0x0000FF00L
12243 #define SPI_CDBG_SYS_CS0__PIPE2_MASK                                                                          0x00FF0000L
12244 #define SPI_CDBG_SYS_CS0__PIPE3_MASK                                                                          0xFF000000L
12245 //SPI_CDBG_SYS_CS1
12246 #define SPI_CDBG_SYS_CS1__PIPE0__SHIFT                                                                        0x0
12247 #define SPI_CDBG_SYS_CS1__PIPE1__SHIFT                                                                        0x8
12248 #define SPI_CDBG_SYS_CS1__PIPE2__SHIFT                                                                        0x10
12249 #define SPI_CDBG_SYS_CS1__PIPE3__SHIFT                                                                        0x18
12250 #define SPI_CDBG_SYS_CS1__PIPE0_MASK                                                                          0x000000FFL
12251 #define SPI_CDBG_SYS_CS1__PIPE1_MASK                                                                          0x0000FF00L
12252 #define SPI_CDBG_SYS_CS1__PIPE2_MASK                                                                          0x00FF0000L
12253 #define SPI_CDBG_SYS_CS1__PIPE3_MASK                                                                          0xFF000000L
12254 //SPI_WCL_PIPE_PERCENT_GFX
12255 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT                                                                0x0
12256 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT                                                         0x7
12257 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT                                                         0xc
12258 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT                                                         0x11
12259 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT                                                         0x16
12260 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK                                                                  0x0000007FL
12261 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK                                                           0x00000F80L
12262 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK                                                           0x0001F000L
12263 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK                                                           0x003E0000L
12264 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK                                                           0x07C00000L
12265 //SPI_WCL_PIPE_PERCENT_HP3D
12266 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT                                                               0x0
12267 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT                                                        0xc
12268 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT                                                        0x16
12269 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK                                                                 0x0000007FL
12270 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK                                                          0x0001F000L
12271 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK                                                          0x07C00000L
12272 //SPI_WCL_PIPE_PERCENT_CS0
12273 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT                                                                0x0
12274 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK                                                                  0x7FL
12275 //SPI_WCL_PIPE_PERCENT_CS1
12276 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT                                                                0x0
12277 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK                                                                  0x7FL
12278 //SPI_WCL_PIPE_PERCENT_CS2
12279 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT                                                                0x0
12280 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK                                                                  0x7FL
12281 //SPI_WCL_PIPE_PERCENT_CS3
12282 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT                                                                0x0
12283 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK                                                                  0x7FL
12284 //SPI_WCL_PIPE_PERCENT_CS4
12285 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT                                                                0x0
12286 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK                                                                  0x7FL
12287 //SPI_WCL_PIPE_PERCENT_CS5
12288 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT                                                                0x0
12289 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK                                                                  0x7FL
12290 //SPI_WCL_PIPE_PERCENT_CS6
12291 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT                                                                0x0
12292 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK                                                                  0x7FL
12293 //SPI_WCL_PIPE_PERCENT_CS7
12294 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT                                                                0x0
12295 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK                                                                  0x7FL
12296 //SPI_GDBG_WAVE_CNTL
12297 #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT                                                                   0x0
12298 #define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT                                                                 0x1
12299 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK                                                                     0x00000001L
12300 #define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK                                                                   0x0001FFFEL
12301 //SPI_GDBG_TRAP_CONFIG
12302 #define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT                                                                   0x0
12303 #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT                                                                 0x2
12304 #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT                                                                0x4
12305 #define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT                                                                 0x7
12306 #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT                                                               0x8
12307 #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT                                                              0x9
12308 #define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT                                                                  0xf
12309 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT                                                                 0x10
12310 #define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK                                                                     0x00000003L
12311 #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK                                                                   0x0000000CL
12312 #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK                                                                  0x00000070L
12313 #define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK                                                                   0x00000080L
12314 #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK                                                                 0x00000100L
12315 #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK                                                                0x00000200L
12316 #define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK                                                                    0x00008000L
12317 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK                                                                   0xFFFF0000L
12318 //SPI_GDBG_TRAP_MASK
12319 #define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT                                                                    0x0
12320 #define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT                                                                    0x9
12321 #define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK                                                                      0x01FFL
12322 #define SPI_GDBG_TRAP_MASK__REPLACE_MASK                                                                      0x0200L
12323 //SPI_GDBG_WAVE_CNTL2
12324 #define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT                                                                 0x0
12325 #define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT                                                                      0x10
12326 #define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK                                                                   0x0000FFFFL
12327 #define SPI_GDBG_WAVE_CNTL2__MODE_MASK                                                                        0x00030000L
12328 //SPI_GDBG_WAVE_CNTL3
12329 #define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT                                                                  0x0
12330 #define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT                                                                  0x1
12331 #define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT                                                                  0x2
12332 #define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT                                                                  0x3
12333 #define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT                                                                 0x4
12334 #define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT                                                                 0x5
12335 #define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT                                                                 0x6
12336 #define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT                                                                 0x7
12337 #define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT                                                                 0x8
12338 #define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT                                                                 0x9
12339 #define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT                                                                 0xa
12340 #define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT                                                                 0xb
12341 #define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT                                                                 0xc
12342 #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT                                                            0xd
12343 #define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT                                                                0x1c
12344 #define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK                                                                    0x00000001L
12345 #define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK                                                                    0x00000002L
12346 #define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK                                                                    0x00000004L
12347 #define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK                                                                    0x00000008L
12348 #define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK                                                                   0x00000010L
12349 #define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK                                                                   0x00000020L
12350 #define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK                                                                   0x00000040L
12351 #define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK                                                                   0x00000080L
12352 #define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK                                                                   0x00000100L
12353 #define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK                                                                   0x00000200L
12354 #define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK                                                                   0x00000400L
12355 #define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK                                                                   0x00000800L
12356 #define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK                                                                   0x00001000L
12357 #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK                                                              0x0FFFE000L
12358 #define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK                                                                  0x10000000L
12359 //SPI_GDBG_TRAP_DATA0
12360 #define SPI_GDBG_TRAP_DATA0__DATA__SHIFT                                                                      0x0
12361 #define SPI_GDBG_TRAP_DATA0__DATA_MASK                                                                        0xFFFFFFFFL
12362 //SPI_GDBG_TRAP_DATA1
12363 #define SPI_GDBG_TRAP_DATA1__DATA__SHIFT                                                                      0x0
12364 #define SPI_GDBG_TRAP_DATA1__DATA_MASK                                                                        0xFFFFFFFFL
12365 //SPI_RESET_DEBUG
12366 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT                                                             0x0
12367 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT                                                    0x1
12368 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT                                                    0x2
12369 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT                                                    0x3
12370 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT                                                    0x4
12371 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK                                                               0x01L
12372 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK                                                      0x02L
12373 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK                                                      0x04L
12374 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK                                                      0x08L
12375 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK                                                      0x10L
12376 //SPI_COMPUTE_QUEUE_RESET
12377 #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT                                                                 0x0
12378 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK                                                                   0x01L
12379 //SPI_RESOURCE_RESERVE_CU_0
12380 #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT                                                                0x0
12381 #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT                                                                0x4
12382 #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT                                                                 0x8
12383 #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT                                                               0xc
12384 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT                                                            0xf
12385 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK                                                                  0x0000000FL
12386 #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK                                                                  0x000000F0L
12387 #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK                                                                   0x00000F00L
12388 #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK                                                                 0x00007000L
12389 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK                                                              0x00078000L
12390 //SPI_RESOURCE_RESERVE_CU_1
12391 #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT                                                                0x0
12392 #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT                                                                0x4
12393 #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT                                                                 0x8
12394 #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT                                                               0xc
12395 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT                                                            0xf
12396 #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK                                                                  0x0000000FL
12397 #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK                                                                  0x000000F0L
12398 #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK                                                                   0x00000F00L
12399 #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK                                                                 0x00007000L
12400 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK                                                              0x00078000L
12401 //SPI_RESOURCE_RESERVE_CU_2
12402 #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT                                                                0x0
12403 #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT                                                                0x4
12404 #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT                                                                 0x8
12405 #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT                                                               0xc
12406 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT                                                            0xf
12407 #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK                                                                  0x0000000FL
12408 #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK                                                                  0x000000F0L
12409 #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK                                                                   0x00000F00L
12410 #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK                                                                 0x00007000L
12411 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK                                                              0x00078000L
12412 //SPI_RESOURCE_RESERVE_CU_3
12413 #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT                                                                0x0
12414 #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT                                                                0x4
12415 #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT                                                                 0x8
12416 #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT                                                               0xc
12417 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT                                                            0xf
12418 #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK                                                                  0x0000000FL
12419 #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK                                                                  0x000000F0L
12420 #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK                                                                   0x00000F00L
12421 #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK                                                                 0x00007000L
12422 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK                                                              0x00078000L
12423 //SPI_RESOURCE_RESERVE_CU_4
12424 #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT                                                                0x0
12425 #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT                                                                0x4
12426 #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT                                                                 0x8
12427 #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT                                                               0xc
12428 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT                                                            0xf
12429 #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK                                                                  0x0000000FL
12430 #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK                                                                  0x000000F0L
12431 #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK                                                                   0x00000F00L
12432 #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK                                                                 0x00007000L
12433 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK                                                              0x00078000L
12434 //SPI_RESOURCE_RESERVE_CU_5
12435 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT                                                                0x0
12436 #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT                                                                0x4
12437 #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT                                                                 0x8
12438 #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT                                                               0xc
12439 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT                                                            0xf
12440 #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK                                                                  0x0000000FL
12441 #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK                                                                  0x000000F0L
12442 #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK                                                                   0x00000F00L
12443 #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK                                                                 0x00007000L
12444 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK                                                              0x00078000L
12445 //SPI_RESOURCE_RESERVE_CU_6
12446 #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT                                                                0x0
12447 #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT                                                                0x4
12448 #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT                                                                 0x8
12449 #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT                                                               0xc
12450 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT                                                            0xf
12451 #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK                                                                  0x0000000FL
12452 #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK                                                                  0x000000F0L
12453 #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK                                                                   0x00000F00L
12454 #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK                                                                 0x00007000L
12455 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK                                                              0x00078000L
12456 //SPI_RESOURCE_RESERVE_CU_7
12457 #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT                                                                0x0
12458 #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT                                                                0x4
12459 #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT                                                                 0x8
12460 #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT                                                               0xc
12461 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT                                                            0xf
12462 #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK                                                                  0x0000000FL
12463 #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK                                                                  0x000000F0L
12464 #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK                                                                   0x00000F00L
12465 #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK                                                                 0x00007000L
12466 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK                                                              0x00078000L
12467 //SPI_RESOURCE_RESERVE_CU_8
12468 #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT                                                                0x0
12469 #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT                                                                0x4
12470 #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT                                                                 0x8
12471 #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT                                                               0xc
12472 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT                                                            0xf
12473 #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK                                                                  0x0000000FL
12474 #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK                                                                  0x000000F0L
12475 #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK                                                                   0x00000F00L
12476 #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK                                                                 0x00007000L
12477 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK                                                              0x00078000L
12478 //SPI_RESOURCE_RESERVE_CU_9
12479 #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT                                                                0x0
12480 #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT                                                                0x4
12481 #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT                                                                 0x8
12482 #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT                                                               0xc
12483 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT                                                            0xf
12484 #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK                                                                  0x0000000FL
12485 #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK                                                                  0x000000F0L
12486 #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK                                                                   0x00000F00L
12487 #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK                                                                 0x00007000L
12488 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK                                                              0x00078000L
12489 //SPI_RESOURCE_RESERVE_EN_CU_0
12490 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT                                                               0x0
12491 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT                                                        0x1
12492 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT                                                       0x10
12493 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12494 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK                                                                 0x00000001L
12495 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK                                                          0x0000FFFEL
12496 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK                                                         0x00FF0000L
12497 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12498 //SPI_RESOURCE_RESERVE_EN_CU_1
12499 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT                                                               0x0
12500 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT                                                        0x1
12501 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT                                                       0x10
12502 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12503 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK                                                                 0x00000001L
12504 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK                                                          0x0000FFFEL
12505 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK                                                         0x00FF0000L
12506 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12507 //SPI_RESOURCE_RESERVE_EN_CU_2
12508 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT                                                               0x0
12509 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT                                                        0x1
12510 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT                                                       0x10
12511 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12512 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK                                                                 0x00000001L
12513 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK                                                          0x0000FFFEL
12514 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK                                                         0x00FF0000L
12515 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12516 //SPI_RESOURCE_RESERVE_EN_CU_3
12517 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT                                                               0x0
12518 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT                                                        0x1
12519 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT                                                       0x10
12520 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12521 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK                                                                 0x00000001L
12522 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK                                                          0x0000FFFEL
12523 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK                                                         0x00FF0000L
12524 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12525 //SPI_RESOURCE_RESERVE_EN_CU_4
12526 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT                                                               0x0
12527 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT                                                        0x1
12528 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT                                                       0x10
12529 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12530 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK                                                                 0x00000001L
12531 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK                                                          0x0000FFFEL
12532 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK                                                         0x00FF0000L
12533 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12534 //SPI_RESOURCE_RESERVE_EN_CU_5
12535 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT                                                               0x0
12536 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT                                                        0x1
12537 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT                                                       0x10
12538 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12539 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK                                                                 0x00000001L
12540 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK                                                          0x0000FFFEL
12541 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK                                                         0x00FF0000L
12542 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12543 //SPI_RESOURCE_RESERVE_EN_CU_6
12544 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT                                                               0x0
12545 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT                                                        0x1
12546 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT                                                       0x10
12547 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12548 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK                                                                 0x00000001L
12549 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK                                                          0x0000FFFEL
12550 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK                                                         0x00FF0000L
12551 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12552 //SPI_RESOURCE_RESERVE_EN_CU_7
12553 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT                                                               0x0
12554 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT                                                        0x1
12555 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT                                                       0x10
12556 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12557 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK                                                                 0x00000001L
12558 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK                                                          0x0000FFFEL
12559 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK                                                         0x00FF0000L
12560 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12561 //SPI_RESOURCE_RESERVE_EN_CU_8
12562 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT                                                               0x0
12563 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT                                                        0x1
12564 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT                                                       0x10
12565 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12566 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK                                                                 0x00000001L
12567 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK                                                          0x0000FFFEL
12568 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK                                                         0x00FF0000L
12569 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12570 //SPI_RESOURCE_RESERVE_EN_CU_9
12571 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT                                                               0x0
12572 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT                                                        0x1
12573 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT                                                       0x10
12574 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12575 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK                                                                 0x00000001L
12576 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK                                                          0x0000FFFEL
12577 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK                                                         0x00FF0000L
12578 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12579 //SPI_RESOURCE_RESERVE_CU_10
12580 #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT                                                               0x0
12581 #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT                                                               0x4
12582 #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT                                                                0x8
12583 #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT                                                              0xc
12584 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT                                                           0xf
12585 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK                                                                 0x0000000FL
12586 #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK                                                                 0x000000F0L
12587 #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK                                                                  0x00000F00L
12588 #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK                                                                0x00007000L
12589 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK                                                             0x00078000L
12590 //SPI_RESOURCE_RESERVE_CU_11
12591 #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT                                                               0x0
12592 #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT                                                               0x4
12593 #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT                                                                0x8
12594 #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT                                                              0xc
12595 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT                                                           0xf
12596 #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK                                                                 0x0000000FL
12597 #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK                                                                 0x000000F0L
12598 #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK                                                                  0x00000F00L
12599 #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK                                                                0x00007000L
12600 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK                                                             0x00078000L
12601 //SPI_RESOURCE_RESERVE_EN_CU_10
12602 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT                                                              0x0
12603 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT                                                       0x1
12604 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT                                                      0x10
12605 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12606 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK                                                                0x00000001L
12607 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK                                                         0x0000FFFEL
12608 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK                                                        0x00FF0000L
12609 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12610 //SPI_RESOURCE_RESERVE_EN_CU_11
12611 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT                                                              0x0
12612 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT                                                       0x1
12613 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT                                                      0x10
12614 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12615 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK                                                                0x00000001L
12616 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK                                                         0x0000FFFEL
12617 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK                                                        0x00FF0000L
12618 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12619 //SPI_RESOURCE_RESERVE_CU_12
12620 #define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT                                                               0x0
12621 #define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT                                                               0x4
12622 #define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT                                                                0x8
12623 #define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT                                                              0xc
12624 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT                                                           0xf
12625 #define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK                                                                 0x0000000FL
12626 #define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK                                                                 0x000000F0L
12627 #define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK                                                                  0x00000F00L
12628 #define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK                                                                0x00007000L
12629 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK                                                             0x00078000L
12630 //SPI_RESOURCE_RESERVE_CU_13
12631 #define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT                                                               0x0
12632 #define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT                                                               0x4
12633 #define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT                                                                0x8
12634 #define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT                                                              0xc
12635 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT                                                           0xf
12636 #define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK                                                                 0x0000000FL
12637 #define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK                                                                 0x000000F0L
12638 #define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK                                                                  0x00000F00L
12639 #define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK                                                                0x00007000L
12640 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK                                                             0x00078000L
12641 //SPI_RESOURCE_RESERVE_CU_14
12642 #define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT                                                               0x0
12643 #define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT                                                               0x4
12644 #define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT                                                                0x8
12645 #define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT                                                              0xc
12646 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT                                                           0xf
12647 #define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK                                                                 0x0000000FL
12648 #define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK                                                                 0x000000F0L
12649 #define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK                                                                  0x00000F00L
12650 #define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK                                                                0x00007000L
12651 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK                                                             0x00078000L
12652 //SPI_RESOURCE_RESERVE_CU_15
12653 #define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT                                                               0x0
12654 #define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT                                                               0x4
12655 #define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT                                                                0x8
12656 #define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT                                                              0xc
12657 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT                                                           0xf
12658 #define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK                                                                 0x0000000FL
12659 #define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK                                                                 0x000000F0L
12660 #define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK                                                                  0x00000F00L
12661 #define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK                                                                0x00007000L
12662 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK                                                             0x00078000L
12663 //SPI_RESOURCE_RESERVE_EN_CU_12
12664 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT                                                              0x0
12665 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT                                                       0x1
12666 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT                                                      0x10
12667 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12668 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK                                                                0x00000001L
12669 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK                                                         0x0000FFFEL
12670 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK                                                        0x00FF0000L
12671 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12672 //SPI_RESOURCE_RESERVE_EN_CU_13
12673 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT                                                              0x0
12674 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT                                                       0x1
12675 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT                                                      0x10
12676 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12677 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK                                                                0x00000001L
12678 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK                                                         0x0000FFFEL
12679 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK                                                        0x00FF0000L
12680 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12681 //SPI_RESOURCE_RESERVE_EN_CU_14
12682 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT                                                              0x0
12683 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT                                                       0x1
12684 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT                                                      0x10
12685 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12686 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK                                                                0x00000001L
12687 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK                                                         0x0000FFFEL
12688 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK                                                        0x00FF0000L
12689 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12690 //SPI_RESOURCE_RESERVE_EN_CU_15
12691 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT                                                              0x0
12692 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT                                                       0x1
12693 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT                                                      0x10
12694 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12695 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK                                                                0x00000001L
12696 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK                                                         0x0000FFFEL
12697 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK                                                        0x00FF0000L
12698 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12699 //SPI_COMPUTE_WF_CTX_SAVE
12700 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT                                                              0x0
12701 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT                                                      0x1
12702 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT                                                     0x2
12703 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT                                                          0x1e
12704 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT                                                             0x1f
12705 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK                                                                0x00000001L
12706 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK                                                        0x00000002L
12707 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK                                                       0x00000004L
12708 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK                                                            0x40000000L
12709 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK                                                               0x80000000L
12710 //SPI_ARB_CNTL_0
12711 #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT                                                                 0x0
12712 #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT                                                                 0x4
12713 #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT                                                                 0x8
12714 #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK                                                                   0x0000000FL
12715 #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK                                                                   0x000000F0L
12716 #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK                                                                   0x00000F00L
12717 
12718 
12719 // addressBlock: gc_cpphqddec
12720 //CP_HQD_GFX_CONTROL
12721 #define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT                                                                    0x0
12722 #define CP_HQD_GFX_CONTROL__MISC__SHIFT                                                                       0x4
12723 #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT                                                          0xf
12724 #define CP_HQD_GFX_CONTROL__MESSAGE_MASK                                                                      0x0000000FL
12725 #define CP_HQD_GFX_CONTROL__MISC_MASK                                                                         0x00007FF0L
12726 #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK                                                            0x00008000L
12727 //CP_HQD_GFX_STATUS
12728 #define CP_HQD_GFX_STATUS__STATUS__SHIFT                                                                      0x0
12729 #define CP_HQD_GFX_STATUS__STATUS_MASK                                                                        0x0000FFFFL
12730 //CP_HPD_ROQ_OFFSETS
12731 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT                                                                  0x0
12732 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT                                                                  0x8
12733 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                                  0x10
12734 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK                                                                    0x00000007L
12735 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK                                                                    0x00003F00L
12736 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK                                                                    0x003F0000L
12737 //CP_HPD_STATUS0
12738 #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT                                                                    0x0
12739 #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT                                                                   0x5
12740 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT                                                                0x8
12741 #define CP_HPD_STATUS0__FETCHING_MQD__SHIFT                                                                   0x10
12742 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT                                                           0x11
12743 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT                                                             0x12
12744 #define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT                                                              0x14
12745 #define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT                                                                    0x1f
12746 #define CP_HPD_STATUS0__QUEUE_STATE_MASK                                                                      0x0000001FL
12747 #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK                                                                     0x000000E0L
12748 #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK                                                                  0x0000FF00L
12749 #define CP_HPD_STATUS0__FETCHING_MQD_MASK                                                                     0x00010000L
12750 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK                                                             0x00020000L
12751 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK                                                               0x00040000L
12752 #define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK                                                                0x01F00000L
12753 #define CP_HPD_STATUS0__FORCE_QUEUE_MASK                                                                      0x80000000L
12754 //CP_HPD_UTCL1_CNTL
12755 #define CP_HPD_UTCL1_CNTL__SELECT__SHIFT                                                                      0x0
12756 #define CP_HPD_UTCL1_CNTL__SELECT_MASK                                                                        0x0000000FL
12757 //CP_HPD_UTCL1_ERROR
12758 #define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT                                                                    0x0
12759 #define CP_HPD_UTCL1_ERROR__TYPE__SHIFT                                                                       0x10
12760 #define CP_HPD_UTCL1_ERROR__VMID__SHIFT                                                                       0x14
12761 #define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK                                                                      0x0000FFFFL
12762 #define CP_HPD_UTCL1_ERROR__TYPE_MASK                                                                         0x00010000L
12763 #define CP_HPD_UTCL1_ERROR__VMID_MASK                                                                         0x00F00000L
12764 //CP_HPD_UTCL1_ERROR_ADDR
12765 #define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT                                                                  0xc
12766 #define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK                                                                    0xFFFFF000L
12767 //CP_MQD_BASE_ADDR
12768 #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                    0x2
12769 #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                      0xFFFFFFFCL
12770 //CP_MQD_BASE_ADDR_HI
12771 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                              0x0
12772 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                                0x0000FFFFL
12773 //CP_HQD_ACTIVE
12774 #define CP_HQD_ACTIVE__ACTIVE__SHIFT                                                                          0x0
12775 #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT                                                                       0x1
12776 #define CP_HQD_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
12777 #define CP_HQD_ACTIVE__BUSY_GATE_MASK                                                                         0x00000002L
12778 //CP_HQD_VMID
12779 #define CP_HQD_VMID__VMID__SHIFT                                                                              0x0
12780 #define CP_HQD_VMID__IB_VMID__SHIFT                                                                           0x8
12781 #define CP_HQD_VMID__VQID__SHIFT                                                                              0x10
12782 #define CP_HQD_VMID__VMID_MASK                                                                                0x0000000FL
12783 #define CP_HQD_VMID__IB_VMID_MASK                                                                             0x00000F00L
12784 #define CP_HQD_VMID__VQID_MASK                                                                                0x03FF0000L
12785 //CP_HQD_PERSISTENT_STATE
12786 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT                                                           0x0
12787 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT                                                          0x8
12788 #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT                                                     0x15
12789 #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT                                                      0x16
12790 #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT                                                      0x17
12791 #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT                                                     0x18
12792 #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT                                                      0x19
12793 #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT                                                     0x1a
12794 #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT                                                  0x1b
12795 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT                                                        0x1c
12796 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT                                                        0x1d
12797 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT                                                          0x1e
12798 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT                                                           0x1f
12799 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK                                                             0x00000001L
12800 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK                                                            0x0003FF00L
12801 #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK                                                       0x00200000L
12802 #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK                                                        0x00400000L
12803 #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK                                                        0x00800000L
12804 #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK                                                       0x01000000L
12805 #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK                                                        0x02000000L
12806 #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK                                                       0x04000000L
12807 #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK                                                    0x08000000L
12808 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK                                                          0x10000000L
12809 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK                                                          0x20000000L
12810 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK                                                            0x40000000L
12811 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK                                                             0x80000000L
12812 //CP_HQD_PIPE_PRIORITY
12813 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT                                                            0x0
12814 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK                                                              0x00000003L
12815 //CP_HQD_QUEUE_PRIORITY
12816 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT                                                          0x0
12817 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK                                                            0x0000000FL
12818 //CP_HQD_QUANTUM
12819 #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT                                                                     0x0
12820 #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT                                                                  0x4
12821 #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT                                                               0x8
12822 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT                                                                 0x1f
12823 #define CP_HQD_QUANTUM__QUANTUM_EN_MASK                                                                       0x00000001L
12824 #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK                                                                    0x00000010L
12825 #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK                                                                 0x00003F00L
12826 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK                                                                   0x80000000L
12827 //CP_HQD_PQ_BASE
12828 #define CP_HQD_PQ_BASE__ADDR__SHIFT                                                                           0x0
12829 #define CP_HQD_PQ_BASE__ADDR_MASK                                                                             0xFFFFFFFFL
12830 //CP_HQD_PQ_BASE_HI
12831 #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT                                                                     0x0
12832 #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK                                                                       0x000000FFL
12833 //CP_HQD_PQ_RPTR
12834 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
12835 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK                                                                  0xFFFFFFFFL
12836 //CP_HQD_PQ_RPTR_REPORT_ADDR
12837 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT                                                   0x2
12838 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK                                                     0xFFFFFFFCL
12839 //CP_HQD_PQ_RPTR_REPORT_ADDR_HI
12840 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT                                             0x0
12841 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK                                               0x0000FFFFL
12842 //CP_HQD_PQ_WPTR_POLL_ADDR
12843 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT                                                            0x3
12844 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK                                                              0xFFFFFFF8L
12845 //CP_HQD_PQ_WPTR_POLL_ADDR_HI
12846 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT                                                      0x0
12847 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK                                                        0x0000FFFFL
12848 //CP_HQD_PQ_DOORBELL_CONTROL
12849 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT                                                      0x0
12850 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                  0x1
12851 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                    0x2
12852 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT                                                    0x1c
12853 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT                                                  0x1d
12854 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                        0x1e
12855 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                       0x1f
12856 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK                                                        0x00000001L
12857 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                    0x00000002L
12858 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                      0x0FFFFFFCL
12859 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK                                                      0x10000000L
12860 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK                                                    0x20000000L
12861 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                          0x40000000L
12862 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                         0x80000000L
12863 //CP_HQD_PQ_CONTROL
12864 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT                                                                  0x0
12865 #define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT                                                                  0x6
12866 #define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT                                                                  0x7
12867 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT                                                             0x8
12868 #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT                                                               0xe
12869 #define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT                                                                    0xf
12870 #define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT                                                                0x10
12871 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT                                                                 0x11
12872 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT                                                              0x14
12873 #define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT                                                                 0x17
12874 #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT                                                                0x18
12875 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT                                                             0x19
12876 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT                                                              0x1b
12877 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT                                                              0x1c
12878 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT                                                              0x1d
12879 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT                                                                  0x1e
12880 #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT                                                                   0x1f
12881 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK                                                                    0x0000003FL
12882 #define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK                                                                    0x00000040L
12883 #define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK                                                                    0x00000080L
12884 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK                                                               0x00003F00L
12885 #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK                                                                 0x00004000L
12886 #define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK                                                                      0x00008000L
12887 #define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK                                                                  0x00010000L
12888 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK                                                                   0x00060000L
12889 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK                                                                0x00300000L
12890 #define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK                                                                   0x00800000L
12891 #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK                                                                  0x01000000L
12892 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK                                                               0x06000000L
12893 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK                                                                0x08000000L
12894 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK                                                                0x10000000L
12895 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK                                                                0x20000000L
12896 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK                                                                    0x40000000L
12897 #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK                                                                     0x80000000L
12898 //CP_HQD_IB_BASE_ADDR
12899 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT                                                              0x2
12900 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK                                                                0xFFFFFFFCL
12901 //CP_HQD_IB_BASE_ADDR_HI
12902 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT                                                        0x0
12903 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK                                                          0x0000FFFFL
12904 //CP_HQD_IB_RPTR
12905 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
12906 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK                                                                  0x000FFFFFL
12907 //CP_HQD_IB_CONTROL
12908 #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT                                                                     0x0
12909 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT                                                           0x14
12910 #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT                                                              0x17
12911 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT                                                             0x18
12912 #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT                                                               0x1f
12913 #define CP_HQD_IB_CONTROL__IB_SIZE_MASK                                                                       0x000FFFFFL
12914 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK                                                             0x00300000L
12915 #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK                                                                0x00800000L
12916 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK                                                               0x01000000L
12917 #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK                                                                 0x80000000L
12918 //CP_HQD_IQ_TIMER
12919 #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT                                                                     0x0
12920 #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT                                                                    0x8
12921 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT                                                              0xb
12922 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT                                                                0xc
12923 #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT                                                                   0xe
12924 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT                                                                0x10
12925 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT                                                                 0x16
12926 #define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT                                                                   0x17
12927 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT                                                                  0x18
12928 #define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT                                                                    0x19
12929 #define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT                                                                   0x1c
12930 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT                                                                 0x1d
12931 #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT                                                                 0x1e
12932 #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT                                                                        0x1f
12933 #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK                                                                       0x000000FFL
12934 #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK                                                                      0x00000700L
12935 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK                                                                0x00000800L
12936 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK                                                                  0x00003000L
12937 #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK                                                                     0x0000C000L
12938 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK                                                                  0x003F0000L
12939 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK                                                                   0x00400000L
12940 #define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK                                                                     0x00800000L
12941 #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK                                                                    0x01000000L
12942 #define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK                                                                      0x02000000L
12943 #define CP_HQD_IQ_TIMER__REARM_TIMER_MASK                                                                     0x10000000L
12944 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK                                                                   0x20000000L
12945 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK                                                                   0x40000000L
12946 #define CP_HQD_IQ_TIMER__ACTIVE_MASK                                                                          0x80000000L
12947 //CP_HQD_IQ_RPTR
12948 #define CP_HQD_IQ_RPTR__OFFSET__SHIFT                                                                         0x0
12949 #define CP_HQD_IQ_RPTR__OFFSET_MASK                                                                           0x0000003FL
12950 //CP_HQD_DEQUEUE_REQUEST
12951 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT                                                            0x0
12952 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT                                                            0x4
12953 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT                                                            0x8
12954 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT                                                         0x9
12955 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT                                                         0xa
12956 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK                                                              0x00000007L
12957 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK                                                              0x00000010L
12958 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK                                                              0x00000100L
12959 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK                                                           0x00000200L
12960 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK                                                           0x00000400L
12961 //CP_HQD_DMA_OFFLOAD
12962 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                0x0
12963 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK                                                                  0x00000001L
12964 //CP_HQD_OFFLOAD
12965 #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                    0x0
12966 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT                                                                 0x1
12967 #define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT                                                                    0x2
12968 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT                                                                 0x3
12969 #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT                                                                    0x4
12970 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT                                                                 0x5
12971 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK                                                                      0x00000001L
12972 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK                                                                   0x00000002L
12973 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK                                                                      0x00000004L
12974 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK                                                                   0x00000008L
12975 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK                                                                      0x00000010L
12976 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK                                                                   0x00000020L
12977 //CP_HQD_SEMA_CMD
12978 #define CP_HQD_SEMA_CMD__RETRY__SHIFT                                                                         0x0
12979 #define CP_HQD_SEMA_CMD__RESULT__SHIFT                                                                        0x1
12980 #define CP_HQD_SEMA_CMD__RETRY_MASK                                                                           0x00000001L
12981 #define CP_HQD_SEMA_CMD__RESULT_MASK                                                                          0x00000006L
12982 //CP_HQD_MSG_TYPE
12983 #define CP_HQD_MSG_TYPE__ACTION__SHIFT                                                                        0x0
12984 #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT                                                                    0x4
12985 #define CP_HQD_MSG_TYPE__ACTION_MASK                                                                          0x00000007L
12986 #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK                                                                      0x00000070L
12987 //CP_HQD_ATOMIC0_PREOP_LO
12988 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT                                                      0x0
12989 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK                                                        0xFFFFFFFFL
12990 //CP_HQD_ATOMIC0_PREOP_HI
12991 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT                                                      0x0
12992 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK                                                        0xFFFFFFFFL
12993 //CP_HQD_ATOMIC1_PREOP_LO
12994 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT                                                      0x0
12995 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK                                                        0xFFFFFFFFL
12996 //CP_HQD_ATOMIC1_PREOP_HI
12997 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT                                                      0x0
12998 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK                                                        0xFFFFFFFFL
12999 //CP_HQD_HQ_SCHEDULER0
13000 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT                                                                0x0
13001 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK                                                                  0xFFFFFFFFL
13002 //CP_HQD_HQ_STATUS0
13003 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT                                                              0x0
13004 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT                                                           0x2
13005 #define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT                                                                     0x4
13006 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT                                                            0x7
13007 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT                                                                  0x8
13008 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT                                                                0x9
13009 #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT                                                                  0xa
13010 #define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT                                                                  0x1e
13011 #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT                                                           0x1f
13012 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK                                                                0x00000003L
13013 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK                                                             0x0000000CL
13014 #define CP_HQD_HQ_STATUS0__RSV_6_4_MASK                                                                       0x00000070L
13015 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK                                                              0x00000080L
13016 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK                                                                    0x00000100L
13017 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK                                                                  0x00000200L
13018 #define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK                                                                    0x3FFFFC00L
13019 #define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK                                                                    0x40000000L
13020 #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK                                                             0x80000000L
13021 //CP_HQD_HQ_CONTROL0
13022 #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT                                                                    0x0
13023 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK                                                                      0xFFFFFFFFL
13024 //CP_HQD_HQ_SCHEDULER1
13025 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT                                                                0x0
13026 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK                                                                  0xFFFFFFFFL
13027 //CP_MQD_CONTROL
13028 #define CP_MQD_CONTROL__VMID__SHIFT                                                                           0x0
13029 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT                                                                     0x8
13030 #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT                                                                 0xc
13031 #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT                                                              0xd
13032 #define CP_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                    0x17
13033 #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT                                                                   0x18
13034 #define CP_MQD_CONTROL__VMID_MASK                                                                             0x0000000FL
13035 #define CP_MQD_CONTROL__PRIV_STATE_MASK                                                                       0x00000100L
13036 #define CP_MQD_CONTROL__PROCESSING_MQD_MASK                                                                   0x00001000L
13037 #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK                                                                0x00002000L
13038 #define CP_MQD_CONTROL__EXE_DISABLE_MASK                                                                      0x00800000L
13039 #define CP_MQD_CONTROL__CACHE_POLICY_MASK                                                                     0x01000000L
13040 //CP_HQD_HQ_STATUS1
13041 #define CP_HQD_HQ_STATUS1__STATUS__SHIFT                                                                      0x0
13042 #define CP_HQD_HQ_STATUS1__STATUS_MASK                                                                        0xFFFFFFFFL
13043 //CP_HQD_HQ_CONTROL1
13044 #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT                                                                    0x0
13045 #define CP_HQD_HQ_CONTROL1__CONTROL_MASK                                                                      0xFFFFFFFFL
13046 //CP_HQD_EOP_BASE_ADDR
13047 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x0
13048 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFFL
13049 //CP_HQD_EOP_BASE_ADDR_HI
13050 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
13051 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x000000FFL
13052 //CP_HQD_EOP_CONTROL
13053 #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT                                                                   0x0
13054 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT                                                             0x8
13055 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT                                                             0xc
13056 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT                                                           0xd
13057 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT                                                           0xe
13058 #define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT                                                               0x15
13059 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT                                                            0x16
13060 #define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
13061 #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
13062 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT                                                             0x1d
13063 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT                                                               0x1f
13064 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK                                                                     0x0000003FL
13065 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK                                                               0x00000100L
13066 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK                                                               0x00001000L
13067 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK                                                             0x00002000L
13068 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK                                                             0x00004000L
13069 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK                                                                 0x00200000L
13070 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK                                                              0x00400000L
13071 #define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
13072 #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK                                                                 0x01000000L
13073 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK                                                               0x60000000L
13074 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK                                                                 0x80000000L
13075 //CP_HQD_EOP_RPTR
13076 #define CP_HQD_EOP_RPTR__RPTR__SHIFT                                                                          0x0
13077 #define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT                                                                 0x1c
13078 #define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT                                                                  0x1d
13079 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT                                                             0x1e
13080 #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT                                                                  0x1f
13081 #define CP_HQD_EOP_RPTR__RPTR_MASK                                                                            0x00001FFFL
13082 #define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK                                                                   0x10000000L
13083 #define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK                                                                    0x20000000L
13084 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK                                                               0x40000000L
13085 #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK                                                                    0x80000000L
13086 //CP_HQD_EOP_WPTR
13087 #define CP_HQD_EOP_WPTR__WPTR__SHIFT                                                                          0x0
13088 #define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT                                                                     0xf
13089 #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT                                                                     0x10
13090 #define CP_HQD_EOP_WPTR__WPTR_MASK                                                                            0x00001FFFL
13091 #define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK                                                                       0x00008000L
13092 #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK                                                                       0x1FFF0000L
13093 //CP_HQD_EOP_EVENTS
13094 #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT                                                                 0x0
13095 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT                                                       0x10
13096 #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK                                                                   0x00000FFFL
13097 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK                                                         0x00010000L
13098 //CP_HQD_CTX_SAVE_BASE_ADDR_LO
13099 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT                                                             0xc
13100 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK                                                               0xFFFFF000L
13101 //CP_HQD_CTX_SAVE_BASE_ADDR_HI
13102 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
13103 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
13104 //CP_HQD_CTX_SAVE_CONTROL
13105 #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT                                                                0x3
13106 #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT                                                           0x17
13107 #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK                                                                  0x00000008L
13108 #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK                                                             0x00800000L
13109 //CP_HQD_CNTL_STACK_OFFSET
13110 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT                                                               0x2
13111 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK                                                                 0x00007FFCL
13112 //CP_HQD_CNTL_STACK_SIZE
13113 #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT                                                                   0xc
13114 #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK                                                                     0x00007000L
13115 //CP_HQD_WG_STATE_OFFSET
13116 #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT                                                                 0x2
13117 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK                                                                   0x01FFFFFCL
13118 //CP_HQD_CTX_SAVE_SIZE
13119 #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT                                                                     0xc
13120 #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK                                                                       0x01FFF000L
13121 //CP_HQD_GDS_RESOURCE_STATE
13122 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT                                                         0x0
13123 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT                                                         0x1
13124 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT                                                            0x4
13125 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT                                                            0xc
13126 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK                                                           0x00000001L
13127 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK                                                           0x00000002L
13128 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK                                                              0x000003F0L
13129 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK                                                              0x0003F000L
13130 //CP_HQD_ERROR
13131 #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
13132 #define CP_HQD_ERROR__SUA_ERROR__SHIFT                                                                        0x4
13133 #define CP_HQD_ERROR__AQL_ERROR__SHIFT                                                                        0x5
13134 #define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT                                                                   0x8
13135 #define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT                                                                   0x9
13136 #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT                                                                  0xa
13137 #define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT                                                                   0xb
13138 #define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT                                                                 0xc
13139 #define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT                                                                  0xd
13140 #define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0xe
13141 #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0xf
13142 #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x10
13143 #define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT                                                                   0x11
13144 #define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT                                                                   0x12
13145 #define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT                                                                   0x13
13146 #define CP_HQD_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
13147 #define CP_HQD_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
13148 #define CP_HQD_ERROR__AQL_ERROR_MASK                                                                          0x00000020L
13149 #define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK                                                                     0x00000100L
13150 #define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK                                                                     0x00000200L
13151 #define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK                                                                    0x00000400L
13152 #define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK                                                                     0x00000800L
13153 #define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK                                                                   0x00001000L
13154 #define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK                                                                    0x00002000L
13155 #define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00004000L
13156 #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00008000L
13157 #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00010000L
13158 #define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK                                                                     0x00020000L
13159 #define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK                                                                     0x00040000L
13160 #define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK                                                                     0x00080000L
13161 //CP_HQD_EOP_WPTR_MEM
13162 #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT                                                                      0x0
13163 #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK                                                                        0x00001FFFL
13164 //CP_HQD_AQL_CONTROL
13165 #define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT                                                                   0x0
13166 #define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT                                                                0xf
13167 #define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT                                                                   0x10
13168 #define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT                                                                0x1f
13169 #define CP_HQD_AQL_CONTROL__CONTROL0_MASK                                                                     0x00007FFFL
13170 #define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK                                                                  0x00008000L
13171 #define CP_HQD_AQL_CONTROL__CONTROL1_MASK                                                                     0x7FFF0000L
13172 #define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK                                                                  0x80000000L
13173 //CP_HQD_PQ_WPTR_LO
13174 #define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT                                                                      0x0
13175 #define CP_HQD_PQ_WPTR_LO__OFFSET_MASK                                                                        0xFFFFFFFFL
13176 //CP_HQD_PQ_WPTR_HI
13177 #define CP_HQD_PQ_WPTR_HI__DATA__SHIFT                                                                        0x0
13178 #define CP_HQD_PQ_WPTR_HI__DATA_MASK                                                                          0xFFFFFFFFL
13179 
13180 
13181 // addressBlock: gc_didtdec
13182 //DIDT_IND_INDEX
13183 #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT                                                                 0x0
13184 #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK                                                                   0xFFFFFFFFL
13185 //DIDT_IND_DATA
13186 #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT                                                                   0x0
13187 #define DIDT_IND_DATA__DIDT_IND_DATA_MASK                                                                     0xFFFFFFFFL
13188 
13189 
13190 // addressBlock: gc_gccacdec
13191 //GC_CAC_CTRL_1
13192 #define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT                                                                      0x0
13193 #define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT                                                                      0x18
13194 #define GC_CAC_CTRL_1__CAC_WINDOW_MASK                                                                        0x00FFFFFFL
13195 #define GC_CAC_CTRL_1__TDP_WINDOW_MASK                                                                        0xFF000000L
13196 //GC_CAC_CTRL_2
13197 #define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT                                                                      0x0
13198 #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT                                                            0x1
13199 #define GC_CAC_CTRL_2__UNUSED_0__SHIFT                                                                        0x2
13200 #define GC_CAC_CTRL_2__CAC_ENABLE_MASK                                                                        0x00000001L
13201 #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK                                                              0x00000002L
13202 #define GC_CAC_CTRL_2__UNUSED_0_MASK                                                                          0xFFFFFFFCL
13203 //GC_CAC_CGTT_CLK_CTRL
13204 #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
13205 #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
13206 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                        0x1e
13207 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                        0x1f
13208 #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
13209 #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
13210 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                          0x40000000L
13211 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                          0x80000000L
13212 //GC_CAC_AGGR_LOWER
13213 #define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT                                                                   0x0
13214 #define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK                                                                     0xFFFFFFFFL
13215 //GC_CAC_AGGR_UPPER
13216 #define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT                                                                  0x0
13217 #define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK                                                                    0xFFFFFFFFL
13218 //GC_CAC_SOFT_CTRL
13219 #define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT                                                                    0x0
13220 #define GC_CAC_SOFT_CTRL__UNUSED__SHIFT                                                                       0x1
13221 #define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK                                                                      0x00000001L
13222 #define GC_CAC_SOFT_CTRL__UNUSED_MASK                                                                         0xFFFFFFFEL
13223 //GC_DIDT_CTRL0
13224 #define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
13225 #define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
13226 #define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT                                                                     0x3
13227 #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
13228 #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x5
13229 #define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
13230 #define GC_DIDT_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
13231 #define GC_DIDT_CTRL0__DIDT_SW_RST_MASK                                                                       0x00000008L
13232 #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
13233 #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001E0L
13234 //GC_DIDT_CTRL1
13235 #define GC_DIDT_CTRL1__MIN_POWER__SHIFT                                                                       0x0
13236 #define GC_DIDT_CTRL1__MAX_POWER__SHIFT                                                                       0x10
13237 #define GC_DIDT_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
13238 #define GC_DIDT_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
13239 //GC_DIDT_CTRL2
13240 #define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
13241 #define GC_DIDT_CTRL2__UNUSED_0__SHIFT                                                                        0xe
13242 #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
13243 #define GC_DIDT_CTRL2__UNUSED_1__SHIFT                                                                        0x1a
13244 #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
13245 #define GC_DIDT_CTRL2__UNUSED_2__SHIFT                                                                        0x1f
13246 #define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
13247 #define GC_DIDT_CTRL2__UNUSED_0_MASK                                                                          0x0000C000L
13248 #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
13249 #define GC_DIDT_CTRL2__UNUSED_1_MASK                                                                          0x04000000L
13250 #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
13251 #define GC_DIDT_CTRL2__UNUSED_2_MASK                                                                          0x80000000L
13252 //GC_DIDT_WEIGHT
13253 #define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT                                                                      0x0
13254 #define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT                                                                      0x8
13255 #define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT                                                                      0x10
13256 #define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT                                                                     0x18
13257 #define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK                                                                        0x000000FFL
13258 #define GC_DIDT_WEIGHT__DB_WEIGHT_MASK                                                                        0x0000FF00L
13259 #define GC_DIDT_WEIGHT__TD_WEIGHT_MASK                                                                        0x00FF0000L
13260 #define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK                                                                       0xFF000000L
13261 //GC_DIDT_WEIGHT_1
13262 #define GC_DIDT_WEIGHT_1__DBR_WEIGHT__SHIFT                                                                   0x0
13263 #define GC_DIDT_WEIGHT_1__DBR_WEIGHT_MASK                                                                     0x000000FFL
13264 //GC_EDC_CTRL
13265 #define GC_EDC_CTRL__EDC_EN__SHIFT                                                                            0x0
13266 #define GC_EDC_CTRL__EDC_SW_RST__SHIFT                                                                        0x1
13267 #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                               0x2
13268 #define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                                   0x3
13269 #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                       0x4
13270 #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                          0x9
13271 #define GC_EDC_CTRL__UNUSED_0__SHIFT                                                                          0xa
13272 #define GC_EDC_CTRL__EDC_EN_MASK                                                                              0x00000001L
13273 #define GC_EDC_CTRL__EDC_SW_RST_MASK                                                                          0x00000002L
13274 #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                                 0x00000004L
13275 #define GC_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                     0x00000008L
13276 #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                         0x000001F0L
13277 #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                            0x00000200L
13278 #define GC_EDC_CTRL__UNUSED_0_MASK                                                                            0xFFFFFC00L
13279 //GC_EDC_THRESHOLD
13280 #define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                                0x0
13281 #define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                                  0xFFFFFFFFL
13282 //GC_EDC_STATUS
13283 #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                              0x0
13284 #define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT                                                         0x3
13285 #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                                0x00000007L
13286 #define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK                                                           0x03FFFFF8L
13287 //GC_EDC_OVERFLOW
13288 #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                              0x0
13289 #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                           0x1
13290 #define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT                                                      0x11
13291 #define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT                                                                   0x12
13292 #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                                0x00000001L
13293 #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                             0x0001FFFEL
13294 #define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK                                                        0x00020000L
13295 #define GC_EDC_OVERFLOW__PSM_COUNTER_MASK                                                                     0xFFFC0000L
13296 //GC_EDC_ROLLING_POWER_DELTA
13297 #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                            0x0
13298 #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                              0xFFFFFFFFL
13299 //GC_DIDT_DROOP_CTRL
13300 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT                                                        0x0
13301 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT                                                       0x1
13302 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT                                                     0xf
13303 #define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT                                                             0x13
13304 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT                                                  0x1f
13305 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK                                                          0x00000001L
13306 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK                                                         0x00007FFEL
13307 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK                                                       0x00078000L
13308 #define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK                                                               0x00080000L
13309 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK                                                    0x80000000L
13310 //GC_EDC_DROOP_CTRL
13311 #define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT                                                          0x0
13312 #define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT                                                         0x1
13313 #define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT                                                       0xf
13314 #define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT                                                                 0x14
13315 #define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT                                                               0x15
13316 #define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK                                                            0x00000001L
13317 #define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK                                                           0x00007FFEL
13318 #define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK                                                         0x000F8000L
13319 #define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK                                                                   0x00100000L
13320 #define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK                                                                 0x00200000L
13321 //GC_CAC_IND_INDEX
13322 #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT                                                              0x0
13323 #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK                                                                0xFFFFFFFFL
13324 //GC_CAC_IND_DATA
13325 #define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT                                                               0x0
13326 #define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK                                                                 0xFFFFFFFFL
13327 //SE_CAC_CGTT_CLK_CTRL
13328 #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
13329 #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
13330 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                        0x1e
13331 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                        0x1f
13332 #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
13333 #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
13334 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                          0x40000000L
13335 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                          0x80000000L
13336 //SE_CAC_IND_INDEX
13337 #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT                                                              0x0
13338 #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK                                                                0xFFFFFFFFL
13339 //SE_CAC_IND_DATA
13340 #define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT                                                               0x0
13341 #define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK                                                                 0xFFFFFFFFL
13342 
13343 
13344 // addressBlock: gc_tcpdec
13345 //TCP_WATCH0_ADDR_H
13346 #define TCP_WATCH0_ADDR_H__ADDR__SHIFT                                                                        0x0
13347 #define TCP_WATCH0_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
13348 //TCP_WATCH0_ADDR_L
13349 #define TCP_WATCH0_ADDR_L__ADDR__SHIFT                                                                        0x6
13350 #define TCP_WATCH0_ADDR_L__ADDR_MASK                                                                          0xFFFFFFC0L
13351 //TCP_WATCH0_CNTL
13352 #define TCP_WATCH0_CNTL__MASK__SHIFT                                                                          0x0
13353 #define TCP_WATCH0_CNTL__VMID__SHIFT                                                                          0x18
13354 #define TCP_WATCH0_CNTL__ATC__SHIFT                                                                           0x1c
13355 #define TCP_WATCH0_CNTL__MODE__SHIFT                                                                          0x1d
13356 #define TCP_WATCH0_CNTL__VALID__SHIFT                                                                         0x1f
13357 #define TCP_WATCH0_CNTL__MASK_MASK                                                                            0x00FFFFFFL
13358 #define TCP_WATCH0_CNTL__VMID_MASK                                                                            0x0F000000L
13359 #define TCP_WATCH0_CNTL__ATC_MASK                                                                             0x10000000L
13360 #define TCP_WATCH0_CNTL__MODE_MASK                                                                            0x60000000L
13361 #define TCP_WATCH0_CNTL__VALID_MASK                                                                           0x80000000L
13362 //TCP_WATCH1_ADDR_H
13363 #define TCP_WATCH1_ADDR_H__ADDR__SHIFT                                                                        0x0
13364 #define TCP_WATCH1_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
13365 //TCP_WATCH1_ADDR_L
13366 #define TCP_WATCH1_ADDR_L__ADDR__SHIFT                                                                        0x6
13367 #define TCP_WATCH1_ADDR_L__ADDR_MASK                                                                          0xFFFFFFC0L
13368 //TCP_WATCH1_CNTL
13369 #define TCP_WATCH1_CNTL__MASK__SHIFT                                                                          0x0
13370 #define TCP_WATCH1_CNTL__VMID__SHIFT                                                                          0x18
13371 #define TCP_WATCH1_CNTL__ATC__SHIFT                                                                           0x1c
13372 #define TCP_WATCH1_CNTL__MODE__SHIFT                                                                          0x1d
13373 #define TCP_WATCH1_CNTL__VALID__SHIFT                                                                         0x1f
13374 #define TCP_WATCH1_CNTL__MASK_MASK                                                                            0x00FFFFFFL
13375 #define TCP_WATCH1_CNTL__VMID_MASK                                                                            0x0F000000L
13376 #define TCP_WATCH1_CNTL__ATC_MASK                                                                             0x10000000L
13377 #define TCP_WATCH1_CNTL__MODE_MASK                                                                            0x60000000L
13378 #define TCP_WATCH1_CNTL__VALID_MASK                                                                           0x80000000L
13379 //TCP_WATCH2_ADDR_H
13380 #define TCP_WATCH2_ADDR_H__ADDR__SHIFT                                                                        0x0
13381 #define TCP_WATCH2_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
13382 //TCP_WATCH2_ADDR_L
13383 #define TCP_WATCH2_ADDR_L__ADDR__SHIFT                                                                        0x6
13384 #define TCP_WATCH2_ADDR_L__ADDR_MASK                                                                          0xFFFFFFC0L
13385 //TCP_WATCH2_CNTL
13386 #define TCP_WATCH2_CNTL__MASK__SHIFT                                                                          0x0
13387 #define TCP_WATCH2_CNTL__VMID__SHIFT                                                                          0x18
13388 #define TCP_WATCH2_CNTL__ATC__SHIFT                                                                           0x1c
13389 #define TCP_WATCH2_CNTL__MODE__SHIFT                                                                          0x1d
13390 #define TCP_WATCH2_CNTL__VALID__SHIFT                                                                         0x1f
13391 #define TCP_WATCH2_CNTL__MASK_MASK                                                                            0x00FFFFFFL
13392 #define TCP_WATCH2_CNTL__VMID_MASK                                                                            0x0F000000L
13393 #define TCP_WATCH2_CNTL__ATC_MASK                                                                             0x10000000L
13394 #define TCP_WATCH2_CNTL__MODE_MASK                                                                            0x60000000L
13395 #define TCP_WATCH2_CNTL__VALID_MASK                                                                           0x80000000L
13396 //TCP_WATCH3_ADDR_H
13397 #define TCP_WATCH3_ADDR_H__ADDR__SHIFT                                                                        0x0
13398 #define TCP_WATCH3_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
13399 //TCP_WATCH3_ADDR_L
13400 #define TCP_WATCH3_ADDR_L__ADDR__SHIFT                                                                        0x6
13401 #define TCP_WATCH3_ADDR_L__ADDR_MASK                                                                          0xFFFFFFC0L
13402 //TCP_WATCH3_CNTL
13403 #define TCP_WATCH3_CNTL__MASK__SHIFT                                                                          0x0
13404 #define TCP_WATCH3_CNTL__VMID__SHIFT                                                                          0x18
13405 #define TCP_WATCH3_CNTL__ATC__SHIFT                                                                           0x1c
13406 #define TCP_WATCH3_CNTL__MODE__SHIFT                                                                          0x1d
13407 #define TCP_WATCH3_CNTL__VALID__SHIFT                                                                         0x1f
13408 #define TCP_WATCH3_CNTL__MASK_MASK                                                                            0x00FFFFFFL
13409 #define TCP_WATCH3_CNTL__VMID_MASK                                                                            0x0F000000L
13410 #define TCP_WATCH3_CNTL__ATC_MASK                                                                             0x10000000L
13411 #define TCP_WATCH3_CNTL__MODE_MASK                                                                            0x60000000L
13412 #define TCP_WATCH3_CNTL__VALID_MASK                                                                           0x80000000L
13413 //TCP_GATCL1_CNTL
13414 #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT                                                           0x19
13415 #define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT                                                                    0x1a
13416 #define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT                                                                0x1b
13417 #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
13418 #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
13419 #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK                                                             0x02000000L
13420 #define TCP_GATCL1_CNTL__FORCE_MISS_MASK                                                                      0x04000000L
13421 #define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK                                                                  0x08000000L
13422 #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
13423 #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
13424 //TCP_ATC_EDC_GATCL1_CNT
13425 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT                                                               0x0
13426 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK                                                                 0x000000FFL
13427 //TCP_GATCL1_DSM_CNTL
13428 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT                                      0x0
13429 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT                                      0x1
13430 #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT                                          0x2
13431 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK                                        0x00000001L
13432 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK                                        0x00000002L
13433 #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK                                            0x00000004L
13434 //TCP_CNTL2
13435 #define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT                                                                   0x0
13436 #define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK                                                                     0x000000FFL
13437 //TCP_UTCL1_CNTL1
13438 #define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
13439 #define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT                                                             0x1
13440 #define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
13441 #define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                     0x3
13442 #define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
13443 #define TCP_UTCL1_CNTL1__CLIENTID__SHIFT                                                                      0x7
13444 #define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
13445 #define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
13446 #define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
13447 #define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
13448 #define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
13449 #define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
13450 #define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
13451 #define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
13452 #define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK                                                               0x00000002L
13453 #define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
13454 #define TCP_UTCL1_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
13455 #define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
13456 #define TCP_UTCL1_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
13457 #define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
13458 #define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
13459 #define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
13460 #define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
13461 #define TCP_UTCL1_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
13462 #define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
13463 #define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
13464 //TCP_UTCL1_CNTL2
13465 #define TCP_UTCL1_CNTL2__SPARE__SHIFT                                                                         0x0
13466 #define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
13467 #define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT                                                                0xa
13468 #define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
13469 #define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
13470 #define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
13471 #define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                          0x1a
13472 #define TCP_UTCL1_CNTL2__SPARE_MASK                                                                           0x000000FFL
13473 #define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
13474 #define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK                                                                  0x00000400L
13475 #define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
13476 #define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
13477 #define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
13478 #define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                            0x04000000L
13479 //TCP_UTCL1_STATUS
13480 #define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
13481 #define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
13482 #define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
13483 #define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
13484 #define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
13485 #define TCP_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
13486 //TCP_PERFCOUNTER_FILTER
13487 #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT                                                                 0x0
13488 #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT                                                                   0x1
13489 #define TCP_PERFCOUNTER_FILTER__DIM__SHIFT                                                                    0x2
13490 #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT                                                            0x5
13491 #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT                                                             0xb
13492 #define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT                                                                0xf
13493 #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT                                                            0x14
13494 #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT                                                            0x16
13495 #define TCP_PERFCOUNTER_FILTER__GLC__SHIFT                                                                    0x19
13496 #define TCP_PERFCOUNTER_FILTER__SLC__SHIFT                                                                    0x1a
13497 #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT                                                     0x1b
13498 #define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT                                                              0x1c
13499 #define TCP_PERFCOUNTER_FILTER__BUFFER_MASK                                                                   0x00000001L
13500 #define TCP_PERFCOUNTER_FILTER__FLAT_MASK                                                                     0x00000002L
13501 #define TCP_PERFCOUNTER_FILTER__DIM_MASK                                                                      0x0000001CL
13502 #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK                                                              0x000007E0L
13503 #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK                                                               0x00007800L
13504 #define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK                                                                  0x000F8000L
13505 #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK                                                              0x00300000L
13506 #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK                                                              0x01C00000L
13507 #define TCP_PERFCOUNTER_FILTER__GLC_MASK                                                                      0x02000000L
13508 #define TCP_PERFCOUNTER_FILTER__SLC_MASK                                                                      0x04000000L
13509 #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK                                                       0x08000000L
13510 #define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK                                                                0x70000000L
13511 //TCP_PERFCOUNTER_FILTER_EN
13512 #define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT                                                              0x0
13513 #define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT                                                                0x1
13514 #define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT                                                                 0x2
13515 #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT                                                         0x3
13516 #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT                                                          0x4
13517 #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT                                                             0x5
13518 #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT                                                         0x6
13519 #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT                                                         0x7
13520 #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT                                                                 0x8
13521 #define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT                                                                 0x9
13522 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT                                                  0xa
13523 #define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT                                                           0xb
13524 #define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK                                                                0x00000001L
13525 #define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK                                                                  0x00000002L
13526 #define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK                                                                   0x00000004L
13527 #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK                                                           0x00000008L
13528 #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK                                                            0x00000010L
13529 #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK                                                               0x00000020L
13530 #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK                                                           0x00000040L
13531 #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK                                                           0x00000080L
13532 #define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK                                                                   0x00000100L
13533 #define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK                                                                   0x00000200L
13534 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK                                                    0x00000400L
13535 #define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK                                                             0x00000800L
13536 
13537 
13538 // addressBlock: gc_gdspdec
13539 //GDS_VMID0_BASE
13540 #define GDS_VMID0_BASE__BASE__SHIFT                                                                           0x0
13541 #define GDS_VMID0_BASE__BASE_MASK                                                                             0x0000FFFFL
13542 //GDS_VMID0_SIZE
13543 #define GDS_VMID0_SIZE__SIZE__SHIFT                                                                           0x0
13544 #define GDS_VMID0_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13545 //GDS_VMID1_BASE
13546 #define GDS_VMID1_BASE__BASE__SHIFT                                                                           0x0
13547 #define GDS_VMID1_BASE__BASE_MASK                                                                             0x0000FFFFL
13548 //GDS_VMID1_SIZE
13549 #define GDS_VMID1_SIZE__SIZE__SHIFT                                                                           0x0
13550 #define GDS_VMID1_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13551 //GDS_VMID2_BASE
13552 #define GDS_VMID2_BASE__BASE__SHIFT                                                                           0x0
13553 #define GDS_VMID2_BASE__BASE_MASK                                                                             0x0000FFFFL
13554 //GDS_VMID2_SIZE
13555 #define GDS_VMID2_SIZE__SIZE__SHIFT                                                                           0x0
13556 #define GDS_VMID2_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13557 //GDS_VMID3_BASE
13558 #define GDS_VMID3_BASE__BASE__SHIFT                                                                           0x0
13559 #define GDS_VMID3_BASE__BASE_MASK                                                                             0x0000FFFFL
13560 //GDS_VMID3_SIZE
13561 #define GDS_VMID3_SIZE__SIZE__SHIFT                                                                           0x0
13562 #define GDS_VMID3_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13563 //GDS_VMID4_BASE
13564 #define GDS_VMID4_BASE__BASE__SHIFT                                                                           0x0
13565 #define GDS_VMID4_BASE__BASE_MASK                                                                             0x0000FFFFL
13566 //GDS_VMID4_SIZE
13567 #define GDS_VMID4_SIZE__SIZE__SHIFT                                                                           0x0
13568 #define GDS_VMID4_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13569 //GDS_VMID5_BASE
13570 #define GDS_VMID5_BASE__BASE__SHIFT                                                                           0x0
13571 #define GDS_VMID5_BASE__BASE_MASK                                                                             0x0000FFFFL
13572 //GDS_VMID5_SIZE
13573 #define GDS_VMID5_SIZE__SIZE__SHIFT                                                                           0x0
13574 #define GDS_VMID5_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13575 //GDS_VMID6_BASE
13576 #define GDS_VMID6_BASE__BASE__SHIFT                                                                           0x0
13577 #define GDS_VMID6_BASE__BASE_MASK                                                                             0x0000FFFFL
13578 //GDS_VMID6_SIZE
13579 #define GDS_VMID6_SIZE__SIZE__SHIFT                                                                           0x0
13580 #define GDS_VMID6_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13581 //GDS_VMID7_BASE
13582 #define GDS_VMID7_BASE__BASE__SHIFT                                                                           0x0
13583 #define GDS_VMID7_BASE__BASE_MASK                                                                             0x0000FFFFL
13584 //GDS_VMID7_SIZE
13585 #define GDS_VMID7_SIZE__SIZE__SHIFT                                                                           0x0
13586 #define GDS_VMID7_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13587 //GDS_VMID8_BASE
13588 #define GDS_VMID8_BASE__BASE__SHIFT                                                                           0x0
13589 #define GDS_VMID8_BASE__BASE_MASK                                                                             0x0000FFFFL
13590 //GDS_VMID8_SIZE
13591 #define GDS_VMID8_SIZE__SIZE__SHIFT                                                                           0x0
13592 #define GDS_VMID8_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13593 //GDS_VMID9_BASE
13594 #define GDS_VMID9_BASE__BASE__SHIFT                                                                           0x0
13595 #define GDS_VMID9_BASE__BASE_MASK                                                                             0x0000FFFFL
13596 //GDS_VMID9_SIZE
13597 #define GDS_VMID9_SIZE__SIZE__SHIFT                                                                           0x0
13598 #define GDS_VMID9_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13599 //GDS_VMID10_BASE
13600 #define GDS_VMID10_BASE__BASE__SHIFT                                                                          0x0
13601 #define GDS_VMID10_BASE__BASE_MASK                                                                            0x0000FFFFL
13602 //GDS_VMID10_SIZE
13603 #define GDS_VMID10_SIZE__SIZE__SHIFT                                                                          0x0
13604 #define GDS_VMID10_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13605 //GDS_VMID11_BASE
13606 #define GDS_VMID11_BASE__BASE__SHIFT                                                                          0x0
13607 #define GDS_VMID11_BASE__BASE_MASK                                                                            0x0000FFFFL
13608 //GDS_VMID11_SIZE
13609 #define GDS_VMID11_SIZE__SIZE__SHIFT                                                                          0x0
13610 #define GDS_VMID11_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13611 //GDS_VMID12_BASE
13612 #define GDS_VMID12_BASE__BASE__SHIFT                                                                          0x0
13613 #define GDS_VMID12_BASE__BASE_MASK                                                                            0x0000FFFFL
13614 //GDS_VMID12_SIZE
13615 #define GDS_VMID12_SIZE__SIZE__SHIFT                                                                          0x0
13616 #define GDS_VMID12_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13617 //GDS_VMID13_BASE
13618 #define GDS_VMID13_BASE__BASE__SHIFT                                                                          0x0
13619 #define GDS_VMID13_BASE__BASE_MASK                                                                            0x0000FFFFL
13620 //GDS_VMID13_SIZE
13621 #define GDS_VMID13_SIZE__SIZE__SHIFT                                                                          0x0
13622 #define GDS_VMID13_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13623 //GDS_VMID14_BASE
13624 #define GDS_VMID14_BASE__BASE__SHIFT                                                                          0x0
13625 #define GDS_VMID14_BASE__BASE_MASK                                                                            0x0000FFFFL
13626 //GDS_VMID14_SIZE
13627 #define GDS_VMID14_SIZE__SIZE__SHIFT                                                                          0x0
13628 #define GDS_VMID14_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13629 //GDS_VMID15_BASE
13630 #define GDS_VMID15_BASE__BASE__SHIFT                                                                          0x0
13631 #define GDS_VMID15_BASE__BASE_MASK                                                                            0x0000FFFFL
13632 //GDS_VMID15_SIZE
13633 #define GDS_VMID15_SIZE__SIZE__SHIFT                                                                          0x0
13634 #define GDS_VMID15_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13635 //GDS_GWS_VMID0
13636 #define GDS_GWS_VMID0__BASE__SHIFT                                                                            0x0
13637 #define GDS_GWS_VMID0__SIZE__SHIFT                                                                            0x10
13638 #define GDS_GWS_VMID0__BASE_MASK                                                                              0x0000003FL
13639 #define GDS_GWS_VMID0__SIZE_MASK                                                                              0x007F0000L
13640 //GDS_GWS_VMID1
13641 #define GDS_GWS_VMID1__BASE__SHIFT                                                                            0x0
13642 #define GDS_GWS_VMID1__SIZE__SHIFT                                                                            0x10
13643 #define GDS_GWS_VMID1__BASE_MASK                                                                              0x0000003FL
13644 #define GDS_GWS_VMID1__SIZE_MASK                                                                              0x007F0000L
13645 //GDS_GWS_VMID2
13646 #define GDS_GWS_VMID2__BASE__SHIFT                                                                            0x0
13647 #define GDS_GWS_VMID2__SIZE__SHIFT                                                                            0x10
13648 #define GDS_GWS_VMID2__BASE_MASK                                                                              0x0000003FL
13649 #define GDS_GWS_VMID2__SIZE_MASK                                                                              0x007F0000L
13650 //GDS_GWS_VMID3
13651 #define GDS_GWS_VMID3__BASE__SHIFT                                                                            0x0
13652 #define GDS_GWS_VMID3__SIZE__SHIFT                                                                            0x10
13653 #define GDS_GWS_VMID3__BASE_MASK                                                                              0x0000003FL
13654 #define GDS_GWS_VMID3__SIZE_MASK                                                                              0x007F0000L
13655 //GDS_GWS_VMID4
13656 #define GDS_GWS_VMID4__BASE__SHIFT                                                                            0x0
13657 #define GDS_GWS_VMID4__SIZE__SHIFT                                                                            0x10
13658 #define GDS_GWS_VMID4__BASE_MASK                                                                              0x0000003FL
13659 #define GDS_GWS_VMID4__SIZE_MASK                                                                              0x007F0000L
13660 //GDS_GWS_VMID5
13661 #define GDS_GWS_VMID5__BASE__SHIFT                                                                            0x0
13662 #define GDS_GWS_VMID5__SIZE__SHIFT                                                                            0x10
13663 #define GDS_GWS_VMID5__BASE_MASK                                                                              0x0000003FL
13664 #define GDS_GWS_VMID5__SIZE_MASK                                                                              0x007F0000L
13665 //GDS_GWS_VMID6
13666 #define GDS_GWS_VMID6__BASE__SHIFT                                                                            0x0
13667 #define GDS_GWS_VMID6__SIZE__SHIFT                                                                            0x10
13668 #define GDS_GWS_VMID6__BASE_MASK                                                                              0x0000003FL
13669 #define GDS_GWS_VMID6__SIZE_MASK                                                                              0x007F0000L
13670 //GDS_GWS_VMID7
13671 #define GDS_GWS_VMID7__BASE__SHIFT                                                                            0x0
13672 #define GDS_GWS_VMID7__SIZE__SHIFT                                                                            0x10
13673 #define GDS_GWS_VMID7__BASE_MASK                                                                              0x0000003FL
13674 #define GDS_GWS_VMID7__SIZE_MASK                                                                              0x007F0000L
13675 //GDS_GWS_VMID8
13676 #define GDS_GWS_VMID8__BASE__SHIFT                                                                            0x0
13677 #define GDS_GWS_VMID8__SIZE__SHIFT                                                                            0x10
13678 #define GDS_GWS_VMID8__BASE_MASK                                                                              0x0000003FL
13679 #define GDS_GWS_VMID8__SIZE_MASK                                                                              0x007F0000L
13680 //GDS_GWS_VMID9
13681 #define GDS_GWS_VMID9__BASE__SHIFT                                                                            0x0
13682 #define GDS_GWS_VMID9__SIZE__SHIFT                                                                            0x10
13683 #define GDS_GWS_VMID9__BASE_MASK                                                                              0x0000003FL
13684 #define GDS_GWS_VMID9__SIZE_MASK                                                                              0x007F0000L
13685 //GDS_GWS_VMID10
13686 #define GDS_GWS_VMID10__BASE__SHIFT                                                                           0x0
13687 #define GDS_GWS_VMID10__SIZE__SHIFT                                                                           0x10
13688 #define GDS_GWS_VMID10__BASE_MASK                                                                             0x0000003FL
13689 #define GDS_GWS_VMID10__SIZE_MASK                                                                             0x007F0000L
13690 //GDS_GWS_VMID11
13691 #define GDS_GWS_VMID11__BASE__SHIFT                                                                           0x0
13692 #define GDS_GWS_VMID11__SIZE__SHIFT                                                                           0x10
13693 #define GDS_GWS_VMID11__BASE_MASK                                                                             0x0000003FL
13694 #define GDS_GWS_VMID11__SIZE_MASK                                                                             0x007F0000L
13695 //GDS_GWS_VMID12
13696 #define GDS_GWS_VMID12__BASE__SHIFT                                                                           0x0
13697 #define GDS_GWS_VMID12__SIZE__SHIFT                                                                           0x10
13698 #define GDS_GWS_VMID12__BASE_MASK                                                                             0x0000003FL
13699 #define GDS_GWS_VMID12__SIZE_MASK                                                                             0x007F0000L
13700 //GDS_GWS_VMID13
13701 #define GDS_GWS_VMID13__BASE__SHIFT                                                                           0x0
13702 #define GDS_GWS_VMID13__SIZE__SHIFT                                                                           0x10
13703 #define GDS_GWS_VMID13__BASE_MASK                                                                             0x0000003FL
13704 #define GDS_GWS_VMID13__SIZE_MASK                                                                             0x007F0000L
13705 //GDS_GWS_VMID14
13706 #define GDS_GWS_VMID14__BASE__SHIFT                                                                           0x0
13707 #define GDS_GWS_VMID14__SIZE__SHIFT                                                                           0x10
13708 #define GDS_GWS_VMID14__BASE_MASK                                                                             0x0000003FL
13709 #define GDS_GWS_VMID14__SIZE_MASK                                                                             0x007F0000L
13710 //GDS_GWS_VMID15
13711 #define GDS_GWS_VMID15__BASE__SHIFT                                                                           0x0
13712 #define GDS_GWS_VMID15__SIZE__SHIFT                                                                           0x10
13713 #define GDS_GWS_VMID15__BASE_MASK                                                                             0x0000003FL
13714 #define GDS_GWS_VMID15__SIZE_MASK                                                                             0x007F0000L
13715 //GDS_OA_VMID0
13716 #define GDS_OA_VMID0__MASK__SHIFT                                                                             0x0
13717 #define GDS_OA_VMID0__UNUSED__SHIFT                                                                           0x10
13718 #define GDS_OA_VMID0__MASK_MASK                                                                               0x0000FFFFL
13719 #define GDS_OA_VMID0__UNUSED_MASK                                                                             0xFFFF0000L
13720 //GDS_OA_VMID1
13721 #define GDS_OA_VMID1__MASK__SHIFT                                                                             0x0
13722 #define GDS_OA_VMID1__UNUSED__SHIFT                                                                           0x10
13723 #define GDS_OA_VMID1__MASK_MASK                                                                               0x0000FFFFL
13724 #define GDS_OA_VMID1__UNUSED_MASK                                                                             0xFFFF0000L
13725 //GDS_OA_VMID2
13726 #define GDS_OA_VMID2__MASK__SHIFT                                                                             0x0
13727 #define GDS_OA_VMID2__UNUSED__SHIFT                                                                           0x10
13728 #define GDS_OA_VMID2__MASK_MASK                                                                               0x0000FFFFL
13729 #define GDS_OA_VMID2__UNUSED_MASK                                                                             0xFFFF0000L
13730 //GDS_OA_VMID3
13731 #define GDS_OA_VMID3__MASK__SHIFT                                                                             0x0
13732 #define GDS_OA_VMID3__UNUSED__SHIFT                                                                           0x10
13733 #define GDS_OA_VMID3__MASK_MASK                                                                               0x0000FFFFL
13734 #define GDS_OA_VMID3__UNUSED_MASK                                                                             0xFFFF0000L
13735 //GDS_OA_VMID4
13736 #define GDS_OA_VMID4__MASK__SHIFT                                                                             0x0
13737 #define GDS_OA_VMID4__UNUSED__SHIFT                                                                           0x10
13738 #define GDS_OA_VMID4__MASK_MASK                                                                               0x0000FFFFL
13739 #define GDS_OA_VMID4__UNUSED_MASK                                                                             0xFFFF0000L
13740 //GDS_OA_VMID5
13741 #define GDS_OA_VMID5__MASK__SHIFT                                                                             0x0
13742 #define GDS_OA_VMID5__UNUSED__SHIFT                                                                           0x10
13743 #define GDS_OA_VMID5__MASK_MASK                                                                               0x0000FFFFL
13744 #define GDS_OA_VMID5__UNUSED_MASK                                                                             0xFFFF0000L
13745 //GDS_OA_VMID6
13746 #define GDS_OA_VMID6__MASK__SHIFT                                                                             0x0
13747 #define GDS_OA_VMID6__UNUSED__SHIFT                                                                           0x10
13748 #define GDS_OA_VMID6__MASK_MASK                                                                               0x0000FFFFL
13749 #define GDS_OA_VMID6__UNUSED_MASK                                                                             0xFFFF0000L
13750 //GDS_OA_VMID7
13751 #define GDS_OA_VMID7__MASK__SHIFT                                                                             0x0
13752 #define GDS_OA_VMID7__UNUSED__SHIFT                                                                           0x10
13753 #define GDS_OA_VMID7__MASK_MASK                                                                               0x0000FFFFL
13754 #define GDS_OA_VMID7__UNUSED_MASK                                                                             0xFFFF0000L
13755 //GDS_OA_VMID8
13756 #define GDS_OA_VMID8__MASK__SHIFT                                                                             0x0
13757 #define GDS_OA_VMID8__UNUSED__SHIFT                                                                           0x10
13758 #define GDS_OA_VMID8__MASK_MASK                                                                               0x0000FFFFL
13759 #define GDS_OA_VMID8__UNUSED_MASK                                                                             0xFFFF0000L
13760 //GDS_OA_VMID9
13761 #define GDS_OA_VMID9__MASK__SHIFT                                                                             0x0
13762 #define GDS_OA_VMID9__UNUSED__SHIFT                                                                           0x10
13763 #define GDS_OA_VMID9__MASK_MASK                                                                               0x0000FFFFL
13764 #define GDS_OA_VMID9__UNUSED_MASK                                                                             0xFFFF0000L
13765 //GDS_OA_VMID10
13766 #define GDS_OA_VMID10__MASK__SHIFT                                                                            0x0
13767 #define GDS_OA_VMID10__UNUSED__SHIFT                                                                          0x10
13768 #define GDS_OA_VMID10__MASK_MASK                                                                              0x0000FFFFL
13769 #define GDS_OA_VMID10__UNUSED_MASK                                                                            0xFFFF0000L
13770 //GDS_OA_VMID11
13771 #define GDS_OA_VMID11__MASK__SHIFT                                                                            0x0
13772 #define GDS_OA_VMID11__UNUSED__SHIFT                                                                          0x10
13773 #define GDS_OA_VMID11__MASK_MASK                                                                              0x0000FFFFL
13774 #define GDS_OA_VMID11__UNUSED_MASK                                                                            0xFFFF0000L
13775 //GDS_OA_VMID12
13776 #define GDS_OA_VMID12__MASK__SHIFT                                                                            0x0
13777 #define GDS_OA_VMID12__UNUSED__SHIFT                                                                          0x10
13778 #define GDS_OA_VMID12__MASK_MASK                                                                              0x0000FFFFL
13779 #define GDS_OA_VMID12__UNUSED_MASK                                                                            0xFFFF0000L
13780 //GDS_OA_VMID13
13781 #define GDS_OA_VMID13__MASK__SHIFT                                                                            0x0
13782 #define GDS_OA_VMID13__UNUSED__SHIFT                                                                          0x10
13783 #define GDS_OA_VMID13__MASK_MASK                                                                              0x0000FFFFL
13784 #define GDS_OA_VMID13__UNUSED_MASK                                                                            0xFFFF0000L
13785 //GDS_OA_VMID14
13786 #define GDS_OA_VMID14__MASK__SHIFT                                                                            0x0
13787 #define GDS_OA_VMID14__UNUSED__SHIFT                                                                          0x10
13788 #define GDS_OA_VMID14__MASK_MASK                                                                              0x0000FFFFL
13789 #define GDS_OA_VMID14__UNUSED_MASK                                                                            0xFFFF0000L
13790 //GDS_OA_VMID15
13791 #define GDS_OA_VMID15__MASK__SHIFT                                                                            0x0
13792 #define GDS_OA_VMID15__UNUSED__SHIFT                                                                          0x10
13793 #define GDS_OA_VMID15__MASK_MASK                                                                              0x0000FFFFL
13794 #define GDS_OA_VMID15__UNUSED_MASK                                                                            0xFFFF0000L
13795 //GDS_GWS_RESET0
13796 #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT                                                                0x0
13797 #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT                                                                0x1
13798 #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT                                                                0x2
13799 #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT                                                                0x3
13800 #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT                                                                0x4
13801 #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT                                                                0x5
13802 #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT                                                                0x6
13803 #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT                                                                0x7
13804 #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT                                                                0x8
13805 #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT                                                                0x9
13806 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT                                                               0xa
13807 #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT                                                               0xb
13808 #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT                                                               0xc
13809 #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT                                                               0xd
13810 #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT                                                               0xe
13811 #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT                                                               0xf
13812 #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT                                                               0x10
13813 #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT                                                               0x11
13814 #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT                                                               0x12
13815 #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT                                                               0x13
13816 #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT                                                               0x14
13817 #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT                                                               0x15
13818 #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT                                                               0x16
13819 #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT                                                               0x17
13820 #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT                                                               0x18
13821 #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT                                                               0x19
13822 #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT                                                               0x1a
13823 #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT                                                               0x1b
13824 #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT                                                               0x1c
13825 #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT                                                               0x1d
13826 #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT                                                               0x1e
13827 #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT                                                               0x1f
13828 #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK                                                                  0x00000001L
13829 #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK                                                                  0x00000002L
13830 #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK                                                                  0x00000004L
13831 #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK                                                                  0x00000008L
13832 #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK                                                                  0x00000010L
13833 #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK                                                                  0x00000020L
13834 #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK                                                                  0x00000040L
13835 #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK                                                                  0x00000080L
13836 #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK                                                                  0x00000100L
13837 #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK                                                                  0x00000200L
13838 #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK                                                                 0x00000400L
13839 #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK                                                                 0x00000800L
13840 #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK                                                                 0x00001000L
13841 #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK                                                                 0x00002000L
13842 #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK                                                                 0x00004000L
13843 #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK                                                                 0x00008000L
13844 #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK                                                                 0x00010000L
13845 #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK                                                                 0x00020000L
13846 #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK                                                                 0x00040000L
13847 #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK                                                                 0x00080000L
13848 #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK                                                                 0x00100000L
13849 #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK                                                                 0x00200000L
13850 #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK                                                                 0x00400000L
13851 #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK                                                                 0x00800000L
13852 #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK                                                                 0x01000000L
13853 #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK                                                                 0x02000000L
13854 #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK                                                                 0x04000000L
13855 #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK                                                                 0x08000000L
13856 #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK                                                                 0x10000000L
13857 #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK                                                                 0x20000000L
13858 #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK                                                                 0x40000000L
13859 #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK                                                                 0x80000000L
13860 //GDS_GWS_RESET1
13861 #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT                                                               0x0
13862 #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT                                                               0x1
13863 #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT                                                               0x2
13864 #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT                                                               0x3
13865 #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT                                                               0x4
13866 #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT                                                               0x5
13867 #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT                                                               0x6
13868 #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT                                                               0x7
13869 #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT                                                               0x8
13870 #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT                                                               0x9
13871 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT                                                               0xa
13872 #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT                                                               0xb
13873 #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT                                                               0xc
13874 #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT                                                               0xd
13875 #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT                                                               0xe
13876 #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT                                                               0xf
13877 #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT                                                               0x10
13878 #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT                                                               0x11
13879 #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT                                                               0x12
13880 #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT                                                               0x13
13881 #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT                                                               0x14
13882 #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT                                                               0x15
13883 #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT                                                               0x16
13884 #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT                                                               0x17
13885 #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT                                                               0x18
13886 #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT                                                               0x19
13887 #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT                                                               0x1a
13888 #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT                                                               0x1b
13889 #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT                                                               0x1c
13890 #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT                                                               0x1d
13891 #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT                                                               0x1e
13892 #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT                                                               0x1f
13893 #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK                                                                 0x00000001L
13894 #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK                                                                 0x00000002L
13895 #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK                                                                 0x00000004L
13896 #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK                                                                 0x00000008L
13897 #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK                                                                 0x00000010L
13898 #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK                                                                 0x00000020L
13899 #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK                                                                 0x00000040L
13900 #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK                                                                 0x00000080L
13901 #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK                                                                 0x00000100L
13902 #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK                                                                 0x00000200L
13903 #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK                                                                 0x00000400L
13904 #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK                                                                 0x00000800L
13905 #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK                                                                 0x00001000L
13906 #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK                                                                 0x00002000L
13907 #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK                                                                 0x00004000L
13908 #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK                                                                 0x00008000L
13909 #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK                                                                 0x00010000L
13910 #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK                                                                 0x00020000L
13911 #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK                                                                 0x00040000L
13912 #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK                                                                 0x00080000L
13913 #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK                                                                 0x00100000L
13914 #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK                                                                 0x00200000L
13915 #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK                                                                 0x00400000L
13916 #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK                                                                 0x00800000L
13917 #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK                                                                 0x01000000L
13918 #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK                                                                 0x02000000L
13919 #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK                                                                 0x04000000L
13920 #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK                                                                 0x08000000L
13921 #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK                                                                 0x10000000L
13922 #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK                                                                 0x20000000L
13923 #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK                                                                 0x40000000L
13924 #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK                                                                 0x80000000L
13925 //GDS_GWS_RESOURCE_RESET
13926 #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT                                                                  0x0
13927 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT                                                            0x8
13928 #define GDS_GWS_RESOURCE_RESET__RESET_MASK                                                                    0x00000001L
13929 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK                                                              0x0000FF00L
13930 //GDS_COMPUTE_MAX_WAVE_ID
13931 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                           0x0
13932 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                             0x00000FFFL
13933 //GDS_OA_RESET_MASK
13934 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT                                                       0x0
13935 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT                                                       0x1
13936 #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT                                                                0x2
13937 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT                                                        0x3
13938 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT                                                             0x4
13939 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT                                                             0x5
13940 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT                                                             0x6
13941 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT                                                             0x7
13942 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT                                                             0x8
13943 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT                                                             0x9
13944 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT                                                             0xa
13945 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT                                                             0xb
13946 #define GDS_OA_RESET_MASK__UNUSED1__SHIFT                                                                     0xc
13947 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK                                                         0x00000001L
13948 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK                                                         0x00000002L
13949 #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK                                                                  0x00000004L
13950 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK                                                          0x00000008L
13951 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK                                                               0x00000010L
13952 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK                                                               0x00000020L
13953 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK                                                               0x00000040L
13954 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK                                                               0x00000080L
13955 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK                                                               0x00000100L
13956 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK                                                               0x00000200L
13957 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK                                                               0x00000400L
13958 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK                                                               0x00000800L
13959 #define GDS_OA_RESET_MASK__UNUSED1_MASK                                                                       0xFFFFF000L
13960 //GDS_OA_RESET
13961 #define GDS_OA_RESET__RESET__SHIFT                                                                            0x0
13962 #define GDS_OA_RESET__PIPE_ID__SHIFT                                                                          0x8
13963 #define GDS_OA_RESET__RESET_MASK                                                                              0x00000001L
13964 #define GDS_OA_RESET__PIPE_ID_MASK                                                                            0x0000FF00L
13965 //GDS_ENHANCE
13966 #define GDS_ENHANCE__MISC__SHIFT                                                                              0x0
13967 #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT                                                                    0x10
13968 #define GDS_ENHANCE__CGPG_RESTORE__SHIFT                                                                      0x11
13969 #define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT                                                                   0x12
13970 #define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT                                                                  0x13
13971 #define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT                                                                  0x14
13972 #define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT                                                               0x15
13973 #define GDS_ENHANCE__UNUSED__SHIFT                                                                            0x16
13974 #define GDS_ENHANCE__MISC_MASK                                                                                0x0000FFFFL
13975 #define GDS_ENHANCE__AUTO_INC_INDEX_MASK                                                                      0x00010000L
13976 #define GDS_ENHANCE__CGPG_RESTORE_MASK                                                                        0x00020000L
13977 #define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK                                                                     0x00040000L
13978 #define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK                                                                    0x00080000L
13979 #define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK                                                                    0x00100000L
13980 #define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK                                                                 0x00200000L
13981 #define GDS_ENHANCE__UNUSED_MASK                                                                              0xFFC00000L
13982 //GDS_OA_CGPG_RESTORE
13983 #define GDS_OA_CGPG_RESTORE__VMID__SHIFT                                                                      0x0
13984 #define GDS_OA_CGPG_RESTORE__MEID__SHIFT                                                                      0x8
13985 #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT                                                                    0xc
13986 #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT                                                                   0x10
13987 #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT                                                                    0x14
13988 #define GDS_OA_CGPG_RESTORE__VMID_MASK                                                                        0x000000FFL
13989 #define GDS_OA_CGPG_RESTORE__MEID_MASK                                                                        0x00000F00L
13990 #define GDS_OA_CGPG_RESTORE__PIPEID_MASK                                                                      0x0000F000L
13991 #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK                                                                     0x000F0000L
13992 #define GDS_OA_CGPG_RESTORE__UNUSED_MASK                                                                      0xFFF00000L
13993 //GDS_CS_CTXSW_STATUS
13994 #define GDS_CS_CTXSW_STATUS__R__SHIFT                                                                         0x0
13995 #define GDS_CS_CTXSW_STATUS__W__SHIFT                                                                         0x1
13996 #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT                                                                    0x2
13997 #define GDS_CS_CTXSW_STATUS__R_MASK                                                                           0x00000001L
13998 #define GDS_CS_CTXSW_STATUS__W_MASK                                                                           0x00000002L
13999 #define GDS_CS_CTXSW_STATUS__UNUSED_MASK                                                                      0xFFFFFFFCL
14000 //GDS_CS_CTXSW_CNT0
14001 #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
14002 #define GDS_CS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
14003 #define GDS_CS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
14004 #define GDS_CS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
14005 //GDS_CS_CTXSW_CNT1
14006 #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
14007 #define GDS_CS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
14008 #define GDS_CS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
14009 #define GDS_CS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
14010 //GDS_CS_CTXSW_CNT2
14011 #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
14012 #define GDS_CS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
14013 #define GDS_CS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
14014 #define GDS_CS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
14015 //GDS_CS_CTXSW_CNT3
14016 #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
14017 #define GDS_CS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
14018 #define GDS_CS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
14019 #define GDS_CS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
14020 //GDS_GFX_CTXSW_STATUS
14021 #define GDS_GFX_CTXSW_STATUS__R__SHIFT                                                                        0x0
14022 #define GDS_GFX_CTXSW_STATUS__W__SHIFT                                                                        0x1
14023 #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT                                                                   0x2
14024 #define GDS_GFX_CTXSW_STATUS__R_MASK                                                                          0x00000001L
14025 #define GDS_GFX_CTXSW_STATUS__W_MASK                                                                          0x00000002L
14026 #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK                                                                     0xFFFFFFFCL
14027 //GDS_VS_CTXSW_CNT0
14028 #define GDS_VS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
14029 #define GDS_VS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
14030 #define GDS_VS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
14031 #define GDS_VS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
14032 //GDS_VS_CTXSW_CNT1
14033 #define GDS_VS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
14034 #define GDS_VS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
14035 #define GDS_VS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
14036 #define GDS_VS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
14037 //GDS_VS_CTXSW_CNT2
14038 #define GDS_VS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
14039 #define GDS_VS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
14040 #define GDS_VS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
14041 #define GDS_VS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
14042 //GDS_VS_CTXSW_CNT3
14043 #define GDS_VS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
14044 #define GDS_VS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
14045 #define GDS_VS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
14046 #define GDS_VS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
14047 //GDS_PS0_CTXSW_CNT0
14048 #define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14049 #define GDS_PS0_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14050 #define GDS_PS0_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14051 #define GDS_PS0_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14052 //GDS_PS0_CTXSW_CNT1
14053 #define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14054 #define GDS_PS0_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14055 #define GDS_PS0_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14056 #define GDS_PS0_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14057 //GDS_PS0_CTXSW_CNT2
14058 #define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14059 #define GDS_PS0_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14060 #define GDS_PS0_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14061 #define GDS_PS0_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14062 //GDS_PS0_CTXSW_CNT3
14063 #define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14064 #define GDS_PS0_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14065 #define GDS_PS0_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14066 #define GDS_PS0_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14067 //GDS_PS1_CTXSW_CNT0
14068 #define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14069 #define GDS_PS1_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14070 #define GDS_PS1_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14071 #define GDS_PS1_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14072 //GDS_PS1_CTXSW_CNT1
14073 #define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14074 #define GDS_PS1_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14075 #define GDS_PS1_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14076 #define GDS_PS1_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14077 //GDS_PS1_CTXSW_CNT2
14078 #define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14079 #define GDS_PS1_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14080 #define GDS_PS1_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14081 #define GDS_PS1_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14082 //GDS_PS1_CTXSW_CNT3
14083 #define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14084 #define GDS_PS1_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14085 #define GDS_PS1_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14086 #define GDS_PS1_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14087 //GDS_PS2_CTXSW_CNT0
14088 #define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14089 #define GDS_PS2_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14090 #define GDS_PS2_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14091 #define GDS_PS2_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14092 //GDS_PS2_CTXSW_CNT1
14093 #define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14094 #define GDS_PS2_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14095 #define GDS_PS2_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14096 #define GDS_PS2_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14097 //GDS_PS2_CTXSW_CNT2
14098 #define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14099 #define GDS_PS2_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14100 #define GDS_PS2_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14101 #define GDS_PS2_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14102 //GDS_PS2_CTXSW_CNT3
14103 #define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14104 #define GDS_PS2_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14105 #define GDS_PS2_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14106 #define GDS_PS2_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14107 //GDS_PS3_CTXSW_CNT0
14108 #define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14109 #define GDS_PS3_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14110 #define GDS_PS3_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14111 #define GDS_PS3_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14112 //GDS_PS3_CTXSW_CNT1
14113 #define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14114 #define GDS_PS3_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14115 #define GDS_PS3_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14116 #define GDS_PS3_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14117 //GDS_PS3_CTXSW_CNT2
14118 #define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14119 #define GDS_PS3_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14120 #define GDS_PS3_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14121 #define GDS_PS3_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14122 //GDS_PS3_CTXSW_CNT3
14123 #define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14124 #define GDS_PS3_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14125 #define GDS_PS3_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14126 #define GDS_PS3_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14127 //GDS_PS4_CTXSW_CNT0
14128 #define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14129 #define GDS_PS4_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14130 #define GDS_PS4_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14131 #define GDS_PS4_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14132 //GDS_PS4_CTXSW_CNT1
14133 #define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14134 #define GDS_PS4_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14135 #define GDS_PS4_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14136 #define GDS_PS4_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14137 //GDS_PS4_CTXSW_CNT2
14138 #define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14139 #define GDS_PS4_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14140 #define GDS_PS4_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14141 #define GDS_PS4_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14142 //GDS_PS4_CTXSW_CNT3
14143 #define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14144 #define GDS_PS4_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14145 #define GDS_PS4_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14146 #define GDS_PS4_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14147 //GDS_PS5_CTXSW_CNT0
14148 #define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14149 #define GDS_PS5_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14150 #define GDS_PS5_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14151 #define GDS_PS5_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14152 //GDS_PS5_CTXSW_CNT1
14153 #define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14154 #define GDS_PS5_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14155 #define GDS_PS5_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14156 #define GDS_PS5_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14157 //GDS_PS5_CTXSW_CNT2
14158 #define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14159 #define GDS_PS5_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14160 #define GDS_PS5_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14161 #define GDS_PS5_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14162 //GDS_PS5_CTXSW_CNT3
14163 #define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14164 #define GDS_PS5_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14165 #define GDS_PS5_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14166 #define GDS_PS5_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14167 //GDS_PS6_CTXSW_CNT0
14168 #define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14169 #define GDS_PS6_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14170 #define GDS_PS6_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14171 #define GDS_PS6_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14172 //GDS_PS6_CTXSW_CNT1
14173 #define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14174 #define GDS_PS6_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14175 #define GDS_PS6_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14176 #define GDS_PS6_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14177 //GDS_PS6_CTXSW_CNT2
14178 #define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14179 #define GDS_PS6_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14180 #define GDS_PS6_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14181 #define GDS_PS6_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14182 //GDS_PS6_CTXSW_CNT3
14183 #define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14184 #define GDS_PS6_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14185 #define GDS_PS6_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14186 #define GDS_PS6_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14187 //GDS_PS7_CTXSW_CNT0
14188 #define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14189 #define GDS_PS7_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14190 #define GDS_PS7_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14191 #define GDS_PS7_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14192 //GDS_PS7_CTXSW_CNT1
14193 #define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14194 #define GDS_PS7_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14195 #define GDS_PS7_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14196 #define GDS_PS7_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14197 //GDS_PS7_CTXSW_CNT2
14198 #define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14199 #define GDS_PS7_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14200 #define GDS_PS7_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14201 #define GDS_PS7_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14202 //GDS_PS7_CTXSW_CNT3
14203 #define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14204 #define GDS_PS7_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14205 #define GDS_PS7_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14206 #define GDS_PS7_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14207 //GDS_GS_CTXSW_CNT0
14208 #define GDS_GS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
14209 #define GDS_GS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
14210 #define GDS_GS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
14211 #define GDS_GS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
14212 //GDS_GS_CTXSW_CNT1
14213 #define GDS_GS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
14214 #define GDS_GS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
14215 #define GDS_GS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
14216 #define GDS_GS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
14217 //GDS_GS_CTXSW_CNT2
14218 #define GDS_GS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
14219 #define GDS_GS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
14220 #define GDS_GS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
14221 #define GDS_GS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
14222 //GDS_GS_CTXSW_CNT3
14223 #define GDS_GS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
14224 #define GDS_GS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
14225 #define GDS_GS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
14226 #define GDS_GS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
14227 
14228 
14229 // addressBlock: gc_rasdec
14230 //RAS_SIGNATURE_CONTROL
14231 #define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT                                                                  0x0
14232 #define RAS_SIGNATURE_CONTROL__ENABLE_MASK                                                                    0x00000001L
14233 //RAS_SIGNATURE_MASK
14234 #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT                                                             0x0
14235 #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK                                                               0xFFFFFFFFL
14236 //RAS_SX_SIGNATURE0
14237 #define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14238 #define RAS_SX_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14239 //RAS_SX_SIGNATURE1
14240 #define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
14241 #define RAS_SX_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14242 //RAS_SX_SIGNATURE2
14243 #define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT                                                                   0x0
14244 #define RAS_SX_SIGNATURE2__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14245 //RAS_SX_SIGNATURE3
14246 #define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT                                                                   0x0
14247 #define RAS_SX_SIGNATURE3__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14248 //RAS_DB_SIGNATURE0
14249 #define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14250 #define RAS_DB_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14251 //RAS_PA_SIGNATURE0
14252 #define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14253 #define RAS_PA_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14254 //RAS_VGT_SIGNATURE0
14255 #define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT                                                                  0x0
14256 #define RAS_VGT_SIGNATURE0__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14257 //RAS_SQ_SIGNATURE0
14258 #define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14259 #define RAS_SQ_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14260 //RAS_SC_SIGNATURE0
14261 #define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14262 #define RAS_SC_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14263 //RAS_SC_SIGNATURE1
14264 #define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
14265 #define RAS_SC_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14266 //RAS_SC_SIGNATURE2
14267 #define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT                                                                   0x0
14268 #define RAS_SC_SIGNATURE2__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14269 //RAS_SC_SIGNATURE3
14270 #define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT                                                                   0x0
14271 #define RAS_SC_SIGNATURE3__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14272 //RAS_SC_SIGNATURE4
14273 #define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT                                                                   0x0
14274 #define RAS_SC_SIGNATURE4__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14275 //RAS_SC_SIGNATURE5
14276 #define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT                                                                   0x0
14277 #define RAS_SC_SIGNATURE5__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14278 //RAS_SC_SIGNATURE6
14279 #define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT                                                                   0x0
14280 #define RAS_SC_SIGNATURE6__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14281 //RAS_SC_SIGNATURE7
14282 #define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT                                                                   0x0
14283 #define RAS_SC_SIGNATURE7__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14284 //RAS_IA_SIGNATURE0
14285 #define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14286 #define RAS_IA_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14287 //RAS_IA_SIGNATURE1
14288 #define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
14289 #define RAS_IA_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14290 //RAS_SPI_SIGNATURE0
14291 #define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT                                                                  0x0
14292 #define RAS_SPI_SIGNATURE0__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14293 //RAS_SPI_SIGNATURE1
14294 #define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT                                                                  0x0
14295 #define RAS_SPI_SIGNATURE1__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14296 //RAS_TA_SIGNATURE0
14297 #define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14298 #define RAS_TA_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14299 //RAS_TD_SIGNATURE0
14300 #define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14301 #define RAS_TD_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14302 //RAS_CB_SIGNATURE0
14303 #define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14304 #define RAS_CB_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14305 //RAS_BCI_SIGNATURE0
14306 #define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT                                                                  0x0
14307 #define RAS_BCI_SIGNATURE0__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14308 //RAS_BCI_SIGNATURE1
14309 #define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT                                                                  0x0
14310 #define RAS_BCI_SIGNATURE1__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14311 //RAS_TA_SIGNATURE1
14312 #define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
14313 #define RAS_TA_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14314 
14315 
14316 // addressBlock: gc_gfxdec0
14317 //DB_RENDER_CONTROL
14318 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT                                                          0x0
14319 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT                                                        0x1
14320 #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT                                                                  0x2
14321 #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT                                                                0x3
14322 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT                                                          0x4
14323 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT                                                    0x5
14324 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT                                                      0x6
14325 #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT                                                               0x7
14326 #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT                                                                 0x8
14327 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT                                                           0xc
14328 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK                                                            0x00000001L
14329 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK                                                          0x00000002L
14330 #define DB_RENDER_CONTROL__DEPTH_COPY_MASK                                                                    0x00000004L
14331 #define DB_RENDER_CONTROL__STENCIL_COPY_MASK                                                                  0x00000008L
14332 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK                                                            0x00000010L
14333 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK                                                      0x00000020L
14334 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK                                                        0x00000040L
14335 #define DB_RENDER_CONTROL__COPY_CENTROID_MASK                                                                 0x00000080L
14336 #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK                                                                   0x00000F00L
14337 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK                                                             0x00001000L
14338 //DB_COUNT_CONTROL
14339 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT                                                      0x0
14340 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT                                                         0x1
14341 #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT                                                                  0x4
14342 #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT                                                                 0x8
14343 #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT                                                                 0xc
14344 #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT                                                                 0x10
14345 #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT                                                                0x14
14346 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                            0x18
14347 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                             0x1c
14348 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK                                                        0x00000001L
14349 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK                                                           0x00000002L
14350 #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK                                                                    0x00000070L
14351 #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK                                                                   0x00000F00L
14352 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK                                                                   0x0000F000L
14353 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK                                                                   0x000F0000L
14354 #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK                                                                  0x00F00000L
14355 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                              0x0F000000L
14356 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK                                                               0xF0000000L
14357 //DB_DEPTH_VIEW
14358 #define DB_DEPTH_VIEW__SLICE_START__SHIFT                                                                     0x0
14359 #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT                                                                       0xd
14360 #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT                                                                     0x18
14361 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT                                                               0x19
14362 #define DB_DEPTH_VIEW__MIPID__SHIFT                                                                           0x1a
14363 #define DB_DEPTH_VIEW__SLICE_START_MASK                                                                       0x000007FFL
14364 #define DB_DEPTH_VIEW__SLICE_MAX_MASK                                                                         0x00FFE000L
14365 #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK                                                                       0x01000000L
14366 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK                                                                 0x02000000L
14367 #define DB_DEPTH_VIEW__MIPID_MASK                                                                             0x3C000000L
14368 //DB_RENDER_OVERRIDE
14369 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT                                                           0x0
14370 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT                                                          0x2
14371 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT                                                          0x4
14372 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT                                                       0x6
14373 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT                                                             0x7
14374 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT                                                       0x8
14375 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT                                                          0x9
14376 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT                                                           0xa
14377 #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT                                                               0xb
14378 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT                                                         0xc
14379 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT                                                         0xd
14380 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT                                                    0xf
14381 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT                                                     0x10
14382 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT                                                           0x11
14383 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT                                                      0x12
14384 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT                                                         0x13
14385 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT                                                           0x15
14386 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT                                                    0x1a
14387 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT                                                              0x1b
14388 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT                                                        0x1c
14389 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT                                                              0x1d
14390 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT                                                        0x1e
14391 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT                                                       0x1f
14392 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK                                                             0x00000003L
14393 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK                                                            0x0000000CL
14394 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK                                                            0x00000030L
14395 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK                                                         0x00000040L
14396 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK                                                               0x00000080L
14397 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK                                                         0x00000100L
14398 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK                                                            0x00000200L
14399 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK                                                             0x00000400L
14400 #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK                                                                 0x00000800L
14401 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK                                                           0x00001000L
14402 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK                                                           0x00006000L
14403 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK                                                      0x00008000L
14404 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK                                                       0x00010000L
14405 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK                                                             0x00020000L
14406 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK                                                        0x00040000L
14407 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK                                                           0x00180000L
14408 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK                                                             0x03E00000L
14409 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK                                                      0x04000000L
14410 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK                                                                0x08000000L
14411 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK                                                          0x10000000L
14412 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK                                                                0x20000000L
14413 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK                                                          0x40000000L
14414 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK                                                         0x80000000L
14415 //DB_RENDER_OVERRIDE2
14416 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT                                              0x0
14417 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT                                            0x2
14418 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT                                       0x5
14419 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT                                        0x6
14420 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT                                               0x7
14421 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT                                                     0x8
14422 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT                                                         0x9
14423 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT                                           0xa
14424 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT                                                 0xb
14425 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT                                                                 0xc
14426 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT                                                              0xf
14427 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT                                                              0x12
14428 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT                                                           0x15
14429 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT                                                         0x16
14430 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT                                                         0x17
14431 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT                                               0x19
14432 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK                                                0x00000003L
14433 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK                                              0x0000001CL
14434 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK                                         0x00000020L
14435 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK                                          0x00000040L
14436 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK                                                 0x00000080L
14437 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK                                                       0x00000100L
14438 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK                                                           0x00000200L
14439 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK                                             0x00000400L
14440 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK                                                   0x00000800L
14441 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK                                                                   0x00007000L
14442 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK                                                                0x00038000L
14443 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK                                                                0x001C0000L
14444 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK                                                             0x00200000L
14445 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK                                                           0x00400000L
14446 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK                                                           0x00800000L
14447 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK                                                 0x02000000L
14448 //DB_HTILE_DATA_BASE
14449 #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT                                                                  0x0
14450 #define DB_HTILE_DATA_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
14451 //DB_HTILE_DATA_BASE_HI
14452 #define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT                                                                 0x0
14453 #define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
14454 //DB_DEPTH_SIZE
14455 #define DB_DEPTH_SIZE__X_MAX__SHIFT                                                                           0x0
14456 #define DB_DEPTH_SIZE__Y_MAX__SHIFT                                                                           0x10
14457 #define DB_DEPTH_SIZE__X_MAX_MASK                                                                             0x00003FFFL
14458 #define DB_DEPTH_SIZE__Y_MAX_MASK                                                                             0x3FFF0000L
14459 //DB_DEPTH_BOUNDS_MIN
14460 #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT                                                                       0x0
14461 #define DB_DEPTH_BOUNDS_MIN__MIN_MASK                                                                         0xFFFFFFFFL
14462 //DB_DEPTH_BOUNDS_MAX
14463 #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT                                                                       0x0
14464 #define DB_DEPTH_BOUNDS_MAX__MAX_MASK                                                                         0xFFFFFFFFL
14465 //DB_STENCIL_CLEAR
14466 #define DB_STENCIL_CLEAR__CLEAR__SHIFT                                                                        0x0
14467 #define DB_STENCIL_CLEAR__CLEAR_MASK                                                                          0x000000FFL
14468 //DB_DEPTH_CLEAR
14469 #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                                                                    0x0
14470 #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                                                                      0xFFFFFFFFL
14471 //PA_SC_SCREEN_SCISSOR_TL
14472 #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
14473 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
14474 #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                                                                    0x0000FFFFL
14475 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                                                                    0xFFFF0000L
14476 //PA_SC_SCREEN_SCISSOR_BR
14477 #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
14478 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
14479 #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                                                                    0x0000FFFFL
14480 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                                                                    0xFFFF0000L
14481 //DB_Z_INFO
14482 #define DB_Z_INFO__FORMAT__SHIFT                                                                              0x0
14483 #define DB_Z_INFO__NUM_SAMPLES__SHIFT                                                                         0x2
14484 #define DB_Z_INFO__SW_MODE__SHIFT                                                                             0x4
14485 #define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT                                                                  0xc
14486 #define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT                                                                      0xd
14487 #define DB_Z_INFO__ITERATE_FLUSH__SHIFT                                                                       0xf
14488 #define DB_Z_INFO__MAXMIP__SHIFT                                                                              0x10
14489 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT                                                             0x17
14490 #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT                                                                      0x1b
14491 #define DB_Z_INFO__READ_SIZE__SHIFT                                                                           0x1c
14492 #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT                                                                 0x1d
14493 #define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT                                                                    0x1e
14494 #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT                                                                    0x1f
14495 #define DB_Z_INFO__FORMAT_MASK                                                                                0x00000003L
14496 #define DB_Z_INFO__NUM_SAMPLES_MASK                                                                           0x0000000CL
14497 #define DB_Z_INFO__SW_MODE_MASK                                                                               0x000001F0L
14498 #define DB_Z_INFO__PARTIALLY_RESIDENT_MASK                                                                    0x00001000L
14499 #define DB_Z_INFO__FAULT_BEHAVIOR_MASK                                                                        0x00006000L
14500 #define DB_Z_INFO__ITERATE_FLUSH_MASK                                                                         0x00008000L
14501 #define DB_Z_INFO__MAXMIP_MASK                                                                                0x000F0000L
14502 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK                                                               0x07800000L
14503 #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK                                                                        0x08000000L
14504 #define DB_Z_INFO__READ_SIZE_MASK                                                                             0x10000000L
14505 #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK                                                                   0x20000000L
14506 #define DB_Z_INFO__CLEAR_DISALLOWED_MASK                                                                      0x40000000L
14507 #define DB_Z_INFO__ZRANGE_PRECISION_MASK                                                                      0x80000000L
14508 //DB_STENCIL_INFO
14509 #define DB_STENCIL_INFO__FORMAT__SHIFT                                                                        0x0
14510 #define DB_STENCIL_INFO__SW_MODE__SHIFT                                                                       0x4
14511 #define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT                                                            0xc
14512 #define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT                                                                0xd
14513 #define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT                                                                 0xf
14514 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT                                                                0x1b
14515 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT                                                          0x1d
14516 #define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT                                                              0x1e
14517 #define DB_STENCIL_INFO__FORMAT_MASK                                                                          0x00000001L
14518 #define DB_STENCIL_INFO__SW_MODE_MASK                                                                         0x000001F0L
14519 #define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK                                                              0x00001000L
14520 #define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK                                                                  0x00006000L
14521 #define DB_STENCIL_INFO__ITERATE_FLUSH_MASK                                                                   0x00008000L
14522 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK                                                                  0x08000000L
14523 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK                                                            0x20000000L
14524 #define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK                                                                0x40000000L
14525 //DB_Z_READ_BASE
14526 #define DB_Z_READ_BASE__BASE_256B__SHIFT                                                                      0x0
14527 #define DB_Z_READ_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
14528 //DB_Z_READ_BASE_HI
14529 #define DB_Z_READ_BASE_HI__BASE_HI__SHIFT                                                                     0x0
14530 #define DB_Z_READ_BASE_HI__BASE_HI_MASK                                                                       0x000000FFL
14531 //DB_STENCIL_READ_BASE
14532 #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT                                                                0x0
14533 #define DB_STENCIL_READ_BASE__BASE_256B_MASK                                                                  0xFFFFFFFFL
14534 //DB_STENCIL_READ_BASE_HI
14535 #define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT                                                               0x0
14536 #define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK                                                                 0x000000FFL
14537 //DB_Z_WRITE_BASE
14538 #define DB_Z_WRITE_BASE__BASE_256B__SHIFT                                                                     0x0
14539 #define DB_Z_WRITE_BASE__BASE_256B_MASK                                                                       0xFFFFFFFFL
14540 //DB_Z_WRITE_BASE_HI
14541 #define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT                                                                    0x0
14542 #define DB_Z_WRITE_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
14543 //DB_STENCIL_WRITE_BASE
14544 #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT                                                               0x0
14545 #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK                                                                 0xFFFFFFFFL
14546 //DB_STENCIL_WRITE_BASE_HI
14547 #define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT                                                              0x0
14548 #define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK                                                                0x000000FFL
14549 //DB_DFSM_CONTROL
14550 #define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT                                                                 0x0
14551 #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT                                                      0x2
14552 #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT                                                             0x3
14553 #define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK                                                                   0x00000003L
14554 #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK                                                        0x00000004L
14555 #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK                                                               0x00000008L
14556 //DB_Z_INFO2
14557 #define DB_Z_INFO2__EPITCH__SHIFT                                                                             0x0
14558 #define DB_Z_INFO2__EPITCH_MASK                                                                               0x0000FFFFL
14559 //DB_STENCIL_INFO2
14560 #define DB_STENCIL_INFO2__EPITCH__SHIFT                                                                       0x0
14561 #define DB_STENCIL_INFO2__EPITCH_MASK                                                                         0x0000FFFFL
14562 //TA_BC_BASE_ADDR
14563 #define TA_BC_BASE_ADDR__ADDRESS__SHIFT                                                                       0x0
14564 #define TA_BC_BASE_ADDR__ADDRESS_MASK                                                                         0xFFFFFFFFL
14565 //TA_BC_BASE_ADDR_HI
14566 #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT                                                                    0x0
14567 #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK                                                                      0x000000FFL
14568 //COHER_DEST_BASE_HI_0
14569 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT                                                        0x0
14570 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
14571 //COHER_DEST_BASE_HI_1
14572 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT                                                        0x0
14573 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
14574 //COHER_DEST_BASE_HI_2
14575 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT                                                        0x0
14576 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
14577 //COHER_DEST_BASE_HI_3
14578 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT                                                        0x0
14579 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
14580 //COHER_DEST_BASE_2
14581 #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT                                                              0x0
14582 #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
14583 //COHER_DEST_BASE_3
14584 #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT                                                              0x0
14585 #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
14586 //PA_SC_WINDOW_OFFSET
14587 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT                                                           0x0
14588 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT                                                           0x10
14589 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK                                                             0x0000FFFFL
14590 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK                                                             0xFFFF0000L
14591 //PA_SC_WINDOW_SCISSOR_TL
14592 #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
14593 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
14594 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                 0x1f
14595 #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                                                                    0x00007FFFL
14596 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                                                                    0x7FFF0000L
14597 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                   0x80000000L
14598 //PA_SC_WINDOW_SCISSOR_BR
14599 #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
14600 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
14601 #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                                                                    0x00007FFFL
14602 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                                                                    0x7FFF0000L
14603 //PA_SC_CLIPRECT_RULE
14604 #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT                                                                 0x0
14605 #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK                                                                   0x0000FFFFL
14606 //PA_SC_CLIPRECT_0_TL
14607 #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT                                                                      0x0
14608 #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT                                                                      0x10
14609 #define PA_SC_CLIPRECT_0_TL__TL_X_MASK                                                                        0x00007FFFL
14610 #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK                                                                        0x7FFF0000L
14611 //PA_SC_CLIPRECT_0_BR
14612 #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT                                                                      0x0
14613 #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT                                                                      0x10
14614 #define PA_SC_CLIPRECT_0_BR__BR_X_MASK                                                                        0x00007FFFL
14615 #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK                                                                        0x7FFF0000L
14616 //PA_SC_CLIPRECT_1_TL
14617 #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT                                                                      0x0
14618 #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT                                                                      0x10
14619 #define PA_SC_CLIPRECT_1_TL__TL_X_MASK                                                                        0x00007FFFL
14620 #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK                                                                        0x7FFF0000L
14621 //PA_SC_CLIPRECT_1_BR
14622 #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT                                                                      0x0
14623 #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT                                                                      0x10
14624 #define PA_SC_CLIPRECT_1_BR__BR_X_MASK                                                                        0x00007FFFL
14625 #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK                                                                        0x7FFF0000L
14626 //PA_SC_CLIPRECT_2_TL
14627 #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT                                                                      0x0
14628 #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT                                                                      0x10
14629 #define PA_SC_CLIPRECT_2_TL__TL_X_MASK                                                                        0x00007FFFL
14630 #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK                                                                        0x7FFF0000L
14631 //PA_SC_CLIPRECT_2_BR
14632 #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT                                                                      0x0
14633 #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT                                                                      0x10
14634 #define PA_SC_CLIPRECT_2_BR__BR_X_MASK                                                                        0x00007FFFL
14635 #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK                                                                        0x7FFF0000L
14636 //PA_SC_CLIPRECT_3_TL
14637 #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT                                                                      0x0
14638 #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT                                                                      0x10
14639 #define PA_SC_CLIPRECT_3_TL__TL_X_MASK                                                                        0x00007FFFL
14640 #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK                                                                        0x7FFF0000L
14641 //PA_SC_CLIPRECT_3_BR
14642 #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT                                                                      0x0
14643 #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT                                                                      0x10
14644 #define PA_SC_CLIPRECT_3_BR__BR_X_MASK                                                                        0x00007FFFL
14645 #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK                                                                        0x7FFF0000L
14646 //PA_SC_EDGERULE
14647 #define PA_SC_EDGERULE__ER_TRI__SHIFT                                                                         0x0
14648 #define PA_SC_EDGERULE__ER_POINT__SHIFT                                                                       0x4
14649 #define PA_SC_EDGERULE__ER_RECT__SHIFT                                                                        0x8
14650 #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT                                                                     0xc
14651 #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT                                                                     0x12
14652 #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT                                                                     0x18
14653 #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT                                                                     0x1c
14654 #define PA_SC_EDGERULE__ER_TRI_MASK                                                                           0x0000000FL
14655 #define PA_SC_EDGERULE__ER_POINT_MASK                                                                         0x000000F0L
14656 #define PA_SC_EDGERULE__ER_RECT_MASK                                                                          0x00000F00L
14657 #define PA_SC_EDGERULE__ER_LINE_LR_MASK                                                                       0x0003F000L
14658 #define PA_SC_EDGERULE__ER_LINE_RL_MASK                                                                       0x00FC0000L
14659 #define PA_SC_EDGERULE__ER_LINE_TB_MASK                                                                       0x0F000000L
14660 #define PA_SC_EDGERULE__ER_LINE_BT_MASK                                                                       0xF0000000L
14661 //PA_SU_HARDWARE_SCREEN_OFFSET
14662 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT                                               0x0
14663 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT                                               0x10
14664 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK                                                 0x000001FFL
14665 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK                                                 0x01FF0000L
14666 //CB_TARGET_MASK
14667 #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT                                                                 0x0
14668 #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT                                                                 0x4
14669 #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT                                                                 0x8
14670 #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT                                                                 0xc
14671 #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT                                                                 0x10
14672 #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT                                                                 0x14
14673 #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT                                                                 0x18
14674 #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT                                                                 0x1c
14675 #define CB_TARGET_MASK__TARGET0_ENABLE_MASK                                                                   0x0000000FL
14676 #define CB_TARGET_MASK__TARGET1_ENABLE_MASK                                                                   0x000000F0L
14677 #define CB_TARGET_MASK__TARGET2_ENABLE_MASK                                                                   0x00000F00L
14678 #define CB_TARGET_MASK__TARGET3_ENABLE_MASK                                                                   0x0000F000L
14679 #define CB_TARGET_MASK__TARGET4_ENABLE_MASK                                                                   0x000F0000L
14680 #define CB_TARGET_MASK__TARGET5_ENABLE_MASK                                                                   0x00F00000L
14681 #define CB_TARGET_MASK__TARGET6_ENABLE_MASK                                                                   0x0F000000L
14682 #define CB_TARGET_MASK__TARGET7_ENABLE_MASK                                                                   0xF0000000L
14683 //CB_SHADER_MASK
14684 #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT                                                                 0x0
14685 #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT                                                                 0x4
14686 #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT                                                                 0x8
14687 #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT                                                                 0xc
14688 #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT                                                                 0x10
14689 #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT                                                                 0x14
14690 #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT                                                                 0x18
14691 #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT                                                                 0x1c
14692 #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK                                                                   0x0000000FL
14693 #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK                                                                   0x000000F0L
14694 #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK                                                                   0x00000F00L
14695 #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK                                                                   0x0000F000L
14696 #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK                                                                   0x000F0000L
14697 #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK                                                                   0x00F00000L
14698 #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK                                                                   0x0F000000L
14699 #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK                                                                   0xF0000000L
14700 //PA_SC_GENERIC_SCISSOR_TL
14701 #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT                                                                 0x0
14702 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT                                                                 0x10
14703 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14704 #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK                                                                   0x00007FFFL
14705 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK                                                                   0x7FFF0000L
14706 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14707 //PA_SC_GENERIC_SCISSOR_BR
14708 #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT                                                                 0x0
14709 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT                                                                 0x10
14710 #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK                                                                   0x00007FFFL
14711 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK                                                                   0x7FFF0000L
14712 //COHER_DEST_BASE_0
14713 #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT                                                              0x0
14714 #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
14715 //COHER_DEST_BASE_1
14716 #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT                                                              0x0
14717 #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
14718 //PA_SC_VPORT_SCISSOR_0_TL
14719 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT                                                                 0x0
14720 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT                                                                 0x10
14721 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14722 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK                                                                   0x00007FFFL
14723 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK                                                                   0x7FFF0000L
14724 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14725 //PA_SC_VPORT_SCISSOR_0_BR
14726 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT                                                                 0x0
14727 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT                                                                 0x10
14728 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK                                                                   0x00007FFFL
14729 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK                                                                   0x7FFF0000L
14730 //PA_SC_VPORT_SCISSOR_1_TL
14731 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT                                                                 0x0
14732 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT                                                                 0x10
14733 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14734 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK                                                                   0x00007FFFL
14735 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK                                                                   0x7FFF0000L
14736 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14737 //PA_SC_VPORT_SCISSOR_1_BR
14738 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT                                                                 0x0
14739 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT                                                                 0x10
14740 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK                                                                   0x00007FFFL
14741 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK                                                                   0x7FFF0000L
14742 //PA_SC_VPORT_SCISSOR_2_TL
14743 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT                                                                 0x0
14744 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT                                                                 0x10
14745 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14746 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK                                                                   0x00007FFFL
14747 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK                                                                   0x7FFF0000L
14748 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14749 //PA_SC_VPORT_SCISSOR_2_BR
14750 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT                                                                 0x0
14751 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT                                                                 0x10
14752 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK                                                                   0x00007FFFL
14753 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK                                                                   0x7FFF0000L
14754 //PA_SC_VPORT_SCISSOR_3_TL
14755 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT                                                                 0x0
14756 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT                                                                 0x10
14757 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14758 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK                                                                   0x00007FFFL
14759 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK                                                                   0x7FFF0000L
14760 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14761 //PA_SC_VPORT_SCISSOR_3_BR
14762 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT                                                                 0x0
14763 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT                                                                 0x10
14764 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK                                                                   0x00007FFFL
14765 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK                                                                   0x7FFF0000L
14766 //PA_SC_VPORT_SCISSOR_4_TL
14767 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT                                                                 0x0
14768 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT                                                                 0x10
14769 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14770 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK                                                                   0x00007FFFL
14771 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK                                                                   0x7FFF0000L
14772 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14773 //PA_SC_VPORT_SCISSOR_4_BR
14774 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT                                                                 0x0
14775 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT                                                                 0x10
14776 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK                                                                   0x00007FFFL
14777 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK                                                                   0x7FFF0000L
14778 //PA_SC_VPORT_SCISSOR_5_TL
14779 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT                                                                 0x0
14780 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT                                                                 0x10
14781 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14782 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK                                                                   0x00007FFFL
14783 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK                                                                   0x7FFF0000L
14784 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14785 //PA_SC_VPORT_SCISSOR_5_BR
14786 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT                                                                 0x0
14787 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT                                                                 0x10
14788 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK                                                                   0x00007FFFL
14789 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK                                                                   0x7FFF0000L
14790 //PA_SC_VPORT_SCISSOR_6_TL
14791 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT                                                                 0x0
14792 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT                                                                 0x10
14793 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14794 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK                                                                   0x00007FFFL
14795 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK                                                                   0x7FFF0000L
14796 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14797 //PA_SC_VPORT_SCISSOR_6_BR
14798 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT                                                                 0x0
14799 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT                                                                 0x10
14800 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK                                                                   0x00007FFFL
14801 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK                                                                   0x7FFF0000L
14802 //PA_SC_VPORT_SCISSOR_7_TL
14803 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT                                                                 0x0
14804 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT                                                                 0x10
14805 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14806 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK                                                                   0x00007FFFL
14807 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK                                                                   0x7FFF0000L
14808 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14809 //PA_SC_VPORT_SCISSOR_7_BR
14810 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT                                                                 0x0
14811 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT                                                                 0x10
14812 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK                                                                   0x00007FFFL
14813 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK                                                                   0x7FFF0000L
14814 //PA_SC_VPORT_SCISSOR_8_TL
14815 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT                                                                 0x0
14816 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT                                                                 0x10
14817 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14818 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK                                                                   0x00007FFFL
14819 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK                                                                   0x7FFF0000L
14820 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14821 //PA_SC_VPORT_SCISSOR_8_BR
14822 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT                                                                 0x0
14823 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT                                                                 0x10
14824 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK                                                                   0x00007FFFL
14825 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK                                                                   0x7FFF0000L
14826 //PA_SC_VPORT_SCISSOR_9_TL
14827 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT                                                                 0x0
14828 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT                                                                 0x10
14829 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14830 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK                                                                   0x00007FFFL
14831 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK                                                                   0x7FFF0000L
14832 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14833 //PA_SC_VPORT_SCISSOR_9_BR
14834 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT                                                                 0x0
14835 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT                                                                 0x10
14836 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK                                                                   0x00007FFFL
14837 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK                                                                   0x7FFF0000L
14838 //PA_SC_VPORT_SCISSOR_10_TL
14839 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT                                                                0x0
14840 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT                                                                0x10
14841 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14842 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK                                                                  0x00007FFFL
14843 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK                                                                  0x7FFF0000L
14844 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14845 //PA_SC_VPORT_SCISSOR_10_BR
14846 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT                                                                0x0
14847 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT                                                                0x10
14848 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK                                                                  0x00007FFFL
14849 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK                                                                  0x7FFF0000L
14850 //PA_SC_VPORT_SCISSOR_11_TL
14851 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT                                                                0x0
14852 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT                                                                0x10
14853 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14854 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK                                                                  0x00007FFFL
14855 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK                                                                  0x7FFF0000L
14856 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14857 //PA_SC_VPORT_SCISSOR_11_BR
14858 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT                                                                0x0
14859 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT                                                                0x10
14860 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK                                                                  0x00007FFFL
14861 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK                                                                  0x7FFF0000L
14862 //PA_SC_VPORT_SCISSOR_12_TL
14863 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT                                                                0x0
14864 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT                                                                0x10
14865 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14866 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK                                                                  0x00007FFFL
14867 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK                                                                  0x7FFF0000L
14868 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14869 //PA_SC_VPORT_SCISSOR_12_BR
14870 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT                                                                0x0
14871 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT                                                                0x10
14872 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK                                                                  0x00007FFFL
14873 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK                                                                  0x7FFF0000L
14874 //PA_SC_VPORT_SCISSOR_13_TL
14875 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT                                                                0x0
14876 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT                                                                0x10
14877 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14878 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK                                                                  0x00007FFFL
14879 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK                                                                  0x7FFF0000L
14880 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14881 //PA_SC_VPORT_SCISSOR_13_BR
14882 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT                                                                0x0
14883 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT                                                                0x10
14884 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK                                                                  0x00007FFFL
14885 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK                                                                  0x7FFF0000L
14886 //PA_SC_VPORT_SCISSOR_14_TL
14887 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT                                                                0x0
14888 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT                                                                0x10
14889 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14890 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK                                                                  0x00007FFFL
14891 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK                                                                  0x7FFF0000L
14892 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14893 //PA_SC_VPORT_SCISSOR_14_BR
14894 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT                                                                0x0
14895 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT                                                                0x10
14896 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK                                                                  0x00007FFFL
14897 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK                                                                  0x7FFF0000L
14898 //PA_SC_VPORT_SCISSOR_15_TL
14899 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT                                                                0x0
14900 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT                                                                0x10
14901 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14902 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK                                                                  0x00007FFFL
14903 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK                                                                  0x7FFF0000L
14904 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14905 //PA_SC_VPORT_SCISSOR_15_BR
14906 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT                                                                0x0
14907 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT                                                                0x10
14908 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK                                                                  0x00007FFFL
14909 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK                                                                  0x7FFF0000L
14910 //PA_SC_VPORT_ZMIN_0
14911 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT                                                                 0x0
14912 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14913 //PA_SC_VPORT_ZMAX_0
14914 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT                                                                 0x0
14915 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14916 //PA_SC_VPORT_ZMIN_1
14917 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT                                                                 0x0
14918 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14919 //PA_SC_VPORT_ZMAX_1
14920 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT                                                                 0x0
14921 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14922 //PA_SC_VPORT_ZMIN_2
14923 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT                                                                 0x0
14924 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14925 //PA_SC_VPORT_ZMAX_2
14926 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT                                                                 0x0
14927 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14928 //PA_SC_VPORT_ZMIN_3
14929 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT                                                                 0x0
14930 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14931 //PA_SC_VPORT_ZMAX_3
14932 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT                                                                 0x0
14933 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14934 //PA_SC_VPORT_ZMIN_4
14935 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT                                                                 0x0
14936 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14937 //PA_SC_VPORT_ZMAX_4
14938 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT                                                                 0x0
14939 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14940 //PA_SC_VPORT_ZMIN_5
14941 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT                                                                 0x0
14942 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14943 //PA_SC_VPORT_ZMAX_5
14944 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT                                                                 0x0
14945 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14946 //PA_SC_VPORT_ZMIN_6
14947 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT                                                                 0x0
14948 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14949 //PA_SC_VPORT_ZMAX_6
14950 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT                                                                 0x0
14951 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14952 //PA_SC_VPORT_ZMIN_7
14953 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT                                                                 0x0
14954 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14955 //PA_SC_VPORT_ZMAX_7
14956 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT                                                                 0x0
14957 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14958 //PA_SC_VPORT_ZMIN_8
14959 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT                                                                 0x0
14960 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14961 //PA_SC_VPORT_ZMAX_8
14962 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT                                                                 0x0
14963 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14964 //PA_SC_VPORT_ZMIN_9
14965 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT                                                                 0x0
14966 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14967 //PA_SC_VPORT_ZMAX_9
14968 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT                                                                 0x0
14969 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14970 //PA_SC_VPORT_ZMIN_10
14971 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT                                                                0x0
14972 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
14973 //PA_SC_VPORT_ZMAX_10
14974 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT                                                                0x0
14975 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
14976 //PA_SC_VPORT_ZMIN_11
14977 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT                                                                0x0
14978 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
14979 //PA_SC_VPORT_ZMAX_11
14980 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT                                                                0x0
14981 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
14982 //PA_SC_VPORT_ZMIN_12
14983 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT                                                                0x0
14984 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
14985 //PA_SC_VPORT_ZMAX_12
14986 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT                                                                0x0
14987 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
14988 //PA_SC_VPORT_ZMIN_13
14989 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT                                                                0x0
14990 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
14991 //PA_SC_VPORT_ZMAX_13
14992 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT                                                                0x0
14993 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
14994 //PA_SC_VPORT_ZMIN_14
14995 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT                                                                0x0
14996 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
14997 //PA_SC_VPORT_ZMAX_14
14998 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT                                                                0x0
14999 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
15000 //PA_SC_VPORT_ZMIN_15
15001 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT                                                                0x0
15002 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
15003 //PA_SC_VPORT_ZMAX_15
15004 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT                                                                0x0
15005 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
15006 //PA_SC_RASTER_CONFIG
15007 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT                                                               0x0
15008 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT                                                               0x2
15009 #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT                                                                  0x4
15010 #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT                                                                   0x6
15011 #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT                                                                   0x7
15012 #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT                                                                   0x8
15013 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT                                                                  0xa
15014 #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT                                                                  0xc
15015 #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT                                                                 0xe
15016 #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT                                                                    0x10
15017 #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT                                                                   0x12
15018 #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT                                                                   0x14
15019 #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT                                                                    0x18
15020 #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT                                                                   0x1a
15021 #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT                                                                   0x1d
15022 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK                                                                 0x00000003L
15023 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK                                                                 0x0000000CL
15024 #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK                                                                    0x00000030L
15025 #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK                                                                     0x00000040L
15026 #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK                                                                     0x00000080L
15027 #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK                                                                     0x00000300L
15028 #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK                                                                    0x00000C00L
15029 #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK                                                                    0x00003000L
15030 #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK                                                                   0x0000C000L
15031 #define PA_SC_RASTER_CONFIG__SC_MAP_MASK                                                                      0x00030000L
15032 #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK                                                                     0x000C0000L
15033 #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK                                                                     0x00300000L
15034 #define PA_SC_RASTER_CONFIG__SE_MAP_MASK                                                                      0x03000000L
15035 #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK                                                                     0x1C000000L
15036 #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK                                                                     0xE0000000L
15037 //PA_SC_RASTER_CONFIG_1
15038 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT                                                             0x0
15039 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT                                                            0x2
15040 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT                                                            0x5
15041 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK                                                               0x00000003L
15042 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK                                                              0x0000001CL
15043 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK                                                              0x000000E0L
15044 //PA_SC_SCREEN_EXTENT_CONTROL
15045 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                 0x0
15046 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                  0x2
15047 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                   0x00000003L
15048 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK                                                    0x0000000CL
15049 //PA_SC_TILE_STEERING_OVERRIDE
15050 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT                                                           0x0
15051 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT                                                           0x1
15052 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT                                                    0x5
15053 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK                                                             0x00000001L
15054 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK                                                             0x00000006L
15055 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK                                                      0x00000060L
15056 //CP_PERFMON_CNTX_CNTL
15057 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT                                                           0x1f
15058 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK                                                             0x80000000L
15059 //CP_PIPEID
15060 #define CP_PIPEID__PIPE_ID__SHIFT                                                                             0x0
15061 #define CP_PIPEID__PIPE_ID_MASK                                                                               0x00000003L
15062 //CP_RINGID
15063 #define CP_RINGID__RINGID__SHIFT                                                                              0x0
15064 #define CP_RINGID__RINGID_MASK                                                                                0x00000003L
15065 //CP_VMID
15066 #define CP_VMID__VMID__SHIFT                                                                                  0x0
15067 #define CP_VMID__VMID_MASK                                                                                    0x0000000FL
15068 //PA_SC_RIGHT_VERT_GRID
15069 #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT                                                                0x0
15070 #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT                                                               0x8
15071 #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT                                                              0x10
15072 #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT                                                               0x18
15073 #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK                                                                  0x000000FFL
15074 #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK                                                                 0x0000FF00L
15075 #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK                                                                0x00FF0000L
15076 #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK                                                                 0xFF000000L
15077 //PA_SC_LEFT_VERT_GRID
15078 #define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT                                                                 0x0
15079 #define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT                                                                0x8
15080 #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT                                                               0x10
15081 #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT                                                                0x18
15082 #define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK                                                                   0x000000FFL
15083 #define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK                                                                  0x0000FF00L
15084 #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK                                                                 0x00FF0000L
15085 #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK                                                                  0xFF000000L
15086 //PA_SC_HORIZ_GRID
15087 #define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT                                                                      0x0
15088 #define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT                                                                     0x8
15089 #define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT                                                                     0x10
15090 #define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT                                                                      0x18
15091 #define PA_SC_HORIZ_GRID__TOP_QTR_MASK                                                                        0x000000FFL
15092 #define PA_SC_HORIZ_GRID__TOP_HALF_MASK                                                                       0x0000FF00L
15093 #define PA_SC_HORIZ_GRID__BOT_HALF_MASK                                                                       0x00FF0000L
15094 #define PA_SC_HORIZ_GRID__BOT_QTR_MASK                                                                        0xFF000000L
15095 //VGT_MULTI_PRIM_IB_RESET_INDX
15096 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT                                                       0x0
15097 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK                                                         0xFFFFFFFFL
15098 //CB_BLEND_RED
15099 #define CB_BLEND_RED__BLEND_RED__SHIFT                                                                        0x0
15100 #define CB_BLEND_RED__BLEND_RED_MASK                                                                          0xFFFFFFFFL
15101 //CB_BLEND_GREEN
15102 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT                                                                    0x0
15103 #define CB_BLEND_GREEN__BLEND_GREEN_MASK                                                                      0xFFFFFFFFL
15104 //CB_BLEND_BLUE
15105 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT                                                                      0x0
15106 #define CB_BLEND_BLUE__BLEND_BLUE_MASK                                                                        0xFFFFFFFFL
15107 //CB_BLEND_ALPHA
15108 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                                                                    0x0
15109 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK                                                                      0xFFFFFFFFL
15110 //CB_DCC_CONTROL
15111 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                                     0x0
15112 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT                                         0x1
15113 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT                                                   0x2
15114 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                       0x00000001L
15115 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK                                           0x00000002L
15116 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK                                                     0x0000007CL
15117 //DB_STENCIL_CONTROL
15118 #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT                                                                0x0
15119 #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT                                                               0x4
15120 #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT                                                               0x8
15121 #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT                                                             0xc
15122 #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT                                                            0x10
15123 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT                                                            0x14
15124 #define DB_STENCIL_CONTROL__STENCILFAIL_MASK                                                                  0x0000000FL
15125 #define DB_STENCIL_CONTROL__STENCILZPASS_MASK                                                                 0x000000F0L
15126 #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK                                                                 0x00000F00L
15127 #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK                                                               0x0000F000L
15128 #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK                                                              0x000F0000L
15129 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK                                                              0x00F00000L
15130 //DB_STENCILREFMASK
15131 #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT                                                              0x0
15132 #define DB_STENCILREFMASK__STENCILMASK__SHIFT                                                                 0x8
15133 #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT                                                            0x10
15134 #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT                                                                0x18
15135 #define DB_STENCILREFMASK__STENCILTESTVAL_MASK                                                                0x000000FFL
15136 #define DB_STENCILREFMASK__STENCILMASK_MASK                                                                   0x0000FF00L
15137 #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK                                                              0x00FF0000L
15138 #define DB_STENCILREFMASK__STENCILOPVAL_MASK                                                                  0xFF000000L
15139 //DB_STENCILREFMASK_BF
15140 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT                                                        0x0
15141 #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT                                                           0x8
15142 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT                                                      0x10
15143 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT                                                          0x18
15144 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK                                                          0x000000FFL
15145 #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK                                                             0x0000FF00L
15146 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK                                                        0x00FF0000L
15147 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK                                                            0xFF000000L
15148 //PA_CL_VPORT_XSCALE
15149 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT                                                               0x0
15150 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK                                                                 0xFFFFFFFFL
15151 //PA_CL_VPORT_XOFFSET
15152 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT                                                             0x0
15153 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK                                                               0xFFFFFFFFL
15154 //PA_CL_VPORT_YSCALE
15155 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT                                                               0x0
15156 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK                                                                 0xFFFFFFFFL
15157 //PA_CL_VPORT_YOFFSET
15158 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT                                                             0x0
15159 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK                                                               0xFFFFFFFFL
15160 //PA_CL_VPORT_ZSCALE
15161 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT                                                               0x0
15162 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK                                                                 0xFFFFFFFFL
15163 //PA_CL_VPORT_ZOFFSET
15164 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT                                                             0x0
15165 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK                                                               0xFFFFFFFFL
15166 //PA_CL_VPORT_XSCALE_1
15167 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT                                                             0x0
15168 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15169 //PA_CL_VPORT_XOFFSET_1
15170 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT                                                           0x0
15171 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15172 //PA_CL_VPORT_YSCALE_1
15173 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT                                                             0x0
15174 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15175 //PA_CL_VPORT_YOFFSET_1
15176 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT                                                           0x0
15177 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15178 //PA_CL_VPORT_ZSCALE_1
15179 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT                                                             0x0
15180 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15181 //PA_CL_VPORT_ZOFFSET_1
15182 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT                                                           0x0
15183 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15184 //PA_CL_VPORT_XSCALE_2
15185 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT                                                             0x0
15186 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15187 //PA_CL_VPORT_XOFFSET_2
15188 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT                                                           0x0
15189 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15190 //PA_CL_VPORT_YSCALE_2
15191 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT                                                             0x0
15192 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15193 //PA_CL_VPORT_YOFFSET_2
15194 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT                                                           0x0
15195 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15196 //PA_CL_VPORT_ZSCALE_2
15197 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT                                                             0x0
15198 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15199 //PA_CL_VPORT_ZOFFSET_2
15200 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT                                                           0x0
15201 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15202 //PA_CL_VPORT_XSCALE_3
15203 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT                                                             0x0
15204 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15205 //PA_CL_VPORT_XOFFSET_3
15206 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT                                                           0x0
15207 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15208 //PA_CL_VPORT_YSCALE_3
15209 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT                                                             0x0
15210 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15211 //PA_CL_VPORT_YOFFSET_3
15212 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT                                                           0x0
15213 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15214 //PA_CL_VPORT_ZSCALE_3
15215 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT                                                             0x0
15216 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15217 //PA_CL_VPORT_ZOFFSET_3
15218 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT                                                           0x0
15219 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15220 //PA_CL_VPORT_XSCALE_4
15221 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT                                                             0x0
15222 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15223 //PA_CL_VPORT_XOFFSET_4
15224 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT                                                           0x0
15225 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15226 //PA_CL_VPORT_YSCALE_4
15227 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT                                                             0x0
15228 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15229 //PA_CL_VPORT_YOFFSET_4
15230 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT                                                           0x0
15231 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15232 //PA_CL_VPORT_ZSCALE_4
15233 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT                                                             0x0
15234 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15235 //PA_CL_VPORT_ZOFFSET_4
15236 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT                                                           0x0
15237 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15238 //PA_CL_VPORT_XSCALE_5
15239 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT                                                             0x0
15240 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15241 //PA_CL_VPORT_XOFFSET_5
15242 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT                                                           0x0
15243 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15244 //PA_CL_VPORT_YSCALE_5
15245 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT                                                             0x0
15246 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15247 //PA_CL_VPORT_YOFFSET_5
15248 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT                                                           0x0
15249 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15250 //PA_CL_VPORT_ZSCALE_5
15251 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT                                                             0x0
15252 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15253 //PA_CL_VPORT_ZOFFSET_5
15254 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT                                                           0x0
15255 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15256 //PA_CL_VPORT_XSCALE_6
15257 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT                                                             0x0
15258 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15259 //PA_CL_VPORT_XOFFSET_6
15260 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT                                                           0x0
15261 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15262 //PA_CL_VPORT_YSCALE_6
15263 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT                                                             0x0
15264 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15265 //PA_CL_VPORT_YOFFSET_6
15266 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT                                                           0x0
15267 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15268 //PA_CL_VPORT_ZSCALE_6
15269 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT                                                             0x0
15270 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15271 //PA_CL_VPORT_ZOFFSET_6
15272 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT                                                           0x0
15273 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15274 //PA_CL_VPORT_XSCALE_7
15275 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT                                                             0x0
15276 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15277 //PA_CL_VPORT_XOFFSET_7
15278 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT                                                           0x0
15279 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15280 //PA_CL_VPORT_YSCALE_7
15281 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT                                                             0x0
15282 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15283 //PA_CL_VPORT_YOFFSET_7
15284 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT                                                           0x0
15285 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15286 //PA_CL_VPORT_ZSCALE_7
15287 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT                                                             0x0
15288 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15289 //PA_CL_VPORT_ZOFFSET_7
15290 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT                                                           0x0
15291 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15292 //PA_CL_VPORT_XSCALE_8
15293 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT                                                             0x0
15294 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15295 //PA_CL_VPORT_XOFFSET_8
15296 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT                                                           0x0
15297 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15298 //PA_CL_VPORT_YSCALE_8
15299 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT                                                             0x0
15300 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15301 //PA_CL_VPORT_YOFFSET_8
15302 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT                                                           0x0
15303 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15304 //PA_CL_VPORT_ZSCALE_8
15305 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT                                                             0x0
15306 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15307 //PA_CL_VPORT_ZOFFSET_8
15308 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT                                                           0x0
15309 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15310 //PA_CL_VPORT_XSCALE_9
15311 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT                                                             0x0
15312 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15313 //PA_CL_VPORT_XOFFSET_9
15314 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT                                                           0x0
15315 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15316 //PA_CL_VPORT_YSCALE_9
15317 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT                                                             0x0
15318 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15319 //PA_CL_VPORT_YOFFSET_9
15320 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT                                                           0x0
15321 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15322 //PA_CL_VPORT_ZSCALE_9
15323 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT                                                             0x0
15324 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15325 //PA_CL_VPORT_ZOFFSET_9
15326 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT                                                           0x0
15327 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15328 //PA_CL_VPORT_XSCALE_10
15329 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT                                                            0x0
15330 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15331 //PA_CL_VPORT_XOFFSET_10
15332 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT                                                          0x0
15333 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15334 //PA_CL_VPORT_YSCALE_10
15335 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT                                                            0x0
15336 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15337 //PA_CL_VPORT_YOFFSET_10
15338 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT                                                          0x0
15339 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15340 //PA_CL_VPORT_ZSCALE_10
15341 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT                                                            0x0
15342 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15343 //PA_CL_VPORT_ZOFFSET_10
15344 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT                                                          0x0
15345 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15346 //PA_CL_VPORT_XSCALE_11
15347 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT                                                            0x0
15348 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15349 //PA_CL_VPORT_XOFFSET_11
15350 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT                                                          0x0
15351 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15352 //PA_CL_VPORT_YSCALE_11
15353 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT                                                            0x0
15354 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15355 //PA_CL_VPORT_YOFFSET_11
15356 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT                                                          0x0
15357 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15358 //PA_CL_VPORT_ZSCALE_11
15359 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT                                                            0x0
15360 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15361 //PA_CL_VPORT_ZOFFSET_11
15362 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT                                                          0x0
15363 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15364 //PA_CL_VPORT_XSCALE_12
15365 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT                                                            0x0
15366 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15367 //PA_CL_VPORT_XOFFSET_12
15368 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT                                                          0x0
15369 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15370 //PA_CL_VPORT_YSCALE_12
15371 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT                                                            0x0
15372 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15373 //PA_CL_VPORT_YOFFSET_12
15374 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT                                                          0x0
15375 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15376 //PA_CL_VPORT_ZSCALE_12
15377 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT                                                            0x0
15378 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15379 //PA_CL_VPORT_ZOFFSET_12
15380 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT                                                          0x0
15381 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15382 //PA_CL_VPORT_XSCALE_13
15383 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT                                                            0x0
15384 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15385 //PA_CL_VPORT_XOFFSET_13
15386 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT                                                          0x0
15387 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15388 //PA_CL_VPORT_YSCALE_13
15389 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT                                                            0x0
15390 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15391 //PA_CL_VPORT_YOFFSET_13
15392 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT                                                          0x0
15393 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15394 //PA_CL_VPORT_ZSCALE_13
15395 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT                                                            0x0
15396 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15397 //PA_CL_VPORT_ZOFFSET_13
15398 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT                                                          0x0
15399 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15400 //PA_CL_VPORT_XSCALE_14
15401 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT                                                            0x0
15402 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15403 //PA_CL_VPORT_XOFFSET_14
15404 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT                                                          0x0
15405 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15406 //PA_CL_VPORT_YSCALE_14
15407 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT                                                            0x0
15408 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15409 //PA_CL_VPORT_YOFFSET_14
15410 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT                                                          0x0
15411 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15412 //PA_CL_VPORT_ZSCALE_14
15413 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT                                                            0x0
15414 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15415 //PA_CL_VPORT_ZOFFSET_14
15416 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT                                                          0x0
15417 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15418 //PA_CL_VPORT_XSCALE_15
15419 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT                                                            0x0
15420 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15421 //PA_CL_VPORT_XOFFSET_15
15422 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT                                                          0x0
15423 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15424 //PA_CL_VPORT_YSCALE_15
15425 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT                                                            0x0
15426 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15427 //PA_CL_VPORT_YOFFSET_15
15428 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT                                                          0x0
15429 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15430 //PA_CL_VPORT_ZSCALE_15
15431 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT                                                            0x0
15432 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15433 //PA_CL_VPORT_ZOFFSET_15
15434 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT                                                          0x0
15435 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15436 //PA_CL_UCP_0_X
15437 #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT                                                                   0x0
15438 #define PA_CL_UCP_0_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15439 //PA_CL_UCP_0_Y
15440 #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT                                                                   0x0
15441 #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15442 //PA_CL_UCP_0_Z
15443 #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT                                                                   0x0
15444 #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15445 //PA_CL_UCP_0_W
15446 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT                                                                   0x0
15447 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15448 //PA_CL_UCP_1_X
15449 #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT                                                                   0x0
15450 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15451 //PA_CL_UCP_1_Y
15452 #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT                                                                   0x0
15453 #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15454 //PA_CL_UCP_1_Z
15455 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT                                                                   0x0
15456 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15457 //PA_CL_UCP_1_W
15458 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT                                                                   0x0
15459 #define PA_CL_UCP_1_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15460 //PA_CL_UCP_2_X
15461 #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT                                                                   0x0
15462 #define PA_CL_UCP_2_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15463 //PA_CL_UCP_2_Y
15464 #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT                                                                   0x0
15465 #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15466 //PA_CL_UCP_2_Z
15467 #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT                                                                   0x0
15468 #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15469 //PA_CL_UCP_2_W
15470 #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT                                                                   0x0
15471 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15472 //PA_CL_UCP_3_X
15473 #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT                                                                   0x0
15474 #define PA_CL_UCP_3_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15475 //PA_CL_UCP_3_Y
15476 #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT                                                                   0x0
15477 #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15478 //PA_CL_UCP_3_Z
15479 #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT                                                                   0x0
15480 #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15481 //PA_CL_UCP_3_W
15482 #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT                                                                   0x0
15483 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15484 //PA_CL_UCP_4_X
15485 #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT                                                                   0x0
15486 #define PA_CL_UCP_4_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15487 //PA_CL_UCP_4_Y
15488 #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT                                                                   0x0
15489 #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15490 //PA_CL_UCP_4_Z
15491 #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT                                                                   0x0
15492 #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15493 //PA_CL_UCP_4_W
15494 #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT                                                                   0x0
15495 #define PA_CL_UCP_4_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15496 //PA_CL_UCP_5_X
15497 #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT                                                                   0x0
15498 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15499 //PA_CL_UCP_5_Y
15500 #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT                                                                   0x0
15501 #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15502 //PA_CL_UCP_5_Z
15503 #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT                                                                   0x0
15504 #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15505 //PA_CL_UCP_5_W
15506 #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT                                                                   0x0
15507 #define PA_CL_UCP_5_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15508 //SPI_PS_INPUT_CNTL_0
15509 #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT                                                                    0x0
15510 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT                                                               0x8
15511 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT                                                                0xa
15512 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT                                                                  0xd
15513 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT                                                             0x11
15514 #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT                                                                       0x12
15515 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT                                                          0x13
15516 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15517 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15518 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15519 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT                                                               0x18
15520 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT                                                               0x19
15521 #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK                                                                      0x0000003FL
15522 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK                                                                 0x00000300L
15523 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK                                                                  0x00000400L
15524 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK                                                                    0x0001E000L
15525 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK                                                               0x00020000L
15526 #define SPI_PS_INPUT_CNTL_0__DUP_MASK                                                                         0x00040000L
15527 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK                                                            0x00080000L
15528 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15529 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15530 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15531 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK                                                                 0x01000000L
15532 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK                                                                 0x02000000L
15533 //SPI_PS_INPUT_CNTL_1
15534 #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT                                                                    0x0
15535 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT                                                               0x8
15536 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT                                                                0xa
15537 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT                                                                  0xd
15538 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT                                                             0x11
15539 #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT                                                                       0x12
15540 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT                                                          0x13
15541 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15542 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15543 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15544 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT                                                               0x18
15545 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT                                                               0x19
15546 #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK                                                                      0x0000003FL
15547 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK                                                                 0x00000300L
15548 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK                                                                  0x00000400L
15549 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK                                                                    0x0001E000L
15550 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK                                                               0x00020000L
15551 #define SPI_PS_INPUT_CNTL_1__DUP_MASK                                                                         0x00040000L
15552 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK                                                            0x00080000L
15553 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15554 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15555 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15556 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK                                                                 0x01000000L
15557 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK                                                                 0x02000000L
15558 //SPI_PS_INPUT_CNTL_2
15559 #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT                                                                    0x0
15560 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT                                                               0x8
15561 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT                                                                0xa
15562 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT                                                                  0xd
15563 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT                                                             0x11
15564 #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT                                                                       0x12
15565 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT                                                          0x13
15566 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15567 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15568 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15569 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT                                                               0x18
15570 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT                                                               0x19
15571 #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK                                                                      0x0000003FL
15572 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK                                                                 0x00000300L
15573 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK                                                                  0x00000400L
15574 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK                                                                    0x0001E000L
15575 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK                                                               0x00020000L
15576 #define SPI_PS_INPUT_CNTL_2__DUP_MASK                                                                         0x00040000L
15577 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK                                                            0x00080000L
15578 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15579 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15580 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15581 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK                                                                 0x01000000L
15582 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK                                                                 0x02000000L
15583 //SPI_PS_INPUT_CNTL_3
15584 #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT                                                                    0x0
15585 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT                                                               0x8
15586 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT                                                                0xa
15587 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT                                                                  0xd
15588 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT                                                             0x11
15589 #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT                                                                       0x12
15590 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT                                                          0x13
15591 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15592 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15593 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15594 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT                                                               0x18
15595 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT                                                               0x19
15596 #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK                                                                      0x0000003FL
15597 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK                                                                 0x00000300L
15598 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK                                                                  0x00000400L
15599 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK                                                                    0x0001E000L
15600 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK                                                               0x00020000L
15601 #define SPI_PS_INPUT_CNTL_3__DUP_MASK                                                                         0x00040000L
15602 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK                                                            0x00080000L
15603 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15604 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15605 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15606 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK                                                                 0x01000000L
15607 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK                                                                 0x02000000L
15608 //SPI_PS_INPUT_CNTL_4
15609 #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT                                                                    0x0
15610 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT                                                               0x8
15611 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT                                                                0xa
15612 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT                                                                  0xd
15613 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT                                                             0x11
15614 #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT                                                                       0x12
15615 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT                                                          0x13
15616 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15617 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15618 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15619 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT                                                               0x18
15620 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT                                                               0x19
15621 #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK                                                                      0x0000003FL
15622 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK                                                                 0x00000300L
15623 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK                                                                  0x00000400L
15624 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK                                                                    0x0001E000L
15625 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK                                                               0x00020000L
15626 #define SPI_PS_INPUT_CNTL_4__DUP_MASK                                                                         0x00040000L
15627 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK                                                            0x00080000L
15628 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15629 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15630 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15631 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK                                                                 0x01000000L
15632 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK                                                                 0x02000000L
15633 //SPI_PS_INPUT_CNTL_5
15634 #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT                                                                    0x0
15635 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT                                                               0x8
15636 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT                                                                0xa
15637 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT                                                                  0xd
15638 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT                                                             0x11
15639 #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT                                                                       0x12
15640 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT                                                          0x13
15641 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15642 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15643 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15644 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT                                                               0x18
15645 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT                                                               0x19
15646 #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK                                                                      0x0000003FL
15647 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK                                                                 0x00000300L
15648 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK                                                                  0x00000400L
15649 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK                                                                    0x0001E000L
15650 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK                                                               0x00020000L
15651 #define SPI_PS_INPUT_CNTL_5__DUP_MASK                                                                         0x00040000L
15652 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK                                                            0x00080000L
15653 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15654 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15655 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15656 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK                                                                 0x01000000L
15657 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK                                                                 0x02000000L
15658 //SPI_PS_INPUT_CNTL_6
15659 #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT                                                                    0x0
15660 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT                                                               0x8
15661 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT                                                                0xa
15662 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT                                                                  0xd
15663 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT                                                             0x11
15664 #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT                                                                       0x12
15665 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT                                                          0x13
15666 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15667 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15668 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15669 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT                                                               0x18
15670 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT                                                               0x19
15671 #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK                                                                      0x0000003FL
15672 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK                                                                 0x00000300L
15673 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK                                                                  0x00000400L
15674 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK                                                                    0x0001E000L
15675 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK                                                               0x00020000L
15676 #define SPI_PS_INPUT_CNTL_6__DUP_MASK                                                                         0x00040000L
15677 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK                                                            0x00080000L
15678 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15679 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15680 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15681 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK                                                                 0x01000000L
15682 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK                                                                 0x02000000L
15683 //SPI_PS_INPUT_CNTL_7
15684 #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT                                                                    0x0
15685 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT                                                               0x8
15686 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT                                                                0xa
15687 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT                                                                  0xd
15688 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT                                                             0x11
15689 #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT                                                                       0x12
15690 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT                                                          0x13
15691 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15692 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15693 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15694 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT                                                               0x18
15695 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT                                                               0x19
15696 #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK                                                                      0x0000003FL
15697 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK                                                                 0x00000300L
15698 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK                                                                  0x00000400L
15699 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK                                                                    0x0001E000L
15700 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK                                                               0x00020000L
15701 #define SPI_PS_INPUT_CNTL_7__DUP_MASK                                                                         0x00040000L
15702 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK                                                            0x00080000L
15703 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15704 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15705 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15706 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK                                                                 0x01000000L
15707 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK                                                                 0x02000000L
15708 //SPI_PS_INPUT_CNTL_8
15709 #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT                                                                    0x0
15710 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT                                                               0x8
15711 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT                                                                0xa
15712 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT                                                                  0xd
15713 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT                                                             0x11
15714 #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT                                                                       0x12
15715 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT                                                          0x13
15716 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15717 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15718 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15719 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT                                                               0x18
15720 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT                                                               0x19
15721 #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK                                                                      0x0000003FL
15722 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK                                                                 0x00000300L
15723 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK                                                                  0x00000400L
15724 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK                                                                    0x0001E000L
15725 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK                                                               0x00020000L
15726 #define SPI_PS_INPUT_CNTL_8__DUP_MASK                                                                         0x00040000L
15727 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK                                                            0x00080000L
15728 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15729 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15730 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15731 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK                                                                 0x01000000L
15732 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK                                                                 0x02000000L
15733 //SPI_PS_INPUT_CNTL_9
15734 #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT                                                                    0x0
15735 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT                                                               0x8
15736 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT                                                                0xa
15737 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT                                                                  0xd
15738 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT                                                             0x11
15739 #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT                                                                       0x12
15740 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT                                                          0x13
15741 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15742 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15743 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15744 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT                                                               0x18
15745 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT                                                               0x19
15746 #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK                                                                      0x0000003FL
15747 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK                                                                 0x00000300L
15748 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK                                                                  0x00000400L
15749 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK                                                                    0x0001E000L
15750 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK                                                               0x00020000L
15751 #define SPI_PS_INPUT_CNTL_9__DUP_MASK                                                                         0x00040000L
15752 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK                                                            0x00080000L
15753 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15754 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15755 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15756 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK                                                                 0x01000000L
15757 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK                                                                 0x02000000L
15758 //SPI_PS_INPUT_CNTL_10
15759 #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT                                                                   0x0
15760 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT                                                              0x8
15761 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT                                                               0xa
15762 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT                                                                 0xd
15763 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT                                                            0x11
15764 #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT                                                                      0x12
15765 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT                                                         0x13
15766 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15767 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15768 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15769 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT                                                              0x18
15770 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT                                                              0x19
15771 #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK                                                                     0x0000003FL
15772 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK                                                                0x00000300L
15773 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK                                                                 0x00000400L
15774 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK                                                                   0x0001E000L
15775 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK                                                              0x00020000L
15776 #define SPI_PS_INPUT_CNTL_10__DUP_MASK                                                                        0x00040000L
15777 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK                                                           0x00080000L
15778 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15779 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15780 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15781 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK                                                                0x01000000L
15782 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK                                                                0x02000000L
15783 //SPI_PS_INPUT_CNTL_11
15784 #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT                                                                   0x0
15785 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT                                                              0x8
15786 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT                                                               0xa
15787 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT                                                                 0xd
15788 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT                                                            0x11
15789 #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT                                                                      0x12
15790 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT                                                         0x13
15791 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15792 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15793 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15794 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT                                                              0x18
15795 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT                                                              0x19
15796 #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK                                                                     0x0000003FL
15797 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK                                                                0x00000300L
15798 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK                                                                 0x00000400L
15799 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK                                                                   0x0001E000L
15800 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK                                                              0x00020000L
15801 #define SPI_PS_INPUT_CNTL_11__DUP_MASK                                                                        0x00040000L
15802 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK                                                           0x00080000L
15803 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15804 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15805 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15806 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK                                                                0x01000000L
15807 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK                                                                0x02000000L
15808 //SPI_PS_INPUT_CNTL_12
15809 #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT                                                                   0x0
15810 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT                                                              0x8
15811 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT                                                               0xa
15812 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT                                                                 0xd
15813 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT                                                            0x11
15814 #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT                                                                      0x12
15815 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT                                                         0x13
15816 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15817 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15818 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15819 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT                                                              0x18
15820 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT                                                              0x19
15821 #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK                                                                     0x0000003FL
15822 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK                                                                0x00000300L
15823 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK                                                                 0x00000400L
15824 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK                                                                   0x0001E000L
15825 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK                                                              0x00020000L
15826 #define SPI_PS_INPUT_CNTL_12__DUP_MASK                                                                        0x00040000L
15827 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK                                                           0x00080000L
15828 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15829 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15830 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15831 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK                                                                0x01000000L
15832 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK                                                                0x02000000L
15833 //SPI_PS_INPUT_CNTL_13
15834 #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT                                                                   0x0
15835 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT                                                              0x8
15836 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT                                                               0xa
15837 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT                                                                 0xd
15838 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT                                                            0x11
15839 #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT                                                                      0x12
15840 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT                                                         0x13
15841 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15842 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15843 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15844 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT                                                              0x18
15845 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT                                                              0x19
15846 #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK                                                                     0x0000003FL
15847 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK                                                                0x00000300L
15848 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK                                                                 0x00000400L
15849 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK                                                                   0x0001E000L
15850 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK                                                              0x00020000L
15851 #define SPI_PS_INPUT_CNTL_13__DUP_MASK                                                                        0x00040000L
15852 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK                                                           0x00080000L
15853 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15854 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15855 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15856 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK                                                                0x01000000L
15857 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK                                                                0x02000000L
15858 //SPI_PS_INPUT_CNTL_14
15859 #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT                                                                   0x0
15860 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT                                                              0x8
15861 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT                                                               0xa
15862 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT                                                                 0xd
15863 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT                                                            0x11
15864 #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT                                                                      0x12
15865 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT                                                         0x13
15866 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15867 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15868 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15869 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT                                                              0x18
15870 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT                                                              0x19
15871 #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK                                                                     0x0000003FL
15872 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK                                                                0x00000300L
15873 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK                                                                 0x00000400L
15874 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK                                                                   0x0001E000L
15875 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK                                                              0x00020000L
15876 #define SPI_PS_INPUT_CNTL_14__DUP_MASK                                                                        0x00040000L
15877 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK                                                           0x00080000L
15878 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15879 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15880 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15881 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK                                                                0x01000000L
15882 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK                                                                0x02000000L
15883 //SPI_PS_INPUT_CNTL_15
15884 #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT                                                                   0x0
15885 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT                                                              0x8
15886 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT                                                               0xa
15887 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT                                                                 0xd
15888 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT                                                            0x11
15889 #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT                                                                      0x12
15890 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT                                                         0x13
15891 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15892 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15893 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15894 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT                                                              0x18
15895 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT                                                              0x19
15896 #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK                                                                     0x0000003FL
15897 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK                                                                0x00000300L
15898 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK                                                                 0x00000400L
15899 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK                                                                   0x0001E000L
15900 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK                                                              0x00020000L
15901 #define SPI_PS_INPUT_CNTL_15__DUP_MASK                                                                        0x00040000L
15902 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK                                                           0x00080000L
15903 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15904 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15905 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15906 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK                                                                0x01000000L
15907 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK                                                                0x02000000L
15908 //SPI_PS_INPUT_CNTL_16
15909 #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT                                                                   0x0
15910 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT                                                              0x8
15911 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT                                                               0xa
15912 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT                                                                 0xd
15913 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT                                                            0x11
15914 #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT                                                                      0x12
15915 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT                                                         0x13
15916 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15917 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15918 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15919 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT                                                              0x18
15920 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT                                                              0x19
15921 #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK                                                                     0x0000003FL
15922 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK                                                                0x00000300L
15923 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK                                                                 0x00000400L
15924 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK                                                                   0x0001E000L
15925 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK                                                              0x00020000L
15926 #define SPI_PS_INPUT_CNTL_16__DUP_MASK                                                                        0x00040000L
15927 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK                                                           0x00080000L
15928 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15929 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15930 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15931 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK                                                                0x01000000L
15932 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK                                                                0x02000000L
15933 //SPI_PS_INPUT_CNTL_17
15934 #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT                                                                   0x0
15935 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT                                                              0x8
15936 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT                                                               0xa
15937 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT                                                                 0xd
15938 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT                                                            0x11
15939 #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT                                                                      0x12
15940 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT                                                         0x13
15941 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15942 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15943 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15944 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT                                                              0x18
15945 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT                                                              0x19
15946 #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK                                                                     0x0000003FL
15947 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK                                                                0x00000300L
15948 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK                                                                 0x00000400L
15949 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK                                                                   0x0001E000L
15950 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK                                                              0x00020000L
15951 #define SPI_PS_INPUT_CNTL_17__DUP_MASK                                                                        0x00040000L
15952 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK                                                           0x00080000L
15953 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15954 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15955 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15956 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK                                                                0x01000000L
15957 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK                                                                0x02000000L
15958 //SPI_PS_INPUT_CNTL_18
15959 #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT                                                                   0x0
15960 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT                                                              0x8
15961 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT                                                               0xa
15962 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT                                                                 0xd
15963 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT                                                            0x11
15964 #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT                                                                      0x12
15965 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT                                                         0x13
15966 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15967 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15968 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15969 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT                                                              0x18
15970 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT                                                              0x19
15971 #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK                                                                     0x0000003FL
15972 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK                                                                0x00000300L
15973 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK                                                                 0x00000400L
15974 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK                                                                   0x0001E000L
15975 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK                                                              0x00020000L
15976 #define SPI_PS_INPUT_CNTL_18__DUP_MASK                                                                        0x00040000L
15977 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK                                                           0x00080000L
15978 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15979 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15980 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15981 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK                                                                0x01000000L
15982 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK                                                                0x02000000L
15983 //SPI_PS_INPUT_CNTL_19
15984 #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT                                                                   0x0
15985 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT                                                              0x8
15986 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT                                                               0xa
15987 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT                                                                 0xd
15988 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT                                                            0x11
15989 #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT                                                                      0x12
15990 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT                                                         0x13
15991 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15992 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15993 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15994 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT                                                              0x18
15995 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT                                                              0x19
15996 #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK                                                                     0x0000003FL
15997 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK                                                                0x00000300L
15998 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK                                                                 0x00000400L
15999 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK                                                                   0x0001E000L
16000 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK                                                              0x00020000L
16001 #define SPI_PS_INPUT_CNTL_19__DUP_MASK                                                                        0x00040000L
16002 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK                                                           0x00080000L
16003 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16004 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16005 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
16006 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK                                                                0x01000000L
16007 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK                                                                0x02000000L
16008 //SPI_PS_INPUT_CNTL_20
16009 #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT                                                                   0x0
16010 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT                                                              0x8
16011 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT                                                               0xa
16012 #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT                                                                      0x12
16013 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT                                                         0x13
16014 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16015 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16016 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT                                                              0x18
16017 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT                                                              0x19
16018 #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK                                                                     0x0000003FL
16019 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK                                                                0x00000300L
16020 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK                                                                 0x00000400L
16021 #define SPI_PS_INPUT_CNTL_20__DUP_MASK                                                                        0x00040000L
16022 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK                                                           0x00080000L
16023 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16024 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16025 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK                                                                0x01000000L
16026 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK                                                                0x02000000L
16027 //SPI_PS_INPUT_CNTL_21
16028 #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT                                                                   0x0
16029 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT                                                              0x8
16030 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT                                                               0xa
16031 #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT                                                                      0x12
16032 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT                                                         0x13
16033 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16034 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16035 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT                                                              0x18
16036 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT                                                              0x19
16037 #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK                                                                     0x0000003FL
16038 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK                                                                0x00000300L
16039 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK                                                                 0x00000400L
16040 #define SPI_PS_INPUT_CNTL_21__DUP_MASK                                                                        0x00040000L
16041 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK                                                           0x00080000L
16042 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16043 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16044 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK                                                                0x01000000L
16045 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK                                                                0x02000000L
16046 //SPI_PS_INPUT_CNTL_22
16047 #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT                                                                   0x0
16048 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT                                                              0x8
16049 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT                                                               0xa
16050 #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT                                                                      0x12
16051 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT                                                         0x13
16052 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16053 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16054 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT                                                              0x18
16055 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT                                                              0x19
16056 #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK                                                                     0x0000003FL
16057 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK                                                                0x00000300L
16058 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK                                                                 0x00000400L
16059 #define SPI_PS_INPUT_CNTL_22__DUP_MASK                                                                        0x00040000L
16060 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK                                                           0x00080000L
16061 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16062 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16063 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK                                                                0x01000000L
16064 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK                                                                0x02000000L
16065 //SPI_PS_INPUT_CNTL_23
16066 #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT                                                                   0x0
16067 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT                                                              0x8
16068 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT                                                               0xa
16069 #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT                                                                      0x12
16070 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT                                                         0x13
16071 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16072 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16073 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT                                                              0x18
16074 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT                                                              0x19
16075 #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK                                                                     0x0000003FL
16076 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK                                                                0x00000300L
16077 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK                                                                 0x00000400L
16078 #define SPI_PS_INPUT_CNTL_23__DUP_MASK                                                                        0x00040000L
16079 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK                                                           0x00080000L
16080 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16081 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16082 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK                                                                0x01000000L
16083 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK                                                                0x02000000L
16084 //SPI_PS_INPUT_CNTL_24
16085 #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT                                                                   0x0
16086 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT                                                              0x8
16087 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT                                                               0xa
16088 #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT                                                                      0x12
16089 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT                                                         0x13
16090 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16091 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16092 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT                                                              0x18
16093 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT                                                              0x19
16094 #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK                                                                     0x0000003FL
16095 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK                                                                0x00000300L
16096 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK                                                                 0x00000400L
16097 #define SPI_PS_INPUT_CNTL_24__DUP_MASK                                                                        0x00040000L
16098 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK                                                           0x00080000L
16099 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16100 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16101 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK                                                                0x01000000L
16102 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK                                                                0x02000000L
16103 //SPI_PS_INPUT_CNTL_25
16104 #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT                                                                   0x0
16105 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT                                                              0x8
16106 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT                                                               0xa
16107 #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT                                                                      0x12
16108 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT                                                         0x13
16109 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16110 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16111 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT                                                              0x18
16112 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT                                                              0x19
16113 #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK                                                                     0x0000003FL
16114 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK                                                                0x00000300L
16115 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK                                                                 0x00000400L
16116 #define SPI_PS_INPUT_CNTL_25__DUP_MASK                                                                        0x00040000L
16117 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK                                                           0x00080000L
16118 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16119 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16120 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK                                                                0x01000000L
16121 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK                                                                0x02000000L
16122 //SPI_PS_INPUT_CNTL_26
16123 #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT                                                                   0x0
16124 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT                                                              0x8
16125 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT                                                               0xa
16126 #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT                                                                      0x12
16127 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT                                                         0x13
16128 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16129 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16130 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT                                                              0x18
16131 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT                                                              0x19
16132 #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK                                                                     0x0000003FL
16133 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK                                                                0x00000300L
16134 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK                                                                 0x00000400L
16135 #define SPI_PS_INPUT_CNTL_26__DUP_MASK                                                                        0x00040000L
16136 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK                                                           0x00080000L
16137 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16138 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16139 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK                                                                0x01000000L
16140 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK                                                                0x02000000L
16141 //SPI_PS_INPUT_CNTL_27
16142 #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT                                                                   0x0
16143 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT                                                              0x8
16144 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT                                                               0xa
16145 #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT                                                                      0x12
16146 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT                                                         0x13
16147 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16148 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16149 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT                                                              0x18
16150 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT                                                              0x19
16151 #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK                                                                     0x0000003FL
16152 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK                                                                0x00000300L
16153 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK                                                                 0x00000400L
16154 #define SPI_PS_INPUT_CNTL_27__DUP_MASK                                                                        0x00040000L
16155 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK                                                           0x00080000L
16156 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16157 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16158 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK                                                                0x01000000L
16159 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK                                                                0x02000000L
16160 //SPI_PS_INPUT_CNTL_28
16161 #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT                                                                   0x0
16162 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT                                                              0x8
16163 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT                                                               0xa
16164 #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT                                                                      0x12
16165 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT                                                         0x13
16166 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16167 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16168 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT                                                              0x18
16169 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT                                                              0x19
16170 #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK                                                                     0x0000003FL
16171 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK                                                                0x00000300L
16172 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK                                                                 0x00000400L
16173 #define SPI_PS_INPUT_CNTL_28__DUP_MASK                                                                        0x00040000L
16174 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK                                                           0x00080000L
16175 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16176 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16177 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK                                                                0x01000000L
16178 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK                                                                0x02000000L
16179 //SPI_PS_INPUT_CNTL_29
16180 #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT                                                                   0x0
16181 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT                                                              0x8
16182 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT                                                               0xa
16183 #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT                                                                      0x12
16184 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT                                                         0x13
16185 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16186 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16187 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT                                                              0x18
16188 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT                                                              0x19
16189 #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK                                                                     0x0000003FL
16190 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK                                                                0x00000300L
16191 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK                                                                 0x00000400L
16192 #define SPI_PS_INPUT_CNTL_29__DUP_MASK                                                                        0x00040000L
16193 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK                                                           0x00080000L
16194 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16195 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16196 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK                                                                0x01000000L
16197 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK                                                                0x02000000L
16198 //SPI_PS_INPUT_CNTL_30
16199 #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT                                                                   0x0
16200 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT                                                              0x8
16201 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT                                                               0xa
16202 #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT                                                                      0x12
16203 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT                                                         0x13
16204 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16205 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16206 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT                                                              0x18
16207 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT                                                              0x19
16208 #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK                                                                     0x0000003FL
16209 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK                                                                0x00000300L
16210 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK                                                                 0x00000400L
16211 #define SPI_PS_INPUT_CNTL_30__DUP_MASK                                                                        0x00040000L
16212 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK                                                           0x00080000L
16213 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16214 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16215 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK                                                                0x01000000L
16216 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK                                                                0x02000000L
16217 //SPI_PS_INPUT_CNTL_31
16218 #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT                                                                   0x0
16219 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT                                                              0x8
16220 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT                                                               0xa
16221 #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT                                                                      0x12
16222 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT                                                         0x13
16223 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16224 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16225 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT                                                              0x18
16226 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT                                                              0x19
16227 #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK                                                                     0x0000003FL
16228 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK                                                                0x00000300L
16229 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK                                                                 0x00000400L
16230 #define SPI_PS_INPUT_CNTL_31__DUP_MASK                                                                        0x00040000L
16231 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK                                                           0x00080000L
16232 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16233 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16234 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK                                                                0x01000000L
16235 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK                                                                0x02000000L
16236 //SPI_VS_OUT_CONFIG
16237 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT                                                             0x1
16238 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT                                                                0x6
16239 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK                                                               0x0000003EL
16240 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK                                                                  0x00000040L
16241 //SPI_PS_INPUT_ENA
16242 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT                                                             0x0
16243 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT                                                             0x1
16244 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT                                                           0x2
16245 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT                                                         0x3
16246 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT                                                            0x4
16247 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT                                                            0x5
16248 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT                                                          0x6
16249 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT                                                         0x7
16250 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT                                                              0x8
16251 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT                                                              0x9
16252 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT                                                              0xa
16253 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT                                                              0xb
16254 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT                                                               0xc
16255 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT                                                                0xd
16256 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT                                                          0xe
16257 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT                                                             0xf
16258 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK                                                               0x00000001L
16259 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK                                                               0x00000002L
16260 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK                                                             0x00000004L
16261 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK                                                           0x00000008L
16262 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK                                                              0x00000010L
16263 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK                                                              0x00000020L
16264 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK                                                            0x00000040L
16265 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK                                                           0x00000080L
16266 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK                                                                0x00000100L
16267 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK                                                                0x00000200L
16268 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK                                                                0x00000400L
16269 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK                                                                0x00000800L
16270 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK                                                                 0x00001000L
16271 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK                                                                  0x00002000L
16272 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK                                                            0x00004000L
16273 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK                                                               0x00008000L
16274 //SPI_PS_INPUT_ADDR
16275 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT                                                            0x0
16276 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT                                                            0x1
16277 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT                                                          0x2
16278 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT                                                        0x3
16279 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT                                                           0x4
16280 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT                                                           0x5
16281 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT                                                         0x6
16282 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT                                                        0x7
16283 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT                                                             0x8
16284 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT                                                             0x9
16285 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT                                                             0xa
16286 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT                                                             0xb
16287 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT                                                              0xc
16288 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT                                                               0xd
16289 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT                                                         0xe
16290 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT                                                            0xf
16291 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK                                                              0x00000001L
16292 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK                                                              0x00000002L
16293 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK                                                            0x00000004L
16294 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK                                                          0x00000008L
16295 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK                                                             0x00000010L
16296 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK                                                             0x00000020L
16297 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK                                                           0x00000040L
16298 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK                                                          0x00000080L
16299 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK                                                               0x00000100L
16300 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK                                                               0x00000200L
16301 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK                                                               0x00000400L
16302 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK                                                               0x00000800L
16303 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK                                                                0x00001000L
16304 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK                                                                 0x00002000L
16305 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK                                                           0x00004000L
16306 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK                                                              0x00008000L
16307 //SPI_INTERP_CONTROL_0
16308 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT                                                           0x0
16309 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT                                                           0x1
16310 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT                                                        0x2
16311 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT                                                        0x5
16312 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT                                                        0x8
16313 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT                                                        0xb
16314 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT                                                         0xe
16315 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK                                                             0x00000001L
16316 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK                                                             0x00000002L
16317 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK                                                          0x0000001CL
16318 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK                                                          0x000000E0L
16319 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK                                                          0x00000700L
16320 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK                                                          0x00003800L
16321 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK                                                           0x00004000L
16322 //SPI_PS_IN_CONTROL
16323 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT                                                                  0x0
16324 #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT                                                                   0x6
16325 #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT                                                            0x7
16326 #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT                                                             0x8
16327 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT                                                         0xe
16328 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK                                                                    0x0000003FL
16329 #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK                                                                     0x00000040L
16330 #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK                                                              0x00000080L
16331 #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK                                                               0x00000100L
16332 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK                                                           0x00004000L
16333 //SPI_BARYC_CNTL
16334 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT                                                              0x0
16335 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT                                                            0x4
16336 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT                                                             0x8
16337 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT                                                           0xc
16338 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT                                                             0x10
16339 #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT                                                                  0x14
16340 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT                                                            0x18
16341 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK                                                                0x00000001L
16342 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK                                                              0x00000010L
16343 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK                                                               0x00000100L
16344 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK                                                             0x00001000L
16345 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK                                                               0x00030000L
16346 #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK                                                                    0x00100000L
16347 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK                                                              0x01000000L
16348 //SPI_TMPRING_SIZE
16349 #define SPI_TMPRING_SIZE__WAVES__SHIFT                                                                        0x0
16350 #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT                                                                     0xc
16351 #define SPI_TMPRING_SIZE__WAVES_MASK                                                                          0x00000FFFL
16352 #define SPI_TMPRING_SIZE__WAVESIZE_MASK                                                                       0x01FFF000L
16353 //SPI_SHADER_POS_FORMAT
16354 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT                                                      0x0
16355 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT                                                      0x4
16356 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT                                                      0x8
16357 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT                                                      0xc
16358 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK                                                        0x0000000FL
16359 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK                                                        0x000000F0L
16360 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK                                                        0x00000F00L
16361 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK                                                        0x0000F000L
16362 //SPI_SHADER_Z_FORMAT
16363 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT                                                           0x0
16364 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK                                                             0x0000000FL
16365 //SPI_SHADER_COL_FORMAT
16366 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT                                                      0x0
16367 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT                                                      0x4
16368 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT                                                      0x8
16369 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT                                                      0xc
16370 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT                                                      0x10
16371 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT                                                      0x14
16372 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT                                                      0x18
16373 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT                                                      0x1c
16374 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK                                                        0x0000000FL
16375 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK                                                        0x000000F0L
16376 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK                                                        0x00000F00L
16377 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK                                                        0x0000F000L
16378 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK                                                        0x000F0000L
16379 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK                                                        0x00F00000L
16380 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK                                                        0x0F000000L
16381 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK                                                        0xF0000000L
16382 //SX_PS_DOWNCONVERT
16383 #define SX_PS_DOWNCONVERT__MRT0__SHIFT                                                                        0x0
16384 #define SX_PS_DOWNCONVERT__MRT1__SHIFT                                                                        0x4
16385 #define SX_PS_DOWNCONVERT__MRT2__SHIFT                                                                        0x8
16386 #define SX_PS_DOWNCONVERT__MRT3__SHIFT                                                                        0xc
16387 #define SX_PS_DOWNCONVERT__MRT4__SHIFT                                                                        0x10
16388 #define SX_PS_DOWNCONVERT__MRT5__SHIFT                                                                        0x14
16389 #define SX_PS_DOWNCONVERT__MRT6__SHIFT                                                                        0x18
16390 #define SX_PS_DOWNCONVERT__MRT7__SHIFT                                                                        0x1c
16391 #define SX_PS_DOWNCONVERT__MRT0_MASK                                                                          0x0000000FL
16392 #define SX_PS_DOWNCONVERT__MRT1_MASK                                                                          0x000000F0L
16393 #define SX_PS_DOWNCONVERT__MRT2_MASK                                                                          0x00000F00L
16394 #define SX_PS_DOWNCONVERT__MRT3_MASK                                                                          0x0000F000L
16395 #define SX_PS_DOWNCONVERT__MRT4_MASK                                                                          0x000F0000L
16396 #define SX_PS_DOWNCONVERT__MRT5_MASK                                                                          0x00F00000L
16397 #define SX_PS_DOWNCONVERT__MRT6_MASK                                                                          0x0F000000L
16398 #define SX_PS_DOWNCONVERT__MRT7_MASK                                                                          0xF0000000L
16399 //SX_BLEND_OPT_EPSILON
16400 #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT                                                             0x0
16401 #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT                                                             0x4
16402 #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT                                                             0x8
16403 #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT                                                             0xc
16404 #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT                                                             0x10
16405 #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT                                                             0x14
16406 #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT                                                             0x18
16407 #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT                                                             0x1c
16408 #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK                                                               0x0000000FL
16409 #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK                                                               0x000000F0L
16410 #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK                                                               0x00000F00L
16411 #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK                                                               0x0000F000L
16412 #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK                                                               0x000F0000L
16413 #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK                                                               0x00F00000L
16414 #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK                                                               0x0F000000L
16415 #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK                                                               0xF0000000L
16416 //SX_BLEND_OPT_CONTROL
16417 #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT                                                   0x0
16418 #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT                                                   0x1
16419 #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT                                                   0x4
16420 #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT                                                   0x5
16421 #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT                                                   0x8
16422 #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT                                                   0x9
16423 #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT                                                   0xc
16424 #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT                                                   0xd
16425 #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT                                                   0x10
16426 #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT                                                   0x11
16427 #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT                                                   0x14
16428 #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT                                                   0x15
16429 #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT                                                   0x18
16430 #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT                                                   0x19
16431 #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT                                                   0x1c
16432 #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT                                                   0x1d
16433 #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT                                                   0x1f
16434 #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK                                                     0x00000001L
16435 #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK                                                     0x00000002L
16436 #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK                                                     0x00000010L
16437 #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK                                                     0x00000020L
16438 #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK                                                     0x00000100L
16439 #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK                                                     0x00000200L
16440 #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK                                                     0x00001000L
16441 #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK                                                     0x00002000L
16442 #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK                                                     0x00010000L
16443 #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK                                                     0x00020000L
16444 #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK                                                     0x00100000L
16445 #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK                                                     0x00200000L
16446 #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK                                                     0x01000000L
16447 #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK                                                     0x02000000L
16448 #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK                                                     0x10000000L
16449 #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK                                                     0x20000000L
16450 #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK                                                     0x80000000L
16451 //SX_MRT0_BLEND_OPT
16452 #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16453 #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16454 #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16455 #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16456 #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16457 #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16458 #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16459 #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16460 #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16461 #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16462 #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16463 #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16464 //SX_MRT1_BLEND_OPT
16465 #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16466 #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16467 #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16468 #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16469 #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16470 #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16471 #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16472 #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16473 #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16474 #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16475 #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16476 #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16477 //SX_MRT2_BLEND_OPT
16478 #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16479 #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16480 #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16481 #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16482 #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16483 #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16484 #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16485 #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16486 #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16487 #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16488 #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16489 #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16490 //SX_MRT3_BLEND_OPT
16491 #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16492 #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16493 #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16494 #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16495 #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16496 #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16497 #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16498 #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16499 #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16500 #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16501 #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16502 #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16503 //SX_MRT4_BLEND_OPT
16504 #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16505 #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16506 #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16507 #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16508 #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16509 #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16510 #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16511 #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16512 #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16513 #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16514 #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16515 #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16516 //SX_MRT5_BLEND_OPT
16517 #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16518 #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16519 #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16520 #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16521 #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16522 #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16523 #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16524 #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16525 #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16526 #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16527 #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16528 #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16529 //SX_MRT6_BLEND_OPT
16530 #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16531 #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16532 #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16533 #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16534 #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16535 #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16536 #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16537 #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16538 #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16539 #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16540 #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16541 #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16542 //SX_MRT7_BLEND_OPT
16543 #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16544 #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16545 #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16546 #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16547 #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16548 #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16549 #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16550 #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16551 #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16552 #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16553 #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16554 #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16555 //CB_BLEND0_CONTROL
16556 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16557 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16558 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16559 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16560 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16561 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16562 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16563 #define CB_BLEND0_CONTROL__ENABLE__SHIFT                                                                      0x1e
16564 #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16565 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16566 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16567 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16568 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16569 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16570 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16571 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16572 #define CB_BLEND0_CONTROL__ENABLE_MASK                                                                        0x40000000L
16573 #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16574 //CB_BLEND1_CONTROL
16575 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16576 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16577 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16578 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16579 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16580 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16581 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16582 #define CB_BLEND1_CONTROL__ENABLE__SHIFT                                                                      0x1e
16583 #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16584 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16585 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16586 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16587 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16588 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16589 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16590 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16591 #define CB_BLEND1_CONTROL__ENABLE_MASK                                                                        0x40000000L
16592 #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16593 //CB_BLEND2_CONTROL
16594 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16595 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16596 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16597 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16598 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16599 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16600 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16601 #define CB_BLEND2_CONTROL__ENABLE__SHIFT                                                                      0x1e
16602 #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16603 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16604 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16605 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16606 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16607 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16608 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16609 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16610 #define CB_BLEND2_CONTROL__ENABLE_MASK                                                                        0x40000000L
16611 #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16612 //CB_BLEND3_CONTROL
16613 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16614 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16615 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16616 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16617 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16618 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16619 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16620 #define CB_BLEND3_CONTROL__ENABLE__SHIFT                                                                      0x1e
16621 #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16622 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16623 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16624 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16625 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16626 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16627 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16628 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16629 #define CB_BLEND3_CONTROL__ENABLE_MASK                                                                        0x40000000L
16630 #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16631 //CB_BLEND4_CONTROL
16632 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16633 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16634 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16635 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16636 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16637 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16638 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16639 #define CB_BLEND4_CONTROL__ENABLE__SHIFT                                                                      0x1e
16640 #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16641 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16642 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16643 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16644 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16645 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16646 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16647 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16648 #define CB_BLEND4_CONTROL__ENABLE_MASK                                                                        0x40000000L
16649 #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16650 //CB_BLEND5_CONTROL
16651 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16652 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16653 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16654 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16655 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16656 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16657 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16658 #define CB_BLEND5_CONTROL__ENABLE__SHIFT                                                                      0x1e
16659 #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16660 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16661 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16662 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16663 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16664 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16665 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16666 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16667 #define CB_BLEND5_CONTROL__ENABLE_MASK                                                                        0x40000000L
16668 #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16669 //CB_BLEND6_CONTROL
16670 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16671 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16672 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16673 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16674 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16675 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16676 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16677 #define CB_BLEND6_CONTROL__ENABLE__SHIFT                                                                      0x1e
16678 #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16679 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16680 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16681 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16682 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16683 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16684 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16685 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16686 #define CB_BLEND6_CONTROL__ENABLE_MASK                                                                        0x40000000L
16687 #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16688 //CB_BLEND7_CONTROL
16689 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16690 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16691 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16692 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16693 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16694 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16695 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16696 #define CB_BLEND7_CONTROL__ENABLE__SHIFT                                                                      0x1e
16697 #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16698 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16699 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16700 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16701 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16702 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16703 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16704 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16705 #define CB_BLEND7_CONTROL__ENABLE_MASK                                                                        0x40000000L
16706 #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16707 //CB_MRT0_EPITCH
16708 #define CB_MRT0_EPITCH__EPITCH__SHIFT                                                                         0x0
16709 #define CB_MRT0_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16710 //CB_MRT1_EPITCH
16711 #define CB_MRT1_EPITCH__EPITCH__SHIFT                                                                         0x0
16712 #define CB_MRT1_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16713 //CB_MRT2_EPITCH
16714 #define CB_MRT2_EPITCH__EPITCH__SHIFT                                                                         0x0
16715 #define CB_MRT2_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16716 //CB_MRT3_EPITCH
16717 #define CB_MRT3_EPITCH__EPITCH__SHIFT                                                                         0x0
16718 #define CB_MRT3_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16719 //CB_MRT4_EPITCH
16720 #define CB_MRT4_EPITCH__EPITCH__SHIFT                                                                         0x0
16721 #define CB_MRT4_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16722 //CB_MRT5_EPITCH
16723 #define CB_MRT5_EPITCH__EPITCH__SHIFT                                                                         0x0
16724 #define CB_MRT5_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16725 //CB_MRT6_EPITCH
16726 #define CB_MRT6_EPITCH__EPITCH__SHIFT                                                                         0x0
16727 #define CB_MRT6_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16728 //CB_MRT7_EPITCH
16729 #define CB_MRT7_EPITCH__EPITCH__SHIFT                                                                         0x0
16730 #define CB_MRT7_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16731 //CS_COPY_STATE
16732 #define CS_COPY_STATE__SRC_STATE_ID__SHIFT                                                                    0x0
16733 #define CS_COPY_STATE__SRC_STATE_ID_MASK                                                                      0x00000007L
16734 //GFX_COPY_STATE
16735 #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                                                                   0x0
16736 #define GFX_COPY_STATE__SRC_STATE_ID_MASK                                                                     0x00000007L
16737 //PA_CL_POINT_X_RAD
16738 #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT                                                               0x0
16739 #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
16740 //PA_CL_POINT_Y_RAD
16741 #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT                                                               0x0
16742 #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
16743 //PA_CL_POINT_SIZE
16744 #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT                                                                0x0
16745 #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK                                                                  0xFFFFFFFFL
16746 //PA_CL_POINT_CULL_RAD
16747 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT                                                            0x0
16748 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK                                                              0xFFFFFFFFL
16749 //VGT_DMA_BASE_HI
16750 #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT                                                                     0x0
16751 #define VGT_DMA_BASE_HI__BASE_ADDR_MASK                                                                       0x0000FFFFL
16752 //VGT_DMA_BASE
16753 #define VGT_DMA_BASE__BASE_ADDR__SHIFT                                                                        0x0
16754 #define VGT_DMA_BASE__BASE_ADDR_MASK                                                                          0xFFFFFFFFL
16755 //VGT_DRAW_INITIATOR
16756 #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT                                                              0x0
16757 #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT                                                                 0x2
16758 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT                                                             0x4
16759 #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                                                                    0x5
16760 #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT                                                                 0x6
16761 #define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT                                                              0x7
16762 #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT                                                           0x8
16763 #define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT                                                               0x1d
16764 #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK                                                                0x00000003L
16765 #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK                                                                   0x0000000CL
16766 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK                                                               0x00000010L
16767 #define VGT_DRAW_INITIATOR__NOT_EOP_MASK                                                                      0x00000020L
16768 #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK                                                                   0x00000040L
16769 #define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK                                                                0x00000080L
16770 #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK                                                             0x00000100L
16771 #define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK                                                                 0xE0000000L
16772 //VGT_IMMED_DATA
16773 #define VGT_IMMED_DATA__DATA__SHIFT                                                                           0x0
16774 #define VGT_IMMED_DATA__DATA_MASK                                                                             0xFFFFFFFFL
16775 //VGT_EVENT_ADDRESS_REG
16776 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT                                                             0x0
16777 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK                                                               0x0FFFFFFFL
16778 //DB_DEPTH_CONTROL
16779 #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT                                                               0x0
16780 #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT                                                                     0x1
16781 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT                                                               0x2
16782 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT                                                          0x3
16783 #define DB_DEPTH_CONTROL__ZFUNC__SHIFT                                                                        0x4
16784 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT                                                              0x7
16785 #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT                                                                  0x8
16786 #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT                                                               0x14
16787 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT                                            0x1e
16788 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT                                           0x1f
16789 #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK                                                                 0x00000001L
16790 #define DB_DEPTH_CONTROL__Z_ENABLE_MASK                                                                       0x00000002L
16791 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK                                                                 0x00000004L
16792 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK                                                            0x00000008L
16793 #define DB_DEPTH_CONTROL__ZFUNC_MASK                                                                          0x00000070L
16794 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK                                                                0x00000080L
16795 #define DB_DEPTH_CONTROL__STENCILFUNC_MASK                                                                    0x00000700L
16796 #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK                                                                 0x00700000L
16797 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK                                              0x40000000L
16798 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK                                             0x80000000L
16799 //DB_EQAA
16800 #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT                                                                    0x0
16801 #define DB_EQAA__PS_ITER_SAMPLES__SHIFT                                                                       0x4
16802 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT                                                               0x8
16803 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT                                                             0xc
16804 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT                                                            0x10
16805 #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT                                                                 0x11
16806 #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT                                                                    0x12
16807 #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT                                                                     0x13
16808 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT                                                            0x14
16809 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT                                                            0x15
16810 #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT                                                              0x18
16811 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT                                                        0x1b
16812 #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK                                                                      0x00000007L
16813 #define DB_EQAA__PS_ITER_SAMPLES_MASK                                                                         0x00000070L
16814 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK                                                                 0x00000700L
16815 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK                                                               0x00007000L
16816 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK                                                              0x00010000L
16817 #define DB_EQAA__INCOHERENT_EQAA_READS_MASK                                                                   0x00020000L
16818 #define DB_EQAA__INTERPOLATE_COMP_Z_MASK                                                                      0x00040000L
16819 #define DB_EQAA__INTERPOLATE_SRC_Z_MASK                                                                       0x00080000L
16820 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK                                                              0x00100000L
16821 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK                                                              0x00200000L
16822 #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK                                                                0x07000000L
16823 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK                                                          0x08000000L
16824 //CB_COLOR_CONTROL
16825 #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT                                                            0x0
16826 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT                                                               0x3
16827 #define CB_COLOR_CONTROL__MODE__SHIFT                                                                         0x4
16828 #define CB_COLOR_CONTROL__ROP3__SHIFT                                                                         0x10
16829 #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK                                                              0x00000001L
16830 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK                                                                 0x00000008L
16831 #define CB_COLOR_CONTROL__MODE_MASK                                                                           0x00000070L
16832 #define CB_COLOR_CONTROL__ROP3_MASK                                                                           0x00FF0000L
16833 //DB_SHADER_CONTROL
16834 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT                                                             0x0
16835 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT                                              0x1
16836 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT                                                0x2
16837 #define DB_SHADER_CONTROL__Z_ORDER__SHIFT                                                                     0x4
16838 #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT                                                                 0x6
16839 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT                                                     0x7
16840 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT                                                          0x8
16841 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT                                                           0x9
16842 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT                                                                0xa
16843 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT                                                       0xb
16844 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT                                                         0xc
16845 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT                                                       0xd
16846 #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT                                                           0xf
16847 #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT                                              0x10
16848 #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT                                                          0x11
16849 #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT                                                    0x14
16850 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK                                                               0x00000001L
16851 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK                                                0x00000002L
16852 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK                                                  0x00000004L
16853 #define DB_SHADER_CONTROL__Z_ORDER_MASK                                                                       0x00000030L
16854 #define DB_SHADER_CONTROL__KILL_ENABLE_MASK                                                                   0x00000040L
16855 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK                                                       0x00000080L
16856 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK                                                            0x00000100L
16857 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK                                                             0x00000200L
16858 #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK                                                                  0x00000400L
16859 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK                                                         0x00000800L
16860 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK                                                           0x00001000L
16861 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK                                                         0x00006000L
16862 #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK                                                             0x00008000L
16863 #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK                                                0x00010000L
16864 #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK                                                            0x00020000L
16865 #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK                                                      0x00700000L
16866 //PA_CL_CLIP_CNTL
16867 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT                                                                     0x0
16868 #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT                                                                     0x1
16869 #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT                                                                     0x2
16870 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT                                                                     0x3
16871 #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT                                                                     0x4
16872 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT                                                                     0x5
16873 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT                                                            0xd
16874 #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT                                                                   0xe
16875 #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT                                                                  0x10
16876 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT                                                             0x11
16877 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT                                                        0x12
16878 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT                                                             0x13
16879 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT                                                           0x14
16880 #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                                                                   0x15
16881 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT                                                         0x16
16882 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT                                                       0x18
16883 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT                                                     0x19
16884 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT                                                            0x1a
16885 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT                                                             0x1b
16886 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK                                                                       0x00000001L
16887 #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK                                                                       0x00000002L
16888 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK                                                                       0x00000004L
16889 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK                                                                       0x00000008L
16890 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK                                                                       0x00000010L
16891 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK                                                                       0x00000020L
16892 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK                                                              0x00002000L
16893 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK                                                                     0x0000C000L
16894 #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                                                                    0x00010000L
16895 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK                                                               0x00020000L
16896 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK                                                          0x00040000L
16897 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK                                                               0x00080000L
16898 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK                                                             0x00100000L
16899 #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                                                                     0x00200000L
16900 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK                                                           0x00400000L
16901 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK                                                         0x01000000L
16902 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK                                                       0x02000000L
16903 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK                                                              0x04000000L
16904 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK                                                               0x08000000L
16905 //PA_SU_SC_MODE_CNTL
16906 #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT                                                                 0x0
16907 #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT                                                                  0x1
16908 #define PA_SU_SC_MODE_CNTL__FACE__SHIFT                                                                       0x2
16909 #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT                                                                  0x3
16910 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT                                                       0x5
16911 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT                                                        0x8
16912 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT                                                   0xb
16913 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT                                                    0xc
16914 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT                                                    0xd
16915 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT                                                   0x10
16916 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT                                                         0x13
16917 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT                                                             0x14
16918 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT                                                          0x15
16919 #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT                                      0x16
16920 #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT                                                     0x17
16921 #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                                                                   0x00000001L
16922 #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                                                                    0x00000002L
16923 #define PA_SU_SC_MODE_CNTL__FACE_MASK                                                                         0x00000004L
16924 #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                                                                    0x00000018L
16925 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK                                                         0x000000E0L
16926 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK                                                          0x00000700L
16927 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK                                                     0x00000800L
16928 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK                                                      0x00001000L
16929 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK                                                      0x00002000L
16930 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK                                                     0x00010000L
16931 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK                                                           0x00080000L
16932 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK                                                               0x00100000L
16933 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK                                                            0x00200000L
16934 #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK                                        0x00400000L
16935 #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK                                                       0x00800000L
16936 //PA_CL_VTE_CNTL
16937 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT                                                              0x0
16938 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT                                                             0x1
16939 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT                                                              0x2
16940 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT                                                             0x3
16941 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT                                                              0x4
16942 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT                                                             0x5
16943 #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                                                                     0x8
16944 #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                                                                      0x9
16945 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                                                                     0xa
16946 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT                                                                0xb
16947 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK                                                                0x00000001L
16948 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK                                                               0x00000002L
16949 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK                                                                0x00000004L
16950 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK                                                               0x00000008L
16951 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK                                                                0x00000010L
16952 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK                                                               0x00000020L
16953 #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                                                                       0x00000100L
16954 #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                                                                        0x00000200L
16955 #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                                                                       0x00000400L
16956 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK                                                                  0x00000800L
16957 //PA_CL_VS_OUT_CNTL
16958 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT                                                             0x0
16959 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT                                                             0x1
16960 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT                                                             0x2
16961 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT                                                             0x3
16962 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT                                                             0x4
16963 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT                                                             0x5
16964 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT                                                             0x6
16965 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT                                                             0x7
16966 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT                                                             0x8
16967 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT                                                             0x9
16968 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT                                                             0xa
16969 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT                                                             0xb
16970 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT                                                             0xc
16971 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT                                                             0xd
16972 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT                                                             0xe
16973 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT                                                             0xf
16974 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT                                                          0x10
16975 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT                                                           0x11
16976 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT                                                  0x12
16977 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT                                                       0x13
16978 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT                                                           0x14
16979 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT                                                         0x15
16980 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT                                                      0x16
16981 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT                                                      0x17
16982 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT                                                    0x18
16983 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT                                                         0x19
16984 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT                                                          0x1a
16985 #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT                                                      0x1b
16986 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK                                                               0x00000001L
16987 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK                                                               0x00000002L
16988 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK                                                               0x00000004L
16989 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK                                                               0x00000008L
16990 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK                                                               0x00000010L
16991 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK                                                               0x00000020L
16992 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK                                                               0x00000040L
16993 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK                                                               0x00000080L
16994 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK                                                               0x00000100L
16995 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK                                                               0x00000200L
16996 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK                                                               0x00000400L
16997 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK                                                               0x00000800L
16998 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK                                                               0x00001000L
16999 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK                                                               0x00002000L
17000 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK                                                               0x00004000L
17001 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK                                                               0x00008000L
17002 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK                                                            0x00010000L
17003 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK                                                             0x00020000L
17004 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK                                                    0x00040000L
17005 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK                                                         0x00080000L
17006 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK                                                             0x00100000L
17007 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK                                                           0x00200000L
17008 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK                                                        0x00400000L
17009 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK                                                        0x00800000L
17010 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK                                                      0x01000000L
17011 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK                                                           0x02000000L
17012 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK                                                            0x04000000L
17013 #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK                                                        0x08000000L
17014 //PA_CL_NANINF_CNTL
17015 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT                                                          0x0
17016 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT                                                           0x1
17017 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT                                                           0x2
17018 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT                                                           0x3
17019 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT                                                           0x4
17020 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT                                                            0x5
17021 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT                                                            0x6
17022 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT                                                        0x7
17023 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT                                                            0x8
17024 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT                                                            0x9
17025 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT                                                             0xa
17026 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT                                                             0xb
17027 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT                                                             0xc
17028 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT                                                             0xd
17029 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT                                                    0xe
17030 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT                                                         0x14
17031 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK                                                            0x00000001L
17032 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK                                                             0x00000002L
17033 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK                                                             0x00000004L
17034 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK                                                             0x00000008L
17035 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK                                                             0x00000010L
17036 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK                                                              0x00000020L
17037 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK                                                              0x00000040L
17038 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK                                                          0x00000080L
17039 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK                                                              0x00000100L
17040 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK                                                              0x00000200L
17041 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK                                                               0x00000400L
17042 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK                                                               0x00000800L
17043 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK                                                               0x00001000L
17044 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK                                                               0x00002000L
17045 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK                                                      0x00004000L
17046 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK                                                           0x00100000L
17047 //PA_SU_LINE_STIPPLE_CNTL
17048 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT                                                    0x0
17049 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT                                                    0x2
17050 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT                                                      0x3
17051 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT                                                        0x4
17052 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK                                                      0x00000003L
17053 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK                                                      0x00000004L
17054 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK                                                        0x00000008L
17055 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK                                                          0x00000010L
17056 //PA_SU_LINE_STIPPLE_SCALE
17057 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT                                                   0x0
17058 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK                                                     0xFFFFFFFFL
17059 //PA_SU_PRIM_FILTER_CNTL
17060 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                                0x0
17061 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                                    0x1
17062 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                                   0x2
17063 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                               0x3
17064 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT                                                    0x4
17065 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT                                                        0x5
17066 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT                                                       0x6
17067 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT                                                   0x7
17068 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT                                                   0x8
17069 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT                                                   0x1e
17070 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT                                                  0x1f
17071 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                                  0x00000001L
17072 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                      0x00000002L
17073 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                                     0x00000004L
17074 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                                 0x00000008L
17075 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK                                                      0x00000010L
17076 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK                                                          0x00000020L
17077 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK                                                         0x00000040L
17078 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK                                                     0x00000080L
17079 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK                                                     0x0000FF00L
17080 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK                                                     0x40000000L
17081 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK                                                    0x80000000L
17082 //PA_SU_SMALL_PRIM_FILTER_CNTL
17083 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT                                         0x0
17084 #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                          0x1
17085 #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                              0x2
17086 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                             0x3
17087 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                         0x4
17088 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK                                           0x00000001L
17089 #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                            0x00000002L
17090 #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                0x00000004L
17091 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                               0x00000008L
17092 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                           0x00000010L
17093 //PA_CL_OBJPRIM_ID_CNTL
17094 #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT                                                              0x0
17095 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT                                                       0x1
17096 #define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT                                                      0x2
17097 #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK                                                                0x00000001L
17098 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK                                                         0x00000002L
17099 #define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK                                                        0x00000004L
17100 //PA_CL_NGG_CNTL
17101 #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT                                                               0x0
17102 #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT                                                        0x1
17103 #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK                                                                 0x00000001L
17104 #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK                                                          0x00000002L
17105 //PA_SU_OVER_RASTERIZATION_CNTL
17106 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT                                        0x0
17107 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT                                            0x1
17108 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT                                           0x2
17109 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT                                       0x3
17110 #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT                                                0x4
17111 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK                                          0x00000001L
17112 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK                                              0x00000002L
17113 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK                                             0x00000004L
17114 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK                                         0x00000008L
17115 #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK                                                  0x00000010L
17116 //PA_SU_POINT_SIZE
17117 #define PA_SU_POINT_SIZE__HEIGHT__SHIFT                                                                       0x0
17118 #define PA_SU_POINT_SIZE__WIDTH__SHIFT                                                                        0x10
17119 #define PA_SU_POINT_SIZE__HEIGHT_MASK                                                                         0x0000FFFFL
17120 #define PA_SU_POINT_SIZE__WIDTH_MASK                                                                          0xFFFF0000L
17121 //PA_SU_POINT_MINMAX
17122 #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                                                                   0x0
17123 #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                                                                   0x10
17124 #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                                                                     0x0000FFFFL
17125 #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                                                                     0xFFFF0000L
17126 //PA_SU_LINE_CNTL
17127 #define PA_SU_LINE_CNTL__WIDTH__SHIFT                                                                         0x0
17128 #define PA_SU_LINE_CNTL__WIDTH_MASK                                                                           0x0000FFFFL
17129 //PA_SC_LINE_STIPPLE
17130 #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT                                                               0x0
17131 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT                                                               0x10
17132 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT                                                          0x1c
17133 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT                                                            0x1d
17134 #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK                                                                 0x0000FFFFL
17135 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK                                                                 0x00FF0000L
17136 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK                                                            0x10000000L
17137 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK                                                              0x60000000L
17138 //VGT_OUTPUT_PATH_CNTL
17139 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT                                                              0x0
17140 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK                                                                0x00000007L
17141 //VGT_HOS_CNTL
17142 #define VGT_HOS_CNTL__TESS_MODE__SHIFT                                                                        0x0
17143 #define VGT_HOS_CNTL__TESS_MODE_MASK                                                                          0x00000003L
17144 //VGT_HOS_MAX_TESS_LEVEL
17145 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT                                                               0x0
17146 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK                                                                 0xFFFFFFFFL
17147 //VGT_HOS_MIN_TESS_LEVEL
17148 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT                                                               0x0
17149 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK                                                                 0xFFFFFFFFL
17150 //VGT_HOS_REUSE_DEPTH
17151 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT                                                               0x0
17152 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK                                                                 0x000000FFL
17153 //VGT_GROUP_PRIM_TYPE
17154 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT                                                                 0x0
17155 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT                                                              0xe
17156 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT                                                              0xf
17157 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT                                                                0x10
17158 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK                                                                   0x0000001FL
17159 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK                                                                0x00004000L
17160 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK                                                                0x00008000L
17161 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK                                                                  0x00070000L
17162 //VGT_GROUP_FIRST_DECR
17163 #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT                                                               0x0
17164 #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK                                                                 0x0000000FL
17165 //VGT_GROUP_DECR
17166 #define VGT_GROUP_DECR__DECR__SHIFT                                                                           0x0
17167 #define VGT_GROUP_DECR__DECR_MASK                                                                             0x0000000FL
17168 //VGT_GROUP_VECT_0_CNTL
17169 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT                                                               0x0
17170 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT                                                               0x1
17171 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT                                                               0x2
17172 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT                                                               0x3
17173 #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT                                                                  0x8
17174 #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT                                                                   0x10
17175 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
17176 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
17177 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
17178 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
17179 #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK                                                                    0x0000FF00L
17180 #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK                                                                     0x00FF0000L
17181 //VGT_GROUP_VECT_1_CNTL
17182 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT                                                               0x0
17183 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT                                                               0x1
17184 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT                                                               0x2
17185 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT                                                               0x3
17186 #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT                                                                  0x8
17187 #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT                                                                   0x10
17188 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
17189 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
17190 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
17191 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
17192 #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK                                                                    0x0000FF00L
17193 #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK                                                                     0x00FF0000L
17194 //VGT_GROUP_VECT_0_FMT_CNTL
17195 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT                                                              0x0
17196 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
17197 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
17198 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
17199 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
17200 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
17201 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT                                                              0x18
17202 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
17203 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
17204 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
17205 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
17206 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
17207 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
17208 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
17209 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
17210 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
17211 //VGT_GROUP_VECT_1_FMT_CNTL
17212 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT                                                              0x0
17213 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
17214 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
17215 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
17216 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
17217 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
17218 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT                                                              0x18
17219 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
17220 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
17221 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
17222 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
17223 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
17224 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
17225 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
17226 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
17227 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
17228 //VGT_GS_MODE
17229 #define VGT_GS_MODE__MODE__SHIFT                                                                              0x0
17230 #define VGT_GS_MODE__RESERVED_0__SHIFT                                                                        0x3
17231 #define VGT_GS_MODE__CUT_MODE__SHIFT                                                                          0x4
17232 #define VGT_GS_MODE__RESERVED_1__SHIFT                                                                        0x6
17233 #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT                                                                      0xb
17234 #define VGT_GS_MODE__RESERVED_2__SHIFT                                                                        0xc
17235 #define VGT_GS_MODE__ES_PASSTHRU__SHIFT                                                                       0xd
17236 #define VGT_GS_MODE__RESERVED_3__SHIFT                                                                        0xe
17237 #define VGT_GS_MODE__RESERVED_4__SHIFT                                                                        0xf
17238 #define VGT_GS_MODE__RESERVED_5__SHIFT                                                                        0x10
17239 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT                                                                0x11
17240 #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT                                                                     0x12
17241 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT                                                                 0x13
17242 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT                                                                 0x14
17243 #define VGT_GS_MODE__ONCHIP__SHIFT                                                                            0x15
17244 #define VGT_GS_MODE__MODE_MASK                                                                                0x00000007L
17245 #define VGT_GS_MODE__RESERVED_0_MASK                                                                          0x00000008L
17246 #define VGT_GS_MODE__CUT_MODE_MASK                                                                            0x00000030L
17247 #define VGT_GS_MODE__RESERVED_1_MASK                                                                          0x000007C0L
17248 #define VGT_GS_MODE__GS_C_PACK_EN_MASK                                                                        0x00000800L
17249 #define VGT_GS_MODE__RESERVED_2_MASK                                                                          0x00001000L
17250 #define VGT_GS_MODE__ES_PASSTHRU_MASK                                                                         0x00002000L
17251 #define VGT_GS_MODE__RESERVED_3_MASK                                                                          0x00004000L
17252 #define VGT_GS_MODE__RESERVED_4_MASK                                                                          0x00008000L
17253 #define VGT_GS_MODE__RESERVED_5_MASK                                                                          0x00010000L
17254 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK                                                                  0x00020000L
17255 #define VGT_GS_MODE__SUPPRESS_CUTS_MASK                                                                       0x00040000L
17256 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK                                                                   0x00080000L
17257 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK                                                                   0x00100000L
17258 #define VGT_GS_MODE__ONCHIP_MASK                                                                              0x00600000L
17259 //VGT_GS_ONCHIP_CNTL
17260 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT                                                        0x0
17261 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT                                                        0xb
17262 #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT                                                    0x16
17263 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK                                                          0x000007FFL
17264 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK                                                          0x003FF800L
17265 #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK                                                      0xFFC00000L
17266 //PA_SC_MODE_CNTL_0
17267 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT                                                                 0x0
17268 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT                                                        0x1
17269 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT                                                         0x2
17270 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT                                                    0x3
17271 #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT                                                        0x4
17272 #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT                                                      0x5
17273 #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT                                               0x6
17274 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK                                                                   0x00000001L
17275 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK                                                          0x00000002L
17276 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK                                                           0x00000004L
17277 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK                                                      0x00000008L
17278 #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK                                                          0x00000010L
17279 #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK                                                        0x00000020L
17280 #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK                                                 0x00000040L
17281 //PA_SC_MODE_CNTL_1
17282 #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT                                                                   0x0
17283 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT                                                              0x1
17284 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT                                                    0x2
17285 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT                                                           0x3
17286 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT                                                             0x4
17287 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT                                                 0x7
17288 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT                                                      0x8
17289 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT                                                          0x9
17290 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT                                                       0xa
17291 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT                                                             0xb
17292 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT                                                             0xc
17293 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT                                                             0xd
17294 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT                                                          0xe
17295 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT                                                   0xf
17296 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT                                                              0x10
17297 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT                                     0x11
17298 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT                                                  0x12
17299 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT                                                      0x13
17300 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT                                                             0x14
17301 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT                                               0x18
17302 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT                                                     0x19
17303 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT                                                        0x1a
17304 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT                                               0x1b
17305 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT                                                     0x1c
17306 #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK                                                                     0x00000001L
17307 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK                                                                0x00000002L
17308 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK                                                      0x00000004L
17309 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK                                                             0x00000008L
17310 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK                                                               0x00000070L
17311 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK                                                   0x00000080L
17312 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK                                                        0x00000100L
17313 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK                                                            0x00000200L
17314 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK                                                         0x00000400L
17315 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK                                                               0x00000800L
17316 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK                                                               0x00001000L
17317 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK                                                               0x00002000L
17318 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK                                                            0x00004000L
17319 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK                                                     0x00008000L
17320 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK                                                                0x00010000L
17321 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK                                       0x00020000L
17322 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK                                                    0x00040000L
17323 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK                                                        0x00080000L
17324 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK                                                               0x00F00000L
17325 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK                                                 0x01000000L
17326 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK                                                       0x02000000L
17327 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK                                                          0x04000000L
17328 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK                                                 0x08000000L
17329 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK                                                       0x70000000L
17330 //VGT_ENHANCE
17331 #define VGT_ENHANCE__MISC__SHIFT                                                                              0x0
17332 #define VGT_ENHANCE__MISC_MASK                                                                                0xFFFFFFFFL
17333 //VGT_GS_PER_ES
17334 #define VGT_GS_PER_ES__GS_PER_ES__SHIFT                                                                       0x0
17335 #define VGT_GS_PER_ES__GS_PER_ES_MASK                                                                         0x000007FFL
17336 //VGT_ES_PER_GS
17337 #define VGT_ES_PER_GS__ES_PER_GS__SHIFT                                                                       0x0
17338 #define VGT_ES_PER_GS__ES_PER_GS_MASK                                                                         0x000007FFL
17339 //VGT_GS_PER_VS
17340 #define VGT_GS_PER_VS__GS_PER_VS__SHIFT                                                                       0x0
17341 #define VGT_GS_PER_VS__GS_PER_VS_MASK                                                                         0x0000000FL
17342 //VGT_GSVS_RING_OFFSET_1
17343 #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT                                                                 0x0
17344 #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK                                                                   0x00007FFFL
17345 //VGT_GSVS_RING_OFFSET_2
17346 #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT                                                                 0x0
17347 #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK                                                                   0x00007FFFL
17348 //VGT_GSVS_RING_OFFSET_3
17349 #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT                                                                 0x0
17350 #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK                                                                   0x00007FFFL
17351 //VGT_GS_OUT_PRIM_TYPE
17352 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT                                                             0x0
17353 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT                                                           0x8
17354 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT                                                           0x10
17355 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT                                                           0x16
17356 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT                                                   0x1f
17357 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK                                                               0x0000003FL
17358 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK                                                             0x00003F00L
17359 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK                                                             0x003F0000L
17360 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK                                                             0x0FC00000L
17361 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK                                                     0x80000000L
17362 //IA_ENHANCE
17363 #define IA_ENHANCE__MISC__SHIFT                                                                               0x0
17364 #define IA_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
17365 //VGT_DMA_SIZE
17366 #define VGT_DMA_SIZE__NUM_INDICES__SHIFT                                                                      0x0
17367 #define VGT_DMA_SIZE__NUM_INDICES_MASK                                                                        0xFFFFFFFFL
17368 //VGT_DMA_MAX_SIZE
17369 #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT                                                                     0x0
17370 #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK                                                                       0xFFFFFFFFL
17371 //VGT_DMA_INDEX_TYPE
17372 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                 0x0
17373 #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT                                                                  0x2
17374 #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT                                                                   0x4
17375 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT                                                               0x6
17376 #define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT                                                                 0x8
17377 #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT                                                                    0x9
17378 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT                                                                   0xa
17379 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK                                                                   0x00000003L
17380 #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK                                                                    0x0000000CL
17381 #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK                                                                     0x00000030L
17382 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK                                                                 0x00000040L
17383 #define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK                                                                   0x00000100L
17384 #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK                                                                      0x00000200L
17385 #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK                                                                     0x00000400L
17386 //WD_ENHANCE
17387 #define WD_ENHANCE__MISC__SHIFT                                                                               0x0
17388 #define WD_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
17389 //VGT_PRIMITIVEID_EN
17390 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT                                                             0x0
17391 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT                                                       0x1
17392 #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT                                                   0x2
17393 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK                                                               0x00000001L
17394 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK                                                         0x00000002L
17395 #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK                                                     0x00000004L
17396 //VGT_DMA_NUM_INSTANCES
17397 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                           0x0
17398 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK                                                             0xFFFFFFFFL
17399 //VGT_PRIMITIVEID_RESET
17400 #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT                                                                   0x0
17401 #define VGT_PRIMITIVEID_RESET__VALUE_MASK                                                                     0xFFFFFFFFL
17402 //VGT_EVENT_INITIATOR
17403 #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                                0x0
17404 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                                0xa
17405 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                            0x1b
17406 #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK                                                                  0x0000003FL
17407 #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK                                                                  0x07FFFC00L
17408 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                              0x08000000L
17409 //VGT_GS_MAX_PRIMS_PER_SUBGROUP
17410 #define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT                                          0x0
17411 #define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK                                            0x0000FFFFL
17412 //VGT_DRAW_PAYLOAD_CNTL
17413 #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT                                                           0x0
17414 #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT                                                         0x1
17415 #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT                                                      0x2
17416 #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT                                                       0x3
17417 #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK                                                             0x00000001L
17418 #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK                                                           0x00000002L
17419 #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK                                                        0x00000004L
17420 #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK                                                         0x00000008L
17421 //VGT_INSTANCE_STEP_RATE_0
17422 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT                                                            0x0
17423 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK                                                              0xFFFFFFFFL
17424 //VGT_INSTANCE_STEP_RATE_1
17425 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT                                                            0x0
17426 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK                                                              0xFFFFFFFFL
17427 //VGT_ESGS_RING_ITEMSIZE
17428 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
17429 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
17430 //VGT_GSVS_RING_ITEMSIZE
17431 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
17432 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
17433 //VGT_REUSE_OFF
17434 #define VGT_REUSE_OFF__REUSE_OFF__SHIFT                                                                       0x0
17435 #define VGT_REUSE_OFF__REUSE_OFF_MASK                                                                         0x00000001L
17436 //VGT_VTX_CNT_EN
17437 #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT                                                                     0x0
17438 #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK                                                                       0x00000001L
17439 //DB_HTILE_SURFACE
17440 #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT                                                                   0x1
17441 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT                                                       0x2
17442 #define DB_HTILE_SURFACE__PRELOAD__SHIFT                                                                      0x3
17443 #define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT                                                               0x4
17444 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT                                                              0xa
17445 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT                                                      0x10
17446 #define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT                                                                 0x12
17447 #define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT                                                                   0x13
17448 #define DB_HTILE_SURFACE__FULL_CACHE_MASK                                                                     0x00000002L
17449 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK                                                         0x00000004L
17450 #define DB_HTILE_SURFACE__PRELOAD_MASK                                                                        0x00000008L
17451 #define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK                                                                 0x000003F0L
17452 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK                                                                0x0000FC00L
17453 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK                                                        0x00010000L
17454 #define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK                                                                   0x00040000L
17455 #define DB_HTILE_SURFACE__RB_ALIGNED_MASK                                                                     0x00080000L
17456 //DB_SRESULTS_COMPARE_STATE0
17457 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT                                                       0x0
17458 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT                                                      0x4
17459 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT                                                       0xc
17460 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT                                                            0x18
17461 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK                                                         0x00000007L
17462 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK                                                        0x00000FF0L
17463 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK                                                         0x000FF000L
17464 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK                                                              0x01000000L
17465 //DB_SRESULTS_COMPARE_STATE1
17466 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT                                                       0x0
17467 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT                                                      0x4
17468 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT                                                       0xc
17469 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT                                                            0x18
17470 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK                                                         0x00000007L
17471 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK                                                        0x00000FF0L
17472 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK                                                         0x000FF000L
17473 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK                                                              0x01000000L
17474 //DB_PRELOAD_CONTROL
17475 #define DB_PRELOAD_CONTROL__START_X__SHIFT                                                                    0x0
17476 #define DB_PRELOAD_CONTROL__START_Y__SHIFT                                                                    0x8
17477 #define DB_PRELOAD_CONTROL__MAX_X__SHIFT                                                                      0x10
17478 #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT                                                                      0x18
17479 #define DB_PRELOAD_CONTROL__START_X_MASK                                                                      0x000000FFL
17480 #define DB_PRELOAD_CONTROL__START_Y_MASK                                                                      0x0000FF00L
17481 #define DB_PRELOAD_CONTROL__MAX_X_MASK                                                                        0x00FF0000L
17482 #define DB_PRELOAD_CONTROL__MAX_Y_MASK                                                                        0xFF000000L
17483 //VGT_STRMOUT_BUFFER_SIZE_0
17484 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT                                                                0x0
17485 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK                                                                  0xFFFFFFFFL
17486 //VGT_STRMOUT_VTX_STRIDE_0
17487 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT                                                               0x0
17488 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK                                                                 0x000003FFL
17489 //VGT_STRMOUT_BUFFER_OFFSET_0
17490 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT                                                            0x0
17491 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK                                                              0xFFFFFFFFL
17492 //VGT_STRMOUT_BUFFER_SIZE_1
17493 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT                                                                0x0
17494 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK                                                                  0xFFFFFFFFL
17495 //VGT_STRMOUT_VTX_STRIDE_1
17496 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT                                                               0x0
17497 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK                                                                 0x000003FFL
17498 //VGT_STRMOUT_BUFFER_OFFSET_1
17499 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT                                                            0x0
17500 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK                                                              0xFFFFFFFFL
17501 //VGT_STRMOUT_BUFFER_SIZE_2
17502 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT                                                                0x0
17503 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK                                                                  0xFFFFFFFFL
17504 //VGT_STRMOUT_VTX_STRIDE_2
17505 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT                                                               0x0
17506 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK                                                                 0x000003FFL
17507 //VGT_STRMOUT_BUFFER_OFFSET_2
17508 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT                                                            0x0
17509 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK                                                              0xFFFFFFFFL
17510 //VGT_STRMOUT_BUFFER_SIZE_3
17511 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT                                                                0x0
17512 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK                                                                  0xFFFFFFFFL
17513 //VGT_STRMOUT_VTX_STRIDE_3
17514 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT                                                               0x0
17515 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK                                                                 0x000003FFL
17516 //VGT_STRMOUT_BUFFER_OFFSET_3
17517 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT                                                            0x0
17518 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK                                                              0xFFFFFFFFL
17519 //VGT_STRMOUT_DRAW_OPAQUE_OFFSET
17520 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT                                                         0x0
17521 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
17522 //VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
17523 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT                                               0x0
17524 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK                                                 0xFFFFFFFFL
17525 //VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
17526 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT                                           0x0
17527 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK                                             0x000001FFL
17528 //VGT_GS_MAX_VERT_OUT
17529 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT                                                              0x0
17530 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK                                                                0x000007FFL
17531 //VGT_TESS_DISTRIBUTION
17532 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT                                                           0x0
17533 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT                                                               0x8
17534 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT                                                              0x10
17535 #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT                                                             0x18
17536 #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT                                                              0x1d
17537 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK                                                             0x000000FFL
17538 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK                                                                 0x0000FF00L
17539 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK                                                                0x00FF0000L
17540 #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK                                                               0x1F000000L
17541 #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK                                                                0xE0000000L
17542 //VGT_SHADER_STAGES_EN
17543 #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT                                                                    0x0
17544 #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT                                                                    0x2
17545 #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT                                                                    0x3
17546 #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT                                                                    0x5
17547 #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT                                                                    0x6
17548 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT                                                         0x9
17549 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT                                                      0xa
17550 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT                                                      0xb
17551 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT                                                            0xc
17552 #define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT                                                               0xd
17553 #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT                                                          0xe
17554 #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT                                                      0xf
17555 #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT                                                           0x13
17556 #define VGT_SHADER_STAGES_EN__LS_EN_MASK                                                                      0x00000003L
17557 #define VGT_SHADER_STAGES_EN__HS_EN_MASK                                                                      0x00000004L
17558 #define VGT_SHADER_STAGES_EN__ES_EN_MASK                                                                      0x00000018L
17559 #define VGT_SHADER_STAGES_EN__GS_EN_MASK                                                                      0x00000020L
17560 #define VGT_SHADER_STAGES_EN__VS_EN_MASK                                                                      0x000000C0L
17561 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK                                                           0x00000200L
17562 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK                                                        0x00000400L
17563 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK                                                        0x00000800L
17564 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK                                                              0x00001000L
17565 #define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK                                                                 0x00002000L
17566 #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK                                                            0x00004000L
17567 #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK                                                        0x00078000L
17568 #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK                                                             0x00080000L
17569 //VGT_LS_HS_CONFIG
17570 #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT                                                                  0x0
17571 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                              0x8
17572 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT                                                             0xe
17573 #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK                                                                    0x000000FFL
17574 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                                0x00003F00L
17575 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK                                                               0x000FC000L
17576 //VGT_GS_VERT_ITEMSIZE
17577 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT                                                                 0x0
17578 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK                                                                   0x00007FFFL
17579 //VGT_GS_VERT_ITEMSIZE_1
17580 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT                                                               0x0
17581 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK                                                                 0x00007FFFL
17582 //VGT_GS_VERT_ITEMSIZE_2
17583 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT                                                               0x0
17584 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK                                                                 0x00007FFFL
17585 //VGT_GS_VERT_ITEMSIZE_3
17586 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT                                                               0x0
17587 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK                                                                 0x00007FFFL
17588 //VGT_TF_PARAM
17589 #define VGT_TF_PARAM__TYPE__SHIFT                                                                             0x0
17590 #define VGT_TF_PARAM__PARTITIONING__SHIFT                                                                     0x2
17591 #define VGT_TF_PARAM__TOPOLOGY__SHIFT                                                                         0x5
17592 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT                                                              0x8
17593 #define VGT_TF_PARAM__DEPRECATED__SHIFT                                                                       0x9
17594 #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT                                                                   0xe
17595 #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT                                                                     0xf
17596 #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT                                                                0x11
17597 #define VGT_TF_PARAM__TYPE_MASK                                                                               0x00000003L
17598 #define VGT_TF_PARAM__PARTITIONING_MASK                                                                       0x0000001CL
17599 #define VGT_TF_PARAM__TOPOLOGY_MASK                                                                           0x000000E0L
17600 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK                                                                0x00000100L
17601 #define VGT_TF_PARAM__DEPRECATED_MASK                                                                         0x00000200L
17602 #define VGT_TF_PARAM__DISABLE_DONUTS_MASK                                                                     0x00004000L
17603 #define VGT_TF_PARAM__RDREQ_POLICY_MASK                                                                       0x00008000L
17604 #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK                                                                  0x00060000L
17605 //DB_ALPHA_TO_MASK
17606 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT                                                         0x0
17607 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT                                                        0x8
17608 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT                                                        0xa
17609 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT                                                        0xc
17610 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT                                                        0xe
17611 #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT                                                                 0x10
17612 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK                                                           0x00000001L
17613 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK                                                          0x00000300L
17614 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK                                                          0x00000C00L
17615 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK                                                          0x00003000L
17616 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK                                                          0x0000C000L
17617 #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK                                                                   0x00010000L
17618 //VGT_DISPATCH_DRAW_INDEX
17619 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT                                                           0x0
17620 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK                                                             0xFFFFFFFFL
17621 //PA_SU_POLY_OFFSET_DB_FMT_CNTL
17622 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT                                     0x0
17623 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT                                     0x8
17624 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK                                       0x000000FFL
17625 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK                                       0x00000100L
17626 //PA_SU_POLY_OFFSET_CLAMP
17627 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT                                                                 0x0
17628 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK                                                                   0xFFFFFFFFL
17629 //PA_SU_POLY_OFFSET_FRONT_SCALE
17630 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT                                                           0x0
17631 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK                                                             0xFFFFFFFFL
17632 //PA_SU_POLY_OFFSET_FRONT_OFFSET
17633 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT                                                         0x0
17634 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
17635 //PA_SU_POLY_OFFSET_BACK_SCALE
17636 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT                                                            0x0
17637 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK                                                              0xFFFFFFFFL
17638 //PA_SU_POLY_OFFSET_BACK_OFFSET
17639 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT                                                          0x0
17640 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK                                                            0xFFFFFFFFL
17641 //VGT_GS_INSTANCE_CNT
17642 #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT                                                                    0x0
17643 #define VGT_GS_INSTANCE_CNT__CNT__SHIFT                                                                       0x2
17644 #define VGT_GS_INSTANCE_CNT__ENABLE_MASK                                                                      0x00000001L
17645 #define VGT_GS_INSTANCE_CNT__CNT_MASK                                                                         0x000001FCL
17646 //VGT_STRMOUT_CONFIG
17647 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT                                                             0x0
17648 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT                                                             0x1
17649 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT                                                             0x2
17650 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT                                                             0x3
17651 #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT                                                                0x4
17652 #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT                                                        0x7
17653 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT                                                           0x8
17654 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT                                                       0x1f
17655 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK                                                               0x00000001L
17656 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK                                                               0x00000002L
17657 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK                                                               0x00000004L
17658 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK                                                               0x00000008L
17659 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK                                                                  0x00000070L
17660 #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK                                                          0x00000080L
17661 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK                                                             0x00000F00L
17662 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK                                                         0x80000000L
17663 //VGT_STRMOUT_BUFFER_CONFIG
17664 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT                                                  0x0
17665 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT                                                  0x4
17666 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT                                                  0x8
17667 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT                                                  0xc
17668 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK                                                    0x0000000FL
17669 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK                                                    0x000000F0L
17670 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK                                                    0x00000F00L
17671 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK                                                    0x0000F000L
17672 //VGT_DMA_EVENT_INITIATOR
17673 #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                            0x0
17674 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                            0xa
17675 #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                        0x1b
17676 #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK                                                              0x0000003FL
17677 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK                                                              0x07FFFC00L
17678 #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                          0x08000000L
17679 //PA_SC_CENTROID_PRIORITY_0
17680 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT                                                          0x0
17681 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT                                                          0x4
17682 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT                                                          0x8
17683 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT                                                          0xc
17684 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT                                                          0x10
17685 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT                                                          0x14
17686 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT                                                          0x18
17687 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT                                                          0x1c
17688 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK                                                            0x0000000FL
17689 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK                                                            0x000000F0L
17690 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK                                                            0x00000F00L
17691 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK                                                            0x0000F000L
17692 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK                                                            0x000F0000L
17693 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK                                                            0x00F00000L
17694 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK                                                            0x0F000000L
17695 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK                                                            0xF0000000L
17696 //PA_SC_CENTROID_PRIORITY_1
17697 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT                                                          0x0
17698 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT                                                          0x4
17699 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT                                                         0x8
17700 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT                                                         0xc
17701 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT                                                         0x10
17702 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT                                                         0x14
17703 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT                                                         0x18
17704 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT                                                         0x1c
17705 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK                                                            0x0000000FL
17706 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK                                                            0x000000F0L
17707 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK                                                           0x00000F00L
17708 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK                                                           0x0000F000L
17709 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK                                                           0x000F0000L
17710 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK                                                           0x00F00000L
17711 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK                                                           0x0F000000L
17712 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK                                                           0xF0000000L
17713 //PA_SC_LINE_CNTL
17714 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT                                                             0x9
17715 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                                                                    0xa
17716 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT                                                      0xb
17717 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT                                                         0xc
17718 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK                                                               0x00000200L
17719 #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                                                                      0x00000400L
17720 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK                                                        0x00000800L
17721 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK                                                           0x00001000L
17722 //PA_SC_AA_CONFIG
17723 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT                                                              0x0
17724 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT                                                         0x4
17725 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT                                                               0xd
17726 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT                                                          0x14
17727 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT                                                        0x18
17728 #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT                                                     0x1a
17729 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK                                                                0x00000007L
17730 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK                                                           0x00000010L
17731 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK                                                                 0x0001E000L
17732 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK                                                            0x00700000L
17733 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK                                                          0x03000000L
17734 #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK                                                       0x0C000000L
17735 //PA_SU_VTX_CNTL
17736 #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                                                                     0x0
17737 #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                                                                     0x1
17738 #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                                                                     0x3
17739 #define PA_SU_VTX_CNTL__PIX_CENTER_MASK                                                                       0x00000001L
17740 #define PA_SU_VTX_CNTL__ROUND_MODE_MASK                                                                       0x00000006L
17741 #define PA_SU_VTX_CNTL__QUANT_MODE_MASK                                                                       0x00000038L
17742 //PA_CL_GB_VERT_CLIP_ADJ
17743 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
17744 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
17745 //PA_CL_GB_VERT_DISC_ADJ
17746 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
17747 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
17748 //PA_CL_GB_HORZ_CLIP_ADJ
17749 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
17750 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
17751 //PA_CL_GB_HORZ_DISC_ADJ
17752 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
17753 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
17754 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
17755 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT                                                        0x0
17756 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT                                                        0x4
17757 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT                                                        0x8
17758 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT                                                        0xc
17759 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT                                                        0x10
17760 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT                                                        0x14
17761 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT                                                        0x18
17762 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT                                                        0x1c
17763 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK                                                          0x0000000FL
17764 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK                                                          0x000000F0L
17765 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK                                                          0x00000F00L
17766 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK                                                          0x0000F000L
17767 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK                                                          0x000F0000L
17768 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK                                                          0x00F00000L
17769 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK                                                          0x0F000000L
17770 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK                                                          0xF0000000L
17771 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
17772 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT                                                        0x0
17773 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT                                                        0x4
17774 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT                                                        0x8
17775 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT                                                        0xc
17776 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT                                                        0x10
17777 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT                                                        0x14
17778 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT                                                        0x18
17779 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT                                                        0x1c
17780 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK                                                          0x0000000FL
17781 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK                                                          0x000000F0L
17782 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK                                                          0x00000F00L
17783 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK                                                          0x0000F000L
17784 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK                                                          0x000F0000L
17785 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK                                                          0x00F00000L
17786 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK                                                          0x0F000000L
17787 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK                                                          0xF0000000L
17788 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
17789 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT                                                        0x0
17790 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT                                                        0x4
17791 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT                                                        0x8
17792 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT                                                        0xc
17793 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT                                                       0x10
17794 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT                                                       0x14
17795 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT                                                       0x18
17796 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT                                                       0x1c
17797 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK                                                          0x0000000FL
17798 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK                                                          0x000000F0L
17799 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK                                                          0x00000F00L
17800 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK                                                          0x0000F000L
17801 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK                                                         0x000F0000L
17802 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK                                                         0x00F00000L
17803 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK                                                         0x0F000000L
17804 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK                                                         0xF0000000L
17805 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
17806 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT                                                       0x0
17807 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT                                                       0x4
17808 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT                                                       0x8
17809 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT                                                       0xc
17810 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT                                                       0x10
17811 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT                                                       0x14
17812 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT                                                       0x18
17813 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT                                                       0x1c
17814 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK                                                         0x0000000FL
17815 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK                                                         0x000000F0L
17816 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK                                                         0x00000F00L
17817 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK                                                         0x0000F000L
17818 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK                                                         0x000F0000L
17819 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK                                                         0x00F00000L
17820 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK                                                         0x0F000000L
17821 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK                                                         0xF0000000L
17822 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
17823 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT                                                        0x0
17824 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT                                                        0x4
17825 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT                                                        0x8
17826 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT                                                        0xc
17827 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT                                                        0x10
17828 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT                                                        0x14
17829 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT                                                        0x18
17830 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT                                                        0x1c
17831 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK                                                          0x0000000FL
17832 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK                                                          0x000000F0L
17833 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK                                                          0x00000F00L
17834 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK                                                          0x0000F000L
17835 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK                                                          0x000F0000L
17836 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK                                                          0x00F00000L
17837 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK                                                          0x0F000000L
17838 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK                                                          0xF0000000L
17839 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
17840 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT                                                        0x0
17841 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT                                                        0x4
17842 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT                                                        0x8
17843 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT                                                        0xc
17844 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT                                                        0x10
17845 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT                                                        0x14
17846 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT                                                        0x18
17847 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT                                                        0x1c
17848 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK                                                          0x0000000FL
17849 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK                                                          0x000000F0L
17850 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK                                                          0x00000F00L
17851 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK                                                          0x0000F000L
17852 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK                                                          0x000F0000L
17853 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK                                                          0x00F00000L
17854 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK                                                          0x0F000000L
17855 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK                                                          0xF0000000L
17856 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
17857 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT                                                        0x0
17858 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT                                                        0x4
17859 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT                                                        0x8
17860 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT                                                        0xc
17861 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT                                                       0x10
17862 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT                                                       0x14
17863 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT                                                       0x18
17864 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT                                                       0x1c
17865 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK                                                          0x0000000FL
17866 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK                                                          0x000000F0L
17867 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK                                                          0x00000F00L
17868 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK                                                          0x0000F000L
17869 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK                                                         0x000F0000L
17870 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK                                                         0x00F00000L
17871 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK                                                         0x0F000000L
17872 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK                                                         0xF0000000L
17873 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
17874 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT                                                       0x0
17875 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT                                                       0x4
17876 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT                                                       0x8
17877 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT                                                       0xc
17878 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT                                                       0x10
17879 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT                                                       0x14
17880 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT                                                       0x18
17881 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT                                                       0x1c
17882 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK                                                         0x0000000FL
17883 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK                                                         0x000000F0L
17884 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK                                                         0x00000F00L
17885 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK                                                         0x0000F000L
17886 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK                                                         0x000F0000L
17887 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK                                                         0x00F00000L
17888 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK                                                         0x0F000000L
17889 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK                                                         0xF0000000L
17890 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
17891 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT                                                        0x0
17892 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT                                                        0x4
17893 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT                                                        0x8
17894 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT                                                        0xc
17895 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT                                                        0x10
17896 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT                                                        0x14
17897 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT                                                        0x18
17898 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT                                                        0x1c
17899 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK                                                          0x0000000FL
17900 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK                                                          0x000000F0L
17901 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK                                                          0x00000F00L
17902 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK                                                          0x0000F000L
17903 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK                                                          0x000F0000L
17904 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK                                                          0x00F00000L
17905 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK                                                          0x0F000000L
17906 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK                                                          0xF0000000L
17907 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
17908 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT                                                        0x0
17909 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT                                                        0x4
17910 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT                                                        0x8
17911 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT                                                        0xc
17912 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT                                                        0x10
17913 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT                                                        0x14
17914 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT                                                        0x18
17915 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT                                                        0x1c
17916 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK                                                          0x0000000FL
17917 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK                                                          0x000000F0L
17918 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK                                                          0x00000F00L
17919 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK                                                          0x0000F000L
17920 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK                                                          0x000F0000L
17921 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK                                                          0x00F00000L
17922 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK                                                          0x0F000000L
17923 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK                                                          0xF0000000L
17924 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
17925 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT                                                        0x0
17926 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT                                                        0x4
17927 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT                                                        0x8
17928 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT                                                        0xc
17929 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT                                                       0x10
17930 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT                                                       0x14
17931 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT                                                       0x18
17932 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT                                                       0x1c
17933 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK                                                          0x0000000FL
17934 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK                                                          0x000000F0L
17935 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK                                                          0x00000F00L
17936 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK                                                          0x0000F000L
17937 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK                                                         0x000F0000L
17938 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK                                                         0x00F00000L
17939 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK                                                         0x0F000000L
17940 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK                                                         0xF0000000L
17941 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
17942 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT                                                       0x0
17943 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT                                                       0x4
17944 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT                                                       0x8
17945 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT                                                       0xc
17946 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT                                                       0x10
17947 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT                                                       0x14
17948 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT                                                       0x18
17949 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT                                                       0x1c
17950 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK                                                         0x0000000FL
17951 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK                                                         0x000000F0L
17952 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK                                                         0x00000F00L
17953 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK                                                         0x0000F000L
17954 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK                                                         0x000F0000L
17955 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK                                                         0x00F00000L
17956 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK                                                         0x0F000000L
17957 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK                                                         0xF0000000L
17958 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
17959 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT                                                        0x0
17960 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT                                                        0x4
17961 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT                                                        0x8
17962 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT                                                        0xc
17963 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT                                                        0x10
17964 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT                                                        0x14
17965 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT                                                        0x18
17966 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT                                                        0x1c
17967 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK                                                          0x0000000FL
17968 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK                                                          0x000000F0L
17969 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK                                                          0x00000F00L
17970 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK                                                          0x0000F000L
17971 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK                                                          0x000F0000L
17972 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK                                                          0x00F00000L
17973 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK                                                          0x0F000000L
17974 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK                                                          0xF0000000L
17975 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
17976 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT                                                        0x0
17977 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT                                                        0x4
17978 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT                                                        0x8
17979 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT                                                        0xc
17980 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT                                                        0x10
17981 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT                                                        0x14
17982 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT                                                        0x18
17983 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT                                                        0x1c
17984 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK                                                          0x0000000FL
17985 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK                                                          0x000000F0L
17986 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK                                                          0x00000F00L
17987 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK                                                          0x0000F000L
17988 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK                                                          0x000F0000L
17989 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK                                                          0x00F00000L
17990 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK                                                          0x0F000000L
17991 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK                                                          0xF0000000L
17992 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
17993 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT                                                        0x0
17994 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT                                                        0x4
17995 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT                                                        0x8
17996 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT                                                        0xc
17997 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT                                                       0x10
17998 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT                                                       0x14
17999 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT                                                       0x18
18000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT                                                       0x1c
18001 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK                                                          0x0000000FL
18002 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK                                                          0x000000F0L
18003 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK                                                          0x00000F00L
18004 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK                                                          0x0000F000L
18005 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK                                                         0x000F0000L
18006 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK                                                         0x00F00000L
18007 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK                                                         0x0F000000L
18008 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK                                                         0xF0000000L
18009 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
18010 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT                                                       0x0
18011 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT                                                       0x4
18012 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT                                                       0x8
18013 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT                                                       0xc
18014 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT                                                       0x10
18015 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT                                                       0x14
18016 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT                                                       0x18
18017 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT                                                       0x1c
18018 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK                                                         0x0000000FL
18019 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK                                                         0x000000F0L
18020 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK                                                         0x00000F00L
18021 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK                                                         0x0000F000L
18022 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK                                                         0x000F0000L
18023 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK                                                         0x00F00000L
18024 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK                                                         0x0F000000L
18025 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK                                                         0xF0000000L
18026 //PA_SC_AA_MASK_X0Y0_X1Y0
18027 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT                                                          0x0
18028 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT                                                          0x10
18029 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK                                                            0x0000FFFFL
18030 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK                                                            0xFFFF0000L
18031 //PA_SC_AA_MASK_X0Y1_X1Y1
18032 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT                                                          0x0
18033 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT                                                          0x10
18034 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK                                                            0x0000FFFFL
18035 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK                                                            0xFFFF0000L
18036 //PA_SC_SHADER_CONTROL
18037 #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT                                             0x0
18038 #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT                                                    0x2
18039 #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT                                                 0x3
18040 #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK                                               0x00000003L
18041 #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK                                                      0x00000004L
18042 #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK                                                   0x00000008L
18043 //PA_SC_BINNER_CNTL_0
18044 #define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT                                                              0x0
18045 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT                                                                0x2
18046 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT                                                                0x3
18047 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT                                                         0x4
18048 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT                                                         0x7
18049 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT                                                    0xa
18050 #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT                                                 0xd
18051 #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT                                                     0x12
18052 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT                                                           0x13
18053 #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT                                                     0x1b
18054 #define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK                                                                0x00000003L
18055 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK                                                                  0x00000004L
18056 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK                                                                  0x00000008L
18057 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK                                                           0x00000070L
18058 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK                                                           0x00000380L
18059 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK                                                      0x00001C00L
18060 #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK                                                   0x0003E000L
18061 #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK                                                       0x00040000L
18062 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK                                                             0x07F80000L
18063 #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK                                                       0x08000000L
18064 //PA_SC_BINNER_CNTL_1
18065 #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT                                                           0x0
18066 #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT                                                        0x10
18067 #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK                                                             0x0000FFFFL
18068 #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK                                                          0xFFFF0000L
18069 //PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
18070 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT                                        0x0
18071 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT                                 0x1
18072 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT                                       0x5
18073 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT                                0x6
18074 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT                           0xa
18075 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT                                          0xb
18076 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT                                          0xc
18077 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT                      0xd
18078 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT                     0xe
18079 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT             0xf
18080 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT                                 0x10
18081 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x12
18082 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x13
18083 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT                               0x14
18084 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT                                 0x15
18085 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT                                     0x16
18086 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT                                    0x17
18087 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT                                0x18
18088 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK                                          0x00000001L
18089 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK                                   0x0000001EL
18090 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK                                         0x00000020L
18091 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK                                  0x000003C0L
18092 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK                             0x00000400L
18093 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK                                            0x00000800L
18094 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK                                            0x00001000L
18095 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK                        0x00002000L
18096 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK                       0x00004000L
18097 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK               0x00008000L
18098 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK                                   0x00030000L
18099 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00040000L
18100 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00080000L
18101 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK                                 0x00100000L
18102 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK                                   0x00200000L
18103 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK                                       0x00400000L
18104 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK                                      0x00800000L
18105 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK                                  0x01000000L
18106 //PA_SC_NGG_MODE_CNTL
18107 #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT                                                      0x0
18108 #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK                                                        0x000007FFL
18109 //VGT_VERTEX_REUSE_BLOCK_CNTL
18110 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT                                                   0x0
18111 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK                                                     0x000000FFL
18112 //VGT_OUT_DEALLOC_CNTL
18113 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT                                                             0x0
18114 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK                                                               0x0000007FL
18115 //CB_COLOR0_BASE
18116 #define CB_COLOR0_BASE__BASE_256B__SHIFT                                                                      0x0
18117 #define CB_COLOR0_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18118 //CB_COLOR0_BASE_EXT
18119 #define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18120 #define CB_COLOR0_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18121 //CB_COLOR0_ATTRIB2
18122 #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18123 #define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18124 #define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18125 #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18126 #define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18127 #define CB_COLOR0_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18128 //CB_COLOR0_VIEW
18129 #define CB_COLOR0_VIEW__SLICE_START__SHIFT                                                                    0x0
18130 #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18131 #define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18132 #define CB_COLOR0_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18133 #define CB_COLOR0_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18134 #define CB_COLOR0_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18135 //CB_COLOR0_INFO
18136 #define CB_COLOR0_INFO__ENDIAN__SHIFT                                                                         0x0
18137 #define CB_COLOR0_INFO__FORMAT__SHIFT                                                                         0x2
18138 #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18139 #define CB_COLOR0_INFO__COMP_SWAP__SHIFT                                                                      0xb
18140 #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18141 #define CB_COLOR0_INFO__COMPRESSION__SHIFT                                                                    0xe
18142 #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18143 #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18144 #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18145 #define CB_COLOR0_INFO__ROUND_MODE__SHIFT                                                                     0x12
18146 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18147 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18148 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18149 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18150 #define CB_COLOR0_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18151 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18152 #define CB_COLOR0_INFO__ENDIAN_MASK                                                                           0x00000003L
18153 #define CB_COLOR0_INFO__FORMAT_MASK                                                                           0x0000007CL
18154 #define CB_COLOR0_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18155 #define CB_COLOR0_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18156 #define CB_COLOR0_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18157 #define CB_COLOR0_INFO__COMPRESSION_MASK                                                                      0x00004000L
18158 #define CB_COLOR0_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18159 #define CB_COLOR0_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18160 #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18161 #define CB_COLOR0_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18162 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18163 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18164 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18165 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18166 #define CB_COLOR0_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18167 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18168 //CB_COLOR0_ATTRIB
18169 #define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18170 #define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18171 #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18172 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18173 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18174 #define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18175 #define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18176 #define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18177 #define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18178 #define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18179 #define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18180 #define CB_COLOR0_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18181 #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18182 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18183 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18184 #define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18185 #define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18186 #define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18187 #define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18188 #define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18189 //CB_COLOR0_DCC_CONTROL
18190 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18191 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18192 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18193 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18194 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18195 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18196 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18197 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18198 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18199 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18200 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18201 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18202 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18203 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18204 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18205 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18206 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18207 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18208 //CB_COLOR0_CMASK
18209 #define CB_COLOR0_CMASK__BASE_256B__SHIFT                                                                     0x0
18210 #define CB_COLOR0_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18211 //CB_COLOR0_CMASK_BASE_EXT
18212 #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18213 #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18214 //CB_COLOR0_FMASK
18215 #define CB_COLOR0_FMASK__BASE_256B__SHIFT                                                                     0x0
18216 #define CB_COLOR0_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18217 //CB_COLOR0_FMASK_BASE_EXT
18218 #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18219 #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18220 //CB_COLOR0_CLEAR_WORD0
18221 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18222 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18223 //CB_COLOR0_CLEAR_WORD1
18224 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18225 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18226 //CB_COLOR0_DCC_BASE
18227 #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18228 #define CB_COLOR0_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18229 //CB_COLOR0_DCC_BASE_EXT
18230 #define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18231 #define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18232 //CB_COLOR1_BASE
18233 #define CB_COLOR1_BASE__BASE_256B__SHIFT                                                                      0x0
18234 #define CB_COLOR1_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18235 //CB_COLOR1_BASE_EXT
18236 #define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18237 #define CB_COLOR1_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18238 //CB_COLOR1_ATTRIB2
18239 #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18240 #define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18241 #define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18242 #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18243 #define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18244 #define CB_COLOR1_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18245 //CB_COLOR1_VIEW
18246 #define CB_COLOR1_VIEW__SLICE_START__SHIFT                                                                    0x0
18247 #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18248 #define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18249 #define CB_COLOR1_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18250 #define CB_COLOR1_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18251 #define CB_COLOR1_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18252 //CB_COLOR1_INFO
18253 #define CB_COLOR1_INFO__ENDIAN__SHIFT                                                                         0x0
18254 #define CB_COLOR1_INFO__FORMAT__SHIFT                                                                         0x2
18255 #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18256 #define CB_COLOR1_INFO__COMP_SWAP__SHIFT                                                                      0xb
18257 #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18258 #define CB_COLOR1_INFO__COMPRESSION__SHIFT                                                                    0xe
18259 #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18260 #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18261 #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18262 #define CB_COLOR1_INFO__ROUND_MODE__SHIFT                                                                     0x12
18263 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18264 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18265 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18266 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18267 #define CB_COLOR1_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18268 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18269 #define CB_COLOR1_INFO__ENDIAN_MASK                                                                           0x00000003L
18270 #define CB_COLOR1_INFO__FORMAT_MASK                                                                           0x0000007CL
18271 #define CB_COLOR1_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18272 #define CB_COLOR1_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18273 #define CB_COLOR1_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18274 #define CB_COLOR1_INFO__COMPRESSION_MASK                                                                      0x00004000L
18275 #define CB_COLOR1_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18276 #define CB_COLOR1_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18277 #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18278 #define CB_COLOR1_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18279 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18280 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18281 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18282 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18283 #define CB_COLOR1_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18284 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18285 //CB_COLOR1_ATTRIB
18286 #define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18287 #define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18288 #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18289 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18290 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18291 #define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18292 #define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18293 #define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18294 #define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18295 #define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18296 #define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18297 #define CB_COLOR1_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18298 #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18299 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18300 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18301 #define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18302 #define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18303 #define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18304 #define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18305 #define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18306 //CB_COLOR1_DCC_CONTROL
18307 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18308 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18309 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18310 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18311 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18312 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18313 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18314 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18315 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18316 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18317 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18318 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18319 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18320 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18321 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18322 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18323 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18324 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18325 //CB_COLOR1_CMASK
18326 #define CB_COLOR1_CMASK__BASE_256B__SHIFT                                                                     0x0
18327 #define CB_COLOR1_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18328 //CB_COLOR1_CMASK_BASE_EXT
18329 #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18330 #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18331 //CB_COLOR1_FMASK
18332 #define CB_COLOR1_FMASK__BASE_256B__SHIFT                                                                     0x0
18333 #define CB_COLOR1_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18334 //CB_COLOR1_FMASK_BASE_EXT
18335 #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18336 #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18337 //CB_COLOR1_CLEAR_WORD0
18338 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18339 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18340 //CB_COLOR1_CLEAR_WORD1
18341 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18342 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18343 //CB_COLOR1_DCC_BASE
18344 #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18345 #define CB_COLOR1_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18346 //CB_COLOR1_DCC_BASE_EXT
18347 #define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18348 #define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18349 //CB_COLOR2_BASE
18350 #define CB_COLOR2_BASE__BASE_256B__SHIFT                                                                      0x0
18351 #define CB_COLOR2_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18352 //CB_COLOR2_BASE_EXT
18353 #define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18354 #define CB_COLOR2_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18355 //CB_COLOR2_ATTRIB2
18356 #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18357 #define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18358 #define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18359 #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18360 #define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18361 #define CB_COLOR2_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18362 //CB_COLOR2_VIEW
18363 #define CB_COLOR2_VIEW__SLICE_START__SHIFT                                                                    0x0
18364 #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18365 #define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18366 #define CB_COLOR2_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18367 #define CB_COLOR2_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18368 #define CB_COLOR2_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18369 //CB_COLOR2_INFO
18370 #define CB_COLOR2_INFO__ENDIAN__SHIFT                                                                         0x0
18371 #define CB_COLOR2_INFO__FORMAT__SHIFT                                                                         0x2
18372 #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18373 #define CB_COLOR2_INFO__COMP_SWAP__SHIFT                                                                      0xb
18374 #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18375 #define CB_COLOR2_INFO__COMPRESSION__SHIFT                                                                    0xe
18376 #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18377 #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18378 #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18379 #define CB_COLOR2_INFO__ROUND_MODE__SHIFT                                                                     0x12
18380 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18381 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18382 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18383 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18384 #define CB_COLOR2_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18385 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18386 #define CB_COLOR2_INFO__ENDIAN_MASK                                                                           0x00000003L
18387 #define CB_COLOR2_INFO__FORMAT_MASK                                                                           0x0000007CL
18388 #define CB_COLOR2_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18389 #define CB_COLOR2_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18390 #define CB_COLOR2_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18391 #define CB_COLOR2_INFO__COMPRESSION_MASK                                                                      0x00004000L
18392 #define CB_COLOR2_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18393 #define CB_COLOR2_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18394 #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18395 #define CB_COLOR2_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18396 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18397 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18398 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18399 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18400 #define CB_COLOR2_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18401 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18402 //CB_COLOR2_ATTRIB
18403 #define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18404 #define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18405 #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18406 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18407 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18408 #define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18409 #define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18410 #define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18411 #define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18412 #define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18413 #define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18414 #define CB_COLOR2_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18415 #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18416 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18417 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18418 #define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18419 #define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18420 #define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18421 #define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18422 #define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18423 //CB_COLOR2_DCC_CONTROL
18424 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18425 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18426 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18427 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18428 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18429 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18430 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18431 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18432 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18433 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18434 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18435 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18436 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18437 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18438 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18439 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18440 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18441 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18442 //CB_COLOR2_CMASK
18443 #define CB_COLOR2_CMASK__BASE_256B__SHIFT                                                                     0x0
18444 #define CB_COLOR2_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18445 //CB_COLOR2_CMASK_BASE_EXT
18446 #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18447 #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18448 //CB_COLOR2_FMASK
18449 #define CB_COLOR2_FMASK__BASE_256B__SHIFT                                                                     0x0
18450 #define CB_COLOR2_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18451 //CB_COLOR2_FMASK_BASE_EXT
18452 #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18453 #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18454 //CB_COLOR2_CLEAR_WORD0
18455 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18456 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18457 //CB_COLOR2_CLEAR_WORD1
18458 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18459 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18460 //CB_COLOR2_DCC_BASE
18461 #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18462 #define CB_COLOR2_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18463 //CB_COLOR2_DCC_BASE_EXT
18464 #define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18465 #define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18466 //CB_COLOR3_BASE
18467 #define CB_COLOR3_BASE__BASE_256B__SHIFT                                                                      0x0
18468 #define CB_COLOR3_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18469 //CB_COLOR3_BASE_EXT
18470 #define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18471 #define CB_COLOR3_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18472 //CB_COLOR3_ATTRIB2
18473 #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18474 #define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18475 #define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18476 #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18477 #define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18478 #define CB_COLOR3_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18479 //CB_COLOR3_VIEW
18480 #define CB_COLOR3_VIEW__SLICE_START__SHIFT                                                                    0x0
18481 #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18482 #define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18483 #define CB_COLOR3_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18484 #define CB_COLOR3_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18485 #define CB_COLOR3_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18486 //CB_COLOR3_INFO
18487 #define CB_COLOR3_INFO__ENDIAN__SHIFT                                                                         0x0
18488 #define CB_COLOR3_INFO__FORMAT__SHIFT                                                                         0x2
18489 #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18490 #define CB_COLOR3_INFO__COMP_SWAP__SHIFT                                                                      0xb
18491 #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18492 #define CB_COLOR3_INFO__COMPRESSION__SHIFT                                                                    0xe
18493 #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18494 #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18495 #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18496 #define CB_COLOR3_INFO__ROUND_MODE__SHIFT                                                                     0x12
18497 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18498 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18499 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18500 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18501 #define CB_COLOR3_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18502 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18503 #define CB_COLOR3_INFO__ENDIAN_MASK                                                                           0x00000003L
18504 #define CB_COLOR3_INFO__FORMAT_MASK                                                                           0x0000007CL
18505 #define CB_COLOR3_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18506 #define CB_COLOR3_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18507 #define CB_COLOR3_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18508 #define CB_COLOR3_INFO__COMPRESSION_MASK                                                                      0x00004000L
18509 #define CB_COLOR3_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18510 #define CB_COLOR3_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18511 #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18512 #define CB_COLOR3_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18513 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18514 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18515 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18516 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18517 #define CB_COLOR3_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18518 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18519 //CB_COLOR3_ATTRIB
18520 #define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18521 #define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18522 #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18523 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18524 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18525 #define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18526 #define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18527 #define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18528 #define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18529 #define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18530 #define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18531 #define CB_COLOR3_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18532 #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18533 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18534 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18535 #define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18536 #define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18537 #define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18538 #define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18539 #define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18540 //CB_COLOR3_DCC_CONTROL
18541 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18542 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18543 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18544 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18545 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18546 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18547 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18548 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18549 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18550 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18551 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18552 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18553 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18554 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18555 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18556 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18557 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18558 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18559 //CB_COLOR3_CMASK
18560 #define CB_COLOR3_CMASK__BASE_256B__SHIFT                                                                     0x0
18561 #define CB_COLOR3_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18562 //CB_COLOR3_CMASK_BASE_EXT
18563 #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18564 #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18565 //CB_COLOR3_FMASK
18566 #define CB_COLOR3_FMASK__BASE_256B__SHIFT                                                                     0x0
18567 #define CB_COLOR3_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18568 //CB_COLOR3_FMASK_BASE_EXT
18569 #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18570 #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18571 //CB_COLOR3_CLEAR_WORD0
18572 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18573 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18574 //CB_COLOR3_CLEAR_WORD1
18575 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18576 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18577 //CB_COLOR3_DCC_BASE
18578 #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18579 #define CB_COLOR3_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18580 //CB_COLOR3_DCC_BASE_EXT
18581 #define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18582 #define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18583 //CB_COLOR4_BASE
18584 #define CB_COLOR4_BASE__BASE_256B__SHIFT                                                                      0x0
18585 #define CB_COLOR4_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18586 //CB_COLOR4_BASE_EXT
18587 #define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18588 #define CB_COLOR4_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18589 //CB_COLOR4_ATTRIB2
18590 #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18591 #define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18592 #define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18593 #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18594 #define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18595 #define CB_COLOR4_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18596 //CB_COLOR4_VIEW
18597 #define CB_COLOR4_VIEW__SLICE_START__SHIFT                                                                    0x0
18598 #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18599 #define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18600 #define CB_COLOR4_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18601 #define CB_COLOR4_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18602 #define CB_COLOR4_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18603 //CB_COLOR4_INFO
18604 #define CB_COLOR4_INFO__ENDIAN__SHIFT                                                                         0x0
18605 #define CB_COLOR4_INFO__FORMAT__SHIFT                                                                         0x2
18606 #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18607 #define CB_COLOR4_INFO__COMP_SWAP__SHIFT                                                                      0xb
18608 #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18609 #define CB_COLOR4_INFO__COMPRESSION__SHIFT                                                                    0xe
18610 #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18611 #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18612 #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18613 #define CB_COLOR4_INFO__ROUND_MODE__SHIFT                                                                     0x12
18614 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18615 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18616 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18617 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18618 #define CB_COLOR4_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18619 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18620 #define CB_COLOR4_INFO__ENDIAN_MASK                                                                           0x00000003L
18621 #define CB_COLOR4_INFO__FORMAT_MASK                                                                           0x0000007CL
18622 #define CB_COLOR4_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18623 #define CB_COLOR4_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18624 #define CB_COLOR4_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18625 #define CB_COLOR4_INFO__COMPRESSION_MASK                                                                      0x00004000L
18626 #define CB_COLOR4_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18627 #define CB_COLOR4_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18628 #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18629 #define CB_COLOR4_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18630 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18631 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18632 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18633 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18634 #define CB_COLOR4_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18635 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18636 //CB_COLOR4_ATTRIB
18637 #define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18638 #define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18639 #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18640 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18641 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18642 #define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18643 #define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18644 #define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18645 #define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18646 #define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18647 #define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18648 #define CB_COLOR4_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18649 #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18650 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18651 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18652 #define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18653 #define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18654 #define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18655 #define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18656 #define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18657 //CB_COLOR4_DCC_CONTROL
18658 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18659 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18660 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18661 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18662 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18663 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18664 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18665 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18666 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18667 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18668 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18669 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18670 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18671 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18672 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18673 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18674 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18675 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18676 //CB_COLOR4_CMASK
18677 #define CB_COLOR4_CMASK__BASE_256B__SHIFT                                                                     0x0
18678 #define CB_COLOR4_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18679 //CB_COLOR4_CMASK_BASE_EXT
18680 #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18681 #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18682 //CB_COLOR4_FMASK
18683 #define CB_COLOR4_FMASK__BASE_256B__SHIFT                                                                     0x0
18684 #define CB_COLOR4_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18685 //CB_COLOR4_FMASK_BASE_EXT
18686 #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18687 #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18688 //CB_COLOR4_CLEAR_WORD0
18689 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18690 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18691 //CB_COLOR4_CLEAR_WORD1
18692 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18693 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18694 //CB_COLOR4_DCC_BASE
18695 #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18696 #define CB_COLOR4_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18697 //CB_COLOR4_DCC_BASE_EXT
18698 #define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18699 #define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18700 //CB_COLOR5_BASE
18701 #define CB_COLOR5_BASE__BASE_256B__SHIFT                                                                      0x0
18702 #define CB_COLOR5_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18703 //CB_COLOR5_BASE_EXT
18704 #define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18705 #define CB_COLOR5_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18706 //CB_COLOR5_ATTRIB2
18707 #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18708 #define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18709 #define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18710 #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18711 #define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18712 #define CB_COLOR5_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18713 //CB_COLOR5_VIEW
18714 #define CB_COLOR5_VIEW__SLICE_START__SHIFT                                                                    0x0
18715 #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18716 #define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18717 #define CB_COLOR5_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18718 #define CB_COLOR5_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18719 #define CB_COLOR5_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18720 //CB_COLOR5_INFO
18721 #define CB_COLOR5_INFO__ENDIAN__SHIFT                                                                         0x0
18722 #define CB_COLOR5_INFO__FORMAT__SHIFT                                                                         0x2
18723 #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18724 #define CB_COLOR5_INFO__COMP_SWAP__SHIFT                                                                      0xb
18725 #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18726 #define CB_COLOR5_INFO__COMPRESSION__SHIFT                                                                    0xe
18727 #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18728 #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18729 #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18730 #define CB_COLOR5_INFO__ROUND_MODE__SHIFT                                                                     0x12
18731 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18732 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18733 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18734 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18735 #define CB_COLOR5_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18736 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18737 #define CB_COLOR5_INFO__ENDIAN_MASK                                                                           0x00000003L
18738 #define CB_COLOR5_INFO__FORMAT_MASK                                                                           0x0000007CL
18739 #define CB_COLOR5_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18740 #define CB_COLOR5_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18741 #define CB_COLOR5_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18742 #define CB_COLOR5_INFO__COMPRESSION_MASK                                                                      0x00004000L
18743 #define CB_COLOR5_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18744 #define CB_COLOR5_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18745 #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18746 #define CB_COLOR5_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18747 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18748 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18749 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18750 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18751 #define CB_COLOR5_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18752 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18753 //CB_COLOR5_ATTRIB
18754 #define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18755 #define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18756 #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18757 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18758 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18759 #define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18760 #define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18761 #define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18762 #define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18763 #define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18764 #define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18765 #define CB_COLOR5_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18766 #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18767 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18768 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18769 #define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18770 #define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18771 #define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18772 #define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18773 #define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18774 //CB_COLOR5_DCC_CONTROL
18775 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18776 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18777 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18778 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18779 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18780 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18781 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18782 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18783 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18784 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18785 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18786 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18787 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18788 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18789 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18790 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18791 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18792 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18793 //CB_COLOR5_CMASK
18794 #define CB_COLOR5_CMASK__BASE_256B__SHIFT                                                                     0x0
18795 #define CB_COLOR5_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18796 //CB_COLOR5_CMASK_BASE_EXT
18797 #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18798 #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18799 //CB_COLOR5_FMASK
18800 #define CB_COLOR5_FMASK__BASE_256B__SHIFT                                                                     0x0
18801 #define CB_COLOR5_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18802 //CB_COLOR5_FMASK_BASE_EXT
18803 #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18804 #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18805 //CB_COLOR5_CLEAR_WORD0
18806 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18807 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18808 //CB_COLOR5_CLEAR_WORD1
18809 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18810 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18811 //CB_COLOR5_DCC_BASE
18812 #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18813 #define CB_COLOR5_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18814 //CB_COLOR5_DCC_BASE_EXT
18815 #define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18816 #define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18817 //CB_COLOR6_BASE
18818 #define CB_COLOR6_BASE__BASE_256B__SHIFT                                                                      0x0
18819 #define CB_COLOR6_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18820 //CB_COLOR6_BASE_EXT
18821 #define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18822 #define CB_COLOR6_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18823 //CB_COLOR6_ATTRIB2
18824 #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18825 #define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18826 #define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18827 #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18828 #define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18829 #define CB_COLOR6_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18830 //CB_COLOR6_VIEW
18831 #define CB_COLOR6_VIEW__SLICE_START__SHIFT                                                                    0x0
18832 #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18833 #define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18834 #define CB_COLOR6_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18835 #define CB_COLOR6_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18836 #define CB_COLOR6_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18837 //CB_COLOR6_INFO
18838 #define CB_COLOR6_INFO__ENDIAN__SHIFT                                                                         0x0
18839 #define CB_COLOR6_INFO__FORMAT__SHIFT                                                                         0x2
18840 #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18841 #define CB_COLOR6_INFO__COMP_SWAP__SHIFT                                                                      0xb
18842 #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18843 #define CB_COLOR6_INFO__COMPRESSION__SHIFT                                                                    0xe
18844 #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18845 #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18846 #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18847 #define CB_COLOR6_INFO__ROUND_MODE__SHIFT                                                                     0x12
18848 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18849 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18850 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18851 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18852 #define CB_COLOR6_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18853 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18854 #define CB_COLOR6_INFO__ENDIAN_MASK                                                                           0x00000003L
18855 #define CB_COLOR6_INFO__FORMAT_MASK                                                                           0x0000007CL
18856 #define CB_COLOR6_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18857 #define CB_COLOR6_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18858 #define CB_COLOR6_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18859 #define CB_COLOR6_INFO__COMPRESSION_MASK                                                                      0x00004000L
18860 #define CB_COLOR6_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18861 #define CB_COLOR6_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18862 #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18863 #define CB_COLOR6_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18864 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18865 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18866 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18867 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18868 #define CB_COLOR6_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18869 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18870 //CB_COLOR6_ATTRIB
18871 #define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18872 #define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18873 #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18874 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18875 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18876 #define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18877 #define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18878 #define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18879 #define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18880 #define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18881 #define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18882 #define CB_COLOR6_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18883 #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18884 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18885 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18886 #define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18887 #define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18888 #define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18889 #define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18890 #define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18891 //CB_COLOR6_DCC_CONTROL
18892 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18893 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18894 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18895 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18896 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18897 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18898 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18899 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18900 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18901 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18902 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18903 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18904 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18905 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18906 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18907 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18908 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18909 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18910 //CB_COLOR6_CMASK
18911 #define CB_COLOR6_CMASK__BASE_256B__SHIFT                                                                     0x0
18912 #define CB_COLOR6_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18913 //CB_COLOR6_CMASK_BASE_EXT
18914 #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18915 #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18916 //CB_COLOR6_FMASK
18917 #define CB_COLOR6_FMASK__BASE_256B__SHIFT                                                                     0x0
18918 #define CB_COLOR6_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18919 //CB_COLOR6_FMASK_BASE_EXT
18920 #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18921 #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18922 //CB_COLOR6_CLEAR_WORD0
18923 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18924 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18925 //CB_COLOR6_CLEAR_WORD1
18926 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18927 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18928 //CB_COLOR6_DCC_BASE
18929 #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18930 #define CB_COLOR6_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18931 //CB_COLOR6_DCC_BASE_EXT
18932 #define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18933 #define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18934 //CB_COLOR7_BASE
18935 #define CB_COLOR7_BASE__BASE_256B__SHIFT                                                                      0x0
18936 #define CB_COLOR7_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18937 //CB_COLOR7_BASE_EXT
18938 #define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18939 #define CB_COLOR7_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18940 //CB_COLOR7_ATTRIB2
18941 #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18942 #define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18943 #define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18944 #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18945 #define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18946 #define CB_COLOR7_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18947 //CB_COLOR7_VIEW
18948 #define CB_COLOR7_VIEW__SLICE_START__SHIFT                                                                    0x0
18949 #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18950 #define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18951 #define CB_COLOR7_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18952 #define CB_COLOR7_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18953 #define CB_COLOR7_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18954 //CB_COLOR7_INFO
18955 #define CB_COLOR7_INFO__ENDIAN__SHIFT                                                                         0x0
18956 #define CB_COLOR7_INFO__FORMAT__SHIFT                                                                         0x2
18957 #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18958 #define CB_COLOR7_INFO__COMP_SWAP__SHIFT                                                                      0xb
18959 #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18960 #define CB_COLOR7_INFO__COMPRESSION__SHIFT                                                                    0xe
18961 #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18962 #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18963 #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18964 #define CB_COLOR7_INFO__ROUND_MODE__SHIFT                                                                     0x12
18965 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18966 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18967 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18968 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18969 #define CB_COLOR7_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18970 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18971 #define CB_COLOR7_INFO__ENDIAN_MASK                                                                           0x00000003L
18972 #define CB_COLOR7_INFO__FORMAT_MASK                                                                           0x0000007CL
18973 #define CB_COLOR7_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18974 #define CB_COLOR7_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18975 #define CB_COLOR7_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18976 #define CB_COLOR7_INFO__COMPRESSION_MASK                                                                      0x00004000L
18977 #define CB_COLOR7_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18978 #define CB_COLOR7_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18979 #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18980 #define CB_COLOR7_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18981 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18982 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18983 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18984 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18985 #define CB_COLOR7_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18986 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18987 //CB_COLOR7_ATTRIB
18988 #define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18989 #define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18990 #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18991 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18992 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18993 #define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18994 #define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18995 #define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18996 #define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18997 #define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18998 #define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18999 #define CB_COLOR7_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
19000 #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
19001 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
19002 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
19003 #define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
19004 #define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
19005 #define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
19006 #define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
19007 #define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
19008 //CB_COLOR7_DCC_CONTROL
19009 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
19010 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
19011 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
19012 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
19013 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
19014 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
19015 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
19016 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
19017 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
19018 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
19019 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
19020 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
19021 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
19022 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
19023 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
19024 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
19025 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
19026 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
19027 //CB_COLOR7_CMASK
19028 #define CB_COLOR7_CMASK__BASE_256B__SHIFT                                                                     0x0
19029 #define CB_COLOR7_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
19030 //CB_COLOR7_CMASK_BASE_EXT
19031 #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
19032 #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
19033 //CB_COLOR7_FMASK
19034 #define CB_COLOR7_FMASK__BASE_256B__SHIFT                                                                     0x0
19035 #define CB_COLOR7_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
19036 //CB_COLOR7_FMASK_BASE_EXT
19037 #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
19038 #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
19039 //CB_COLOR7_CLEAR_WORD0
19040 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
19041 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
19042 //CB_COLOR7_CLEAR_WORD1
19043 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
19044 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
19045 //CB_COLOR7_DCC_BASE
19046 #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
19047 #define CB_COLOR7_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
19048 //CB_COLOR7_DCC_BASE_EXT
19049 #define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
19050 #define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
19051 
19052 
19053 // addressBlock: gc_gfxudec
19054 //CP_EOP_DONE_ADDR_LO
19055 #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT                                                                   0x2
19056 #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK                                                                     0xFFFFFFFCL
19057 //CP_EOP_DONE_ADDR_HI
19058 #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
19059 #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
19060 //CP_EOP_DONE_DATA_LO
19061 #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT                                                                   0x0
19062 #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK                                                                     0xFFFFFFFFL
19063 //CP_EOP_DONE_DATA_HI
19064 #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT                                                                   0x0
19065 #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK                                                                     0xFFFFFFFFL
19066 //CP_EOP_LAST_FENCE_LO
19067 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT                                                            0x0
19068 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK                                                              0xFFFFFFFFL
19069 //CP_EOP_LAST_FENCE_HI
19070 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT                                                            0x0
19071 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK                                                              0xFFFFFFFFL
19072 //CP_STREAM_OUT_ADDR_LO
19073 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT                                                      0x2
19074 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK                                                        0xFFFFFFFCL
19075 //CP_STREAM_OUT_ADDR_HI
19076 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT                                                      0x0
19077 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK                                                        0x0000FFFFL
19078 //CP_NUM_PRIM_WRITTEN_COUNT0_LO
19079 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT                                        0x0
19080 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK                                          0xFFFFFFFFL
19081 //CP_NUM_PRIM_WRITTEN_COUNT0_HI
19082 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT                                        0x0
19083 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK                                          0xFFFFFFFFL
19084 //CP_NUM_PRIM_NEEDED_COUNT0_LO
19085 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT                                          0x0
19086 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK                                            0xFFFFFFFFL
19087 //CP_NUM_PRIM_NEEDED_COUNT0_HI
19088 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT                                          0x0
19089 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK                                            0xFFFFFFFFL
19090 //CP_NUM_PRIM_WRITTEN_COUNT1_LO
19091 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT                                        0x0
19092 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK                                          0xFFFFFFFFL
19093 //CP_NUM_PRIM_WRITTEN_COUNT1_HI
19094 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT                                        0x0
19095 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK                                          0xFFFFFFFFL
19096 //CP_NUM_PRIM_NEEDED_COUNT1_LO
19097 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT                                          0x0
19098 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK                                            0xFFFFFFFFL
19099 //CP_NUM_PRIM_NEEDED_COUNT1_HI
19100 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT                                          0x0
19101 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK                                            0xFFFFFFFFL
19102 //CP_NUM_PRIM_WRITTEN_COUNT2_LO
19103 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT                                        0x0
19104 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK                                          0xFFFFFFFFL
19105 //CP_NUM_PRIM_WRITTEN_COUNT2_HI
19106 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT                                        0x0
19107 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK                                          0xFFFFFFFFL
19108 //CP_NUM_PRIM_NEEDED_COUNT2_LO
19109 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT                                          0x0
19110 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK                                            0xFFFFFFFFL
19111 //CP_NUM_PRIM_NEEDED_COUNT2_HI
19112 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT                                          0x0
19113 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK                                            0xFFFFFFFFL
19114 //CP_NUM_PRIM_WRITTEN_COUNT3_LO
19115 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT                                        0x0
19116 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK                                          0xFFFFFFFFL
19117 //CP_NUM_PRIM_WRITTEN_COUNT3_HI
19118 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT                                        0x0
19119 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK                                          0xFFFFFFFFL
19120 //CP_NUM_PRIM_NEEDED_COUNT3_LO
19121 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT                                          0x0
19122 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK                                            0xFFFFFFFFL
19123 //CP_NUM_PRIM_NEEDED_COUNT3_HI
19124 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT                                          0x0
19125 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK                                            0xFFFFFFFFL
19126 //CP_PIPE_STATS_ADDR_LO
19127 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT                                                      0x2
19128 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK                                                        0xFFFFFFFCL
19129 //CP_PIPE_STATS_ADDR_HI
19130 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT                                                      0x0
19131 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK                                                        0x0000FFFFL
19132 //CP_VGT_IAVERT_COUNT_LO
19133 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT                                                        0x0
19134 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK                                                          0xFFFFFFFFL
19135 //CP_VGT_IAVERT_COUNT_HI
19136 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT                                                        0x0
19137 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK                                                          0xFFFFFFFFL
19138 //CP_VGT_IAPRIM_COUNT_LO
19139 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT                                                        0x0
19140 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
19141 //CP_VGT_IAPRIM_COUNT_HI
19142 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT                                                        0x0
19143 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
19144 //CP_VGT_GSPRIM_COUNT_LO
19145 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT                                                        0x0
19146 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
19147 //CP_VGT_GSPRIM_COUNT_HI
19148 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT                                                        0x0
19149 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
19150 //CP_VGT_VSINVOC_COUNT_LO
19151 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT                                                      0x0
19152 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19153 //CP_VGT_VSINVOC_COUNT_HI
19154 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT                                                      0x0
19155 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19156 //CP_VGT_GSINVOC_COUNT_LO
19157 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT                                                      0x0
19158 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19159 //CP_VGT_GSINVOC_COUNT_HI
19160 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT                                                      0x0
19161 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19162 //CP_VGT_HSINVOC_COUNT_LO
19163 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT                                                      0x0
19164 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19165 //CP_VGT_HSINVOC_COUNT_HI
19166 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT                                                      0x0
19167 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19168 //CP_VGT_DSINVOC_COUNT_LO
19169 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT                                                      0x0
19170 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19171 //CP_VGT_DSINVOC_COUNT_HI
19172 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT                                                      0x0
19173 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19174 //CP_PA_CINVOC_COUNT_LO
19175 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT                                                         0x0
19176 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK                                                           0xFFFFFFFFL
19177 //CP_PA_CINVOC_COUNT_HI
19178 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT                                                         0x0
19179 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK                                                           0xFFFFFFFFL
19180 //CP_PA_CPRIM_COUNT_LO
19181 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT                                                           0x0
19182 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK                                                             0xFFFFFFFFL
19183 //CP_PA_CPRIM_COUNT_HI
19184 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT                                                           0x0
19185 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK                                                             0xFFFFFFFFL
19186 //CP_SC_PSINVOC_COUNT0_LO
19187 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT                                                     0x0
19188 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK                                                       0xFFFFFFFFL
19189 //CP_SC_PSINVOC_COUNT0_HI
19190 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT                                                     0x0
19191 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK                                                       0xFFFFFFFFL
19192 //CP_SC_PSINVOC_COUNT1_LO
19193 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT                                                              0x0
19194 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK                                                                0xFFFFFFFFL
19195 //CP_SC_PSINVOC_COUNT1_HI
19196 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT                                                              0x0
19197 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK                                                                0xFFFFFFFFL
19198 //CP_VGT_CSINVOC_COUNT_LO
19199 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT                                                      0x0
19200 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19201 //CP_VGT_CSINVOC_COUNT_HI
19202 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT                                                      0x0
19203 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19204 //CP_PIPE_STATS_CONTROL
19205 #define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
19206 #define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK                                                              0x02000000L
19207 //CP_STREAM_OUT_CONTROL
19208 #define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
19209 #define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK                                                              0x02000000L
19210 //CP_STRMOUT_CNTL
19211 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT                                                            0x0
19212 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK                                                              0x00000001L
19213 //SCRATCH_REG0
19214 #define SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                     0x0
19215 #define SCRATCH_REG0__SCRATCH_REG0_MASK                                                                       0xFFFFFFFFL
19216 //SCRATCH_REG1
19217 #define SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                     0x0
19218 #define SCRATCH_REG1__SCRATCH_REG1_MASK                                                                       0xFFFFFFFFL
19219 //SCRATCH_REG2
19220 #define SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                     0x0
19221 #define SCRATCH_REG2__SCRATCH_REG2_MASK                                                                       0xFFFFFFFFL
19222 //SCRATCH_REG3
19223 #define SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                     0x0
19224 #define SCRATCH_REG3__SCRATCH_REG3_MASK                                                                       0xFFFFFFFFL
19225 //SCRATCH_REG4
19226 #define SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                     0x0
19227 #define SCRATCH_REG4__SCRATCH_REG4_MASK                                                                       0xFFFFFFFFL
19228 //SCRATCH_REG5
19229 #define SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                     0x0
19230 #define SCRATCH_REG5__SCRATCH_REG5_MASK                                                                       0xFFFFFFFFL
19231 //SCRATCH_REG6
19232 #define SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                     0x0
19233 #define SCRATCH_REG6__SCRATCH_REG6_MASK                                                                       0xFFFFFFFFL
19234 //SCRATCH_REG7
19235 #define SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                     0x0
19236 #define SCRATCH_REG7__SCRATCH_REG7_MASK                                                                       0xFFFFFFFFL
19237 //CP_APPEND_DATA_HI
19238 #define CP_APPEND_DATA_HI__DATA__SHIFT                                                                        0x0
19239 #define CP_APPEND_DATA_HI__DATA_MASK                                                                          0xFFFFFFFFL
19240 //CP_APPEND_LAST_CS_FENCE_HI
19241 #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
19242 #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
19243 //CP_APPEND_LAST_PS_FENCE_HI
19244 #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
19245 #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
19246 //SCRATCH_UMSK
19247 #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT                                                                    0x0
19248 #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT                                                                    0x10
19249 #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK                                                                      0x000000FFL
19250 #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK                                                                      0x00030000L
19251 //SCRATCH_ADDR
19252 #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT                                                                    0x0
19253 #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK                                                                      0xFFFFFFFFL
19254 //CP_PFP_ATOMIC_PREOP_LO
19255 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                        0x0
19256 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                          0xFFFFFFFFL
19257 //CP_PFP_ATOMIC_PREOP_HI
19258 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                        0x0
19259 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                          0xFFFFFFFFL
19260 //CP_PFP_GDS_ATOMIC0_PREOP_LO
19261 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                              0x0
19262 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                0xFFFFFFFFL
19263 //CP_PFP_GDS_ATOMIC0_PREOP_HI
19264 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                              0x0
19265 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                0xFFFFFFFFL
19266 //CP_PFP_GDS_ATOMIC1_PREOP_LO
19267 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                              0x0
19268 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                0xFFFFFFFFL
19269 //CP_PFP_GDS_ATOMIC1_PREOP_HI
19270 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                              0x0
19271 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                0xFFFFFFFFL
19272 //CP_APPEND_ADDR_LO
19273 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT                                                                 0x2
19274 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK                                                                   0xFFFFFFFCL
19275 //CP_APPEND_ADDR_HI
19276 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT                                                                 0x0
19277 #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT                                                                   0x10
19278 #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT                                                                0x19
19279 #define CP_APPEND_ADDR_HI__COMMAND__SHIFT                                                                     0x1d
19280 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK                                                                   0x0000FFFFL
19281 #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK                                                                     0x00010000L
19282 #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK                                                                  0x02000000L
19283 #define CP_APPEND_ADDR_HI__COMMAND_MASK                                                                       0xE0000000L
19284 //CP_APPEND_DATA_LO
19285 #define CP_APPEND_DATA_LO__DATA__SHIFT                                                                        0x0
19286 #define CP_APPEND_DATA_LO__DATA_MASK                                                                          0xFFFFFFFFL
19287 //CP_APPEND_LAST_CS_FENCE_LO
19288 #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
19289 #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
19290 //CP_APPEND_LAST_PS_FENCE_LO
19291 #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
19292 #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
19293 //CP_ATOMIC_PREOP_LO
19294 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                            0x0
19295 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                              0xFFFFFFFFL
19296 //CP_ME_ATOMIC_PREOP_LO
19297 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                         0x0
19298 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                           0xFFFFFFFFL
19299 //CP_ATOMIC_PREOP_HI
19300 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                            0x0
19301 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                              0xFFFFFFFFL
19302 //CP_ME_ATOMIC_PREOP_HI
19303 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                         0x0
19304 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                           0xFFFFFFFFL
19305 //CP_GDS_ATOMIC0_PREOP_LO
19306 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                                  0x0
19307 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                    0xFFFFFFFFL
19308 //CP_ME_GDS_ATOMIC0_PREOP_LO
19309 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                               0x0
19310 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                 0xFFFFFFFFL
19311 //CP_GDS_ATOMIC0_PREOP_HI
19312 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                                  0x0
19313 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                    0xFFFFFFFFL
19314 //CP_ME_GDS_ATOMIC0_PREOP_HI
19315 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                               0x0
19316 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                 0xFFFFFFFFL
19317 //CP_GDS_ATOMIC1_PREOP_LO
19318 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                                  0x0
19319 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                    0xFFFFFFFFL
19320 //CP_ME_GDS_ATOMIC1_PREOP_LO
19321 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                               0x0
19322 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                 0xFFFFFFFFL
19323 //CP_GDS_ATOMIC1_PREOP_HI
19324 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                                  0x0
19325 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                    0xFFFFFFFFL
19326 //CP_ME_GDS_ATOMIC1_PREOP_HI
19327 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                               0x0
19328 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                 0xFFFFFFFFL
19329 //CP_ME_MC_WADDR_LO
19330 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT                                                              0x2
19331 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK                                                                0xFFFFFFFCL
19332 //CP_ME_MC_WADDR_HI
19333 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT                                                              0x0
19334 #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
19335 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK                                                                0x0000FFFFL
19336 #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK                                                                  0x00400000L
19337 //CP_ME_MC_WDATA_LO
19338 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT                                                              0x0
19339 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK                                                                0xFFFFFFFFL
19340 //CP_ME_MC_WDATA_HI
19341 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT                                                              0x0
19342 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK                                                                0xFFFFFFFFL
19343 //CP_ME_MC_RADDR_LO
19344 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT                                                              0x2
19345 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK                                                                0xFFFFFFFCL
19346 //CP_ME_MC_RADDR_HI
19347 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT                                                              0x0
19348 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
19349 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK                                                                0x0000FFFFL
19350 #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK                                                                  0x00400000L
19351 //CP_SEM_WAIT_TIMER
19352 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT                                                              0x0
19353 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK                                                                0xFFFFFFFFL
19354 //CP_SIG_SEM_ADDR_LO
19355 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT                                                              0x0
19356 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                                0x3
19357 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK                                                                0x00000003L
19358 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                  0xFFFFFFF8L
19359 //CP_SIG_SEM_ADDR_HI
19360 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                                0x0
19361 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                            0x10
19362 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                            0x14
19363 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                            0x18
19364 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                 0x1d
19365 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                  0x0000FFFFL
19366 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                              0x00010000L
19367 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                              0x00100000L
19368 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                              0x03000000L
19369 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK                                                                   0xE0000000L
19370 //CP_WAIT_REG_MEM_TIMEOUT
19371 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT                                                  0x0
19372 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK                                                    0xFFFFFFFFL
19373 //CP_WAIT_SEM_ADDR_LO
19374 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT                                                             0x0
19375 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                               0x3
19376 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK                                                               0x00000003L
19377 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                 0xFFFFFFF8L
19378 //CP_WAIT_SEM_ADDR_HI
19379 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                               0x0
19380 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                           0x10
19381 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                           0x14
19382 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                           0x18
19383 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                0x1d
19384 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                 0x0000FFFFL
19385 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                             0x00010000L
19386 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                             0x00100000L
19387 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                             0x03000000L
19388 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK                                                                  0xE0000000L
19389 //CP_DMA_PFP_CONTROL
19390 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT                                                               0xa
19391 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT                                                           0xd
19392 #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT                                                                 0x14
19393 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT                                                           0x19
19394 #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT                                                                 0x1d
19395 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK                                                                 0x00000400L
19396 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK                                                             0x00002000L
19397 #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK                                                                   0x00300000L
19398 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK                                                             0x02000000L
19399 #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK                                                                   0x60000000L
19400 //CP_DMA_ME_CONTROL
19401 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT                                                                0xa
19402 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT                                                            0xd
19403 #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT                                                                  0x14
19404 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT                                                            0x19
19405 #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT                                                                  0x1d
19406 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK                                                                  0x00000400L
19407 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK                                                              0x00002000L
19408 #define CP_DMA_ME_CONTROL__DST_SELECT_MASK                                                                    0x00300000L
19409 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK                                                              0x02000000L
19410 #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK                                                                    0x60000000L
19411 //CP_COHER_BASE_HI
19412 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                           0x0
19413 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                             0x000000FFL
19414 //CP_COHER_START_DELAY
19415 #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT                                                        0x0
19416 #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK                                                          0x0000003FL
19417 //CP_COHER_CNTL
19418 #define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT                                                                0x3
19419 #define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT                                                                0x4
19420 #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT                                                      0x5
19421 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT                                                             0xf
19422 #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT                                                                0x12
19423 #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT                                                                 0x16
19424 #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT                                                                   0x17
19425 #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT                                                                   0x19
19426 #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT                                                                   0x1a
19427 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT                                                            0x1b
19428 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT                                                        0x1c
19429 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT                                                            0x1d
19430 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT                                                         0x1e
19431 #define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK                                                                  0x00000008L
19432 #define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK                                                                  0x00000010L
19433 #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK                                                        0x00000020L
19434 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK                                                               0x00008000L
19435 #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK                                                                  0x00040000L
19436 #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK                                                                   0x00400000L
19437 #define CP_COHER_CNTL__TC_ACTION_ENA_MASK                                                                     0x00800000L
19438 #define CP_COHER_CNTL__CB_ACTION_ENA_MASK                                                                     0x02000000L
19439 #define CP_COHER_CNTL__DB_ACTION_ENA_MASK                                                                     0x04000000L
19440 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK                                                              0x08000000L
19441 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK                                                          0x10000000L
19442 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK                                                              0x20000000L
19443 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK                                                           0x40000000L
19444 //CP_COHER_SIZE
19445 #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                                 0x0
19446 #define CP_COHER_SIZE__COHER_SIZE_256B_MASK                                                                   0xFFFFFFFFL
19447 //CP_COHER_BASE
19448 #define CP_COHER_BASE__COHER_BASE_256B__SHIFT                                                                 0x0
19449 #define CP_COHER_BASE__COHER_BASE_256B_MASK                                                                   0xFFFFFFFFL
19450 //CP_COHER_STATUS
19451 #define CP_COHER_STATUS__MEID__SHIFT                                                                          0x18
19452 #define CP_COHER_STATUS__STATUS__SHIFT                                                                        0x1f
19453 #define CP_COHER_STATUS__MEID_MASK                                                                            0x03000000L
19454 #define CP_COHER_STATUS__STATUS_MASK                                                                          0x80000000L
19455 //CP_DMA_ME_SRC_ADDR
19456 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT                                                                   0x0
19457 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK                                                                     0xFFFFFFFFL
19458 //CP_DMA_ME_SRC_ADDR_HI
19459 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                             0x0
19460 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                               0x0000FFFFL
19461 //CP_DMA_ME_DST_ADDR
19462 #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT                                                                   0x0
19463 #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK                                                                     0xFFFFFFFFL
19464 //CP_DMA_ME_DST_ADDR_HI
19465 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                             0x0
19466 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK                                                               0x0000FFFFL
19467 //CP_DMA_ME_COMMAND
19468 #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT                                                                  0x0
19469 #define CP_DMA_ME_COMMAND__SAS__SHIFT                                                                         0x1a
19470 #define CP_DMA_ME_COMMAND__DAS__SHIFT                                                                         0x1b
19471 #define CP_DMA_ME_COMMAND__SAIC__SHIFT                                                                        0x1c
19472 #define CP_DMA_ME_COMMAND__DAIC__SHIFT                                                                        0x1d
19473 #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT                                                                    0x1e
19474 #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT                                                                      0x1f
19475 #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK                                                                    0x03FFFFFFL
19476 #define CP_DMA_ME_COMMAND__SAS_MASK                                                                           0x04000000L
19477 #define CP_DMA_ME_COMMAND__DAS_MASK                                                                           0x08000000L
19478 #define CP_DMA_ME_COMMAND__SAIC_MASK                                                                          0x10000000L
19479 #define CP_DMA_ME_COMMAND__DAIC_MASK                                                                          0x20000000L
19480 #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK                                                                      0x40000000L
19481 #define CP_DMA_ME_COMMAND__DIS_WC_MASK                                                                        0x80000000L
19482 //CP_DMA_PFP_SRC_ADDR
19483 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT                                                                  0x0
19484 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK                                                                    0xFFFFFFFFL
19485 //CP_DMA_PFP_SRC_ADDR_HI
19486 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                            0x0
19487 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                              0x0000FFFFL
19488 //CP_DMA_PFP_DST_ADDR
19489 #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT                                                                  0x0
19490 #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK                                                                    0xFFFFFFFFL
19491 //CP_DMA_PFP_DST_ADDR_HI
19492 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                            0x0
19493 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK                                                              0x0000FFFFL
19494 //CP_DMA_PFP_COMMAND
19495 #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT                                                                 0x0
19496 #define CP_DMA_PFP_COMMAND__SAS__SHIFT                                                                        0x1a
19497 #define CP_DMA_PFP_COMMAND__DAS__SHIFT                                                                        0x1b
19498 #define CP_DMA_PFP_COMMAND__SAIC__SHIFT                                                                       0x1c
19499 #define CP_DMA_PFP_COMMAND__DAIC__SHIFT                                                                       0x1d
19500 #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT                                                                   0x1e
19501 #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT                                                                     0x1f
19502 #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK                                                                   0x03FFFFFFL
19503 #define CP_DMA_PFP_COMMAND__SAS_MASK                                                                          0x04000000L
19504 #define CP_DMA_PFP_COMMAND__DAS_MASK                                                                          0x08000000L
19505 #define CP_DMA_PFP_COMMAND__SAIC_MASK                                                                         0x10000000L
19506 #define CP_DMA_PFP_COMMAND__DAIC_MASK                                                                         0x20000000L
19507 #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK                                                                     0x40000000L
19508 #define CP_DMA_PFP_COMMAND__DIS_WC_MASK                                                                       0x80000000L
19509 //CP_DMA_CNTL
19510 #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT                                                               0x0
19511 #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x4
19512 #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT                                                                      0x10
19513 #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT                                                                    0x1c
19514 #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT                                                                     0x1d
19515 #define CP_DMA_CNTL__PIO_COUNT__SHIFT                                                                         0x1e
19516 #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK                                                                 0x00000001L
19517 #define CP_DMA_CNTL__MIN_AVAILSZ_MASK                                                                         0x00000030L
19518 #define CP_DMA_CNTL__BUFFER_DEPTH_MASK                                                                        0x000F0000L
19519 #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK                                                                      0x10000000L
19520 #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK                                                                       0x20000000L
19521 #define CP_DMA_CNTL__PIO_COUNT_MASK                                                                           0xC0000000L
19522 //CP_DMA_READ_TAGS
19523 #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT                                                                 0x0
19524 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT                                                           0x1c
19525 #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK                                                                   0x03FFFFFFL
19526 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK                                                             0x10000000L
19527 //CP_COHER_SIZE_HI
19528 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                           0x0
19529 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                             0x000000FFL
19530 //CP_PFP_IB_CONTROL
19531 #define CP_PFP_IB_CONTROL__IB_EN__SHIFT                                                                       0x0
19532 #define CP_PFP_IB_CONTROL__IB_EN_MASK                                                                         0x000000FFL
19533 //CP_PFP_LOAD_CONTROL
19534 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT                                                             0x0
19535 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT                                                               0x1
19536 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT                                                             0x10
19537 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT                                                              0x18
19538 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK                                                               0x00000001L
19539 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK                                                                 0x00000002L
19540 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK                                                               0x00010000L
19541 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK                                                                0x01000000L
19542 //CP_SCRATCH_INDEX
19543 #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                                0x0
19544 #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                                  0x000000FFL
19545 //CP_SCRATCH_DATA
19546 #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                                  0x0
19547 #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                    0xFFFFFFFFL
19548 //CP_RB_OFFSET
19549 #define CP_RB_OFFSET__RB_OFFSET__SHIFT                                                                        0x0
19550 #define CP_RB_OFFSET__RB_OFFSET_MASK                                                                          0x000FFFFFL
19551 //CP_IB1_OFFSET
19552 #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT                                                                      0x0
19553 #define CP_IB1_OFFSET__IB1_OFFSET_MASK                                                                        0x000FFFFFL
19554 //CP_IB2_OFFSET
19555 #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                      0x0
19556 #define CP_IB2_OFFSET__IB2_OFFSET_MASK                                                                        0x000FFFFFL
19557 //CP_IB1_PREAMBLE_BEGIN
19558 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT                                                      0x0
19559 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK                                                        0x000FFFFFL
19560 //CP_IB1_PREAMBLE_END
19561 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT                                                          0x0
19562 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK                                                            0x000FFFFFL
19563 //CP_IB2_PREAMBLE_BEGIN
19564 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT                                                      0x0
19565 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK                                                        0x000FFFFFL
19566 //CP_IB2_PREAMBLE_END
19567 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT                                                          0x0
19568 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK                                                            0x000FFFFFL
19569 //CP_CE_IB1_OFFSET
19570 #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT                                                                   0x0
19571 #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK                                                                     0x000FFFFFL
19572 //CP_CE_IB2_OFFSET
19573 #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                   0x0
19574 #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK                                                                     0x000FFFFFL
19575 //CP_CE_COUNTER
19576 #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT                                                              0x0
19577 #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
19578 //CP_CE_RB_OFFSET
19579 #define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT                                                                     0x0
19580 #define CP_CE_RB_OFFSET__RB_OFFSET_MASK                                                                       0x000FFFFFL
19581 //CP_CE_INIT_CMD_BUFSZ
19582 #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT                                                           0x0
19583 #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK                                                             0x00000FFFL
19584 //CP_CE_IB1_CMD_BUFSZ
19585 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT                                                             0x0
19586 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK                                                               0x000FFFFFL
19587 //CP_CE_IB2_CMD_BUFSZ
19588 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                             0x0
19589 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                               0x000FFFFFL
19590 //CP_IB1_CMD_BUFSZ
19591 #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT                                                                0x0
19592 #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK                                                                  0x000FFFFFL
19593 //CP_IB2_CMD_BUFSZ
19594 #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                                0x0
19595 #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                                  0x000FFFFFL
19596 //CP_ST_CMD_BUFSZ
19597 #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT                                                                  0x0
19598 #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK                                                                    0x000FFFFFL
19599 //CP_CE_INIT_BASE_LO
19600 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT                                                               0x5
19601 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK                                                                 0xFFFFFFE0L
19602 //CP_CE_INIT_BASE_HI
19603 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT                                                               0x0
19604 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK                                                                 0x0000FFFFL
19605 //CP_CE_INIT_BUFSZ
19606 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT                                                                   0x0
19607 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK                                                                     0x00000FFFL
19608 //CP_CE_IB1_BASE_LO
19609 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                 0x2
19610 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                   0xFFFFFFFCL
19611 //CP_CE_IB1_BASE_HI
19612 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                 0x0
19613 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                   0x0000FFFFL
19614 //CP_CE_IB1_BUFSZ
19615 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                     0x0
19616 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                       0x000FFFFFL
19617 //CP_CE_IB2_BASE_LO
19618 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                 0x2
19619 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                   0xFFFFFFFCL
19620 //CP_CE_IB2_BASE_HI
19621 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                 0x0
19622 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                   0x0000FFFFL
19623 //CP_CE_IB2_BUFSZ
19624 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                     0x0
19625 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                       0x000FFFFFL
19626 //CP_IB1_BASE_LO
19627 #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                    0x2
19628 #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                      0xFFFFFFFCL
19629 //CP_IB1_BASE_HI
19630 #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                    0x0
19631 #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                      0x0000FFFFL
19632 //CP_IB1_BUFSZ
19633 #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                        0x0
19634 #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                          0x000FFFFFL
19635 //CP_IB2_BASE_LO
19636 #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                    0x2
19637 #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                      0xFFFFFFFCL
19638 //CP_IB2_BASE_HI
19639 #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                    0x0
19640 #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                      0x0000FFFFL
19641 //CP_IB2_BUFSZ
19642 #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                        0x0
19643 #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                          0x000FFFFFL
19644 //CP_ST_BASE_LO
19645 #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT                                                                      0x2
19646 #define CP_ST_BASE_LO__ST_BASE_LO_MASK                                                                        0xFFFFFFFCL
19647 //CP_ST_BASE_HI
19648 #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT                                                                      0x0
19649 #define CP_ST_BASE_HI__ST_BASE_HI_MASK                                                                        0x0000FFFFL
19650 //CP_ST_BUFSZ
19651 #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                                                                          0x0
19652 #define CP_ST_BUFSZ__ST_BUFSZ_MASK                                                                            0x000FFFFFL
19653 //CP_EOP_DONE_EVENT_CNTL
19654 #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT                                                            0x0
19655 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT                                                       0xc
19656 #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT                                                           0x19
19657 #define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT                                                                0x1c
19658 #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK                                                              0x0000007FL
19659 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK                                                         0x0003F000L
19660 #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK                                                             0x02000000L
19661 #define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK                                                                  0x10000000L
19662 //CP_EOP_DONE_DATA_CNTL
19663 #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT                                                                 0x10
19664 #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT                                                                 0x18
19665 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT                                                                0x1d
19666 #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK                                                                   0x00030000L
19667 #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK                                                                   0x07000000L
19668 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK                                                                  0xE0000000L
19669 //CP_EOP_DONE_CNTX_ID
19670 #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT                                                                   0x0
19671 #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK                                                                     0xFFFFFFFFL
19672 //CP_PFP_COMPLETION_STATUS
19673 #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT                                                               0x0
19674 #define CP_PFP_COMPLETION_STATUS__STATUS_MASK                                                                 0x00000003L
19675 //CP_CE_COMPLETION_STATUS
19676 #define CP_CE_COMPLETION_STATUS__STATUS__SHIFT                                                                0x0
19677 #define CP_CE_COMPLETION_STATUS__STATUS_MASK                                                                  0x00000003L
19678 //CP_PRED_NOT_VISIBLE
19679 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT                                                               0x0
19680 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK                                                                 0x00000001L
19681 //CP_PFP_METADATA_BASE_ADDR
19682 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                             0x0
19683 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK                                                               0xFFFFFFFFL
19684 //CP_PFP_METADATA_BASE_ADDR_HI
19685 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
19686 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
19687 //CP_CE_METADATA_BASE_ADDR
19688 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                              0x0
19689 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK                                                                0xFFFFFFFFL
19690 //CP_CE_METADATA_BASE_ADDR_HI
19691 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                           0x0
19692 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                             0x0000FFFFL
19693 //CP_DRAW_INDX_INDR_ADDR
19694 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT                                                                0x0
19695 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK                                                                  0xFFFFFFFFL
19696 //CP_DRAW_INDX_INDR_ADDR_HI
19697 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT                                                             0x0
19698 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK                                                               0x0000FFFFL
19699 //CP_DISPATCH_INDR_ADDR
19700 #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT                                                                 0x0
19701 #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK                                                                   0xFFFFFFFFL
19702 //CP_DISPATCH_INDR_ADDR_HI
19703 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT                                                              0x0
19704 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK                                                                0x0000FFFFL
19705 //CP_INDEX_BASE_ADDR
19706 #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT                                                                    0x0
19707 #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK                                                                      0xFFFFFFFFL
19708 //CP_INDEX_BASE_ADDR_HI
19709 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
19710 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
19711 //CP_INDEX_TYPE
19712 #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                      0x0
19713 #define CP_INDEX_TYPE__INDEX_TYPE_MASK                                                                        0x00000003L
19714 //CP_GDS_BKUP_ADDR
19715 #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT                                                                      0x0
19716 #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK                                                                        0xFFFFFFFFL
19717 //CP_GDS_BKUP_ADDR_HI
19718 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
19719 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
19720 //CP_SAMPLE_STATUS
19721 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT                                                                0x0
19722 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT                                                             0x1
19723 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT                                                              0x2
19724 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT                                                               0x3
19725 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT                                                           0x4
19726 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT                                                            0x5
19727 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT                                                         0x6
19728 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT                                                         0x7
19729 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK                                                                  0x00000001L
19730 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK                                                               0x00000002L
19731 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK                                                                0x00000004L
19732 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK                                                                 0x00000008L
19733 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK                                                             0x00000010L
19734 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK                                                              0x00000020L
19735 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK                                                           0x00000040L
19736 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK                                                           0x00000080L
19737 //CP_ME_COHER_CNTL
19738 #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT                                                              0x0
19739 #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT                                                              0x1
19740 #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT                                                            0x6
19741 #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT                                                            0x7
19742 #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT                                                            0x8
19743 #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT                                                            0x9
19744 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT                                                            0xa
19745 #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT                                                            0xb
19746 #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT                                                            0xc
19747 #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT                                                            0xd
19748 #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT                                                             0xe
19749 #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT                                                              0x13
19750 #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT                                                              0x15
19751 #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK                                                                0x00000001L
19752 #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK                                                                0x00000002L
19753 #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK                                                              0x00000040L
19754 #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK                                                              0x00000080L
19755 #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK                                                              0x00000100L
19756 #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK                                                              0x00000200L
19757 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK                                                              0x00000400L
19758 #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK                                                              0x00000800L
19759 #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK                                                              0x00001000L
19760 #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK                                                              0x00002000L
19761 #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK                                                               0x00004000L
19762 #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK                                                                0x00080000L
19763 #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK                                                                0x00200000L
19764 //CP_ME_COHER_SIZE
19765 #define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                              0x0
19766 #define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK                                                                0xFFFFFFFFL
19767 //CP_ME_COHER_SIZE_HI
19768 #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                        0x0
19769 #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                          0x000000FFL
19770 //CP_ME_COHER_BASE
19771 #define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT                                                              0x0
19772 #define CP_ME_COHER_BASE__COHER_BASE_256B_MASK                                                                0xFFFFFFFFL
19773 //CP_ME_COHER_BASE_HI
19774 #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                        0x0
19775 #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                          0x000000FFL
19776 //CP_ME_COHER_STATUS
19777 #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT                                                          0x0
19778 #define CP_ME_COHER_STATUS__STATUS__SHIFT                                                                     0x1f
19779 #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK                                                            0x000000FFL
19780 #define CP_ME_COHER_STATUS__STATUS_MASK                                                                       0x80000000L
19781 //RLC_GPM_PERF_COUNT_0
19782 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT                                                              0x0
19783 #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT                                                                 0x4
19784 #define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT                                                                 0x8
19785 #define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT                                                                 0xc
19786 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT                                                                0x10
19787 #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT                                                                   0x12
19788 #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT                                                                   0x14
19789 #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT                                                                 0x15
19790 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK                                                                0x0000000FL
19791 #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK                                                                   0x000000F0L
19792 #define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK                                                                   0x00000F00L
19793 #define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK                                                                   0x0000F000L
19794 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK                                                                  0x00030000L
19795 #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK                                                                     0x000C0000L
19796 #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK                                                                     0x00100000L
19797 #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK                                                                   0xFFE00000L
19798 //RLC_GPM_PERF_COUNT_1
19799 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT                                                              0x0
19800 #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT                                                                 0x4
19801 #define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT                                                                 0x8
19802 #define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT                                                                 0xc
19803 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT                                                                0x10
19804 #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT                                                                   0x12
19805 #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT                                                                   0x14
19806 #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT                                                                 0x15
19807 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK                                                                0x0000000FL
19808 #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK                                                                   0x000000F0L
19809 #define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK                                                                   0x00000F00L
19810 #define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK                                                                   0x0000F000L
19811 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK                                                                  0x00030000L
19812 #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK                                                                     0x000C0000L
19813 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK                                                                     0x00100000L
19814 #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK                                                                   0xFFE00000L
19815 //GRBM_GFX_INDEX
19816 #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT                                                                 0x0
19817 #define GRBM_GFX_INDEX__SH_INDEX__SHIFT                                                                       0x8
19818 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT                                                                       0x10
19819 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT                                                            0x1d
19820 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT                                                      0x1e
19821 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT                                                            0x1f
19822 #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK                                                                   0x000000FFL
19823 #define GRBM_GFX_INDEX__SH_INDEX_MASK                                                                         0x0000FF00L
19824 #define GRBM_GFX_INDEX__SE_INDEX_MASK                                                                         0x00FF0000L
19825 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK                                                              0x20000000L
19826 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK                                                        0x40000000L
19827 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK                                                              0x80000000L
19828 //VGT_GSVS_RING_SIZE
19829 #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT                                                                   0x0
19830 #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK                                                                     0xFFFFFFFFL
19831 //VGT_PRIMITIVE_TYPE
19832 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                                  0x0
19833 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                    0x0000003FL
19834 //VGT_INDEX_TYPE
19835 #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                     0x0
19836 #define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT                                                                     0x8
19837 #define VGT_INDEX_TYPE__INDEX_TYPE_MASK                                                                       0x00000003L
19838 #define VGT_INDEX_TYPE__PRIMGEN_EN_MASK                                                                       0x00000100L
19839 //VGT_STRMOUT_BUFFER_FILLED_SIZE_0
19840 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT                                                         0x0
19841 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK                                                           0xFFFFFFFFL
19842 //VGT_STRMOUT_BUFFER_FILLED_SIZE_1
19843 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT                                                         0x0
19844 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK                                                           0xFFFFFFFFL
19845 //VGT_STRMOUT_BUFFER_FILLED_SIZE_2
19846 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT                                                         0x0
19847 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK                                                           0xFFFFFFFFL
19848 //VGT_STRMOUT_BUFFER_FILLED_SIZE_3
19849 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT                                                         0x0
19850 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK                                                           0xFFFFFFFFL
19851 //VGT_MAX_VTX_INDX
19852 #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                                                                     0x0
19853 #define VGT_MAX_VTX_INDX__MAX_INDX_MASK                                                                       0xFFFFFFFFL
19854 //VGT_MIN_VTX_INDX
19855 #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                                                                     0x0
19856 #define VGT_MIN_VTX_INDX__MIN_INDX_MASK                                                                       0xFFFFFFFFL
19857 //VGT_INDX_OFFSET
19858 #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                                                                   0x0
19859 #define VGT_INDX_OFFSET__INDX_OFFSET_MASK                                                                     0xFFFFFFFFL
19860 //VGT_MULTI_PRIM_IB_RESET_EN
19861 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT                                                           0x0
19862 #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT                                                     0x1
19863 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK                                                             0x00000001L
19864 #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK                                                       0x00000002L
19865 //VGT_NUM_INDICES
19866 #define VGT_NUM_INDICES__NUM_INDICES__SHIFT                                                                   0x0
19867 #define VGT_NUM_INDICES__NUM_INDICES_MASK                                                                     0xFFFFFFFFL
19868 //VGT_NUM_INSTANCES
19869 #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                               0x0
19870 #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK                                                                 0xFFFFFFFFL
19871 //VGT_TF_RING_SIZE
19872 #define VGT_TF_RING_SIZE__SIZE__SHIFT                                                                         0x0
19873 #define VGT_TF_RING_SIZE__SIZE_MASK                                                                           0x0000FFFFL
19874 //VGT_HS_OFFCHIP_PARAM
19875 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT                                                        0x0
19876 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT                                                      0x9
19877 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK                                                          0x000001FFL
19878 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK                                                        0x00000600L
19879 //VGT_TF_MEMORY_BASE
19880 #define VGT_TF_MEMORY_BASE__BASE__SHIFT                                                                       0x0
19881 #define VGT_TF_MEMORY_BASE__BASE_MASK                                                                         0xFFFFFFFFL
19882 //VGT_TF_MEMORY_BASE_HI
19883 #define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT                                                                 0x0
19884 #define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
19885 //WD_POS_BUF_BASE
19886 #define WD_POS_BUF_BASE__BASE__SHIFT                                                                          0x0
19887 #define WD_POS_BUF_BASE__BASE_MASK                                                                            0xFFFFFFFFL
19888 //WD_POS_BUF_BASE_HI
19889 #define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT                                                                    0x0
19890 #define WD_POS_BUF_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
19891 //WD_CNTL_SB_BUF_BASE
19892 #define WD_CNTL_SB_BUF_BASE__BASE__SHIFT                                                                      0x0
19893 #define WD_CNTL_SB_BUF_BASE__BASE_MASK                                                                        0xFFFFFFFFL
19894 //WD_CNTL_SB_BUF_BASE_HI
19895 #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT                                                                0x0
19896 #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK                                                                  0x000000FFL
19897 //WD_INDEX_BUF_BASE
19898 #define WD_INDEX_BUF_BASE__BASE__SHIFT                                                                        0x0
19899 #define WD_INDEX_BUF_BASE__BASE_MASK                                                                          0xFFFFFFFFL
19900 //WD_INDEX_BUF_BASE_HI
19901 #define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT                                                                  0x0
19902 #define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK                                                                    0x000000FFL
19903 //IA_MULTI_VGT_PARAM
19904 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT                                                             0x0
19905 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT                                                         0x10
19906 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT                                                              0x11
19907 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT                                                         0x12
19908 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT                                                              0x13
19909 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT                                                           0x14
19910 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT                                                          0x15
19911 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT                                                            0x16
19912 #define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT                                                                0x17
19913 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK                                                               0x0000FFFFL
19914 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK                                                           0x00010000L
19915 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK                                                                0x00020000L
19916 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK                                                           0x00040000L
19917 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK                                                                0x00080000L
19918 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK                                                             0x00100000L
19919 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK                                                            0x00200000L
19920 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK                                                              0x00400000L
19921 #define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK                                                                  0x00800000L
19922 //VGT_INSTANCE_BASE_ID
19923 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT                                                         0x0
19924 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK                                                           0xFFFFFFFFL
19925 //PA_SU_LINE_STIPPLE_VALUE
19926 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT                                                   0x0
19927 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK                                                     0x00FFFFFFL
19928 //PA_SC_LINE_STIPPLE_STATE
19929 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT                                                          0x0
19930 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT                                                        0x8
19931 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK                                                            0x0000000FL
19932 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK                                                          0x0000FF00L
19933 //PA_SC_SCREEN_EXTENT_MIN_0
19934 #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT                                                                   0x0
19935 #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT                                                                   0x10
19936 #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK                                                                     0x0000FFFFL
19937 #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK                                                                     0xFFFF0000L
19938 //PA_SC_SCREEN_EXTENT_MAX_0
19939 #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT                                                                   0x0
19940 #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT                                                                   0x10
19941 #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK                                                                     0x0000FFFFL
19942 #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK                                                                     0xFFFF0000L
19943 //PA_SC_SCREEN_EXTENT_MIN_1
19944 #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT                                                                   0x0
19945 #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT                                                                   0x10
19946 #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK                                                                     0x0000FFFFL
19947 #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK                                                                     0xFFFF0000L
19948 //PA_SC_SCREEN_EXTENT_MAX_1
19949 #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT                                                                   0x0
19950 #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT                                                                   0x10
19951 #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK                                                                     0x0000FFFFL
19952 #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK                                                                     0xFFFF0000L
19953 //PA_SC_P3D_TRAP_SCREEN_HV_EN
19954 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                              0x0
19955 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                       0x1
19956 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                0x00000001L
19957 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                         0x00000002L
19958 //PA_SC_P3D_TRAP_SCREEN_H
19959 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                               0x0
19960 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK                                                                 0x00003FFFL
19961 //PA_SC_P3D_TRAP_SCREEN_V
19962 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                               0x0
19963 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                 0x00003FFFL
19964 //PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
19965 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                        0x0
19966 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                          0x0000FFFFL
19967 //PA_SC_P3D_TRAP_SCREEN_COUNT
19968 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                             0x0
19969 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                               0x0000FFFFL
19970 //PA_SC_HP3D_TRAP_SCREEN_HV_EN
19971 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                             0x0
19972 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                      0x1
19973 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                               0x00000001L
19974 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                        0x00000002L
19975 //PA_SC_HP3D_TRAP_SCREEN_H
19976 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                              0x0
19977 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK                                                                0x00003FFFL
19978 //PA_SC_HP3D_TRAP_SCREEN_V
19979 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                              0x0
19980 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                0x00003FFFL
19981 //PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
19982 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                       0x0
19983 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                         0x0000FFFFL
19984 //PA_SC_HP3D_TRAP_SCREEN_COUNT
19985 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                            0x0
19986 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                              0x0000FFFFL
19987 //PA_SC_TRAP_SCREEN_HV_EN
19988 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                                  0x0
19989 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                           0x1
19990 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                    0x00000001L
19991 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                             0x00000002L
19992 //PA_SC_TRAP_SCREEN_H
19993 #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT                                                                   0x0
19994 #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK                                                                     0x00003FFFL
19995 //PA_SC_TRAP_SCREEN_V
19996 #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT                                                                   0x0
19997 #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK                                                                     0x00003FFFL
19998 //PA_SC_TRAP_SCREEN_OCCURRENCE
19999 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                            0x0
20000 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                              0x0000FFFFL
20001 //PA_SC_TRAP_SCREEN_COUNT
20002 #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                                 0x0
20003 #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK                                                                   0x0000FFFFL
20004 //SQ_THREAD_TRACE_BASE
20005 #define SQ_THREAD_TRACE_BASE__ADDR__SHIFT                                                                     0x0
20006 #define SQ_THREAD_TRACE_BASE__ADDR_MASK                                                                       0xFFFFFFFFL
20007 //SQ_THREAD_TRACE_SIZE
20008 #define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT                                                                     0x0
20009 #define SQ_THREAD_TRACE_SIZE__SIZE_MASK                                                                       0x003FFFFFL
20010 //SQ_THREAD_TRACE_MASK
20011 #define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT                                                                   0x0
20012 #define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT                                                                   0x5
20013 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT                                                             0x7
20014 #define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT                                                                  0x8
20015 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT                                                               0xc
20016 #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT                                                             0xe
20017 #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT                                                              0xf
20018 #define SQ_THREAD_TRACE_MASK__CU_SEL_MASK                                                                     0x0000001FL
20019 #define SQ_THREAD_TRACE_MASK__SH_SEL_MASK                                                                     0x00000020L
20020 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK                                                               0x00000080L
20021 #define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK                                                                    0x00000F00L
20022 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK                                                                 0x00003000L
20023 #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK                                                               0x00004000L
20024 #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK                                                                0x00008000L
20025 //SQ_THREAD_TRACE_TOKEN_MASK
20026 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT                                                         0x0
20027 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT                                                           0x10
20028 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT                                                  0x18
20029 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK                                                           0x0000FFFFL
20030 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK                                                             0x00FF0000L
20031 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK                                                    0x01000000L
20032 //SQ_THREAD_TRACE_PERF_MASK
20033 #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT                                                            0x0
20034 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT                                                            0x10
20035 #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK                                                              0x0000FFFFL
20036 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK                                                              0xFFFF0000L
20037 //SQ_THREAD_TRACE_CTRL
20038 #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT                                                             0x1f
20039 #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK                                                               0x80000000L
20040 //SQ_THREAD_TRACE_MODE
20041 #define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT                                                                  0x0
20042 #define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT                                                                  0x3
20043 #define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT                                                                  0x6
20044 #define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT                                                                  0x9
20045 #define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT                                                                  0xc
20046 #define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT                                                                  0xf
20047 #define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT                                                                  0x12
20048 #define SQ_THREAD_TRACE_MODE__MODE__SHIFT                                                                     0x15
20049 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT                                                             0x17
20050 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT                                                             0x19
20051 #define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT                                                               0x1a
20052 #define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT                                                               0x1b
20053 #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT                                                                0x1d
20054 #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT                                                             0x1e
20055 #define SQ_THREAD_TRACE_MODE__WRAP__SHIFT                                                                     0x1f
20056 #define SQ_THREAD_TRACE_MODE__MASK_PS_MASK                                                                    0x00000007L
20057 #define SQ_THREAD_TRACE_MODE__MASK_VS_MASK                                                                    0x00000038L
20058 #define SQ_THREAD_TRACE_MODE__MASK_GS_MASK                                                                    0x000001C0L
20059 #define SQ_THREAD_TRACE_MODE__MASK_ES_MASK                                                                    0x00000E00L
20060 #define SQ_THREAD_TRACE_MODE__MASK_HS_MASK                                                                    0x00007000L
20061 #define SQ_THREAD_TRACE_MODE__MASK_LS_MASK                                                                    0x00038000L
20062 #define SQ_THREAD_TRACE_MODE__MASK_CS_MASK                                                                    0x001C0000L
20063 #define SQ_THREAD_TRACE_MODE__MODE_MASK                                                                       0x00600000L
20064 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK                                                               0x01800000L
20065 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK                                                               0x02000000L
20066 #define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK                                                                 0x04000000L
20067 #define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK                                                                 0x18000000L
20068 #define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK                                                                  0x20000000L
20069 #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK                                                               0x40000000L
20070 #define SQ_THREAD_TRACE_MODE__WRAP_MASK                                                                       0x80000000L
20071 //SQ_THREAD_TRACE_BASE2
20072 #define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT                                                                 0x0
20073 #define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK                                                                   0x0000000FL
20074 //SQ_THREAD_TRACE_TOKEN_MASK2
20075 #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT                                                         0x0
20076 #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK                                                           0xFFFFFFFFL
20077 //SQ_THREAD_TRACE_WPTR
20078 #define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT                                                                     0x0
20079 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT                                                              0x1e
20080 #define SQ_THREAD_TRACE_WPTR__WPTR_MASK                                                                       0x3FFFFFFFL
20081 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK                                                                0xC0000000L
20082 //SQ_THREAD_TRACE_STATUS
20083 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT                                                         0x0
20084 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT                                                            0x10
20085 #define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT                                                              0x1c
20086 #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT                                                                0x1d
20087 #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT                                                                   0x1e
20088 #define SQ_THREAD_TRACE_STATUS__FULL__SHIFT                                                                   0x1f
20089 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK                                                           0x000003FFL
20090 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK                                                              0x03FF0000L
20091 #define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK                                                                0x10000000L
20092 #define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK                                                                  0x20000000L
20093 #define SQ_THREAD_TRACE_STATUS__BUSY_MASK                                                                     0x40000000L
20094 #define SQ_THREAD_TRACE_STATUS__FULL_MASK                                                                     0x80000000L
20095 //SQ_THREAD_TRACE_HIWATER
20096 #define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT                                                               0x0
20097 #define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK                                                                 0x00000007L
20098 //SQ_THREAD_TRACE_CNTR
20099 #define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT                                                                     0x0
20100 #define SQ_THREAD_TRACE_CNTR__CNTR_MASK                                                                       0xFFFFFFFFL
20101 //SQ_THREAD_TRACE_USERDATA_0
20102 #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT                                                               0x0
20103 #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK                                                                 0xFFFFFFFFL
20104 //SQ_THREAD_TRACE_USERDATA_1
20105 #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT                                                               0x0
20106 #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK                                                                 0xFFFFFFFFL
20107 //SQ_THREAD_TRACE_USERDATA_2
20108 #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT                                                               0x0
20109 #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK                                                                 0xFFFFFFFFL
20110 //SQ_THREAD_TRACE_USERDATA_3
20111 #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT                                                               0x0
20112 #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK                                                                 0xFFFFFFFFL
20113 //SQC_CACHES
20114 #define SQC_CACHES__TARGET_INST__SHIFT                                                                        0x0
20115 #define SQC_CACHES__TARGET_DATA__SHIFT                                                                        0x1
20116 #define SQC_CACHES__INVALIDATE__SHIFT                                                                         0x2
20117 #define SQC_CACHES__WRITEBACK__SHIFT                                                                          0x3
20118 #define SQC_CACHES__VOL__SHIFT                                                                                0x4
20119 #define SQC_CACHES__COMPLETE__SHIFT                                                                           0x10
20120 #define SQC_CACHES__TARGET_INST_MASK                                                                          0x00000001L
20121 #define SQC_CACHES__TARGET_DATA_MASK                                                                          0x00000002L
20122 #define SQC_CACHES__INVALIDATE_MASK                                                                           0x00000004L
20123 #define SQC_CACHES__WRITEBACK_MASK                                                                            0x00000008L
20124 #define SQC_CACHES__VOL_MASK                                                                                  0x00000010L
20125 #define SQC_CACHES__COMPLETE_MASK                                                                             0x00010000L
20126 //SQC_WRITEBACK
20127 #define SQC_WRITEBACK__DWB__SHIFT                                                                             0x0
20128 #define SQC_WRITEBACK__DIRTY__SHIFT                                                                           0x1
20129 #define SQC_WRITEBACK__DWB_MASK                                                                               0x00000001L
20130 #define SQC_WRITEBACK__DIRTY_MASK                                                                             0x00000002L
20131 //TA_CS_BC_BASE_ADDR
20132 #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT                                                                    0x0
20133 #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK                                                                      0xFFFFFFFFL
20134 //TA_CS_BC_BASE_ADDR_HI
20135 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT                                                                 0x0
20136 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK                                                                   0x000000FFL
20137 //DB_OCCLUSION_COUNT0_LOW
20138 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT                                                             0x0
20139 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
20140 //DB_OCCLUSION_COUNT0_HI
20141 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT                                                               0x0
20142 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
20143 //DB_OCCLUSION_COUNT1_LOW
20144 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT                                                             0x0
20145 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
20146 //DB_OCCLUSION_COUNT1_HI
20147 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT                                                               0x0
20148 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
20149 //DB_OCCLUSION_COUNT2_LOW
20150 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT                                                             0x0
20151 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
20152 //DB_OCCLUSION_COUNT2_HI
20153 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT                                                               0x0
20154 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
20155 //DB_OCCLUSION_COUNT3_LOW
20156 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT                                                             0x0
20157 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
20158 //DB_OCCLUSION_COUNT3_HI
20159 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT                                                               0x0
20160 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
20161 //DB_ZPASS_COUNT_LOW
20162 #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT                                                                  0x0
20163 #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK                                                                    0xFFFFFFFFL
20164 //DB_ZPASS_COUNT_HI
20165 #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT                                                                    0x0
20166 #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK                                                                      0x7FFFFFFFL
20167 //GDS_RD_ADDR
20168 #define GDS_RD_ADDR__READ_ADDR__SHIFT                                                                         0x0
20169 #define GDS_RD_ADDR__READ_ADDR_MASK                                                                           0xFFFFFFFFL
20170 //GDS_RD_DATA
20171 #define GDS_RD_DATA__READ_DATA__SHIFT                                                                         0x0
20172 #define GDS_RD_DATA__READ_DATA_MASK                                                                           0xFFFFFFFFL
20173 //GDS_RD_BURST_ADDR
20174 #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT                                                                  0x0
20175 #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK                                                                    0xFFFFFFFFL
20176 //GDS_RD_BURST_COUNT
20177 #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT                                                                0x0
20178 #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK                                                                  0xFFFFFFFFL
20179 //GDS_RD_BURST_DATA
20180 #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT                                                                  0x0
20181 #define GDS_RD_BURST_DATA__BURST_DATA_MASK                                                                    0xFFFFFFFFL
20182 //GDS_WR_ADDR
20183 #define GDS_WR_ADDR__WRITE_ADDR__SHIFT                                                                        0x0
20184 #define GDS_WR_ADDR__WRITE_ADDR_MASK                                                                          0xFFFFFFFFL
20185 //GDS_WR_DATA
20186 #define GDS_WR_DATA__WRITE_DATA__SHIFT                                                                        0x0
20187 #define GDS_WR_DATA__WRITE_DATA_MASK                                                                          0xFFFFFFFFL
20188 //GDS_WR_BURST_ADDR
20189 #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT                                                                  0x0
20190 #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK                                                                    0xFFFFFFFFL
20191 //GDS_WR_BURST_DATA
20192 #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT                                                                  0x0
20193 #define GDS_WR_BURST_DATA__WRITE_DATA_MASK                                                                    0xFFFFFFFFL
20194 //GDS_WRITE_COMPLETE
20195 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT                                                             0x0
20196 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK                                                               0xFFFFFFFFL
20197 //GDS_ATOM_CNTL
20198 #define GDS_ATOM_CNTL__AINC__SHIFT                                                                            0x0
20199 #define GDS_ATOM_CNTL__UNUSED1__SHIFT                                                                         0x6
20200 #define GDS_ATOM_CNTL__DMODE__SHIFT                                                                           0x8
20201 #define GDS_ATOM_CNTL__UNUSED2__SHIFT                                                                         0xa
20202 #define GDS_ATOM_CNTL__AINC_MASK                                                                              0x0000003FL
20203 #define GDS_ATOM_CNTL__UNUSED1_MASK                                                                           0x000000C0L
20204 #define GDS_ATOM_CNTL__DMODE_MASK                                                                             0x00000300L
20205 #define GDS_ATOM_CNTL__UNUSED2_MASK                                                                           0xFFFFFC00L
20206 //GDS_ATOM_COMPLETE
20207 #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT                                                                    0x0
20208 #define GDS_ATOM_COMPLETE__UNUSED__SHIFT                                                                      0x1
20209 #define GDS_ATOM_COMPLETE__COMPLETE_MASK                                                                      0x00000001L
20210 #define GDS_ATOM_COMPLETE__UNUSED_MASK                                                                        0xFFFFFFFEL
20211 //GDS_ATOM_BASE
20212 #define GDS_ATOM_BASE__BASE__SHIFT                                                                            0x0
20213 #define GDS_ATOM_BASE__UNUSED__SHIFT                                                                          0x10
20214 #define GDS_ATOM_BASE__BASE_MASK                                                                              0x0000FFFFL
20215 #define GDS_ATOM_BASE__UNUSED_MASK                                                                            0xFFFF0000L
20216 //GDS_ATOM_SIZE
20217 #define GDS_ATOM_SIZE__SIZE__SHIFT                                                                            0x0
20218 #define GDS_ATOM_SIZE__UNUSED__SHIFT                                                                          0x10
20219 #define GDS_ATOM_SIZE__SIZE_MASK                                                                              0x0000FFFFL
20220 #define GDS_ATOM_SIZE__UNUSED_MASK                                                                            0xFFFF0000L
20221 //GDS_ATOM_OFFSET0
20222 #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT                                                                      0x0
20223 #define GDS_ATOM_OFFSET0__UNUSED__SHIFT                                                                       0x8
20224 #define GDS_ATOM_OFFSET0__OFFSET0_MASK                                                                        0x000000FFL
20225 #define GDS_ATOM_OFFSET0__UNUSED_MASK                                                                         0xFFFFFF00L
20226 //GDS_ATOM_OFFSET1
20227 #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT                                                                      0x0
20228 #define GDS_ATOM_OFFSET1__UNUSED__SHIFT                                                                       0x8
20229 #define GDS_ATOM_OFFSET1__OFFSET1_MASK                                                                        0x000000FFL
20230 #define GDS_ATOM_OFFSET1__UNUSED_MASK                                                                         0xFFFFFF00L
20231 //GDS_ATOM_DST
20232 #define GDS_ATOM_DST__DST__SHIFT                                                                              0x0
20233 #define GDS_ATOM_DST__DST_MASK                                                                                0xFFFFFFFFL
20234 //GDS_ATOM_OP
20235 #define GDS_ATOM_OP__OP__SHIFT                                                                                0x0
20236 #define GDS_ATOM_OP__UNUSED__SHIFT                                                                            0x8
20237 #define GDS_ATOM_OP__OP_MASK                                                                                  0x000000FFL
20238 #define GDS_ATOM_OP__UNUSED_MASK                                                                              0xFFFFFF00L
20239 //GDS_ATOM_SRC0
20240 #define GDS_ATOM_SRC0__DATA__SHIFT                                                                            0x0
20241 #define GDS_ATOM_SRC0__DATA_MASK                                                                              0xFFFFFFFFL
20242 //GDS_ATOM_SRC0_U
20243 #define GDS_ATOM_SRC0_U__DATA__SHIFT                                                                          0x0
20244 #define GDS_ATOM_SRC0_U__DATA_MASK                                                                            0xFFFFFFFFL
20245 //GDS_ATOM_SRC1
20246 #define GDS_ATOM_SRC1__DATA__SHIFT                                                                            0x0
20247 #define GDS_ATOM_SRC1__DATA_MASK                                                                              0xFFFFFFFFL
20248 //GDS_ATOM_SRC1_U
20249 #define GDS_ATOM_SRC1_U__DATA__SHIFT                                                                          0x0
20250 #define GDS_ATOM_SRC1_U__DATA_MASK                                                                            0xFFFFFFFFL
20251 //GDS_ATOM_READ0
20252 #define GDS_ATOM_READ0__DATA__SHIFT                                                                           0x0
20253 #define GDS_ATOM_READ0__DATA_MASK                                                                             0xFFFFFFFFL
20254 //GDS_ATOM_READ0_U
20255 #define GDS_ATOM_READ0_U__DATA__SHIFT                                                                         0x0
20256 #define GDS_ATOM_READ0_U__DATA_MASK                                                                           0xFFFFFFFFL
20257 //GDS_ATOM_READ1
20258 #define GDS_ATOM_READ1__DATA__SHIFT                                                                           0x0
20259 #define GDS_ATOM_READ1__DATA_MASK                                                                             0xFFFFFFFFL
20260 //GDS_ATOM_READ1_U
20261 #define GDS_ATOM_READ1_U__DATA__SHIFT                                                                         0x0
20262 #define GDS_ATOM_READ1_U__DATA_MASK                                                                           0xFFFFFFFFL
20263 //GDS_GWS_RESOURCE_CNTL
20264 #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT                                                                   0x0
20265 #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT                                                                  0x6
20266 #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK                                                                     0x0000003FL
20267 #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK                                                                    0xFFFFFFC0L
20268 //GDS_GWS_RESOURCE
20269 #define GDS_GWS_RESOURCE__FLAG__SHIFT                                                                         0x0
20270 #define GDS_GWS_RESOURCE__COUNTER__SHIFT                                                                      0x1
20271 #define GDS_GWS_RESOURCE__TYPE__SHIFT                                                                         0xd
20272 #define GDS_GWS_RESOURCE__DED__SHIFT                                                                          0xe
20273 #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT                                                                  0xf
20274 #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT                                                                   0x10
20275 #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT                                                                   0x1c
20276 #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT                                                                    0x1d
20277 #define GDS_GWS_RESOURCE__HALTED__SHIFT                                                                       0x1e
20278 #define GDS_GWS_RESOURCE__UNUSED1__SHIFT                                                                      0x1f
20279 #define GDS_GWS_RESOURCE__FLAG_MASK                                                                           0x00000001L
20280 #define GDS_GWS_RESOURCE__COUNTER_MASK                                                                        0x00001FFEL
20281 #define GDS_GWS_RESOURCE__TYPE_MASK                                                                           0x00002000L
20282 #define GDS_GWS_RESOURCE__DED_MASK                                                                            0x00004000L
20283 #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK                                                                    0x00008000L
20284 #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK                                                                     0x0FFF0000L
20285 #define GDS_GWS_RESOURCE__HEAD_VALID_MASK                                                                     0x10000000L
20286 #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK                                                                      0x20000000L
20287 #define GDS_GWS_RESOURCE__HALTED_MASK                                                                         0x40000000L
20288 #define GDS_GWS_RESOURCE__UNUSED1_MASK                                                                        0x80000000L
20289 //GDS_GWS_RESOURCE_CNT
20290 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT                                                             0x0
20291 #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT                                                                   0x10
20292 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK                                                               0x0000FFFFL
20293 #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK                                                                     0xFFFF0000L
20294 //GDS_OA_CNTL
20295 #define GDS_OA_CNTL__INDEX__SHIFT                                                                             0x0
20296 #define GDS_OA_CNTL__UNUSED__SHIFT                                                                            0x4
20297 #define GDS_OA_CNTL__INDEX_MASK                                                                               0x0000000FL
20298 #define GDS_OA_CNTL__UNUSED_MASK                                                                              0xFFFFFFF0L
20299 //GDS_OA_COUNTER
20300 #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT                                                                0x0
20301 #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK                                                                  0xFFFFFFFFL
20302 //GDS_OA_ADDRESS
20303 #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT                                                                     0x0
20304 #define GDS_OA_ADDRESS__CRAWLER__SHIFT                                                                        0x10
20305 #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT                                                                   0x14
20306 #define GDS_OA_ADDRESS__UNUSED__SHIFT                                                                         0x16
20307 #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT                                                                       0x1e
20308 #define GDS_OA_ADDRESS__ENABLE__SHIFT                                                                         0x1f
20309 #define GDS_OA_ADDRESS__DS_ADDRESS_MASK                                                                       0x0000FFFFL
20310 #define GDS_OA_ADDRESS__CRAWLER_MASK                                                                          0x000F0000L
20311 #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK                                                                     0x00300000L
20312 #define GDS_OA_ADDRESS__UNUSED_MASK                                                                           0x3FC00000L
20313 #define GDS_OA_ADDRESS__NO_ALLOC_MASK                                                                         0x40000000L
20314 #define GDS_OA_ADDRESS__ENABLE_MASK                                                                           0x80000000L
20315 //GDS_OA_INCDEC
20316 #define GDS_OA_INCDEC__VALUE__SHIFT                                                                           0x0
20317 #define GDS_OA_INCDEC__INCDEC__SHIFT                                                                          0x1f
20318 #define GDS_OA_INCDEC__VALUE_MASK                                                                             0x7FFFFFFFL
20319 #define GDS_OA_INCDEC__INCDEC_MASK                                                                            0x80000000L
20320 //GDS_OA_RING_SIZE
20321 #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT                                                                    0x0
20322 #define GDS_OA_RING_SIZE__RING_SIZE_MASK                                                                      0xFFFFFFFFL
20323 //SPI_CONFIG_CNTL
20324 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT                                                            0x0
20325 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT                                                            0x15
20326 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT                                                         0x18
20327 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT                                                         0x19
20328 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT                                                               0x1a
20329 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT                                                              0x1b
20330 #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT                                                             0x1c
20331 #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT                                                               0x1d
20332 #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT                                                          0x1e
20333 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK                                                              0x001FFFFFL
20334 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK                                                              0x00E00000L
20335 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK                                                           0x01000000L
20336 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK                                                           0x02000000L
20337 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK                                                                 0x04000000L
20338 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK                                                                0x08000000L
20339 #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK                                                               0x10000000L
20340 #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK                                                                 0x20000000L
20341 #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK                                                            0xC0000000L
20342 //SPI_CONFIG_CNTL_1
20343 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT                                                              0x0
20344 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT                                                     0x4
20345 #define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT                                                         0x5
20346 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT                                                             0x6
20347 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT                                                             0x7
20348 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT                                                   0x8
20349 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT                                                            0x9
20350 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT                                                             0xa
20351 #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT                                                        0xe
20352 #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT                                                        0xf
20353 #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT                                                               0x10
20354 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK                                                                0x0000000FL
20355 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK                                                       0x00000010L
20356 #define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK                                                           0x00000020L
20357 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK                                                               0x00000040L
20358 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK                                                               0x00000080L
20359 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK                                                     0x00000100L
20360 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK                                                              0x00000200L
20361 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK                                                               0x00003C00L
20362 #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK                                                          0x00004000L
20363 #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK                                                          0x00008000L
20364 #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK                                                                 0xFFFF0000L
20365 //SPI_CONFIG_CNTL_2
20366 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT                                    0x0
20367 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT                                      0x4
20368 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK                                      0x0000000FL
20369 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK                                        0x000000F0L
20370 
20371 
20372 // addressBlock: gc_perfddec
20373 //CPG_PERFCOUNTER1_LO
20374 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20375 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20376 //CPG_PERFCOUNTER1_HI
20377 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20378 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20379 //CPG_PERFCOUNTER0_LO
20380 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20381 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20382 //CPG_PERFCOUNTER0_HI
20383 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20384 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20385 //CPC_PERFCOUNTER1_LO
20386 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20387 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20388 //CPC_PERFCOUNTER1_HI
20389 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20390 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20391 //CPC_PERFCOUNTER0_LO
20392 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20393 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20394 //CPC_PERFCOUNTER0_HI
20395 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20396 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20397 //CPF_PERFCOUNTER1_LO
20398 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20399 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20400 //CPF_PERFCOUNTER1_HI
20401 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20402 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20403 //CPF_PERFCOUNTER0_LO
20404 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20405 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20406 //CPF_PERFCOUNTER0_HI
20407 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20408 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20409 //CPF_LATENCY_STATS_DATA
20410 #define CPF_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
20411 #define CPF_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
20412 //CPG_LATENCY_STATS_DATA
20413 #define CPG_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
20414 #define CPG_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
20415 //CPC_LATENCY_STATS_DATA
20416 #define CPC_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
20417 #define CPC_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
20418 //GRBM_PERFCOUNTER0_LO
20419 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
20420 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
20421 //GRBM_PERFCOUNTER0_HI
20422 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
20423 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
20424 //GRBM_PERFCOUNTER1_LO
20425 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
20426 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
20427 //GRBM_PERFCOUNTER1_HI
20428 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
20429 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
20430 //GRBM_SE0_PERFCOUNTER_LO
20431 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
20432 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
20433 //GRBM_SE0_PERFCOUNTER_HI
20434 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
20435 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
20436 //GRBM_SE1_PERFCOUNTER_LO
20437 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
20438 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
20439 //GRBM_SE1_PERFCOUNTER_HI
20440 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
20441 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
20442 //GRBM_SE2_PERFCOUNTER_LO
20443 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
20444 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
20445 //GRBM_SE2_PERFCOUNTER_HI
20446 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
20447 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
20448 //GRBM_SE3_PERFCOUNTER_LO
20449 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
20450 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
20451 //GRBM_SE3_PERFCOUNTER_HI
20452 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
20453 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
20454 //WD_PERFCOUNTER0_LO
20455 #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20456 #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20457 //WD_PERFCOUNTER0_HI
20458 #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20459 #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20460 //WD_PERFCOUNTER1_LO
20461 #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20462 #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20463 //WD_PERFCOUNTER1_HI
20464 #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20465 #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20466 //WD_PERFCOUNTER2_LO
20467 #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20468 #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20469 //WD_PERFCOUNTER2_HI
20470 #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20471 #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20472 //WD_PERFCOUNTER3_LO
20473 #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20474 #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20475 //WD_PERFCOUNTER3_HI
20476 #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20477 #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20478 //IA_PERFCOUNTER0_LO
20479 #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20480 #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20481 //IA_PERFCOUNTER0_HI
20482 #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20483 #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20484 //IA_PERFCOUNTER1_LO
20485 #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20486 #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20487 //IA_PERFCOUNTER1_HI
20488 #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20489 #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20490 //IA_PERFCOUNTER2_LO
20491 #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20492 #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20493 //IA_PERFCOUNTER2_HI
20494 #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20495 #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20496 //IA_PERFCOUNTER3_LO
20497 #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20498 #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20499 //IA_PERFCOUNTER3_HI
20500 #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20501 #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20502 //VGT_PERFCOUNTER0_LO
20503 #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20504 #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20505 //VGT_PERFCOUNTER0_HI
20506 #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20507 #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20508 //VGT_PERFCOUNTER1_LO
20509 #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20510 #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20511 //VGT_PERFCOUNTER1_HI
20512 #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20513 #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20514 //VGT_PERFCOUNTER2_LO
20515 #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20516 #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20517 //VGT_PERFCOUNTER2_HI
20518 #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20519 #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20520 //VGT_PERFCOUNTER3_LO
20521 #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20522 #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20523 //VGT_PERFCOUNTER3_HI
20524 #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20525 #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20526 //PA_SU_PERFCOUNTER0_LO
20527 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20528 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20529 //PA_SU_PERFCOUNTER0_HI
20530 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20531 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
20532 //PA_SU_PERFCOUNTER1_LO
20533 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20534 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20535 //PA_SU_PERFCOUNTER1_HI
20536 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20537 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
20538 //PA_SU_PERFCOUNTER2_LO
20539 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20540 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20541 //PA_SU_PERFCOUNTER2_HI
20542 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20543 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
20544 //PA_SU_PERFCOUNTER3_LO
20545 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20546 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20547 //PA_SU_PERFCOUNTER3_HI
20548 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20549 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
20550 //PA_SC_PERFCOUNTER0_LO
20551 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20552 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20553 //PA_SC_PERFCOUNTER0_HI
20554 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20555 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20556 //PA_SC_PERFCOUNTER1_LO
20557 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20558 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20559 //PA_SC_PERFCOUNTER1_HI
20560 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20561 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20562 //PA_SC_PERFCOUNTER2_LO
20563 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20564 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20565 //PA_SC_PERFCOUNTER2_HI
20566 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20567 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20568 //PA_SC_PERFCOUNTER3_LO
20569 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20570 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20571 //PA_SC_PERFCOUNTER3_HI
20572 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20573 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20574 //PA_SC_PERFCOUNTER4_LO
20575 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20576 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20577 //PA_SC_PERFCOUNTER4_HI
20578 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20579 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20580 //PA_SC_PERFCOUNTER5_LO
20581 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20582 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20583 //PA_SC_PERFCOUNTER5_HI
20584 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20585 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20586 //PA_SC_PERFCOUNTER6_LO
20587 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20588 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20589 //PA_SC_PERFCOUNTER6_HI
20590 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20591 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20592 //PA_SC_PERFCOUNTER7_LO
20593 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20594 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20595 //PA_SC_PERFCOUNTER7_HI
20596 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20597 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20598 //SPI_PERFCOUNTER0_HI
20599 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20600 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20601 //SPI_PERFCOUNTER0_LO
20602 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20603 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20604 //SPI_PERFCOUNTER1_HI
20605 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20606 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20607 //SPI_PERFCOUNTER1_LO
20608 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20609 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20610 //SPI_PERFCOUNTER2_HI
20611 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20612 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20613 //SPI_PERFCOUNTER2_LO
20614 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20615 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20616 //SPI_PERFCOUNTER3_HI
20617 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20618 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20619 //SPI_PERFCOUNTER3_LO
20620 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20621 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20622 //SPI_PERFCOUNTER4_HI
20623 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20624 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20625 //SPI_PERFCOUNTER4_LO
20626 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20627 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20628 //SPI_PERFCOUNTER5_HI
20629 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20630 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20631 //SPI_PERFCOUNTER5_LO
20632 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20633 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20634 //SQ_PERFCOUNTER0_LO
20635 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20636 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20637 //SQ_PERFCOUNTER0_HI
20638 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20639 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20640 //SQ_PERFCOUNTER1_LO
20641 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20642 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20643 //SQ_PERFCOUNTER1_HI
20644 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20645 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20646 //SQ_PERFCOUNTER2_LO
20647 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20648 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20649 //SQ_PERFCOUNTER2_HI
20650 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20651 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20652 //SQ_PERFCOUNTER3_LO
20653 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20654 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20655 //SQ_PERFCOUNTER3_HI
20656 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20657 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20658 //SQ_PERFCOUNTER4_LO
20659 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20660 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20661 //SQ_PERFCOUNTER4_HI
20662 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20663 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20664 //SQ_PERFCOUNTER5_LO
20665 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20666 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20667 //SQ_PERFCOUNTER5_HI
20668 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20669 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20670 //SQ_PERFCOUNTER6_LO
20671 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20672 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20673 //SQ_PERFCOUNTER6_HI
20674 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20675 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20676 //SQ_PERFCOUNTER7_LO
20677 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20678 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20679 //SQ_PERFCOUNTER7_HI
20680 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20681 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20682 //SQ_PERFCOUNTER8_LO
20683 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20684 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20685 //SQ_PERFCOUNTER8_HI
20686 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20687 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20688 //SQ_PERFCOUNTER9_LO
20689 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20690 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20691 //SQ_PERFCOUNTER9_HI
20692 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20693 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20694 //SQ_PERFCOUNTER10_LO
20695 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20696 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20697 //SQ_PERFCOUNTER10_HI
20698 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20699 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20700 //SQ_PERFCOUNTER11_LO
20701 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20702 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20703 //SQ_PERFCOUNTER11_HI
20704 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20705 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20706 //SQ_PERFCOUNTER12_LO
20707 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20708 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20709 //SQ_PERFCOUNTER12_HI
20710 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20711 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20712 //SQ_PERFCOUNTER13_LO
20713 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20714 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20715 //SQ_PERFCOUNTER13_HI
20716 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20717 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20718 //SQ_PERFCOUNTER14_LO
20719 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20720 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20721 //SQ_PERFCOUNTER14_HI
20722 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20723 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20724 //SQ_PERFCOUNTER15_LO
20725 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20726 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20727 //SQ_PERFCOUNTER15_HI
20728 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20729 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20730 //SX_PERFCOUNTER0_LO
20731 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20732 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20733 //SX_PERFCOUNTER0_HI
20734 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20735 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20736 //SX_PERFCOUNTER1_LO
20737 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20738 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20739 //SX_PERFCOUNTER1_HI
20740 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20741 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20742 //SX_PERFCOUNTER2_LO
20743 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20744 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20745 //SX_PERFCOUNTER2_HI
20746 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20747 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20748 //SX_PERFCOUNTER3_LO
20749 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20750 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20751 //SX_PERFCOUNTER3_HI
20752 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20753 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20754 //GDS_PERFCOUNTER0_LO
20755 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20756 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20757 //GDS_PERFCOUNTER0_HI
20758 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20759 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20760 //GDS_PERFCOUNTER1_LO
20761 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20762 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20763 //GDS_PERFCOUNTER1_HI
20764 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20765 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20766 //GDS_PERFCOUNTER2_LO
20767 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20768 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20769 //GDS_PERFCOUNTER2_HI
20770 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20771 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20772 //GDS_PERFCOUNTER3_LO
20773 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20774 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20775 //GDS_PERFCOUNTER3_HI
20776 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20777 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20778 //TA_PERFCOUNTER0_LO
20779 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20780 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20781 //TA_PERFCOUNTER0_HI
20782 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20783 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20784 //TA_PERFCOUNTER1_LO
20785 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20786 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20787 //TA_PERFCOUNTER1_HI
20788 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20789 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20790 //TD_PERFCOUNTER0_LO
20791 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20792 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20793 //TD_PERFCOUNTER0_HI
20794 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20795 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20796 //TD_PERFCOUNTER1_LO
20797 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20798 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20799 //TD_PERFCOUNTER1_HI
20800 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20801 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20802 //TCP_PERFCOUNTER0_LO
20803 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20804 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20805 //TCP_PERFCOUNTER0_HI
20806 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20807 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20808 //TCP_PERFCOUNTER1_LO
20809 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20810 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20811 //TCP_PERFCOUNTER1_HI
20812 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20813 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20814 //TCP_PERFCOUNTER2_LO
20815 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20816 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20817 //TCP_PERFCOUNTER2_HI
20818 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20819 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20820 //TCP_PERFCOUNTER3_LO
20821 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20822 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20823 //TCP_PERFCOUNTER3_HI
20824 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20825 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20826 //TCC_PERFCOUNTER0_LO
20827 #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20828 #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20829 //TCC_PERFCOUNTER0_HI
20830 #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20831 #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20832 //TCC_PERFCOUNTER1_LO
20833 #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20834 #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20835 //TCC_PERFCOUNTER1_HI
20836 #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20837 #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20838 //TCC_PERFCOUNTER2_LO
20839 #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20840 #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20841 //TCC_PERFCOUNTER2_HI
20842 #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20843 #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20844 //TCC_PERFCOUNTER3_LO
20845 #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20846 #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20847 //TCC_PERFCOUNTER3_HI
20848 #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20849 #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20850 //TCA_PERFCOUNTER0_LO
20851 #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20852 #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20853 //TCA_PERFCOUNTER0_HI
20854 #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20855 #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20856 //TCA_PERFCOUNTER1_LO
20857 #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20858 #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20859 //TCA_PERFCOUNTER1_HI
20860 #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20861 #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20862 //TCA_PERFCOUNTER2_LO
20863 #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20864 #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20865 //TCA_PERFCOUNTER2_HI
20866 #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20867 #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20868 //TCA_PERFCOUNTER3_LO
20869 #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20870 #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20871 //TCA_PERFCOUNTER3_HI
20872 #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20873 #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20874 //CB_PERFCOUNTER0_LO
20875 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20876 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20877 //CB_PERFCOUNTER0_HI
20878 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20879 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20880 //CB_PERFCOUNTER1_LO
20881 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20882 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20883 //CB_PERFCOUNTER1_HI
20884 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20885 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20886 //CB_PERFCOUNTER2_LO
20887 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20888 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20889 //CB_PERFCOUNTER2_HI
20890 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20891 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20892 //CB_PERFCOUNTER3_LO
20893 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20894 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20895 //CB_PERFCOUNTER3_HI
20896 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20897 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20898 //DB_PERFCOUNTER0_LO
20899 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20900 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20901 //DB_PERFCOUNTER0_HI
20902 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20903 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20904 //DB_PERFCOUNTER1_LO
20905 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20906 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20907 //DB_PERFCOUNTER1_HI
20908 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20909 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20910 //DB_PERFCOUNTER2_LO
20911 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20912 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20913 //DB_PERFCOUNTER2_HI
20914 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20915 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20916 //DB_PERFCOUNTER3_LO
20917 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20918 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20919 //DB_PERFCOUNTER3_HI
20920 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20921 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20922 //RLC_PERFCOUNTER0_LO
20923 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20924 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20925 //RLC_PERFCOUNTER0_HI
20926 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20927 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20928 //RLC_PERFCOUNTER1_LO
20929 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20930 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20931 //RLC_PERFCOUNTER1_HI
20932 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20933 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20934 //RMI_PERFCOUNTER0_LO
20935 #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20936 #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20937 //RMI_PERFCOUNTER0_HI
20938 #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20939 #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20940 //RMI_PERFCOUNTER1_LO
20941 #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20942 #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20943 //RMI_PERFCOUNTER1_HI
20944 #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20945 #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20946 //RMI_PERFCOUNTER2_LO
20947 #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20948 #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20949 //RMI_PERFCOUNTER2_HI
20950 #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20951 #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20952 //RMI_PERFCOUNTER3_LO
20953 #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20954 #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20955 //RMI_PERFCOUNTER3_HI
20956 #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20957 #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20958 
20959 
20960 // addressBlock: gc_utcl2_atcl2pfcntrdec
20961 //ATC_L2_PERFCOUNTER_LO
20962 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                              0x0
20963 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                0xFFFFFFFFL
20964 //ATC_L2_PERFCOUNTER_HI
20965 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                              0x0
20966 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                           0x10
20967 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                0x0000FFFFL
20968 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                             0xFFFF0000L
20969 
20970 
20971 // addressBlock: gc_utcl2_vml2prdec
20972 //MC_VM_L2_PERFCOUNTER_LO
20973 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                            0x0
20974 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                              0xFFFFFFFFL
20975 //MC_VM_L2_PERFCOUNTER_HI
20976 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                            0x0
20977 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                         0x10
20978 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                              0x0000FFFFL
20979 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                           0xFFFF0000L
20980 
20981 
20982 // addressBlock: gc_perfsdec
20983 //CPG_PERFCOUNTER1_SELECT
20984 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT                                                             0x0
20985 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT                                                             0xa
20986 #define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
20987 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
20988 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
20989 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
20990 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
20991 #define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
20992 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
20993 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
20994 //CPG_PERFCOUNTER0_SELECT1
20995 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT                                                            0x0
20996 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT                                                            0xa
20997 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
20998 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
20999 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK                                                              0x000003FFL
21000 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK                                                              0x000FFC00L
21001 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
21002 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
21003 //CPG_PERFCOUNTER0_SELECT
21004 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21005 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21006 #define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
21007 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21008 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21009 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21010 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21011 #define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21012 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21013 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21014 //CPC_PERFCOUNTER1_SELECT
21015 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21016 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21017 #define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
21018 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21019 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21020 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21021 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21022 #define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21023 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21024 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21025 //CPC_PERFCOUNTER0_SELECT1
21026 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT                                                            0x0
21027 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT                                                            0xa
21028 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
21029 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
21030 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK                                                              0x000003FFL
21031 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK                                                              0x000FFC00L
21032 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
21033 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
21034 //CPF_PERFCOUNTER1_SELECT
21035 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21036 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21037 #define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
21038 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21039 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21040 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21041 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21042 #define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21043 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21044 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21045 //CPF_PERFCOUNTER0_SELECT1
21046 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT                                                            0x0
21047 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT                                                            0xa
21048 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
21049 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
21050 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK                                                              0x000003FFL
21051 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK                                                              0x000FFC00L
21052 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
21053 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
21054 //CPF_PERFCOUNTER0_SELECT
21055 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21056 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21057 #define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
21058 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21059 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21060 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21061 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21062 #define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21063 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21064 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21065 //CP_PERFMON_CNTL
21066 #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                 0x0
21067 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT                                                             0x4
21068 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT                                                           0x8
21069 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                         0xa
21070 #define CP_PERFMON_CNTL__PERFMON_STATE_MASK                                                                   0x0000000FL
21071 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK                                                               0x000000F0L
21072 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK                                                             0x00000300L
21073 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                           0x00000400L
21074 //CPC_PERFCOUNTER0_SELECT
21075 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21076 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21077 #define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
21078 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21079 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21080 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21081 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21082 #define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21083 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21084 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21085 //CPF_TC_PERF_COUNTER_WINDOW_SELECT
21086 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
21087 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
21088 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
21089 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x00000007L
21090 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
21091 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
21092 //CPG_TC_PERF_COUNTER_WINDOW_SELECT
21093 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
21094 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
21095 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
21096 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x0000001FL
21097 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
21098 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
21099 //CPF_LATENCY_STATS_SELECT
21100 #define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
21101 #define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
21102 #define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
21103 #define CPF_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000000FL
21104 #define CPF_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
21105 #define CPF_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
21106 //CPG_LATENCY_STATS_SELECT
21107 #define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
21108 #define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
21109 #define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
21110 #define CPG_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000001FL
21111 #define CPG_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
21112 #define CPG_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
21113 //CPC_LATENCY_STATS_SELECT
21114 #define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
21115 #define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
21116 #define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
21117 #define CPC_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x00000007L
21118 #define CPC_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
21119 #define CPC_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
21120 //CP_DRAW_OBJECT
21121 #define CP_DRAW_OBJECT__OBJECT__SHIFT                                                                         0x0
21122 #define CP_DRAW_OBJECT__OBJECT_MASK                                                                           0xFFFFFFFFL
21123 //CP_DRAW_OBJECT_COUNTER
21124 #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT                                                                  0x0
21125 #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK                                                                    0x0000FFFFL
21126 //CP_DRAW_WINDOW_MASK_HI
21127 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT                                                         0x0
21128 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK                                                           0xFFFFFFFFL
21129 //CP_DRAW_WINDOW_HI
21130 #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT                                                                   0x0
21131 #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK                                                                     0xFFFFFFFFL
21132 //CP_DRAW_WINDOW_LO
21133 #define CP_DRAW_WINDOW_LO__MIN__SHIFT                                                                         0x0
21134 #define CP_DRAW_WINDOW_LO__MAX__SHIFT                                                                         0x10
21135 #define CP_DRAW_WINDOW_LO__MIN_MASK                                                                           0x0000FFFFL
21136 #define CP_DRAW_WINDOW_LO__MAX_MASK                                                                           0xFFFF0000L
21137 //CP_DRAW_WINDOW_CNTL
21138 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT                                                0x0
21139 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT                                                0x1
21140 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT                                                    0x2
21141 #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT                                                                      0x8
21142 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK                                                  0x00000001L
21143 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK                                                  0x00000002L
21144 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK                                                      0x00000004L
21145 #define CP_DRAW_WINDOW_CNTL__MODE_MASK                                                                        0x00000100L
21146 //GRBM_PERFCOUNTER0_SELECT
21147 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
21148 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
21149 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
21150 #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                           0xc
21151 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
21152 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
21153 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
21154 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
21155 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
21156 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
21157 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
21158 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
21159 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
21160 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x17
21161 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
21162 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
21163 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
21164 #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1b
21165 #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
21166 #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
21167 #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
21168 #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
21169 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x0000003FL
21170 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
21171 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
21172 #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                             0x00001000L
21173 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
21174 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
21175 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
21176 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
21177 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
21178 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
21179 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
21180 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
21181 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
21182 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK                                              0x00800000L
21183 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
21184 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
21185 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
21186 #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK                                              0x08000000L
21187 #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
21188 #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
21189 #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
21190 #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
21191 //GRBM_PERFCOUNTER1_SELECT
21192 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
21193 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
21194 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
21195 #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                           0xc
21196 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
21197 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
21198 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
21199 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
21200 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
21201 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
21202 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
21203 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
21204 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
21205 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x17
21206 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
21207 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
21208 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
21209 #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1b
21210 #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
21211 #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
21212 #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
21213 #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
21214 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x0000003FL
21215 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
21216 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
21217 #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                             0x00001000L
21218 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
21219 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
21220 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
21221 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
21222 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
21223 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
21224 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
21225 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
21226 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
21227 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK                                              0x00800000L
21228 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
21229 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
21230 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
21231 #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK                                              0x08000000L
21232 #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
21233 #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
21234 #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
21235 #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
21236 //GRBM_SE0_PERFCOUNTER_SELECT
21237 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
21238 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
21239 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
21240 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
21241 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
21242 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
21243 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
21244 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
21245 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
21246 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
21247 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
21248 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
21249 #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
21250 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
21251 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
21252 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
21253 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
21254 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
21255 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
21256 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
21257 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
21258 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
21259 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
21260 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
21261 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
21262 #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
21263 //GRBM_SE1_PERFCOUNTER_SELECT
21264 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
21265 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
21266 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
21267 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
21268 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
21269 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
21270 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
21271 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
21272 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
21273 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
21274 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
21275 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
21276 #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
21277 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
21278 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
21279 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
21280 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
21281 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
21282 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
21283 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
21284 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
21285 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
21286 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
21287 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
21288 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
21289 #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
21290 //GRBM_SE2_PERFCOUNTER_SELECT
21291 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
21292 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
21293 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
21294 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
21295 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
21296 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
21297 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
21298 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
21299 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
21300 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
21301 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
21302 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
21303 #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
21304 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
21305 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
21306 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
21307 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
21308 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
21309 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
21310 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
21311 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
21312 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
21313 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
21314 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
21315 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
21316 #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
21317 //GRBM_SE3_PERFCOUNTER_SELECT
21318 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
21319 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
21320 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
21321 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
21322 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
21323 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
21324 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
21325 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
21326 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
21327 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
21328 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
21329 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
21330 #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
21331 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
21332 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
21333 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
21334 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
21335 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
21336 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
21337 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
21338 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
21339 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
21340 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
21341 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
21342 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
21343 #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
21344 //WD_PERFCOUNTER0_SELECT
21345 #define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21346 #define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21347 #define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21348 #define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21349 //WD_PERFCOUNTER1_SELECT
21350 #define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
21351 #define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
21352 #define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21353 #define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21354 //WD_PERFCOUNTER2_SELECT
21355 #define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
21356 #define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
21357 #define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21358 #define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21359 //WD_PERFCOUNTER3_SELECT
21360 #define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
21361 #define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
21362 #define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21363 #define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21364 //IA_PERFCOUNTER0_SELECT
21365 #define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21366 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
21367 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
21368 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
21369 #define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21370 #define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
21371 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
21372 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21373 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
21374 #define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21375 //IA_PERFCOUNTER1_SELECT
21376 #define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
21377 #define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
21378 #define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21379 #define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21380 //IA_PERFCOUNTER2_SELECT
21381 #define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
21382 #define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
21383 #define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21384 #define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21385 //IA_PERFCOUNTER3_SELECT
21386 #define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
21387 #define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
21388 #define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21389 #define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21390 //IA_PERFCOUNTER0_SELECT1
21391 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
21392 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
21393 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
21394 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
21395 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
21396 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
21397 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
21398 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
21399 //VGT_PERFCOUNTER0_SELECT
21400 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
21401 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
21402 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
21403 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
21404 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
21405 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21406 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21407 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21408 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21409 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21410 //VGT_PERFCOUNTER1_SELECT
21411 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
21412 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
21413 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
21414 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
21415 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
21416 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21417 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21418 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21419 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21420 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21421 //VGT_PERFCOUNTER2_SELECT
21422 #define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
21423 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
21424 #define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000000FFL
21425 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21426 //VGT_PERFCOUNTER3_SELECT
21427 #define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
21428 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
21429 #define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000000FFL
21430 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21431 //VGT_PERFCOUNTER0_SELECT1
21432 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21433 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21434 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21435 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21436 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21437 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21438 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21439 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21440 //VGT_PERFCOUNTER1_SELECT1
21441 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21442 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21443 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21444 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21445 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21446 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21447 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21448 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21449 //VGT_PERFCOUNTER_SEID_MASK
21450 #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT                                               0x0
21451 #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK                                                 0x000000FFL
21452 //PA_SU_PERFCOUNTER0_SELECT
21453 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
21454 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
21455 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
21456 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21457 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
21458 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21459 //PA_SU_PERFCOUNTER0_SELECT1
21460 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
21461 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
21462 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
21463 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
21464 //PA_SU_PERFCOUNTER1_SELECT
21465 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
21466 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
21467 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
21468 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21469 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
21470 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21471 //PA_SU_PERFCOUNTER1_SELECT1
21472 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
21473 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
21474 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
21475 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
21476 //PA_SU_PERFCOUNTER2_SELECT
21477 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
21478 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                           0x14
21479 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21480 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21481 //PA_SU_PERFCOUNTER3_SELECT
21482 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
21483 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                           0x14
21484 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21485 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21486 //PA_SC_PERFCOUNTER0_SELECT
21487 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
21488 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
21489 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
21490 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21491 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
21492 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21493 //PA_SC_PERFCOUNTER0_SELECT1
21494 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
21495 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
21496 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
21497 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
21498 //PA_SC_PERFCOUNTER1_SELECT
21499 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
21500 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21501 //PA_SC_PERFCOUNTER2_SELECT
21502 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
21503 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21504 //PA_SC_PERFCOUNTER3_SELECT
21505 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
21506 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21507 //PA_SC_PERFCOUNTER4_SELECT
21508 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                            0x0
21509 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21510 //PA_SC_PERFCOUNTER5_SELECT
21511 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                            0x0
21512 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21513 //PA_SC_PERFCOUNTER6_SELECT
21514 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                            0x0
21515 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21516 //PA_SC_PERFCOUNTER7_SELECT
21517 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                            0x0
21518 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21519 //SPI_PERFCOUNTER0_SELECT
21520 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
21521 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
21522 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
21523 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
21524 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
21525 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21526 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21527 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21528 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21529 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21530 //SPI_PERFCOUNTER1_SELECT
21531 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
21532 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
21533 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
21534 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
21535 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
21536 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21537 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21538 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21539 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21540 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21541 //SPI_PERFCOUNTER2_SELECT
21542 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
21543 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
21544 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
21545 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
21546 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
21547 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21548 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21549 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21550 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21551 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21552 //SPI_PERFCOUNTER3_SELECT
21553 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
21554 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                             0xa
21555 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
21556 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                            0x18
21557 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
21558 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21559 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21560 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21561 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21562 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21563 //SPI_PERFCOUNTER0_SELECT1
21564 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21565 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21566 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21567 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21568 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21569 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21570 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21571 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21572 //SPI_PERFCOUNTER1_SELECT1
21573 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21574 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21575 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21576 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21577 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21578 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21579 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21580 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21581 //SPI_PERFCOUNTER2_SELECT1
21582 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21583 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21584 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21585 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21586 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21587 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21588 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21589 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21590 //SPI_PERFCOUNTER3_SELECT1
21591 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21592 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21593 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21594 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21595 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21596 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21597 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21598 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21599 //SPI_PERFCOUNTER4_SELECT
21600 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                              0x0
21601 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                0x000000FFL
21602 //SPI_PERFCOUNTER5_SELECT
21603 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                              0x0
21604 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                0x000000FFL
21605 //SPI_PERFCOUNTER_BINS
21606 #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT                                                                 0x0
21607 #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT                                                                 0x4
21608 #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT                                                                 0x8
21609 #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT                                                                 0xc
21610 #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT                                                                 0x10
21611 #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT                                                                 0x14
21612 #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT                                                                 0x18
21613 #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT                                                                 0x1c
21614 #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK                                                                   0x0000000FL
21615 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK                                                                   0x000000F0L
21616 #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK                                                                   0x00000F00L
21617 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK                                                                   0x0000F000L
21618 #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK                                                                   0x000F0000L
21619 #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK                                                                   0x00F00000L
21620 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK                                                                   0x0F000000L
21621 #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK                                                                   0xF0000000L
21622 //SQ_PERFCOUNTER0_SELECT
21623 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21624 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21625 #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21626 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                               0x14
21627 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT                                                              0x18
21628 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21629 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21630 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21631 #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21632 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21633 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21634 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21635 //SQ_PERFCOUNTER1_SELECT
21636 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
21637 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21638 #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21639 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                               0x14
21640 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT                                                              0x18
21641 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
21642 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21643 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21644 #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21645 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21646 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21647 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21648 //SQ_PERFCOUNTER2_SELECT
21649 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
21650 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21651 #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21652 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT                                                               0x14
21653 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT                                                              0x18
21654 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
21655 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21656 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21657 #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21658 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21659 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21660 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21661 //SQ_PERFCOUNTER3_SELECT
21662 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
21663 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21664 #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21665 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT                                                               0x14
21666 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT                                                              0x18
21667 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
21668 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21669 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21670 #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21671 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21672 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21673 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21674 //SQ_PERFCOUNTER4_SELECT
21675 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                               0x0
21676 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21677 #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21678 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT                                                               0x14
21679 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT                                                              0x18
21680 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT                                                              0x1c
21681 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21682 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21683 #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21684 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21685 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21686 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21687 //SQ_PERFCOUNTER5_SELECT
21688 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                               0x0
21689 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21690 #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21691 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT                                                               0x14
21692 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT                                                              0x18
21693 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT                                                              0x1c
21694 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21695 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21696 #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21697 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21698 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21699 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21700 //SQ_PERFCOUNTER6_SELECT
21701 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                               0x0
21702 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21703 #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21704 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT                                                               0x14
21705 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT                                                              0x18
21706 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT                                                              0x1c
21707 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21708 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21709 #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21710 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21711 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21712 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21713 //SQ_PERFCOUNTER7_SELECT
21714 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                               0x0
21715 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21716 #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21717 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT                                                               0x14
21718 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT                                                              0x18
21719 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT                                                              0x1c
21720 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21721 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21722 #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21723 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21724 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21725 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21726 //SQ_PERFCOUNTER8_SELECT
21727 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT                                                               0x0
21728 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21729 #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21730 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT                                                               0x14
21731 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT                                                              0x18
21732 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT                                                              0x1c
21733 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21734 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21735 #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21736 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21737 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21738 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21739 //SQ_PERFCOUNTER9_SELECT
21740 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT                                                               0x0
21741 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21742 #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21743 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT                                                               0x14
21744 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT                                                              0x18
21745 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT                                                              0x1c
21746 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21747 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21748 #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21749 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21750 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21751 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21752 //SQ_PERFCOUNTER10_SELECT
21753 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT                                                              0x0
21754 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21755 #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21756 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT                                                              0x14
21757 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT                                                             0x18
21758 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT                                                             0x1c
21759 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21760 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21761 #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21762 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21763 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21764 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21765 //SQ_PERFCOUNTER11_SELECT
21766 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT                                                              0x0
21767 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21768 #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21769 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT                                                              0x14
21770 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT                                                             0x18
21771 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT                                                             0x1c
21772 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21773 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21774 #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21775 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21776 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21777 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21778 //SQ_PERFCOUNTER12_SELECT
21779 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT                                                              0x0
21780 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21781 #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21782 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT                                                              0x14
21783 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT                                                             0x18
21784 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT                                                             0x1c
21785 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21786 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21787 #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21788 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21789 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21790 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21791 //SQ_PERFCOUNTER13_SELECT
21792 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT                                                              0x0
21793 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21794 #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21795 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT                                                              0x14
21796 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT                                                             0x18
21797 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT                                                             0x1c
21798 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21799 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21800 #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21801 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21802 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21803 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21804 //SQ_PERFCOUNTER14_SELECT
21805 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT                                                              0x0
21806 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21807 #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21808 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT                                                              0x14
21809 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT                                                             0x18
21810 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT                                                             0x1c
21811 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21812 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21813 #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21814 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21815 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21816 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21817 //SQ_PERFCOUNTER15_SELECT
21818 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT                                                              0x0
21819 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21820 #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21821 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT                                                              0x14
21822 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT                                                             0x18
21823 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT                                                             0x1c
21824 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21825 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21826 #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21827 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21828 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21829 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21830 //SQ_PERFCOUNTER_CTRL
21831 #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT                                                                     0x0
21832 #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT                                                                     0x1
21833 #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT                                                                     0x2
21834 #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT                                                                     0x3
21835 #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT                                                                     0x4
21836 #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT                                                                     0x5
21837 #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT                                                                     0x6
21838 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT                                                                 0x8
21839 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT                                                             0xd
21840 #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK                                                                       0x00000001L
21841 #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK                                                                       0x00000002L
21842 #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK                                                                       0x00000004L
21843 #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK                                                                       0x00000008L
21844 #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK                                                                       0x00000010L
21845 #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK                                                                       0x00000020L
21846 #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK                                                                       0x00000040L
21847 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK                                                                   0x00001F00L
21848 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK                                                               0x00002000L
21849 //SQ_PERFCOUNTER_MASK
21850 #define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT                                                                  0x0
21851 #define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT                                                                  0x10
21852 #define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK                                                                    0x0000FFFFL
21853 #define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK                                                                    0xFFFF0000L
21854 //SQ_PERFCOUNTER_CTRL2
21855 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT                                                                 0x0
21856 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK                                                                   0x00000001L
21857 //SX_PERFCOUNTER0_SELECT
21858 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
21859 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
21860 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
21861 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
21862 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
21863 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21864 //SX_PERFCOUNTER1_SELECT
21865 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
21866 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
21867 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
21868 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
21869 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
21870 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21871 //SX_PERFCOUNTER2_SELECT
21872 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
21873 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
21874 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
21875 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
21876 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
21877 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21878 //SX_PERFCOUNTER3_SELECT
21879 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
21880 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
21881 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
21882 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
21883 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
21884 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21885 //SX_PERFCOUNTER0_SELECT1
21886 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT                                                   0x0
21887 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT                                                   0xa
21888 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK                                                     0x000003FFL
21889 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK                                                     0x000FFC00L
21890 //SX_PERFCOUNTER1_SELECT1
21891 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT                                                   0x0
21892 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT                                                   0xa
21893 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK                                                     0x000003FFL
21894 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK                                                     0x000FFC00L
21895 //GDS_PERFCOUNTER0_SELECT
21896 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
21897 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                   0xa
21898 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
21899 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000003FFL
21900 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK                                                     0x000FFC00L
21901 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21902 //GDS_PERFCOUNTER1_SELECT
21903 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
21904 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                   0xa
21905 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
21906 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000003FFL
21907 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK                                                     0x000FFC00L
21908 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21909 //GDS_PERFCOUNTER2_SELECT
21910 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
21911 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                   0xa
21912 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
21913 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000003FFL
21914 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK                                                     0x000FFC00L
21915 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21916 //GDS_PERFCOUNTER3_SELECT
21917 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
21918 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                   0xa
21919 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
21920 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000003FFL
21921 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK                                                     0x000FFC00L
21922 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21923 //GDS_PERFCOUNTER0_SELECT1
21924 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT                                                  0x0
21925 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT                                                  0xa
21926 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK                                                    0x000003FFL
21927 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK                                                    0x000FFC00L
21928 //TA_PERFCOUNTER0_SELECT
21929 #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21930 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
21931 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
21932 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
21933 #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21934 #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21935 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
21936 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21937 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
21938 #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21939 //TA_PERFCOUNTER0_SELECT1
21940 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
21941 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
21942 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
21943 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
21944 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000000FFL
21945 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0003FC00L
21946 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
21947 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
21948 //TA_PERFCOUNTER1_SELECT
21949 #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
21950 #define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
21951 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
21952 #define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
21953 #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
21954 #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21955 #define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
21956 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21957 #define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
21958 #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21959 //TD_PERFCOUNTER0_SELECT
21960 #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21961 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
21962 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
21963 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
21964 #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21965 #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21966 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
21967 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21968 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
21969 #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21970 //TD_PERFCOUNTER0_SELECT1
21971 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
21972 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
21973 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
21974 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
21975 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000000FFL
21976 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0003FC00L
21977 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
21978 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
21979 //TD_PERFCOUNTER1_SELECT
21980 #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
21981 #define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
21982 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
21983 #define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
21984 #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
21985 #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21986 #define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
21987 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21988 #define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
21989 #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21990 //TCP_PERFCOUNTER0_SELECT
21991 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
21992 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
21993 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
21994 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
21995 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
21996 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21997 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21998 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21999 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22000 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22001 //TCP_PERFCOUNTER0_SELECT1
22002 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22003 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22004 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
22005 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
22006 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22007 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22008 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
22009 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
22010 //TCP_PERFCOUNTER1_SELECT
22011 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
22012 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
22013 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
22014 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
22015 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
22016 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22017 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22018 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22019 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22020 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22021 //TCP_PERFCOUNTER1_SELECT1
22022 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22023 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22024 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
22025 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
22026 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22027 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22028 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
22029 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
22030 //TCP_PERFCOUNTER2_SELECT
22031 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
22032 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
22033 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
22034 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22035 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22036 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22037 //TCP_PERFCOUNTER3_SELECT
22038 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
22039 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
22040 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
22041 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22042 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22043 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22044 //TCC_PERFCOUNTER0_SELECT
22045 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
22046 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
22047 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
22048 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
22049 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
22050 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22051 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22052 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22053 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22054 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22055 //TCC_PERFCOUNTER0_SELECT1
22056 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22057 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22058 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
22059 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
22060 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22061 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22062 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
22063 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
22064 //TCC_PERFCOUNTER1_SELECT
22065 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
22066 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
22067 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
22068 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
22069 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
22070 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22071 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22072 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22073 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22074 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22075 //TCC_PERFCOUNTER1_SELECT1
22076 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22077 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22078 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x18
22079 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
22080 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22081 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22082 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
22083 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
22084 //TCC_PERFCOUNTER2_SELECT
22085 #define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
22086 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
22087 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
22088 #define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22089 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22090 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22091 //TCC_PERFCOUNTER3_SELECT
22092 #define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
22093 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
22094 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
22095 #define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22096 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22097 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22098 //TCA_PERFCOUNTER0_SELECT
22099 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
22100 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
22101 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
22102 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
22103 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
22104 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22105 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22106 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22107 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22108 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22109 //TCA_PERFCOUNTER0_SELECT1
22110 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22111 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22112 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
22113 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
22114 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22115 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22116 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
22117 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
22118 //TCA_PERFCOUNTER1_SELECT
22119 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
22120 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
22121 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
22122 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
22123 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
22124 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22125 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22126 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22127 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22128 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22129 //TCA_PERFCOUNTER1_SELECT1
22130 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22131 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22132 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x18
22133 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
22134 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22135 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22136 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
22137 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
22138 //TCA_PERFCOUNTER2_SELECT
22139 #define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
22140 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
22141 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
22142 #define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22143 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22144 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22145 //TCA_PERFCOUNTER3_SELECT
22146 #define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
22147 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
22148 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
22149 #define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22150 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22151 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22152 //CB_PERFCOUNTER_FILTER
22153 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT                                                        0x0
22154 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT                                                           0x1
22155 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT                                                    0x4
22156 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT                                                       0x5
22157 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT                                                     0xa
22158 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT                                                        0xb
22159 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT                                                       0xc
22160 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT                                                          0xd
22161 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT                                               0x11
22162 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT                                                  0x12
22163 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT                                             0x15
22164 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT                                                0x16
22165 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK                                                          0x00000001L
22166 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK                                                             0x0000000EL
22167 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK                                                      0x00000010L
22168 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK                                                         0x000003E0L
22169 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK                                                       0x00000400L
22170 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK                                                          0x00000800L
22171 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK                                                         0x00001000L
22172 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK                                                            0x0000E000L
22173 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK                                                 0x00020000L
22174 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK                                                    0x001C0000L
22175 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK                                               0x00200000L
22176 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK                                                  0x00C00000L
22177 //CB_PERFCOUNTER0_SELECT
22178 #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
22179 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
22180 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
22181 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
22182 #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
22183 #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
22184 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0007FC00L
22185 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22186 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22187 #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22188 //CB_PERFCOUNTER0_SELECT1
22189 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
22190 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
22191 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
22192 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
22193 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000001FFL
22194 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0007FC00L
22195 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
22196 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
22197 //CB_PERFCOUNTER1_SELECT
22198 #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
22199 #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
22200 #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
22201 #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22202 //CB_PERFCOUNTER2_SELECT
22203 #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
22204 #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
22205 #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
22206 #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22207 //CB_PERFCOUNTER3_SELECT
22208 #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
22209 #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
22210 #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
22211 #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22212 //DB_PERFCOUNTER0_SELECT
22213 #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
22214 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
22215 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
22216 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
22217 #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
22218 #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
22219 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
22220 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22221 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22222 #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22223 //DB_PERFCOUNTER0_SELECT1
22224 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
22225 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
22226 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
22227 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
22228 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
22229 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
22230 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
22231 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
22232 //DB_PERFCOUNTER1_SELECT
22233 #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
22234 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
22235 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
22236 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
22237 #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
22238 #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
22239 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
22240 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22241 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22242 #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22243 //DB_PERFCOUNTER1_SELECT1
22244 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                             0x0
22245 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                             0xa
22246 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                            0x18
22247 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
22248 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
22249 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
22250 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
22251 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
22252 //DB_PERFCOUNTER2_SELECT
22253 #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
22254 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                              0xa
22255 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
22256 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                             0x18
22257 #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
22258 #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
22259 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
22260 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22261 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22262 #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22263 //DB_PERFCOUNTER3_SELECT
22264 #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
22265 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                              0xa
22266 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
22267 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                             0x18
22268 #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
22269 #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
22270 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
22271 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22272 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22273 #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22274 //RLC_SPM_PERFMON_CNTL
22275 #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT                                                                0x0
22276 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT                                                        0xc
22277 #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT                                                                 0xe
22278 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT                                                  0x10
22279 #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK                                                                  0x00000FFFL
22280 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK                                                          0x00003000L
22281 #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK                                                                   0x0000C000L
22282 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK                                                    0xFFFF0000L
22283 //RLC_SPM_PERFMON_RING_BASE_LO
22284 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT                                                     0x0
22285 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK                                                       0xFFFFFFFFL
22286 //RLC_SPM_PERFMON_RING_BASE_HI
22287 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT                                                     0x0
22288 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT                                                         0x10
22289 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK                                                       0x0000FFFFL
22290 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK                                                           0xFFFF0000L
22291 //RLC_SPM_PERFMON_RING_SIZE
22292 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT                                                      0x0
22293 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK                                                        0xFFFFFFFFL
22294 //RLC_SPM_PERFMON_SEGMENT_SIZE
22295 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT                                             0x0
22296 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT                                                        0x8
22297 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT                                                  0xb
22298 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT                                                     0x10
22299 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT                                                     0x15
22300 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT                                                     0x1a
22301 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT                                                         0x1f
22302 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK                                               0x000000FFL
22303 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK                                                          0x00000700L
22304 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK                                                    0x0000F800L
22305 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK                                                       0x001F0000L
22306 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK                                                       0x03E00000L
22307 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK                                                       0x7C000000L
22308 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK                                                           0x80000000L
22309 //RLC_SPM_SE_MUXSEL_ADDR
22310 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                       0x0
22311 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                         0xFFFFFFFFL
22312 //RLC_SPM_SE_MUXSEL_DATA
22313 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                       0x0
22314 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                         0xFFFFFFFFL
22315 //RLC_SPM_CPG_PERFMON_SAMPLE_DELAY
22316 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22317 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22318 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22319 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22320 //RLC_SPM_CPC_PERFMON_SAMPLE_DELAY
22321 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22322 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22323 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22324 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22325 //RLC_SPM_CPF_PERFMON_SAMPLE_DELAY
22326 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22327 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22328 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22329 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22330 //RLC_SPM_CB_PERFMON_SAMPLE_DELAY
22331 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22332 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22333 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22334 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22335 //RLC_SPM_DB_PERFMON_SAMPLE_DELAY
22336 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22337 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22338 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22339 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22340 //RLC_SPM_PA_PERFMON_SAMPLE_DELAY
22341 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22342 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22343 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22344 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22345 //RLC_SPM_GDS_PERFMON_SAMPLE_DELAY
22346 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22347 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22348 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22349 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22350 //RLC_SPM_IA_PERFMON_SAMPLE_DELAY
22351 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22352 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22353 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22354 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22355 //RLC_SPM_SC_PERFMON_SAMPLE_DELAY
22356 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22357 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22358 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22359 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22360 //RLC_SPM_TCC_PERFMON_SAMPLE_DELAY
22361 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22362 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22363 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22364 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22365 //RLC_SPM_TCA_PERFMON_SAMPLE_DELAY
22366 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22367 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22368 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22369 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22370 //RLC_SPM_TCP_PERFMON_SAMPLE_DELAY
22371 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22372 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22373 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22374 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22375 //RLC_SPM_TA_PERFMON_SAMPLE_DELAY
22376 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22377 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22378 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22379 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22380 //RLC_SPM_TD_PERFMON_SAMPLE_DELAY
22381 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22382 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22383 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22384 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22385 //RLC_SPM_VGT_PERFMON_SAMPLE_DELAY
22386 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22387 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22388 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22389 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22390 //RLC_SPM_SPI_PERFMON_SAMPLE_DELAY
22391 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22392 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22393 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22394 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22395 //RLC_SPM_SQG_PERFMON_SAMPLE_DELAY
22396 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22397 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22398 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22399 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22400 //RLC_SPM_SX_PERFMON_SAMPLE_DELAY
22401 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22402 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22403 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22404 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22405 //RLC_SPM_GLOBAL_MUXSEL_ADDR
22406 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                   0x0
22407 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                     0xFFFFFFFFL
22408 //RLC_SPM_GLOBAL_MUXSEL_DATA
22409 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                   0x0
22410 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                     0xFFFFFFFFL
22411 //RLC_SPM_RING_RDPTR
22412 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT                                                         0x0
22413 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK                                                           0xFFFFFFFFL
22414 //RLC_SPM_SEGMENT_THRESHOLD
22415 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT                                               0x0
22416 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK                                                 0xFFFFFFFFL
22417 //RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY
22418 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                        0x0
22419 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                    0x8
22420 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                          0x000000FFL
22421 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                      0xFFFFFF00L
22422 //RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY
22423 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                        0x0
22424 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                    0x8
22425 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                          0x000000FFL
22426 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                      0xFFFFFF00L
22427 //RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY
22428 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                        0x0
22429 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                    0x8
22430 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                          0x000000FFL
22431 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                      0xFFFFFF00L
22432 //RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY
22433 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                        0x0
22434 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                    0x8
22435 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                          0x000000FFL
22436 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                      0xFFFFFF00L
22437 //RLC_SPM_RMI_PERFMON_SAMPLE_DELAY
22438 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22439 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22440 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22441 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22442 //RLC_PERFMON_CLK_CNTL
22443 #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT                                                      0x0
22444 #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK                                                        0x00000001L
22445 //RLC_PERFMON_CNTL
22446 #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                0x0
22447 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                        0xa
22448 #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK                                                                  0x00000007L
22449 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                          0x00000400L
22450 //RLC_PERFCOUNTER0_SELECT
22451 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
22452 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x00FFL
22453 //RLC_PERFCOUNTER1_SELECT
22454 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
22455 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x00FFL
22456 //RLC_GPU_IOV_PERF_CNT_CNTL
22457 #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT                                                              0x0
22458 #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT                                                         0x1
22459 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT                                                               0x2
22460 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT                                                            0x3
22461 #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK                                                                0x00000001L
22462 #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK                                                           0x00000002L
22463 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK                                                                 0x00000004L
22464 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK                                                              0xFFFFFFF8L
22465 //RLC_GPU_IOV_PERF_CNT_WR_ADDR
22466 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT                                                             0x0
22467 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT                                                           0x4
22468 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT                                                         0x6
22469 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK                                                               0x0000000FL
22470 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK                                                             0x00000030L
22471 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
22472 //RLC_GPU_IOV_PERF_CNT_WR_DATA
22473 #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT                                                             0x0
22474 #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK                                                               0x0000000FL
22475 //RLC_GPU_IOV_PERF_CNT_RD_ADDR
22476 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT                                                             0x0
22477 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT                                                           0x4
22478 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT                                                         0x6
22479 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK                                                               0x0000000FL
22480 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK                                                             0x00000030L
22481 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
22482 //RLC_GPU_IOV_PERF_CNT_RD_DATA
22483 #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT                                                             0x0
22484 #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK                                                               0x0000000FL
22485 //RMI_PERFCOUNTER0_SELECT
22486 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
22487 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
22488 #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
22489 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
22490 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
22491 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000001FFL
22492 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
22493 #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22494 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22495 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22496 //RMI_PERFCOUNTER0_SELECT1
22497 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22498 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22499 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
22500 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
22501 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
22502 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
22503 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
22504 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
22505 //RMI_PERFCOUNTER1_SELECT
22506 #define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
22507 #define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
22508 #define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000001FFL
22509 #define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22510 //RMI_PERFCOUNTER2_SELECT
22511 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
22512 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
22513 #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
22514 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
22515 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
22516 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000001FFL
22517 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
22518 #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22519 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22520 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22521 //RMI_PERFCOUNTER2_SELECT1
22522 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22523 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22524 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
22525 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
22526 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
22527 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
22528 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
22529 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
22530 //RMI_PERFCOUNTER3_SELECT
22531 #define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
22532 #define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
22533 #define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000001FFL
22534 #define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22535 //RMI_PERF_COUNTER_CNTL
22536 #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT                                                 0x0
22537 #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT                                                 0x2
22538 #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT                                                          0x4
22539 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT                                                 0x6
22540 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT                                                 0x8
22541 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT                                                        0xa
22542 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT                                                       0xe
22543 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT                                     0x13
22544 #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT                                                         0x19
22545 #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT                                                       0x1a
22546 #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK                                                   0x00000003L
22547 #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK                                                   0x0000000CL
22548 #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK                                                            0x00000030L
22549 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK                                                   0x000000C0L
22550 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK                                                   0x00000300L
22551 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK                                                          0x00003C00L
22552 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK                                                         0x0007C000L
22553 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK                                       0x01F80000L
22554 #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK                                                           0x02000000L
22555 #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK                                                         0x04000000L
22556 
22557 
22558 // addressBlock: gc_utcl2_atcl2pfcntldec
22559 //ATC_L2_PERFCOUNTER0_CFG
22560 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                              0x0
22561 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                          0x8
22562 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                             0x18
22563 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                0x1c
22564 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                 0x1d
22565 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                0x000000FFL
22566 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                            0x0000FF00L
22567 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                               0x0F000000L
22568 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                  0x10000000L
22569 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                   0x20000000L
22570 //ATC_L2_PERFCOUNTER1_CFG
22571 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                              0x0
22572 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                          0x8
22573 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                             0x18
22574 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                0x1c
22575 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                 0x1d
22576 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                0x000000FFL
22577 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                            0x0000FF00L
22578 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                               0x0F000000L
22579 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                  0x10000000L
22580 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                   0x20000000L
22581 //ATC_L2_PERFCOUNTER_RSLT_CNTL
22582 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                              0x0
22583 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                    0x8
22584 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                     0x10
22585 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                       0x18
22586 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                        0x19
22587 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                             0x1a
22588 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                0x0000000FL
22589 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                      0x0000FF00L
22590 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                       0x00FF0000L
22591 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                         0x01000000L
22592 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                          0x02000000L
22593 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                               0x04000000L
22594 
22595 
22596 // addressBlock: gc_utcl2_vml2pldec
22597 //MC_VM_L2_PERFCOUNTER0_CFG
22598 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                            0x0
22599 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                        0x8
22600 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                           0x18
22601 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                              0x1c
22602 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                               0x1d
22603 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                              0x000000FFL
22604 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22605 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                             0x0F000000L
22606 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                0x10000000L
22607 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                 0x20000000L
22608 //MC_VM_L2_PERFCOUNTER1_CFG
22609 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                            0x0
22610 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                        0x8
22611 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                           0x18
22612 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                              0x1c
22613 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                               0x1d
22614 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                              0x000000FFL
22615 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22616 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                             0x0F000000L
22617 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                0x10000000L
22618 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                 0x20000000L
22619 //MC_VM_L2_PERFCOUNTER2_CFG
22620 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                            0x0
22621 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                        0x8
22622 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                           0x18
22623 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                              0x1c
22624 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                               0x1d
22625 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                              0x000000FFL
22626 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22627 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                             0x0F000000L
22628 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                0x10000000L
22629 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                 0x20000000L
22630 //MC_VM_L2_PERFCOUNTER3_CFG
22631 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                            0x0
22632 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                        0x8
22633 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                           0x18
22634 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                              0x1c
22635 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                               0x1d
22636 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                              0x000000FFL
22637 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22638 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                             0x0F000000L
22639 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                                0x10000000L
22640 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                                 0x20000000L
22641 //MC_VM_L2_PERFCOUNTER4_CFG
22642 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                            0x0
22643 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                        0x8
22644 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                           0x18
22645 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                              0x1c
22646 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                               0x1d
22647 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                              0x000000FFL
22648 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22649 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                             0x0F000000L
22650 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                                0x10000000L
22651 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                                 0x20000000L
22652 //MC_VM_L2_PERFCOUNTER5_CFG
22653 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                            0x0
22654 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                        0x8
22655 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                           0x18
22656 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                              0x1c
22657 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                               0x1d
22658 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                              0x000000FFL
22659 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22660 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                             0x0F000000L
22661 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                                0x10000000L
22662 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                                 0x20000000L
22663 //MC_VM_L2_PERFCOUNTER6_CFG
22664 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                            0x0
22665 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                        0x8
22666 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                           0x18
22667 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                              0x1c
22668 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                               0x1d
22669 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                              0x000000FFL
22670 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22671 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                             0x0F000000L
22672 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                                0x10000000L
22673 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                                 0x20000000L
22674 //MC_VM_L2_PERFCOUNTER7_CFG
22675 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                            0x0
22676 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                        0x8
22677 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                           0x18
22678 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                              0x1c
22679 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                               0x1d
22680 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                              0x000000FFL
22681 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22682 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                             0x0F000000L
22683 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                                0x10000000L
22684 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                                 0x20000000L
22685 //MC_VM_L2_PERFCOUNTER_RSLT_CNTL
22686 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                            0x0
22687 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                  0x8
22688 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                   0x10
22689 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                     0x18
22690 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                      0x19
22691 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                           0x1a
22692 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                              0x0000000FL
22693 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                    0x0000FF00L
22694 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                     0x00FF0000L
22695 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                       0x01000000L
22696 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                        0x02000000L
22697 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                             0x04000000L
22698 
22699 
22700 // addressBlock: gc_rlcpdec
22701 //RLC_CNTL
22702 #define RLC_CNTL__RLC_ENABLE_F32__SHIFT                                                                       0x0
22703 #define RLC_CNTL__FORCE_RETRY__SHIFT                                                                          0x1
22704 #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT                                                                   0x2
22705 #define RLC_CNTL__RLC_STEP_F32__SHIFT                                                                         0x3
22706 #define RLC_CNTL__RESERVED__SHIFT                                                                             0x4
22707 #define RLC_CNTL__RLC_ENABLE_F32_MASK                                                                         0x00000001L
22708 #define RLC_CNTL__FORCE_RETRY_MASK                                                                            0x00000002L
22709 #define RLC_CNTL__READ_CACHE_DISABLE_MASK                                                                     0x00000004L
22710 #define RLC_CNTL__RLC_STEP_F32_MASK                                                                           0x00000008L
22711 #define RLC_CNTL__RESERVED_MASK                                                                               0xFFFFFFF0L
22712 //RLC_STAT
22713 #define RLC_STAT__RLC_BUSY__SHIFT                                                                             0x0
22714 #define RLC_STAT__RLC_GPM_BUSY__SHIFT                                                                         0x1
22715 #define RLC_STAT__RLC_SPM_BUSY__SHIFT                                                                         0x2
22716 #define RLC_STAT__RLC_SRM_BUSY__SHIFT                                                                         0x3
22717 #define RLC_STAT__MC_BUSY__SHIFT                                                                              0x4
22718 #define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT                                                                    0x5
22719 #define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT                                                                    0x6
22720 #define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT                                                                    0x7
22721 #define RLC_STAT__RESERVED__SHIFT                                                                             0x8
22722 #define RLC_STAT__RLC_BUSY_MASK                                                                               0x00000001L
22723 #define RLC_STAT__RLC_GPM_BUSY_MASK                                                                           0x00000002L
22724 #define RLC_STAT__RLC_SPM_BUSY_MASK                                                                           0x00000004L
22725 #define RLC_STAT__RLC_SRM_BUSY_MASK                                                                           0x00000008L
22726 #define RLC_STAT__MC_BUSY_MASK                                                                                0x00000010L
22727 #define RLC_STAT__RLC_THREAD_0_BUSY_MASK                                                                      0x00000020L
22728 #define RLC_STAT__RLC_THREAD_1_BUSY_MASK                                                                      0x00000040L
22729 #define RLC_STAT__RLC_THREAD_2_BUSY_MASK                                                                      0x00000080L
22730 #define RLC_STAT__RESERVED_MASK                                                                               0xFFFFFF00L
22731 //RLC_SAFE_MODE
22732 #define RLC_SAFE_MODE__CMD__SHIFT                                                                             0x0
22733 #define RLC_SAFE_MODE__MESSAGE__SHIFT                                                                         0x1
22734 #define RLC_SAFE_MODE__RESERVED1__SHIFT                                                                       0x5
22735 #define RLC_SAFE_MODE__RESPONSE__SHIFT                                                                        0x8
22736 #define RLC_SAFE_MODE__RESERVED__SHIFT                                                                        0xc
22737 #define RLC_SAFE_MODE__CMD_MASK                                                                               0x00000001L
22738 #define RLC_SAFE_MODE__MESSAGE_MASK                                                                           0x0000001EL
22739 #define RLC_SAFE_MODE__RESERVED1_MASK                                                                         0x000000E0L
22740 #define RLC_SAFE_MODE__RESPONSE_MASK                                                                          0x00000F00L
22741 #define RLC_SAFE_MODE__RESERVED_MASK                                                                          0xFFFFF000L
22742 //RLC_MEM_SLP_CNTL
22743 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT                                                                0x0
22744 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT                                                                0x1
22745 #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT                                                                     0x2
22746 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT                                                      0x7
22747 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT                                                          0x8
22748 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT                                                         0x10
22749 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                    0x18
22750 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK                                                                  0x00000001L
22751 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK                                                                  0x00000002L
22752 #define RLC_MEM_SLP_CNTL__RESERVED_MASK                                                                       0x0000007CL
22753 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK                                                        0x00000080L
22754 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK                                                            0x0000FF00L
22755 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK                                                           0x00FF0000L
22756 #define RLC_MEM_SLP_CNTL__RESERVED1_MASK                                                                      0xFF000000L
22757 //SMU_RLC_RESPONSE
22758 #define SMU_RLC_RESPONSE__RESP__SHIFT                                                                         0x0
22759 #define SMU_RLC_RESPONSE__RESP_MASK                                                                           0xFFFFFFFFL
22760 //RLC_RLCV_SAFE_MODE
22761 #define RLC_RLCV_SAFE_MODE__CMD__SHIFT                                                                        0x0
22762 #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT                                                                    0x1
22763 #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT                                                                  0x5
22764 #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT                                                                   0x8
22765 #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT                                                                   0xc
22766 #define RLC_RLCV_SAFE_MODE__CMD_MASK                                                                          0x00000001L
22767 #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK                                                                      0x0000001EL
22768 #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK                                                                    0x000000E0L
22769 #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK                                                                     0x00000F00L
22770 #define RLC_RLCV_SAFE_MODE__RESERVED_MASK                                                                     0xFFFFF000L
22771 //RLC_SMU_SAFE_MODE
22772 #define RLC_SMU_SAFE_MODE__CMD__SHIFT                                                                         0x0
22773 #define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT                                                                     0x1
22774 #define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT                                                                   0x5
22775 #define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT                                                                    0x8
22776 #define RLC_SMU_SAFE_MODE__RESERVED__SHIFT                                                                    0xc
22777 #define RLC_SMU_SAFE_MODE__CMD_MASK                                                                           0x00000001L
22778 #define RLC_SMU_SAFE_MODE__MESSAGE_MASK                                                                       0x0000001EL
22779 #define RLC_SMU_SAFE_MODE__RESERVED1_MASK                                                                     0x000000E0L
22780 #define RLC_SMU_SAFE_MODE__RESPONSE_MASK                                                                      0x00000F00L
22781 #define RLC_SMU_SAFE_MODE__RESERVED_MASK                                                                      0xFFFFF000L
22782 //RLC_RLCV_COMMAND
22783 #define RLC_RLCV_COMMAND__CMD__SHIFT                                                                          0x0
22784 #define RLC_RLCV_COMMAND__RESERVED__SHIFT                                                                     0x4
22785 #define RLC_RLCV_COMMAND__CMD_MASK                                                                            0x0000000FL
22786 #define RLC_RLCV_COMMAND__RESERVED_MASK                                                                       0xFFFFFFF0L
22787 //RLC_REFCLOCK_TIMESTAMP_LSB
22788 #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT                                                      0x0
22789 #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK                                                        0xFFFFFFFFL
22790 //RLC_REFCLOCK_TIMESTAMP_MSB
22791 #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT                                                      0x0
22792 #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK                                                        0xFFFFFFFFL
22793 //RLC_GPM_TIMER_INT_0
22794 #define RLC_GPM_TIMER_INT_0__TIMER__SHIFT                                                                     0x0
22795 #define RLC_GPM_TIMER_INT_0__TIMER_MASK                                                                       0xFFFFFFFFL
22796 //RLC_GPM_TIMER_INT_1
22797 #define RLC_GPM_TIMER_INT_1__TIMER__SHIFT                                                                     0x0
22798 #define RLC_GPM_TIMER_INT_1__TIMER_MASK                                                                       0xFFFFFFFFL
22799 //RLC_GPM_TIMER_INT_2
22800 #define RLC_GPM_TIMER_INT_2__TIMER__SHIFT                                                                     0x0
22801 #define RLC_GPM_TIMER_INT_2__TIMER_MASK                                                                       0xFFFFFFFFL
22802 //RLC_GPM_TIMER_CTRL
22803 #define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                 0x0
22804 #define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                 0x1
22805 #define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT                                                                 0x2
22806 #define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT                                                                 0x3
22807 #define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT                                                                   0x4
22808 #define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK                                                                   0x00000001L
22809 #define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK                                                                   0x00000002L
22810 #define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK                                                                   0x00000004L
22811 #define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK                                                                   0x00000008L
22812 #define RLC_GPM_TIMER_CTRL__RESERVED_MASK                                                                     0xFFFFFFF0L
22813 //RLC_LB_CNTR_MAX
22814 #define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT                                                                   0x0
22815 #define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK                                                                     0xFFFFFFFFL
22816 //RLC_GPM_TIMER_STAT
22817 #define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT                                                               0x0
22818 #define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT                                                               0x1
22819 #define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT                                                               0x2
22820 #define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT                                                               0x3
22821 #define RLC_GPM_TIMER_STAT__RESERVED__SHIFT                                                                   0x4
22822 #define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK                                                                 0x00000001L
22823 #define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK                                                                 0x00000002L
22824 #define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK                                                                 0x00000004L
22825 #define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK                                                                 0x00000008L
22826 #define RLC_GPM_TIMER_STAT__RESERVED_MASK                                                                     0xFFFFFFF0L
22827 //RLC_GPM_TIMER_INT_3
22828 #define RLC_GPM_TIMER_INT_3__TIMER__SHIFT                                                                     0x0
22829 #define RLC_GPM_TIMER_INT_3__TIMER_MASK                                                                       0xFFFFFFFFL
22830 //RLC_SERDES_WR_NONCU_MASTER_MASK_1
22831 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT                                            0x0
22832 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT                                            0x10
22833 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT                                        0x11
22834 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT                                           0x12
22835 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT                                                  0x13
22836 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT                                          0x14
22837 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT                                          0x15
22838 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT                                          0x16
22839 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT                                          0x17
22840 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT                                            0x18
22841 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT                                                    0x19
22842 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK                                              0x0000FFFFL
22843 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK                                              0x00010000L
22844 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK                                          0x00020000L
22845 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK                                             0x00040000L
22846 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK                                                    0x00080000L
22847 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK                                            0x00100000L
22848 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK                                            0x00200000L
22849 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK                                            0x00400000L
22850 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK                                            0x00800000L
22851 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK                                              0x01000000L
22852 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK                                                      0xFE000000L
22853 //RLC_SERDES_NONCU_MASTER_BUSY_1
22854 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT                                               0x0
22855 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT                                               0x10
22856 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT                                           0x11
22857 #define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT                                              0x12
22858 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT                                                     0x13
22859 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT                                             0x14
22860 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT                                             0x15
22861 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT                                             0x16
22862 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT                                             0x17
22863 #define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT                                               0x18
22864 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT                                                       0x19
22865 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK                                                 0x0000FFFFL
22866 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK                                                 0x00010000L
22867 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK                                             0x00020000L
22868 #define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK                                                0x00040000L
22869 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK                                                       0x00080000L
22870 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK                                               0x00100000L
22871 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK                                               0x00200000L
22872 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK                                               0x00400000L
22873 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK                                               0x00800000L
22874 #define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK                                                 0x01000000L
22875 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK                                                         0xFE000000L
22876 //RLC_INT_STAT
22877 #define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT                                                               0x0
22878 #define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT                                                               0x8
22879 #define RLC_INT_STAT__RESERVED__SHIFT                                                                         0x9
22880 #define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK                                                                 0x000000FFL
22881 #define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK                                                                 0x00000100L
22882 #define RLC_INT_STAT__RESERVED_MASK                                                                           0xFFFFFE00L
22883 //RLC_LB_CNTL
22884 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT                                                               0x0
22885 #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT                                                                    0x1
22886 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT                                                                0x2
22887 #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT                                                                    0x3
22888 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT                                                             0x4
22889 #define RLC_LB_CNTL__RESERVED__SHIFT                                                                          0xc
22890 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK                                                                 0x00000001L
22891 #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK                                                                      0x00000002L
22892 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK                                                                  0x00000004L
22893 #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK                                                                      0x00000008L
22894 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK                                                               0x00000FF0L
22895 #define RLC_LB_CNTL__RESERVED_MASK                                                                            0xFFFFF000L
22896 //RLC_MGCG_CTRL
22897 #define RLC_MGCG_CTRL__MGCG_EN__SHIFT                                                                         0x0
22898 #define RLC_MGCG_CTRL__SILICON_EN__SHIFT                                                                      0x1
22899 #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT                                                                   0x2
22900 #define RLC_MGCG_CTRL__ON_DELAY__SHIFT                                                                        0x3
22901 #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT                                                                  0x7
22902 #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT                                                            0xf
22903 #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT                                                            0x10
22904 #define RLC_MGCG_CTRL__SPARE__SHIFT                                                                           0x11
22905 #define RLC_MGCG_CTRL__MGCG_EN_MASK                                                                           0x00000001L
22906 #define RLC_MGCG_CTRL__SILICON_EN_MASK                                                                        0x00000002L
22907 #define RLC_MGCG_CTRL__SIMULATION_EN_MASK                                                                     0x00000004L
22908 #define RLC_MGCG_CTRL__ON_DELAY_MASK                                                                          0x00000078L
22909 #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK                                                                    0x00007F80L
22910 #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK                                                              0x00008000L
22911 #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK                                                              0x00010000L
22912 #define RLC_MGCG_CTRL__SPARE_MASK                                                                             0xFFFE0000L
22913 //RLC_LB_CNTR_INIT
22914 #define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT                                                                 0x0
22915 #define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK                                                                   0xFFFFFFFFL
22916 //RLC_LOAD_BALANCE_CNTR
22917 #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT                                                   0x0
22918 #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK                                                     0xFFFFFFFFL
22919 //RLC_JUMP_TABLE_RESTORE
22920 #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT                                                                   0x0
22921 #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK                                                                     0xFFFFFFFFL
22922 //RLC_PG_DELAY_2
22923 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT                                                           0x0
22924 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT                                                               0x8
22925 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT                                                            0x10
22926 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK                                                             0x000000FFL
22927 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK                                                                 0x0000FF00L
22928 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK                                                              0xFFFF0000L
22929 //RLC_GPU_CLOCK_COUNT_LSB
22930 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT                                                        0x0
22931 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK                                                          0xFFFFFFFFL
22932 //RLC_GPU_CLOCK_COUNT_MSB
22933 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT                                                        0x0
22934 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK                                                          0xFFFFFFFFL
22935 //RLC_CAPTURE_GPU_CLOCK_COUNT
22936 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT                                                           0x0
22937 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT                                                          0x1
22938 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK                                                             0x00000001L
22939 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK                                                            0xFFFFFFFEL
22940 //RLC_UCODE_CNTL
22941 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT                                                                0x0
22942 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK                                                                  0xFFFFFFFFL
22943 //RLC_GPM_THREAD_RESET
22944 #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT                                                            0x0
22945 #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT                                                            0x1
22946 #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT                                                            0x2
22947 #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT                                                            0x3
22948 #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT                                                                 0x4
22949 #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK                                                              0x00000001L
22950 #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK                                                              0x00000002L
22951 #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK                                                              0x00000004L
22952 #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK                                                              0x00000008L
22953 #define RLC_GPM_THREAD_RESET__RESERVED_MASK                                                                   0xFFFFFFF0L
22954 //RLC_GPM_CP_DMA_COMPLETE_T0
22955 #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT                                                               0x0
22956 #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT                                                           0x1
22957 #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK                                                                 0x00000001L
22958 #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK                                                             0xFFFFFFFEL
22959 //RLC_GPM_CP_DMA_COMPLETE_T1
22960 #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT                                                               0x0
22961 #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT                                                           0x1
22962 #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK                                                                 0x00000001L
22963 #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK                                                             0xFFFFFFFEL
22964 //RLC_FIREWALL_VIOLATION
22965 #define RLC_FIREWALL_VIOLATION__ADDR__SHIFT                                                                   0x0
22966 #define RLC_FIREWALL_VIOLATION__ADDR_MASK                                                                     0xFFFFFFFFL
22967 //RLC_GPM_STAT
22968 #define RLC_GPM_STAT__RLC_BUSY__SHIFT                                                                         0x0
22969 #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT                                                                 0x1
22970 #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT                                                                 0x2
22971 #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT                                                                    0x3
22972 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT                                                        0x4
22973 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT                                                        0x5
22974 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT                                                        0x6
22975 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT                                                         0x7
22976 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT                                                         0x8
22977 #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT                                                                 0x9
22978 #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT                                                              0xa
22979 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                0xb
22980 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                  0xc
22981 #define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT                                                            0xd
22982 #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT                                                          0xe
22983 #define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT                                                               0xf
22984 #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT                                                             0x10
22985 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT                                                              0x11
22986 #define RLC_GPM_STAT__CMP_power_status__SHIFT                                                                 0x12
22987 #define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT                                                                 0x13
22988 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT                                                              0x14
22989 #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT                                                             0x15
22990 #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT                                                                0x16
22991 #define RLC_GPM_STAT__RESERVED__SHIFT                                                                         0x17
22992 #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT                                                                  0x18
22993 #define RLC_GPM_STAT__RLC_BUSY_MASK                                                                           0x00000001L
22994 #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK                                                                   0x00000002L
22995 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK                                                                   0x00000004L
22996 #define RLC_GPM_STAT__GFX_LS_STATUS_MASK                                                                      0x00000008L
22997 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK                                                          0x00000010L
22998 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK                                                          0x00000020L
22999 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK                                                          0x00000040L
23000 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK                                                           0x00000080L
23001 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK                                                           0x00000100L
23002 #define RLC_GPM_STAT__SAVING_REGISTERS_MASK                                                                   0x00000200L
23003 #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK                                                                0x00000400L
23004 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK                                                  0x00000800L
23005 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK                                                    0x00001000L
23006 #define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK                                                              0x00002000L
23007 #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK                                                            0x00004000L
23008 #define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK                                                                 0x00008000L
23009 #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK                                                               0x00010000L
23010 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK                                                                0x00020000L
23011 #define RLC_GPM_STAT__CMP_power_status_MASK                                                                   0x00040000L
23012 #define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK                                                                   0x00080000L
23013 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK                                                                0x00100000L
23014 #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK                                                               0x00200000L
23015 #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK                                                                  0x00400000L
23016 #define RLC_GPM_STAT__RESERVED_MASK                                                                           0x00800000L
23017 #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK                                                                    0xFF000000L
23018 //RLC_GPU_CLOCK_32_RES_SEL
23019 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT                                                              0x0
23020 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT                                                             0x6
23021 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK                                                                0x0000003FL
23022 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK                                                               0xFFFFFFC0L
23023 //RLC_GPU_CLOCK_32
23024 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT                                                                 0x0
23025 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK                                                                   0xFFFFFFFFL
23026 //RLC_PG_CNTL
23027 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT                                                           0x0
23028 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT                                                              0x1
23029 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT                                                              0x2
23030 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT                                                           0x3
23031 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT                                                            0x4
23032 #define RLC_PG_CNTL__RESERVED__SHIFT                                                                          0x5
23033 #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT                                                                       0xe
23034 #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT                                                                     0xf
23035 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT                                                             0x10
23036 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT                                                     0x11
23037 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT                                                     0x12
23038 #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT                                                              0x13
23039 #define RLC_PG_CNTL__RESERVED1__SHIFT                                                                         0x14
23040 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK                                                             0x00000001L
23041 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK                                                                0x00000002L
23042 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK                                                                0x00000004L
23043 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK                                                             0x00000008L
23044 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK                                                              0x00000010L
23045 #define RLC_PG_CNTL__RESERVED_MASK                                                                            0x00003FE0L
23046 #define RLC_PG_CNTL__PG_OVERRIDE_MASK                                                                         0x00004000L
23047 #define RLC_PG_CNTL__CP_PG_DISABLE_MASK                                                                       0x00008000L
23048 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK                                                               0x00010000L
23049 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK                                                       0x00020000L
23050 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK                                                       0x00040000L
23051 #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK                                                                0x00080000L
23052 #define RLC_PG_CNTL__RESERVED1_MASK                                                                           0x00F00000L
23053 //RLC_GPM_THREAD_PRIORITY
23054 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT                                                      0x0
23055 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT                                                      0x8
23056 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT                                                      0x10
23057 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT                                                      0x18
23058 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK                                                        0x000000FFL
23059 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK                                                        0x0000FF00L
23060 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK                                                        0x00FF0000L
23061 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK                                                        0xFF000000L
23062 //RLC_GPM_THREAD_ENABLE
23063 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT                                                          0x0
23064 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT                                                          0x1
23065 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT                                                          0x2
23066 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT                                                          0x3
23067 #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT                                                                0x4
23068 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK                                                            0x00000001L
23069 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK                                                            0x00000002L
23070 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK                                                            0x00000004L
23071 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK                                                            0x00000008L
23072 #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK                                                                  0xFFFFFFF0L
23073 //RLC_CGTT_MGCG_OVERRIDE
23074 #define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT                                                 0x0
23075 #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT                                                 0x1
23076 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT                                                    0x2
23077 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT                                                    0x3
23078 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT                                                    0x4
23079 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT                                                0x5
23080 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT                                                    0x6
23081 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT                                                0x7
23082 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT                                                               0x8
23083 #define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK                                                   0x00000001L
23084 #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK                                                   0x00000002L
23085 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK                                                      0x00000004L
23086 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK                                                      0x00000008L
23087 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK                                                      0x00000010L
23088 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK                                                  0x00000020L
23089 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK                                                      0x00000040L
23090 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK                                                  0x00000080L
23091 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK                                                                 0xFFFFFF00L
23092 //RLC_CGCG_CGLS_CTRL
23093 #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT                                                                    0x0
23094 #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT                                                                    0x1
23095 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT                                                   0x2
23096 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT                                                    0x8
23097 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT                                                            0x1b
23098 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT                                                              0x1c
23099 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT                                                                 0x1d
23100 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT                                                             0x1f
23101 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK                                                                      0x00000001L
23102 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK                                                                      0x00000002L
23103 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK                                                     0x000000FCL
23104 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK                                                      0x07FFFF00L
23105 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK                                                              0x08000000L
23106 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK                                                                0x10000000L
23107 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK                                                                   0x60000000L
23108 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK                                                               0x80000000L
23109 //RLC_CGCG_RAMP_CTRL
23110 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT                                                        0x0
23111 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT                                                         0x4
23112 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT                                                          0x8
23113 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT                                                           0xc
23114 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT                                                             0x10
23115 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT                                                            0x1c
23116 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK                                                          0x0000000FL
23117 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK                                                           0x000000F0L
23118 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK                                                            0x00000F00L
23119 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK                                                             0x0000F000L
23120 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK                                                               0x0FFF0000L
23121 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK                                                              0xF0000000L
23122 //RLC_DYN_PG_STATUS
23123 #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT                                                           0x0
23124 #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK                                                             0xFFFFFFFFL
23125 //RLC_DYN_PG_REQUEST
23126 #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT                                                         0x0
23127 #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK                                                           0xFFFFFFFFL
23128 //RLC_PG_DELAY
23129 #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT                                                                   0x0
23130 #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT                                                                 0x8
23131 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT                                                              0x10
23132 #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT                                                                  0x18
23133 #define RLC_PG_DELAY__POWER_UP_DELAY_MASK                                                                     0x000000FFL
23134 #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK                                                                   0x0000FF00L
23135 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK                                                                0x00FF0000L
23136 #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK                                                                    0xFF000000L
23137 //RLC_CU_STATUS
23138 #define RLC_CU_STATUS__WORK_PENDING__SHIFT                                                                    0x0
23139 #define RLC_CU_STATUS__WORK_PENDING_MASK                                                                      0xFFFFFFFFL
23140 //RLC_LB_INIT_CU_MASK
23141 #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT                                                              0x0
23142 #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK                                                                0xFFFFFFFFL
23143 //RLC_LB_ALWAYS_ACTIVE_CU_MASK
23144 #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT                                            0x0
23145 #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK                                              0xFFFFFFFFL
23146 //RLC_LB_PARAMS
23147 #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT                                                                   0x0
23148 #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT                                                                    0x1
23149 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT                                                                 0x8
23150 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT                                                         0x10
23151 #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK                                                                     0x00000001L
23152 #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK                                                                      0x000000FEL
23153 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK                                                                   0x0000FF00L
23154 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK                                                           0xFFFF0000L
23155 //RLC_THREAD1_DELAY
23156 #define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT                                                               0x0
23157 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT                                                       0x8
23158 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT                                                       0x10
23159 #define RLC_THREAD1_DELAY__SPARE__SHIFT                                                                       0x18
23160 #define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK                                                                 0x000000FFL
23161 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK                                                         0x0000FF00L
23162 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK                                                         0x00FF0000L
23163 #define RLC_THREAD1_DELAY__SPARE_MASK                                                                         0xFF000000L
23164 //RLC_PG_ALWAYS_ON_CU_MASK
23165 #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT                                                          0x0
23166 #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK                                                            0xFFFFFFFFL
23167 //RLC_MAX_PG_CU
23168 #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT                                                               0x0
23169 #define RLC_MAX_PG_CU__SPARE__SHIFT                                                                           0x8
23170 #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK                                                                 0x000000FFL
23171 #define RLC_MAX_PG_CU__SPARE_MASK                                                                             0xFFFFFF00L
23172 //RLC_AUTO_PG_CTRL
23173 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT                                                                   0x0
23174 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT                                                0x1
23175 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT                                                              0x2
23176 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT                                             0x3
23177 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT                                             0x13
23178 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK                                                                     0x00000001L
23179 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK                                                  0x00000002L
23180 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK                                                                0x00000004L
23181 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK                                               0x0007FFF8L
23182 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK                                               0xFFF80000L
23183 //RLC_SMU_GRBM_REG_SAVE_CTRL
23184 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT                                                0x0
23185 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT                                                              0x1
23186 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK                                                  0x00000001L
23187 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK                                                                0xFFFFFFFEL
23188 //RLC_SERDES_RD_MASTER_INDEX
23189 #define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT                                                              0x0
23190 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT                                                              0x4
23191 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT                                                              0x6
23192 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT                                                        0x9
23193 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT                                                           0xc
23194 #define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT                                                             0xd
23195 #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT                                                        0x11
23196 #define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT                                                              0x13
23197 #define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK                                                                0x0000000FL
23198 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK                                                                0x00000030L
23199 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK                                                                0x000001C0L
23200 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK                                                          0x00000E00L
23201 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK                                                             0x00001000L
23202 #define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK                                                               0x0001E000L
23203 #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK                                                          0x00060000L
23204 #define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK                                                                0xFFF80000L
23205 //RLC_SERDES_RD_DATA_0
23206 #define RLC_SERDES_RD_DATA_0__DATA__SHIFT                                                                     0x0
23207 #define RLC_SERDES_RD_DATA_0__DATA_MASK                                                                       0xFFFFFFFFL
23208 //RLC_SERDES_RD_DATA_1
23209 #define RLC_SERDES_RD_DATA_1__DATA__SHIFT                                                                     0x0
23210 #define RLC_SERDES_RD_DATA_1__DATA_MASK                                                                       0xFFFFFFFFL
23211 //RLC_SERDES_RD_DATA_2
23212 #define RLC_SERDES_RD_DATA_2__DATA__SHIFT                                                                     0x0
23213 #define RLC_SERDES_RD_DATA_2__DATA_MASK                                                                       0xFFFFFFFFL
23214 //RLC_SERDES_WR_CU_MASTER_MASK
23215 #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT                                                      0x0
23216 #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK                                                        0xFFFFFFFFL
23217 //RLC_SERDES_WR_NONCU_MASTER_MASK
23218 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT                                                0x0
23219 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT                                                0x10
23220 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT                                            0x11
23221 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT                                               0x12
23222 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT                                               0x13
23223 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT                                            0x14
23224 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT                                            0x15
23225 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT                                            0x16
23226 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT                                            0x17
23227 #define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT                                              0x18
23228 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT                                               0x19
23229 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT                                                      0x1a
23230 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK                                                  0x0000FFFFL
23231 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK                                                  0x00010000L
23232 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK                                              0x00020000L
23233 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK                                                 0x00040000L
23234 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK                                                 0x00080000L
23235 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK                                              0x00100000L
23236 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK                                              0x00200000L
23237 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK                                              0x00400000L
23238 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK                                              0x00800000L
23239 #define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK                                                0x01000000L
23240 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK                                                 0x02000000L
23241 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK                                                        0xFC000000L
23242 //RLC_SERDES_WR_CTRL
23243 #define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT                                                                   0x0
23244 #define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT                                                                 0x8
23245 #define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT                                                                   0x9
23246 #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT                                                                  0xa
23247 #define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT                                                                  0xb
23248 #define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT                                                              0xc
23249 #define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT                                                               0xd
23250 #define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT                                                               0xe
23251 #define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT                                                               0xf
23252 #define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT                                                                   0x10
23253 #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT                                                              0x1a
23254 #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT                                                              0x1b
23255 #define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT                                                                   0x1c
23256 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK                                                                     0x000000FFL
23257 #define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK                                                                   0x00000100L
23258 #define RLC_SERDES_WR_CTRL__POWER_UP_MASK                                                                     0x00000200L
23259 #define RLC_SERDES_WR_CTRL__P1_SELECT_MASK                                                                    0x00000400L
23260 #define RLC_SERDES_WR_CTRL__P2_SELECT_MASK                                                                    0x00000800L
23261 #define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK                                                                0x00001000L
23262 #define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK                                                                 0x00002000L
23263 #define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK                                                                 0x00004000L
23264 #define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK                                                                 0x00008000L
23265 #define RLC_SERDES_WR_CTRL__BPM_DATA_MASK                                                                     0x03FF0000L
23266 #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK                                                                0x04000000L
23267 #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK                                                                0x08000000L
23268 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK                                                                     0xF0000000L
23269 //RLC_SERDES_WR_DATA
23270 #define RLC_SERDES_WR_DATA__DATA__SHIFT                                                                       0x0
23271 #define RLC_SERDES_WR_DATA__DATA_MASK                                                                         0xFFFFFFFFL
23272 //RLC_SERDES_CU_MASTER_BUSY
23273 #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT                                                           0x0
23274 #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK                                                             0xFFFFFFFFL
23275 //RLC_SERDES_NONCU_MASTER_BUSY
23276 #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT                                                   0x0
23277 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT                                                   0x10
23278 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT                                               0x11
23279 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT                                                  0x12
23280 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT                                                  0x13
23281 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT                                               0x14
23282 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT                                               0x15
23283 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT                                               0x16
23284 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT                                               0x17
23285 #define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT                                                 0x18
23286 #define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT                                                  0x19
23287 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT                                                         0x1a
23288 #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK                                                     0x0000FFFFL
23289 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK                                                     0x00010000L
23290 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK                                                 0x00020000L
23291 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK                                                    0x00040000L
23292 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK                                                    0x00080000L
23293 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK                                                 0x00100000L
23294 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK                                                 0x00200000L
23295 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK                                                 0x00400000L
23296 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK                                                 0x00800000L
23297 #define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK                                                   0x01000000L
23298 #define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK                                                    0x02000000L
23299 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK                                                           0xFC000000L
23300 //RLC_GPM_GENERAL_0
23301 #define RLC_GPM_GENERAL_0__DATA__SHIFT                                                                        0x0
23302 #define RLC_GPM_GENERAL_0__DATA_MASK                                                                          0xFFFFFFFFL
23303 //RLC_GPM_GENERAL_1
23304 #define RLC_GPM_GENERAL_1__DATA__SHIFT                                                                        0x0
23305 #define RLC_GPM_GENERAL_1__DATA_MASK                                                                          0xFFFFFFFFL
23306 //RLC_GPM_GENERAL_2
23307 #define RLC_GPM_GENERAL_2__DATA__SHIFT                                                                        0x0
23308 #define RLC_GPM_GENERAL_2__DATA_MASK                                                                          0xFFFFFFFFL
23309 //RLC_GPM_GENERAL_3
23310 #define RLC_GPM_GENERAL_3__DATA__SHIFT                                                                        0x0
23311 #define RLC_GPM_GENERAL_3__DATA_MASK                                                                          0xFFFFFFFFL
23312 //RLC_GPM_GENERAL_4
23313 #define RLC_GPM_GENERAL_4__DATA__SHIFT                                                                        0x0
23314 #define RLC_GPM_GENERAL_4__DATA_MASK                                                                          0xFFFFFFFFL
23315 //RLC_GPM_GENERAL_5
23316 #define RLC_GPM_GENERAL_5__DATA__SHIFT                                                                        0x0
23317 #define RLC_GPM_GENERAL_5__DATA_MASK                                                                          0xFFFFFFFFL
23318 //RLC_GPM_GENERAL_6
23319 #define RLC_GPM_GENERAL_6__DATA__SHIFT                                                                        0x0
23320 #define RLC_GPM_GENERAL_6__DATA_MASK                                                                          0xFFFFFFFFL
23321 //RLC_GPM_GENERAL_7
23322 #define RLC_GPM_GENERAL_7__DATA__SHIFT                                                                        0x0
23323 #define RLC_GPM_GENERAL_7__DATA_MASK                                                                          0xFFFFFFFFL
23324 //RLC_GPM_SCRATCH_ADDR
23325 #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT                                                                     0x0
23326 #define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT                                                                 0x9
23327 #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK                                                                       0x000001FFL
23328 #define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK                                                                   0xFFFFFE00L
23329 //RLC_GPM_SCRATCH_DATA
23330 #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT                                                                     0x0
23331 #define RLC_GPM_SCRATCH_DATA__DATA_MASK                                                                       0xFFFFFFFFL
23332 //RLC_STATIC_PG_STATUS
23333 #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT                                                        0x0
23334 #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK                                                          0xFFFFFFFFL
23335 //RLC_SPM_MC_CNTL
23336 #define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT                                                                  0x0
23337 #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT                                                                0x4
23338 #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT                                                             0x5
23339 #define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT                                                                   0x6
23340 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT                                                            0x7
23341 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT                                                                 0x8
23342 #define RLC_SPM_MC_CNTL__RESERVED__SHIFT                                                                      0xa
23343 #define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK                                                                    0x0000000FL
23344 #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK                                                                  0x00000010L
23345 #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK                                                               0x00000020L
23346 #define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK                                                                     0x00000040L
23347 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK                                                              0x00000080L
23348 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK                                                                   0x00000300L
23349 #define RLC_SPM_MC_CNTL__RESERVED_MASK                                                                        0xFFFFFC00L
23350 //RLC_SPM_INT_CNTL
23351 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT                                                             0x0
23352 #define RLC_SPM_INT_CNTL__RESERVED__SHIFT                                                                     0x1
23353 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK                                                               0x00000001L
23354 #define RLC_SPM_INT_CNTL__RESERVED_MASK                                                                       0xFFFFFFFEL
23355 //RLC_SPM_INT_STATUS
23356 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT                                                         0x0
23357 #define RLC_SPM_INT_STATUS__RESERVED__SHIFT                                                                   0x1
23358 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK                                                           0x00000001L
23359 #define RLC_SPM_INT_STATUS__RESERVED_MASK                                                                     0xFFFFFFFEL
23360 //RLC_SMU_MESSAGE
23361 #define RLC_SMU_MESSAGE__CMD__SHIFT                                                                           0x0
23362 #define RLC_SMU_MESSAGE__CMD_MASK                                                                             0xFFFFFFFFL
23363 //RLC_GPM_LOG_SIZE
23364 #define RLC_GPM_LOG_SIZE__SIZE__SHIFT                                                                         0x0
23365 #define RLC_GPM_LOG_SIZE__SIZE_MASK                                                                           0xFFFFFFFFL
23366 //RLC_PG_DELAY_3
23367 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT                                                        0x0
23368 #define RLC_PG_DELAY_3__RESERVED__SHIFT                                                                       0x8
23369 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK                                                          0x000000FFL
23370 #define RLC_PG_DELAY_3__RESERVED_MASK                                                                         0xFFFFFF00L
23371 //RLC_GPR_REG1
23372 #define RLC_GPR_REG1__DATA__SHIFT                                                                             0x0
23373 #define RLC_GPR_REG1__DATA_MASK                                                                               0xFFFFFFFFL
23374 //RLC_GPR_REG2
23375 #define RLC_GPR_REG2__DATA__SHIFT                                                                             0x0
23376 #define RLC_GPR_REG2__DATA_MASK                                                                               0xFFFFFFFFL
23377 //RLC_GPM_LOG_CONT
23378 #define RLC_GPM_LOG_CONT__CONT__SHIFT                                                                         0x0
23379 #define RLC_GPM_LOG_CONT__CONT_MASK                                                                           0xFFFFFFFFL
23380 //RLC_GPM_INT_DISABLE_TH0
23381 #define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT                                                               0x0
23382 #define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK                                                                 0xFFFFFFFFL
23383 //RLC_GPM_INT_DISABLE_TH1
23384 #define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT                                                               0x0
23385 #define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK                                                                 0xFFFFFFFFL
23386 //RLC_GPM_INT_FORCE_TH0
23387 #define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT                                                                   0x0
23388 #define RLC_GPM_INT_FORCE_TH0__FORCE_MASK                                                                     0xFFFFFFFFL
23389 //RLC_GPM_INT_FORCE_TH1
23390 #define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT                                                                   0x0
23391 #define RLC_GPM_INT_FORCE_TH1__FORCE_MASK                                                                     0xFFFFFFFFL
23392 //RLC_SRM_CNTL
23393 #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT                                                                       0x0
23394 #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT                                                                   0x1
23395 #define RLC_SRM_CNTL__RESERVED__SHIFT                                                                         0x2
23396 #define RLC_SRM_CNTL__SRM_ENABLE_MASK                                                                         0x00000001L
23397 #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK                                                                     0x00000002L
23398 #define RLC_SRM_CNTL__RESERVED_MASK                                                                           0xFFFFFFFCL
23399 //RLC_SRM_ARAM_ADDR
23400 #define RLC_SRM_ARAM_ADDR__ADDR__SHIFT                                                                        0x0
23401 #define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT                                                                    0xc
23402 #define RLC_SRM_ARAM_ADDR__ADDR_MASK                                                                          0x00000FFFL
23403 #define RLC_SRM_ARAM_ADDR__RESERVED_MASK                                                                      0xFFFFF000L
23404 //RLC_SRM_ARAM_DATA
23405 #define RLC_SRM_ARAM_DATA__DATA__SHIFT                                                                        0x0
23406 #define RLC_SRM_ARAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
23407 //RLC_SRM_DRAM_ADDR
23408 #define RLC_SRM_DRAM_ADDR__ADDR__SHIFT                                                                        0x0
23409 #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT                                                                    0xc
23410 #define RLC_SRM_DRAM_ADDR__ADDR_MASK                                                                          0x00000FFFL
23411 #define RLC_SRM_DRAM_ADDR__RESERVED_MASK                                                                      0xFFFFF000L
23412 //RLC_SRM_DRAM_DATA
23413 #define RLC_SRM_DRAM_DATA__DATA__SHIFT                                                                        0x0
23414 #define RLC_SRM_DRAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
23415 //RLC_SRM_GPM_COMMAND
23416 #define RLC_SRM_GPM_COMMAND__OP__SHIFT                                                                        0x0
23417 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT                                                                0x1
23418 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT                                                            0x2
23419 #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT                                                                      0x5
23420 #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT                                                              0x11
23421 #define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT                                                                 0x1d
23422 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT                                                               0x1f
23423 #define RLC_SRM_GPM_COMMAND__OP_MASK                                                                          0x00000001L
23424 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK                                                                  0x00000002L
23425 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK                                                              0x0000001CL
23426 #define RLC_SRM_GPM_COMMAND__SIZE_MASK                                                                        0x0001FFE0L
23427 #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK                                                                0x1FFE0000L
23428 #define RLC_SRM_GPM_COMMAND__RESERVED1_MASK                                                                   0x60000000L
23429 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK                                                                 0x80000000L
23430 //RLC_SRM_GPM_COMMAND_STATUS
23431 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                         0x0
23432 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT                                                          0x1
23433 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT                                                           0x2
23434 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK                                                           0x00000001L
23435 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK                                                            0x00000002L
23436 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK                                                             0xFFFFFFFCL
23437 //RLC_SRM_RLCV_COMMAND
23438 #define RLC_SRM_RLCV_COMMAND__OP__SHIFT                                                                       0x0
23439 #define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT                                                                 0x1
23440 #define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT                                                                     0x4
23441 #define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT                                                             0x10
23442 #define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT                                                                0x1c
23443 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT                                                              0x1f
23444 #define RLC_SRM_RLCV_COMMAND__OP_MASK                                                                         0x00000001L
23445 #define RLC_SRM_RLCV_COMMAND__RESERVED_MASK                                                                   0x0000000EL
23446 #define RLC_SRM_RLCV_COMMAND__SIZE_MASK                                                                       0x0000FFF0L
23447 #define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK                                                               0x0FFF0000L
23448 #define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK                                                                  0x70000000L
23449 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK                                                                0x80000000L
23450 //RLC_SRM_RLCV_COMMAND_STATUS
23451 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                        0x0
23452 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT                                                         0x1
23453 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT                                                          0x2
23454 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK                                                          0x00000001L
23455 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK                                                           0x00000002L
23456 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK                                                            0xFFFFFFFCL
23457 //RLC_SRM_INDEX_CNTL_ADDR_0
23458 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT                                                             0x0
23459 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT                                                            0x10
23460 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK                                                               0x0000FFFFL
23461 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK                                                              0xFFFF0000L
23462 //RLC_SRM_INDEX_CNTL_ADDR_1
23463 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT                                                             0x0
23464 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT                                                            0x10
23465 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK                                                               0x0000FFFFL
23466 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK                                                              0xFFFF0000L
23467 //RLC_SRM_INDEX_CNTL_ADDR_2
23468 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT                                                             0x0
23469 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT                                                            0x10
23470 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK                                                               0x0000FFFFL
23471 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK                                                              0xFFFF0000L
23472 //RLC_SRM_INDEX_CNTL_ADDR_3
23473 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT                                                             0x0
23474 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT                                                            0x10
23475 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK                                                               0x0000FFFFL
23476 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK                                                              0xFFFF0000L
23477 //RLC_SRM_INDEX_CNTL_ADDR_4
23478 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT                                                             0x0
23479 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT                                                            0x10
23480 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK                                                               0x0000FFFFL
23481 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK                                                              0xFFFF0000L
23482 //RLC_SRM_INDEX_CNTL_ADDR_5
23483 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT                                                             0x0
23484 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT                                                            0x10
23485 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK                                                               0x0000FFFFL
23486 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK                                                              0xFFFF0000L
23487 //RLC_SRM_INDEX_CNTL_ADDR_6
23488 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT                                                             0x0
23489 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT                                                            0x10
23490 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK                                                               0x0000FFFFL
23491 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK                                                              0xFFFF0000L
23492 //RLC_SRM_INDEX_CNTL_ADDR_7
23493 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT                                                             0x0
23494 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT                                                            0x10
23495 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK                                                               0x0000FFFFL
23496 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK                                                              0xFFFF0000L
23497 //RLC_SRM_INDEX_CNTL_DATA_0
23498 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT                                                                0x0
23499 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK                                                                  0xFFFFFFFFL
23500 //RLC_SRM_INDEX_CNTL_DATA_1
23501 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT                                                                0x0
23502 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK                                                                  0xFFFFFFFFL
23503 //RLC_SRM_INDEX_CNTL_DATA_2
23504 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT                                                                0x0
23505 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK                                                                  0xFFFFFFFFL
23506 //RLC_SRM_INDEX_CNTL_DATA_3
23507 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT                                                                0x0
23508 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK                                                                  0xFFFFFFFFL
23509 //RLC_SRM_INDEX_CNTL_DATA_4
23510 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT                                                                0x0
23511 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK                                                                  0xFFFFFFFFL
23512 //RLC_SRM_INDEX_CNTL_DATA_5
23513 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT                                                                0x0
23514 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK                                                                  0xFFFFFFFFL
23515 //RLC_SRM_INDEX_CNTL_DATA_6
23516 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT                                                                0x0
23517 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK                                                                  0xFFFFFFFFL
23518 //RLC_SRM_INDEX_CNTL_DATA_7
23519 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT                                                                0x0
23520 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK                                                                  0xFFFFFFFFL
23521 //RLC_SRM_STAT
23522 #define RLC_SRM_STAT__SRM_BUSY__SHIFT                                                                         0x0
23523 #define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT                                                                   0x1
23524 #define RLC_SRM_STAT__RESERVED__SHIFT                                                                         0x2
23525 #define RLC_SRM_STAT__SRM_BUSY_MASK                                                                           0x00000001L
23526 #define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK                                                                     0x00000002L
23527 #define RLC_SRM_STAT__RESERVED_MASK                                                                           0xFFFFFFFCL
23528 //RLC_SRM_GPM_ABORT
23529 #define RLC_SRM_GPM_ABORT__ABORT__SHIFT                                                                       0x0
23530 #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT                                                                    0x1
23531 #define RLC_SRM_GPM_ABORT__ABORT_MASK                                                                         0x00000001L
23532 #define RLC_SRM_GPM_ABORT__RESERVED_MASK                                                                      0xFFFFFFFEL
23533 //RLC_CSIB_ADDR_LO
23534 #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT                                                                      0x0
23535 #define RLC_CSIB_ADDR_LO__ADDRESS_MASK                                                                        0xFFFFFFFFL
23536 //RLC_CSIB_ADDR_HI
23537 #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT                                                                      0x0
23538 #define RLC_CSIB_ADDR_HI__ADDRESS_MASK                                                                        0x0000FFFFL
23539 //RLC_CSIB_LENGTH
23540 #define RLC_CSIB_LENGTH__LENGTH__SHIFT                                                                        0x0
23541 #define RLC_CSIB_LENGTH__LENGTH_MASK                                                                          0xFFFFFFFFL
23542 //RLC_SMU_COMMAND
23543 #define RLC_SMU_COMMAND__CMD__SHIFT                                                                           0x0
23544 #define RLC_SMU_COMMAND__CMD_MASK                                                                             0xFFFFFFFFL
23545 //RLC_CP_SCHEDULERS
23546 #define RLC_CP_SCHEDULERS__scheduler0__SHIFT                                                                  0x0
23547 #define RLC_CP_SCHEDULERS__scheduler1__SHIFT                                                                  0x8
23548 #define RLC_CP_SCHEDULERS__scheduler2__SHIFT                                                                  0x10
23549 #define RLC_CP_SCHEDULERS__scheduler3__SHIFT                                                                  0x18
23550 #define RLC_CP_SCHEDULERS__scheduler0_MASK                                                                    0x000000FFL
23551 #define RLC_CP_SCHEDULERS__scheduler1_MASK                                                                    0x0000FF00L
23552 #define RLC_CP_SCHEDULERS__scheduler2_MASK                                                                    0x00FF0000L
23553 #define RLC_CP_SCHEDULERS__scheduler3_MASK                                                                    0xFF000000L
23554 //RLC_SMU_ARGUMENT_1
23555 #define RLC_SMU_ARGUMENT_1__ARG__SHIFT                                                                        0x0
23556 #define RLC_SMU_ARGUMENT_1__ARG_MASK                                                                          0xFFFFFFFFL
23557 //RLC_SMU_ARGUMENT_2
23558 #define RLC_SMU_ARGUMENT_2__ARG__SHIFT                                                                        0x0
23559 #define RLC_SMU_ARGUMENT_2__ARG_MASK                                                                          0xFFFFFFFFL
23560 //RLC_GPM_GENERAL_8
23561 #define RLC_GPM_GENERAL_8__DATA__SHIFT                                                                        0x0
23562 #define RLC_GPM_GENERAL_8__DATA_MASK                                                                          0xFFFFFFFFL
23563 //RLC_GPM_GENERAL_9
23564 #define RLC_GPM_GENERAL_9__DATA__SHIFT                                                                        0x0
23565 #define RLC_GPM_GENERAL_9__DATA_MASK                                                                          0xFFFFFFFFL
23566 //RLC_GPM_GENERAL_10
23567 #define RLC_GPM_GENERAL_10__DATA__SHIFT                                                                       0x0
23568 #define RLC_GPM_GENERAL_10__DATA_MASK                                                                         0xFFFFFFFFL
23569 //RLC_GPM_GENERAL_11
23570 #define RLC_GPM_GENERAL_11__DATA__SHIFT                                                                       0x0
23571 #define RLC_GPM_GENERAL_11__DATA_MASK                                                                         0xFFFFFFFFL
23572 //RLC_GPM_GENERAL_12
23573 #define RLC_GPM_GENERAL_12__DATA__SHIFT                                                                       0x0
23574 #define RLC_GPM_GENERAL_12__DATA_MASK                                                                         0xFFFFFFFFL
23575 //RLC_GPM_UTCL1_CNTL_0
23576 #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
23577 #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT                                                                0x18
23578 #define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT                                                                   0x19
23579 #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT                                                               0x1a
23580 #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
23581 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT                                                              0x1c
23582 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT                                                      0x1d
23583 #define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT                                                                 0x1e
23584 #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
23585 #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK                                                                  0x01000000L
23586 #define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK                                                                     0x02000000L
23587 #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK                                                                 0x04000000L
23588 #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
23589 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK                                                                0x10000000L
23590 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK                                                        0x20000000L
23591 #define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK                                                                   0xC0000000L
23592 //RLC_GPM_UTCL1_CNTL_1
23593 #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
23594 #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT                                                                0x18
23595 #define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT                                                                   0x19
23596 #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT                                                               0x1a
23597 #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
23598 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT                                                              0x1c
23599 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT                                                      0x1d
23600 #define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT                                                                 0x1e
23601 #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
23602 #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK                                                                  0x01000000L
23603 #define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK                                                                     0x02000000L
23604 #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK                                                                 0x04000000L
23605 #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
23606 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK                                                                0x10000000L
23607 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK                                                        0x20000000L
23608 #define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK                                                                   0xC0000000L
23609 //RLC_GPM_UTCL1_CNTL_2
23610 #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
23611 #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT                                                                0x18
23612 #define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT                                                                   0x19
23613 #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT                                                               0x1a
23614 #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
23615 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT                                                              0x1c
23616 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT                                                      0x1d
23617 #define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT                                                                 0x1e
23618 #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
23619 #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK                                                                  0x01000000L
23620 #define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK                                                                     0x02000000L
23621 #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK                                                                 0x04000000L
23622 #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
23623 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK                                                                0x10000000L
23624 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK                                                        0x20000000L
23625 #define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK                                                                   0xC0000000L
23626 //RLC_SPM_UTCL1_CNTL
23627 #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                       0x0
23628 #define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT                                                                  0x18
23629 #define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT                                                                     0x19
23630 #define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT                                                                 0x1a
23631 #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                            0x1b
23632 #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                0x1c
23633 #define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                        0x1d
23634 #define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT                                                                   0x1e
23635 #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                         0x000FFFFFL
23636 #define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK                                                                    0x01000000L
23637 #define RLC_SPM_UTCL1_CNTL__BYPASS_MASK                                                                       0x02000000L
23638 #define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK                                                                   0x04000000L
23639 #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                              0x08000000L
23640 #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                  0x10000000L
23641 #define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                          0x20000000L
23642 #define RLC_SPM_UTCL1_CNTL__RESERVED_MASK                                                                     0xC0000000L
23643 //RLC_UTCL1_STATUS_2
23644 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT                                                         0x0
23645 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT                                                         0x1
23646 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT                                                         0x2
23647 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT                                                             0x3
23648 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT                                                       0x4
23649 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT                                                 0x5
23650 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT                                                 0x6
23651 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT                                                 0x7
23652 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT                                                     0x8
23653 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT                                               0x9
23654 #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT                                                                   0xa
23655 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK                                                           0x00000001L
23656 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK                                                           0x00000002L
23657 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK                                                           0x00000004L
23658 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK                                                               0x00000008L
23659 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK                                                         0x00000010L
23660 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK                                                   0x00000020L
23661 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK                                                   0x00000040L
23662 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK                                                   0x00000080L
23663 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK                                                       0x00000100L
23664 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK                                                 0x00000200L
23665 #define RLC_UTCL1_STATUS_2__RESERVED_MASK                                                                     0xFFFFFC00L
23666 //RLC_LB_THR_CONFIG_2
23667 #define RLC_LB_THR_CONFIG_2__DATA__SHIFT                                                                      0x0
23668 #define RLC_LB_THR_CONFIG_2__DATA_MASK                                                                        0xFFFFFFFFL
23669 //RLC_LB_THR_CONFIG_3
23670 #define RLC_LB_THR_CONFIG_3__DATA__SHIFT                                                                      0x0
23671 #define RLC_LB_THR_CONFIG_3__DATA_MASK                                                                        0xFFFFFFFFL
23672 //RLC_LB_THR_CONFIG_4
23673 #define RLC_LB_THR_CONFIG_4__DATA__SHIFT                                                                      0x0
23674 #define RLC_LB_THR_CONFIG_4__DATA_MASK                                                                        0xFFFFFFFFL
23675 //RLC_SPM_UTCL1_ERROR_1
23676 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT                                                     0x0
23677 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                                 0x2
23678 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                             0x6
23679 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK                                                       0x00000003L
23680 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK                                                   0x0000003CL
23681 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                               0x000003C0L
23682 //RLC_SPM_UTCL1_ERROR_2
23683 #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                             0x0
23684 #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                               0xFFFFFFFFL
23685 //RLC_GPM_UTCL1_TH0_ERROR_1
23686 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
23687 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
23688 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
23689 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
23690 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
23691 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
23692 //RLC_LB_THR_CONFIG_1
23693 #define RLC_LB_THR_CONFIG_1__DATA__SHIFT                                                                      0x0
23694 #define RLC_LB_THR_CONFIG_1__DATA_MASK                                                                        0xFFFFFFFFL
23695 //RLC_GPM_UTCL1_TH0_ERROR_2
23696 #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
23697 #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
23698 //RLC_GPM_UTCL1_TH1_ERROR_1
23699 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
23700 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
23701 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
23702 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
23703 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
23704 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
23705 //RLC_GPM_UTCL1_TH1_ERROR_2
23706 #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
23707 #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
23708 //RLC_GPM_UTCL1_TH2_ERROR_1
23709 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
23710 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
23711 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
23712 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
23713 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
23714 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
23715 //RLC_GPM_UTCL1_TH2_ERROR_2
23716 #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
23717 #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
23718 //RLC_CGCG_CGLS_CTRL_3D
23719 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT                                                                 0x0
23720 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT                                                                 0x1
23721 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT                                                0x2
23722 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT                                                 0x8
23723 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT                                                         0x1b
23724 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT                                                           0x1c
23725 #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT                                                              0x1d
23726 #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT                                                          0x1f
23727 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK                                                                   0x00000001L
23728 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK                                                                   0x00000002L
23729 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK                                                  0x000000FCL
23730 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK                                                   0x07FFFF00L
23731 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK                                                           0x08000000L
23732 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK                                                             0x10000000L
23733 #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK                                                                0x60000000L
23734 #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK                                                            0x80000000L
23735 //RLC_CGCG_RAMP_CTRL_3D
23736 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT                                                     0x0
23737 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT                                                      0x4
23738 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT                                                       0x8
23739 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT                                                        0xc
23740 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT                                                          0x10
23741 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT                                                         0x1c
23742 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK                                                       0x0000000FL
23743 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK                                                        0x000000F0L
23744 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK                                                         0x00000F00L
23745 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK                                                          0x0000F000L
23746 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK                                                            0x0FFF0000L
23747 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK                                                           0xF0000000L
23748 //RLC_SEMAPHORE_0
23749 #define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT                                                                     0x0
23750 #define RLC_SEMAPHORE_0__RESERVED__SHIFT                                                                      0x5
23751 #define RLC_SEMAPHORE_0__CLIENT_ID_MASK                                                                       0x0000001FL
23752 #define RLC_SEMAPHORE_0__RESERVED_MASK                                                                        0xFFFFFFE0L
23753 //RLC_SEMAPHORE_1
23754 #define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT                                                                     0x0
23755 #define RLC_SEMAPHORE_1__RESERVED__SHIFT                                                                      0x5
23756 #define RLC_SEMAPHORE_1__CLIENT_ID_MASK                                                                       0x0000001FL
23757 #define RLC_SEMAPHORE_1__RESERVED_MASK                                                                        0xFFFFFFE0L
23758 //RLC_CP_EOF_INT
23759 #define RLC_CP_EOF_INT__INTERRUPT__SHIFT                                                                      0x0
23760 #define RLC_CP_EOF_INT__RESERVED__SHIFT                                                                       0x1
23761 #define RLC_CP_EOF_INT__INTERRUPT_MASK                                                                        0x00000001L
23762 #define RLC_CP_EOF_INT__RESERVED_MASK                                                                         0xFFFFFFFEL
23763 //RLC_CP_EOF_INT_CNT
23764 #define RLC_CP_EOF_INT_CNT__CNT__SHIFT                                                                        0x0
23765 #define RLC_CP_EOF_INT_CNT__CNT_MASK                                                                          0xFFFFFFFFL
23766 //RLC_SPARE_INT
23767 #define RLC_SPARE_INT__INTERRUPT__SHIFT                                                                       0x0
23768 #define RLC_SPARE_INT__RESERVED__SHIFT                                                                        0x1
23769 #define RLC_SPARE_INT__INTERRUPT_MASK                                                                         0x00000001L
23770 #define RLC_SPARE_INT__RESERVED_MASK                                                                          0xFFFFFFFEL
23771 //RLC_PREWALKER_UTCL1_CNTL
23772 #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                 0x0
23773 #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT                                                            0x18
23774 #define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT                                                               0x19
23775 #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT                                                           0x1a
23776 #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                      0x1b
23777 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                          0x1c
23778 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                  0x1d
23779 #define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT                                                             0x1e
23780 #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                   0x000FFFFFL
23781 #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK                                                              0x01000000L
23782 #define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK                                                                 0x02000000L
23783 #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK                                                             0x04000000L
23784 #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                        0x08000000L
23785 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK                                                            0x10000000L
23786 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                    0x20000000L
23787 #define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK                                                               0xC0000000L
23788 //RLC_PREWALKER_UTCL1_TRIG
23789 #define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT                                                                0x0
23790 #define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT                                                                 0x1
23791 #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT                                                           0x5
23792 #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT                                                            0x6
23793 #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT                                                           0x7
23794 #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT                                                            0x8
23795 #define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT                                                             0x9
23796 #define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT                                                                0x1f
23797 #define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK                                                                  0x00000001L
23798 #define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK                                                                   0x0000001EL
23799 #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK                                                             0x00000020L
23800 #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK                                                              0x00000040L
23801 #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK                                                             0x00000080L
23802 #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK                                                              0x00000100L
23803 #define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK                                                               0x7FFFFE00L
23804 #define RLC_PREWALKER_UTCL1_TRIG__READY_MASK                                                                  0x80000000L
23805 //RLC_PREWALKER_UTCL1_ADDR_LSB
23806 #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT                                                         0x0
23807 #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK                                                           0xFFFFFFFFL
23808 //RLC_PREWALKER_UTCL1_ADDR_MSB
23809 #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT                                                         0x0
23810 #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK                                                           0x0000FFFFL
23811 //RLC_PREWALKER_UTCL1_SIZE_LSB
23812 #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT                                                         0x0
23813 #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK                                                           0xFFFFFFFFL
23814 //RLC_PREWALKER_UTCL1_SIZE_MSB
23815 #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT                                                         0x0
23816 #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK                                                           0x00000003L
23817 //RLC_DSM_TRIG
23818 //RLC_UTCL1_STATUS
23819 #define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
23820 #define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
23821 #define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
23822 #define RLC_UTCL1_STATUS__RESERVED__SHIFT                                                                     0x3
23823 #define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
23824 #define RLC_UTCL1_STATUS__RESERVED_1__SHIFT                                                                   0xe
23825 #define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
23826 #define RLC_UTCL1_STATUS__RESERVED_2__SHIFT                                                                   0x16
23827 #define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
23828 #define RLC_UTCL1_STATUS__RESERVED_3__SHIFT                                                                   0x1e
23829 #define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
23830 #define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
23831 #define RLC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
23832 #define RLC_UTCL1_STATUS__RESERVED_MASK                                                                       0x000000F8L
23833 #define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
23834 #define RLC_UTCL1_STATUS__RESERVED_1_MASK                                                                     0x0000C000L
23835 #define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
23836 #define RLC_UTCL1_STATUS__RESERVED_2_MASK                                                                     0x00C00000L
23837 #define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
23838 #define RLC_UTCL1_STATUS__RESERVED_3_MASK                                                                     0xC0000000L
23839 //RLC_R2I_CNTL_0
23840 #define RLC_R2I_CNTL_0__Data__SHIFT                                                                           0x0
23841 #define RLC_R2I_CNTL_0__Data_MASK                                                                             0xFFFFFFFFL
23842 //RLC_R2I_CNTL_1
23843 #define RLC_R2I_CNTL_1__Data__SHIFT                                                                           0x0
23844 #define RLC_R2I_CNTL_1__Data_MASK                                                                             0xFFFFFFFFL
23845 //RLC_R2I_CNTL_2
23846 #define RLC_R2I_CNTL_2__Data__SHIFT                                                                           0x0
23847 #define RLC_R2I_CNTL_2__Data_MASK                                                                             0xFFFFFFFFL
23848 //RLC_R2I_CNTL_3
23849 #define RLC_R2I_CNTL_3__Data__SHIFT                                                                           0x0
23850 #define RLC_R2I_CNTL_3__Data_MASK                                                                             0xFFFFFFFFL
23851 //RLC_UTCL2_CNTL
23852 #define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x0
23853 #define RLC_UTCL2_CNTL__RESERVED__SHIFT                                                                       0x1
23854 #define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x00000001L
23855 #define RLC_UTCL2_CNTL__RESERVED_MASK                                                                         0xFFFFFFFEL
23856 //RLC_LBPW_CU_STAT
23857 #define RLC_LBPW_CU_STAT__MAX_CU__SHIFT                                                                       0x0
23858 #define RLC_LBPW_CU_STAT__ON_CU__SHIFT                                                                        0x10
23859 #define RLC_LBPW_CU_STAT__MAX_CU_MASK                                                                         0x0000FFFFL
23860 #define RLC_LBPW_CU_STAT__ON_CU_MASK                                                                          0xFFFF0000L
23861 //RLC_DS_CNTL
23862 #define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT                                                          0x0
23863 #define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT                                                           0x1
23864 #define RLC_DS_CNTL__RESRVED__SHIFT                                                                           0x2
23865 #define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT                                                          0x10
23866 #define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT                                                           0x11
23867 #define RLC_DS_CNTL__RESRVED_1__SHIFT                                                                         0x12
23868 #define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK                                                            0x00000001L
23869 #define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK                                                             0x00000002L
23870 #define RLC_DS_CNTL__RESRVED_MASK                                                                             0x0000FFFCL
23871 #define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK                                                            0x00010000L
23872 #define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK                                                             0x00020000L
23873 #define RLC_DS_CNTL__RESRVED_1_MASK                                                                           0xFFFC0000L
23874 //RLC_RLCV_SPARE_INT
23875 #define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT                                                                  0x0
23876 #define RLC_RLCV_SPARE_INT__RESERVED__SHIFT                                                                   0x1
23877 #define RLC_RLCV_SPARE_INT__INTERRUPT_MASK                                                                    0x00000001L
23878 #define RLC_RLCV_SPARE_INT__RESERVED_MASK                                                                     0xFFFFFFFEL
23879 
23880 
23881 // addressBlock: gc_pwrdec
23882 //CGTS_SM_CTRL_REG
23883 #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT                                                                 0x0
23884 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT                                                                0x4
23885 #define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT                                                                 0xc
23886 #define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT                                                                    0x10
23887 #define CGTS_SM_CTRL_REG__SM_MODE__SHIFT                                                                      0x11
23888 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT                                                               0x14
23889 #define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT                                                                     0x15
23890 #define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT                                                                  0x16
23891 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT                                                            0x17
23892 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT                                                               0x18
23893 #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK                                                                   0x0000000FL
23894 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK                                                                  0x00000FF0L
23895 #define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK                                                                   0x00001000L
23896 #define CGTS_SM_CTRL_REG__BASE_MODE_MASK                                                                      0x00010000L
23897 #define CGTS_SM_CTRL_REG__SM_MODE_MASK                                                                        0x000E0000L
23898 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK                                                                 0x00100000L
23899 #define CGTS_SM_CTRL_REG__OVERRIDE_MASK                                                                       0x00200000L
23900 #define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK                                                                    0x00400000L
23901 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK                                                              0x00800000L
23902 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK                                                                 0xFF000000L
23903 //CGTS_RD_CTRL_REG
23904 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT                                                                  0x0
23905 #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT                                                                  0x8
23906 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK                                                                    0x0000001FL
23907 #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK                                                                    0x00001F00L
23908 //CGTS_RD_REG
23909 #define CGTS_RD_REG__READ_DATA__SHIFT                                                                         0x0
23910 #define CGTS_RD_REG__READ_DATA_MASK                                                                           0x00003FFFL
23911 //CGTS_TCC_DISABLE
23912 #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT                                                                  0x10
23913 #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK                                                                    0xFFFF0000L
23914 //CGTS_USER_TCC_DISABLE
23915 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT                                                             0x10
23916 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK                                                               0xFFFF0000L
23917 //CGTS_CU0_SP0_CTRL_REG
23918 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
23919 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
23920 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
23921 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
23922 #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
23923 #define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
23924 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
23925 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
23926 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
23927 #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
23928 #define CGTS_CU0_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
23929 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
23930 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
23931 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
23932 #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
23933 #define CGTS_CU0_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
23934 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
23935 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
23936 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
23937 #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
23938 //CGTS_CU0_LDS_SQ_CTRL_REG
23939 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
23940 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
23941 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
23942 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
23943 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
23944 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
23945 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
23946 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
23947 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
23948 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
23949 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
23950 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
23951 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
23952 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
23953 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
23954 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
23955 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
23956 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
23957 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
23958 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
23959 //CGTS_CU0_TA_SQC_CTRL_REG
23960 #define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
23961 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
23962 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
23963 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
23964 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
23965 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
23966 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
23967 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
23968 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
23969 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
23970 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
23971 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
23972 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
23973 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
23974 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
23975 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
23976 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
23977 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
23978 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
23979 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
23980 //CGTS_CU0_SP1_CTRL_REG
23981 #define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
23982 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
23983 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
23984 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
23985 #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
23986 #define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
23987 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
23988 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
23989 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
23990 #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
23991 #define CGTS_CU0_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
23992 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
23993 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
23994 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
23995 #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
23996 #define CGTS_CU0_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
23997 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
23998 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
23999 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24000 #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24001 //CGTS_CU0_TD_TCP_CTRL_REG
24002 #define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24003 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24004 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24005 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24006 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24007 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24008 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24009 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24010 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24011 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24012 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24013 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24014 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24015 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24016 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24017 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24018 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24019 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24020 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24021 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24022 //CGTS_CU1_SP0_CTRL_REG
24023 #define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24024 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24025 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24026 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24027 #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24028 #define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24029 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24030 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24031 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24032 #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24033 #define CGTS_CU1_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24034 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24035 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24036 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24037 #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24038 #define CGTS_CU1_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24039 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24040 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24041 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24042 #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24043 //CGTS_CU1_LDS_SQ_CTRL_REG
24044 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24045 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24046 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24047 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24048 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24049 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24050 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24051 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24052 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24053 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24054 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24055 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24056 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24057 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24058 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24059 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24060 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24061 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24062 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24063 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24064 //CGTS_CU1_TA_SQC_CTRL_REG
24065 #define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24066 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24067 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24068 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24069 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24070 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24071 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24072 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24073 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24074 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24075 //CGTS_CU1_SP1_CTRL_REG
24076 #define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24077 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24078 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24079 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24080 #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24081 #define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24082 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24083 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24084 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24085 #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24086 #define CGTS_CU1_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24087 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24088 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24089 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24090 #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24091 #define CGTS_CU1_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24092 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24093 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24094 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24095 #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24096 //CGTS_CU1_TD_TCP_CTRL_REG
24097 #define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24098 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24099 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24100 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24101 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24102 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24103 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24104 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24105 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24106 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24107 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24108 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24109 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24110 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24111 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24112 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24113 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24114 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24115 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24116 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24117 //CGTS_CU2_SP0_CTRL_REG
24118 #define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24119 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24120 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24121 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24122 #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24123 #define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24124 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24125 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24126 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24127 #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24128 #define CGTS_CU2_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24129 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24130 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24131 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24132 #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24133 #define CGTS_CU2_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24134 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24135 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24136 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24137 #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24138 //CGTS_CU2_LDS_SQ_CTRL_REG
24139 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24140 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24141 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24142 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24143 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24144 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24145 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24146 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24147 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24148 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24149 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24150 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24151 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24152 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24153 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24154 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24155 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24156 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24157 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24158 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24159 //CGTS_CU2_TA_SQC_CTRL_REG
24160 #define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24161 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24162 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24163 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24164 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24165 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24166 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24167 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24168 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24169 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24170 //CGTS_CU2_SP1_CTRL_REG
24171 #define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24172 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24173 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24174 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24175 #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24176 #define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24177 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24178 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24179 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24180 #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24181 #define CGTS_CU2_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24182 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24183 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24184 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24185 #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24186 #define CGTS_CU2_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24187 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24188 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24189 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24190 #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24191 //CGTS_CU2_TD_TCP_CTRL_REG
24192 #define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24193 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24194 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24195 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24196 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24197 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24198 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24199 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24200 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24201 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24202 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24203 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24204 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24205 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24206 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24207 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24208 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24209 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24210 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24211 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24212 //CGTS_CU3_SP0_CTRL_REG
24213 #define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24214 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24215 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24216 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24217 #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24218 #define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24219 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24220 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24221 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24222 #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24223 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24224 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24225 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24226 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24227 #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24228 #define CGTS_CU3_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24229 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24230 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24231 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24232 #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24233 //CGTS_CU3_LDS_SQ_CTRL_REG
24234 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24235 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24236 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24237 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24238 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24239 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24240 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24241 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24242 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24243 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24244 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24245 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24246 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24247 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24248 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24249 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24250 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24251 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24252 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24253 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24254 //CGTS_CU3_TA_SQC_CTRL_REG
24255 #define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24256 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24257 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24258 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24259 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24260 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
24261 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
24262 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
24263 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
24264 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
24265 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24266 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24267 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24268 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24269 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24270 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
24271 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
24272 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
24273 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
24274 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
24275 //CGTS_CU3_SP1_CTRL_REG
24276 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24277 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24278 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24279 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24280 #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24281 #define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24282 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24283 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24284 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24285 #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24286 #define CGTS_CU3_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24287 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24288 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24289 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24290 #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24291 #define CGTS_CU3_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24292 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24293 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24294 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24295 #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24296 //CGTS_CU3_TD_TCP_CTRL_REG
24297 #define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24298 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24299 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24300 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24301 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24302 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24303 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24304 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24305 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24306 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24307 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24308 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24309 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24310 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24311 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24312 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24313 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24314 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24315 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24316 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24317 //CGTS_CU4_SP0_CTRL_REG
24318 #define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24319 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24320 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24321 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24322 #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24323 #define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24324 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24325 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24326 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24327 #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24328 #define CGTS_CU4_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24329 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24330 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24331 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24332 #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24333 #define CGTS_CU4_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24334 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24335 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24336 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24337 #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24338 //CGTS_CU4_LDS_SQ_CTRL_REG
24339 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24340 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24341 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24342 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24343 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24344 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24345 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24346 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24347 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24348 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24349 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24350 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24351 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24352 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24353 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24354 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24355 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24356 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24357 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24358 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24359 //CGTS_CU4_TA_SQC_CTRL_REG
24360 #define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24361 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24362 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24363 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24364 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24365 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24366 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24367 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24368 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24369 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24370 //CGTS_CU4_SP1_CTRL_REG
24371 #define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24372 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24373 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24374 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24375 #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24376 #define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24377 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24378 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24379 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24380 #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24381 #define CGTS_CU4_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24382 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24383 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24384 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24385 #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24386 #define CGTS_CU4_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24387 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24388 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24389 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24390 #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24391 //CGTS_CU4_TD_TCP_CTRL_REG
24392 #define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24393 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24394 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24395 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24396 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24397 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24398 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24399 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24400 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24401 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24402 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24403 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24404 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24405 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24406 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24407 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24408 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24409 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24410 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24411 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24412 //CGTS_CU5_SP0_CTRL_REG
24413 #define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24414 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24415 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24416 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24417 #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24418 #define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24419 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24420 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24421 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24422 #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24423 #define CGTS_CU5_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24424 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24425 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24426 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24427 #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24428 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24429 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24430 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24431 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24432 #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24433 //CGTS_CU5_LDS_SQ_CTRL_REG
24434 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24435 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24436 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24437 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24438 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24439 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24440 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24441 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24442 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24443 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24444 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24445 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24446 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24447 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24448 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24449 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24450 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24451 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24452 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24453 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24454 //CGTS_CU5_TA_SQC_CTRL_REG
24455 #define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24456 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24457 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24458 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24459 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24460 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24461 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24462 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24463 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24464 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24465 //CGTS_CU5_SP1_CTRL_REG
24466 #define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24467 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24468 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24469 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24470 #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24471 #define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24472 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24473 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24474 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24475 #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24476 #define CGTS_CU5_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24477 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24478 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24479 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24480 #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24481 #define CGTS_CU5_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24482 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24483 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24484 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24485 #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24486 //CGTS_CU5_TD_TCP_CTRL_REG
24487 #define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24488 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24489 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24490 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24491 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24492 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24493 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24494 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24495 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24496 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24497 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24498 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24499 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24500 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24501 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24502 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24503 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24504 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24505 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24506 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24507 //CGTS_CU6_SP0_CTRL_REG
24508 #define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24509 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24510 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24511 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24512 #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24513 #define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24514 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24515 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24516 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24517 #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24518 #define CGTS_CU6_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24519 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24520 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24521 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24522 #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24523 #define CGTS_CU6_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24524 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24525 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24526 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24527 #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24528 //CGTS_CU6_LDS_SQ_CTRL_REG
24529 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24530 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24531 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24532 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24533 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24534 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24535 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24536 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24537 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24538 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24539 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24540 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24541 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24542 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24543 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24544 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24545 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24546 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24547 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24548 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24549 //CGTS_CU6_TA_SQC_CTRL_REG
24550 #define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24551 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24552 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24553 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24554 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24555 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
24556 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
24557 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
24558 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
24559 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
24560 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24561 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24562 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24563 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24564 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24565 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
24566 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
24567 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
24568 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
24569 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
24570 //CGTS_CU6_SP1_CTRL_REG
24571 #define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24572 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24573 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24574 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24575 #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24576 #define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24577 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24578 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24579 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24580 #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24581 #define CGTS_CU6_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24582 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24583 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24584 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24585 #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24586 #define CGTS_CU6_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24587 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24588 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24589 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24590 #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24591 //CGTS_CU6_TD_TCP_CTRL_REG
24592 #define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24593 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24594 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24595 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24596 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24597 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24598 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24599 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24600 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24601 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24602 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24603 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24604 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24605 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24606 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24607 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24608 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24609 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24610 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24611 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24612 //CGTS_CU7_SP0_CTRL_REG
24613 #define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24614 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24615 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24616 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24617 #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24618 #define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24619 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24620 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24621 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24622 #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24623 #define CGTS_CU7_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24624 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24625 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24626 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24627 #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24628 #define CGTS_CU7_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24629 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24630 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24631 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24632 #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24633 //CGTS_CU7_LDS_SQ_CTRL_REG
24634 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24635 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24636 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24637 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24638 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24639 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24640 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24641 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24642 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24643 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24644 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24645 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24646 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24647 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24648 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24649 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24650 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24651 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24652 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24653 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24654 //CGTS_CU7_TA_SQC_CTRL_REG
24655 #define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24656 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24657 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24658 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24659 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24660 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24661 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24662 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24663 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24664 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24665 //CGTS_CU7_SP1_CTRL_REG
24666 #define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24667 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24668 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24669 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24670 #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24671 #define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24672 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24673 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24674 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24675 #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24676 #define CGTS_CU7_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24677 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24678 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24679 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24680 #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24681 #define CGTS_CU7_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24682 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24683 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24684 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24685 #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24686 //CGTS_CU7_TD_TCP_CTRL_REG
24687 #define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24688 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24689 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24690 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24691 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24692 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24693 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24694 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24695 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24696 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24697 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24698 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24699 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24700 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24701 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24702 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24703 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24704 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24705 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24706 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24707 //CGTS_CU8_SP0_CTRL_REG
24708 #define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24709 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24710 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24711 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24712 #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24713 #define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24714 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24715 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24716 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24717 #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24718 #define CGTS_CU8_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24719 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24720 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24721 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24722 #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24723 #define CGTS_CU8_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24724 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24725 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24726 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24727 #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24728 //CGTS_CU8_LDS_SQ_CTRL_REG
24729 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24730 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24731 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24732 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24733 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24734 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24735 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24736 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24737 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24738 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24739 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24740 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24741 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24742 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24743 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24744 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24745 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24746 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24747 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24748 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24749 //CGTS_CU8_TA_SQC_CTRL_REG
24750 #define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24751 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24752 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24753 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24754 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24755 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24756 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24757 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24758 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24759 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24760 //CGTS_CU8_SP1_CTRL_REG
24761 #define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24762 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24763 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24764 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24765 #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24766 #define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24767 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24768 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24769 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24770 #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24771 #define CGTS_CU8_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24772 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24773 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24774 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24775 #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24776 #define CGTS_CU8_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24777 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24778 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24779 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24780 #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24781 //CGTS_CU8_TD_TCP_CTRL_REG
24782 #define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24783 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24784 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24785 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24786 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24787 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24788 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24789 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24790 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24791 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24792 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24793 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24794 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24795 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24796 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24797 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24798 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24799 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24800 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24801 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24802 //CGTS_CU9_SP0_CTRL_REG
24803 #define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24804 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24805 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24806 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24807 #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24808 #define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24809 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24810 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24811 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24812 #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24813 #define CGTS_CU9_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24814 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24815 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24816 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24817 #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24818 #define CGTS_CU9_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24819 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24820 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24821 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24822 #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24823 //CGTS_CU9_LDS_SQ_CTRL_REG
24824 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24825 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24826 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24827 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24828 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24829 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24830 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24831 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24832 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24833 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24834 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24835 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24836 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24837 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24838 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24839 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24840 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24841 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24842 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24843 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24844 //CGTS_CU9_TA_SQC_CTRL_REG
24845 #define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24846 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24847 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24848 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24849 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24850 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
24851 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
24852 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
24853 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
24854 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
24855 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24856 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24857 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24858 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24859 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24860 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
24861 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
24862 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
24863 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
24864 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
24865 //CGTS_CU9_SP1_CTRL_REG
24866 #define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24867 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24868 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24869 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24870 #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24871 #define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24872 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24873 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24874 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24875 #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24876 #define CGTS_CU9_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24877 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24878 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24879 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24880 #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24881 #define CGTS_CU9_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24882 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24883 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24884 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24885 #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24886 //CGTS_CU9_TD_TCP_CTRL_REG
24887 #define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24888 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24889 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24890 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24891 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24892 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24893 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24894 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24895 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24896 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24897 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24898 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24899 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24900 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24901 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24902 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24903 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24904 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24905 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24906 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24907 //CGTS_CU10_SP0_CTRL_REG
24908 #define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
24909 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
24910 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
24911 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
24912 #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24913 #define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
24914 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
24915 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
24916 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
24917 #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24918 #define CGTS_CU10_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
24919 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
24920 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
24921 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
24922 #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24923 #define CGTS_CU10_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
24924 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
24925 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
24926 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
24927 #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24928 //CGTS_CU10_LDS_SQ_CTRL_REG
24929 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
24930 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
24931 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
24932 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
24933 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
24934 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
24935 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
24936 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
24937 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
24938 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
24939 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
24940 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
24941 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
24942 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
24943 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
24944 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
24945 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
24946 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
24947 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
24948 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
24949 //CGTS_CU10_TA_SQC_CTRL_REG
24950 #define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
24951 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
24952 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
24953 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
24954 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24955 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
24956 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
24957 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
24958 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
24959 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24960 //CGTS_CU10_SP1_CTRL_REG
24961 #define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
24962 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
24963 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
24964 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
24965 #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24966 #define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
24967 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
24968 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
24969 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
24970 #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24971 #define CGTS_CU10_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
24972 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
24973 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
24974 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
24975 #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24976 #define CGTS_CU10_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
24977 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
24978 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
24979 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
24980 #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24981 //CGTS_CU10_TD_TCP_CTRL_REG
24982 #define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
24983 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
24984 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
24985 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
24986 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24987 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
24988 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
24989 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
24990 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
24991 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
24992 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
24993 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
24994 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
24995 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
24996 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24997 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
24998 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
24999 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25000 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25001 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25002 //CGTS_CU11_SP0_CTRL_REG
25003 #define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25004 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25005 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25006 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25007 #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25008 #define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25009 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25010 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25011 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25012 #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25013 #define CGTS_CU11_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25014 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25015 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25016 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25017 #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25018 #define CGTS_CU11_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25019 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25020 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25021 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25022 #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25023 //CGTS_CU11_LDS_SQ_CTRL_REG
25024 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25025 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25026 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25027 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25028 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25029 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25030 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25031 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25032 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25033 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25034 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25035 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25036 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25037 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25038 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25039 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25040 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25041 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25042 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25043 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25044 //CGTS_CU11_TA_SQC_CTRL_REG
25045 #define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25046 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25047 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25048 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25049 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25050 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25051 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25052 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25053 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25054 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25055 //CGTS_CU11_SP1_CTRL_REG
25056 #define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25057 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25058 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25059 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25060 #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25061 #define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25062 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25063 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25064 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25065 #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25066 #define CGTS_CU11_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25067 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25068 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25069 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25070 #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25071 #define CGTS_CU11_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25072 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25073 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25074 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25075 #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25076 //CGTS_CU11_TD_TCP_CTRL_REG
25077 #define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25078 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25079 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25080 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25081 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25082 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25083 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25084 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25085 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25086 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25087 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25088 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25089 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25090 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25091 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25092 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25093 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25094 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25095 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25096 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25097 //CGTS_CU12_SP0_CTRL_REG
25098 #define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25099 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25100 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25101 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25102 #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25103 #define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25104 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25105 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25106 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25107 #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25108 #define CGTS_CU12_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25109 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25110 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25111 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25112 #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25113 #define CGTS_CU12_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25114 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25115 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25116 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25117 #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25118 //CGTS_CU12_LDS_SQ_CTRL_REG
25119 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25120 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25121 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25122 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25123 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25124 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25125 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25126 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25127 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25128 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25129 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25130 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25131 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25132 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25133 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25134 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25135 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25136 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25137 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25138 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25139 //CGTS_CU12_TA_SQC_CTRL_REG
25140 #define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25141 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25142 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25143 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25144 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25145 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT                                                                 0x10
25146 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                        0x17
25147 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                   0x18
25148 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                     0x1a
25149 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
25150 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25151 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25152 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25153 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25154 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25155 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK                                                                   0x007F0000L
25156 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                          0x00800000L
25157 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                     0x03000000L
25158 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                       0x04000000L
25159 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
25160 //CGTS_CU12_SP1_CTRL_REG
25161 #define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25162 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25163 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25164 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25165 #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25166 #define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25167 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25168 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25169 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25170 #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25171 #define CGTS_CU12_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25172 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25173 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25174 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25175 #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25176 #define CGTS_CU12_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25177 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25178 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25179 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25180 #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25181 //CGTS_CU12_TD_TCP_CTRL_REG
25182 #define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25183 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25184 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25185 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25186 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25187 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25188 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25189 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25190 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25191 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25192 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25193 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25194 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25195 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25196 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25197 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25198 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25199 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25200 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25201 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25202 //CGTS_CU13_SP0_CTRL_REG
25203 #define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25204 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25205 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25206 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25207 #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25208 #define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25209 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25210 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25211 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25212 #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25213 #define CGTS_CU13_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25214 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25215 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25216 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25217 #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25218 #define CGTS_CU13_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25219 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25220 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25221 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25222 #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25223 //CGTS_CU13_LDS_SQ_CTRL_REG
25224 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25225 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25226 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25227 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25228 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25229 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25230 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25231 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25232 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25233 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25234 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25235 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25236 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25237 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25238 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25239 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25240 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25241 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25242 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25243 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25244 //CGTS_CU13_TA_SQC_CTRL_REG
25245 #define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25246 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25247 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25248 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25249 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25250 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25251 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25252 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25253 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25254 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25255 //CGTS_CU13_SP1_CTRL_REG
25256 #define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25257 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25258 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25259 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25260 #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25261 #define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25262 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25263 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25264 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25265 #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25266 #define CGTS_CU13_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25267 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25268 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25269 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25270 #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25271 #define CGTS_CU13_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25272 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25273 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25274 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25275 #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25276 //CGTS_CU13_TD_TCP_CTRL_REG
25277 #define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25278 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25279 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25280 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25281 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25282 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25283 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25284 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25285 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25286 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25287 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25288 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25289 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25290 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25291 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25292 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25293 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25294 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25295 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25296 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25297 //CGTS_CU14_SP0_CTRL_REG
25298 #define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25299 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25300 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25301 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25302 #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25303 #define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25304 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25305 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25306 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25307 #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25308 #define CGTS_CU14_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25309 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25310 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25311 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25312 #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25313 #define CGTS_CU14_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25314 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25315 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25316 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25317 #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25318 //CGTS_CU14_LDS_SQ_CTRL_REG
25319 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25320 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25321 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25322 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25323 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25324 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25325 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25326 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25327 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25328 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25329 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25330 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25331 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25332 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25333 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25334 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25335 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25336 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25337 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25338 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25339 //CGTS_CU14_TA_SQC_CTRL_REG
25340 #define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25341 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25342 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25343 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25344 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25345 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25346 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25347 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25348 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25349 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25350 //CGTS_CU14_SP1_CTRL_REG
25351 #define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25352 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25353 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25354 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25355 #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25356 #define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25357 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25358 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25359 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25360 #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25361 #define CGTS_CU14_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25362 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25363 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25364 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25365 #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25366 #define CGTS_CU14_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25367 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25368 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25369 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25370 #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25371 //CGTS_CU14_TD_TCP_CTRL_REG
25372 #define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25373 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25374 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25375 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25376 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25377 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25378 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25379 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25380 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25381 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25382 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25383 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25384 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25385 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25386 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25387 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25388 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25389 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25390 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25391 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25392 //CGTS_CU15_SP0_CTRL_REG
25393 #define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25394 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25395 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25396 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25397 #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25398 #define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25399 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25400 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25401 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25402 #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25403 #define CGTS_CU15_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25404 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25405 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25406 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25407 #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25408 #define CGTS_CU15_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25409 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25410 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25411 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25412 #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25413 //CGTS_CU15_LDS_SQ_CTRL_REG
25414 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25415 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25416 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25417 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25418 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25419 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25420 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25421 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25422 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25423 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25424 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25425 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25426 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25427 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25428 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25429 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25430 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25431 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25432 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25433 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25434 //CGTS_CU15_TA_SQC_CTRL_REG
25435 #define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25436 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25437 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25438 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25439 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25440 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT                                                                 0x10
25441 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                        0x17
25442 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                   0x18
25443 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                     0x1a
25444 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
25445 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25446 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25447 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25448 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25449 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25450 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK                                                                   0x007F0000L
25451 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                          0x00800000L
25452 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                     0x03000000L
25453 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                       0x04000000L
25454 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
25455 //CGTS_CU15_SP1_CTRL_REG
25456 #define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25457 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25458 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25459 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25460 #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25461 #define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25462 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25463 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25464 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25465 #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25466 #define CGTS_CU15_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25467 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25468 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25469 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25470 #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25471 #define CGTS_CU15_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25472 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25473 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25474 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25475 #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25476 //CGTS_CU15_TD_TCP_CTRL_REG
25477 #define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25478 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25479 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25480 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25481 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25482 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25483 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25484 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25485 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25486 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25487 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25488 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25489 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25490 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25491 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25492 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25493 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25494 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25495 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25496 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25497 //CGTS_CU0_TCPI_CTRL_REG
25498 #define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25499 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25500 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25501 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25502 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25503 #define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25504 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25505 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25506 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25507 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25508 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25509 #define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25510 //CGTS_CU1_TCPI_CTRL_REG
25511 #define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25512 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25513 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25514 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25515 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25516 #define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25517 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25518 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25519 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25520 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25521 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25522 #define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25523 //CGTS_CU2_TCPI_CTRL_REG
25524 #define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25525 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25526 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25527 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25528 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25529 #define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25530 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25531 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25532 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25533 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25534 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25535 #define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25536 //CGTS_CU3_TCPI_CTRL_REG
25537 #define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25538 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25539 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25540 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25541 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25542 #define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25543 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25544 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25545 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25546 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25547 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25548 #define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25549 //CGTS_CU4_TCPI_CTRL_REG
25550 #define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25551 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25552 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25553 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25554 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25555 #define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25556 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25557 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25558 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25559 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25560 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25561 #define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25562 //CGTS_CU5_TCPI_CTRL_REG
25563 #define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25564 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25565 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25566 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25567 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25568 #define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25569 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25570 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25571 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25572 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25573 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25574 #define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25575 //CGTS_CU6_TCPI_CTRL_REG
25576 #define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25577 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25578 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25579 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25580 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25581 #define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25582 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25583 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25584 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25585 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25586 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25587 #define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25588 //CGTS_CU7_TCPI_CTRL_REG
25589 #define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25590 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25591 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25592 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25593 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25594 #define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25595 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25596 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25597 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25598 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25599 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25600 #define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25601 //CGTS_CU8_TCPI_CTRL_REG
25602 #define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25603 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25604 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25605 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25606 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25607 #define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25608 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25609 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25610 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25611 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25612 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25613 #define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25614 //CGTS_CU9_TCPI_CTRL_REG
25615 #define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25616 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25617 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25618 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25619 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25620 #define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25621 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25622 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25623 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25624 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25625 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25626 #define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25627 //CGTS_CU10_TCPI_CTRL_REG
25628 #define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25629 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25630 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25631 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25632 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25633 #define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25634 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25635 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25636 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25637 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25638 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25639 #define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25640 //CGTS_CU11_TCPI_CTRL_REG
25641 #define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25642 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25643 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25644 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25645 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25646 #define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25647 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25648 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25649 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25650 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25651 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25652 #define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25653 //CGTS_CU12_TCPI_CTRL_REG
25654 #define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25655 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25656 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25657 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25658 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25659 #define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25660 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25661 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25662 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25663 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25664 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25665 #define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25666 //CGTS_CU13_TCPI_CTRL_REG
25667 #define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25668 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25669 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25670 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25671 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25672 #define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25673 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25674 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25675 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25676 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25677 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25678 #define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25679 //CGTS_CU14_TCPI_CTRL_REG
25680 #define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25681 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25682 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25683 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25684 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25685 #define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25686 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25687 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25688 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25689 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25690 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25691 #define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25692 //CGTS_CU15_TCPI_CTRL_REG
25693 #define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25694 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25695 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25696 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25697 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25698 #define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25699 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25700 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25701 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25702 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25703 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25704 #define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25705 //CGTT_SPI_CLK_CTRL
25706 #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
25707 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
25708 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT                                                            0x12
25709 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT                                                            0x18
25710 #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT                                                         0x1a
25711 #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT                                                               0x1b
25712 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT                                                               0x1c
25713 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT                                                               0x1d
25714 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT                                                               0x1e
25715 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
25716 #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
25717 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
25718 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK                                                              0x00FC0000L
25719 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK                                                              0x01000000L
25720 #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK                                                           0x04000000L
25721 #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK                                                                 0x08000000L
25722 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK                                                                 0x10000000L
25723 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK                                                                 0x20000000L
25724 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK                                                                 0x40000000L
25725 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
25726 //CGTT_PC_CLK_CTRL
25727 #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
25728 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
25729 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT                                                             0x12
25730 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT                                                             0x18
25731 #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT                                                     0x19
25732 #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT                                                      0x1a
25733 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT                                                               0x1b
25734 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT                                                               0x1c
25735 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT                                                               0x1d
25736 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT                                                               0x1e
25737 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
25738 #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
25739 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
25740 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK                                                               0x00FC0000L
25741 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK                                                               0x01000000L
25742 #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK                                                       0x02000000L
25743 #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK                                                        0x04000000L
25744 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK                                                                 0x08000000L
25745 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK                                                                 0x10000000L
25746 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK                                                                 0x20000000L
25747 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK                                                                 0x40000000L
25748 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
25749 //CGTT_BCI_CLK_CTRL
25750 #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
25751 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
25752 #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT                                                                    0xc
25753 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
25754 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
25755 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
25756 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
25757 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
25758 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
25759 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
25760 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
25761 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT                                                              0x18
25762 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT                                                              0x19
25763 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT                                                              0x1a
25764 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT                                                              0x1b
25765 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT                                                              0x1c
25766 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT                                                              0x1d
25767 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT                                                              0x1e
25768 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
25769 #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
25770 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
25771 #define CGTT_BCI_CLK_CTRL__RESERVED_MASK                                                                      0x0000F000L
25772 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
25773 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
25774 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
25775 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
25776 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
25777 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
25778 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
25779 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
25780 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK                                                                0x01000000L
25781 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK                                                                0x02000000L
25782 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK                                                                0x04000000L
25783 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK                                                                0x08000000L
25784 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK                                                                0x10000000L
25785 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK                                                                0x20000000L
25786 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK                                                                0x40000000L
25787 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
25788 //CGTT_VGT_CLK_CTRL
25789 #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
25790 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
25791 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT                                                                 0xf
25792 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT                                                                  0x10
25793 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
25794 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
25795 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
25796 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
25797 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
25798 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
25799 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
25800 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT                                                              0x18
25801 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT                                                              0x19
25802 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x1a
25803 #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                            0x1b
25804 #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT                                                               0x1c
25805 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT                                                                 0x1d
25806 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                               0x1e
25807 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
25808 #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
25809 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
25810 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK                                                                   0x00008000L
25811 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK                                                                    0x00010000L
25812 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
25813 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
25814 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
25815 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
25816 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
25817 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
25818 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
25819 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK                                                                0x01000000L
25820 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK                                                                0x02000000L
25821 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x04000000L
25822 #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                              0x08000000L
25823 #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK                                                                 0x10000000L
25824 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK                                                                   0x20000000L
25825 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK                                                                 0x40000000L
25826 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
25827 //CGTT_IA_CLK_CTRL
25828 #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
25829 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
25830 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
25831 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
25832 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
25833 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
25834 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
25835 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
25836 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
25837 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
25838 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x18
25839 #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT                                                                  0x19
25840 #define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT                                                                   0x1a
25841 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                               0x1b
25842 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                               0x1c
25843 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                               0x1d
25844 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1e
25845 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
25846 #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
25847 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
25848 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
25849 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
25850 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
25851 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
25852 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
25853 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
25854 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
25855 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
25856 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x01000000L
25857 #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK                                                                    0x02000000L
25858 #define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK                                                                     0x04000000L
25859 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                 0x08000000L
25860 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                 0x10000000L
25861 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                 0x20000000L
25862 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x40000000L
25863 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
25864 //CGTT_WD_CLK_CTRL
25865 #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
25866 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
25867 #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT                                                                  0xf
25868 #define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT                                                                   0x10
25869 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
25870 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
25871 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
25872 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
25873 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
25874 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
25875 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
25876 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT                                                               0x19
25877 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x1a
25878 #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                             0x1b
25879 #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT                                                                0x1c
25880 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1d
25881 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT                                                          0x1e
25882 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
25883 #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
25884 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
25885 #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK                                                                    0x00008000L
25886 #define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK                                                                     0x00010000L
25887 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
25888 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
25889 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
25890 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
25891 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
25892 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
25893 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
25894 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK                                                                 0x02000000L
25895 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x04000000L
25896 #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                               0x08000000L
25897 #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK                                                                  0x10000000L
25898 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x20000000L
25899 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK                                                            0x40000000L
25900 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
25901 //CGTT_PA_CLK_CTRL
25902 #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
25903 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
25904 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
25905 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
25906 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
25907 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
25908 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
25909 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
25910 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
25911 #define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT                                                                 0x17
25912 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x18
25913 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                               0x19
25914 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                               0x1a
25915 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                               0x1b
25916 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                               0x1c
25917 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT                                                              0x1d
25918 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT                                                              0x1e
25919 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT                                                             0x1f
25920 #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
25921 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
25922 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
25923 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
25924 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
25925 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
25926 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
25927 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
25928 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
25929 #define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK                                                                   0x00800000L
25930 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x01000000L
25931 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                 0x02000000L
25932 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                 0x04000000L
25933 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                 0x08000000L
25934 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                 0x10000000L
25935 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK                                                                0x20000000L
25936 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK                                                                0x40000000L
25937 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK                                                               0x80000000L
25938 //CGTT_SC_CLK_CTRL0
25939 #define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT                                                                    0x0
25940 #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT                                                              0x4
25941 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT                                              0x10
25942 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x11
25943 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x12
25944 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x13
25945 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x14
25946 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x15
25947 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x16
25948 #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT                                                      0x17
25949 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT                                                    0x18
25950 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT                                                              0x19
25951 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT                                                              0x1a
25952 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT                                                              0x1b
25953 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT                                                              0x1c
25954 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT                                                              0x1d
25955 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT                                                              0x1e
25956 #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT                                                            0x1f
25957 #define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK                                                                      0x0000000FL
25958 #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
25959 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK                                                0x00010000L
25960 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK                                                          0x00020000L
25961 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK                                                          0x00040000L
25962 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK                                                          0x00080000L
25963 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK                                                          0x00100000L
25964 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK                                                          0x00200000L
25965 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK                                                          0x00400000L
25966 #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK                                                        0x00800000L
25967 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK                                                      0x01000000L
25968 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK                                                                0x02000000L
25969 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK                                                                0x04000000L
25970 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK                                                                0x08000000L
25971 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK                                                                0x10000000L
25972 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK                                                                0x20000000L
25973 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK                                                                0x40000000L
25974 #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK                                                              0x80000000L
25975 //CGTT_SC_CLK_CTRL1
25976 #define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT                                                                    0x0
25977 #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT                                                              0x4
25978 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT                                              0x11
25979 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT                                              0x12
25980 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT                                     0x13
25981 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT                                           0x14
25982 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT                                            0x15
25983 #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT                                                      0x16
25984 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT                                                    0x19
25985 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT                                                    0x1a
25986 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT                                           0x1b
25987 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT                                                 0x1c
25988 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT                                                  0x1d
25989 #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT                                                            0x1e
25990 #define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK                                                                      0x0000000FL
25991 #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
25992 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK                                                0x00020000L
25993 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK                                                0x00040000L
25994 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK                                       0x00080000L
25995 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK                                             0x00100000L
25996 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK                                              0x00200000L
25997 #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK                                                        0x00400000L
25998 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK                                                      0x02000000L
25999 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK                                                      0x04000000L
26000 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK                                             0x08000000L
26001 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK                                                   0x10000000L
26002 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK                                                    0x20000000L
26003 #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK                                                              0x40000000L
26004 //CGTT_SQ_CLK_CTRL
26005 #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
26006 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
26007 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
26008 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
26009 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
26010 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
26011 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
26012 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
26013 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
26014 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
26015 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT                                                             0x1d
26016 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1e
26017 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
26018 #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
26019 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
26020 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
26021 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
26022 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
26023 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
26024 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
26025 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
26026 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
26027 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
26028 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK                                                               0x20000000L
26029 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x40000000L
26030 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
26031 //CGTT_SQG_CLK_CTRL
26032 #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26033 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26034 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26035 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26036 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26037 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26038 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26039 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26040 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26041 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26042 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT                                                             0x1c
26043 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT                                                            0x1d
26044 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                               0x1e
26045 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
26046 #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26047 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26048 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26049 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26050 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26051 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26052 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26053 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26054 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26055 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26056 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK                                                               0x10000000L
26057 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK                                                              0x20000000L
26058 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK                                                                 0x40000000L
26059 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
26060 //SQ_ALU_CLK_CTRL
26061 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT                                                               0x0
26062 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT                                                               0x10
26063 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK                                                                 0x0000FFFFL
26064 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK                                                                 0xFFFF0000L
26065 //SQ_TEX_CLK_CTRL
26066 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT                                                               0x0
26067 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT                                                               0x10
26068 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK                                                                 0x0000FFFFL
26069 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK                                                                 0xFFFF0000L
26070 //SQ_LDS_CLK_CTRL
26071 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT                                                               0x0
26072 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT                                                               0x10
26073 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK                                                                 0x0000FFFFL
26074 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK                                                                 0xFFFF0000L
26075 //SQ_POWER_THROTTLE
26076 #define SQ_POWER_THROTTLE__MIN_POWER__SHIFT                                                                   0x0
26077 #define SQ_POWER_THROTTLE__MAX_POWER__SHIFT                                                                   0x10
26078 #define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT                                                                0x1e
26079 #define SQ_POWER_THROTTLE__MIN_POWER_MASK                                                                     0x00003FFFL
26080 #define SQ_POWER_THROTTLE__MAX_POWER_MASK                                                                     0x3FFF0000L
26081 #define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK                                                                  0xC0000000L
26082 //SQ_POWER_THROTTLE2
26083 #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT                                                            0x0
26084 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                   0x10
26085 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                   0x1b
26086 #define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT                                                              0x1f
26087 #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK                                                              0x00003FFFL
26088 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK                                                     0x03FF0000L
26089 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK                                                     0x78000000L
26090 #define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK                                                                0x80000000L
26091 //CGTT_SX_CLK_CTRL0
26092 #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT                                                                    0x0
26093 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT                                                              0x4
26094 #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT                                                                    0xc
26095 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26096 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26097 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26098 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26099 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26100 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26101 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26102 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26103 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT                                                              0x18
26104 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT                                                              0x19
26105 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26106 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26107 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26108 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26109 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26110 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26111 #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK                                                                      0x0000000FL
26112 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26113 #define CGTT_SX_CLK_CTRL0__RESERVED_MASK                                                                      0x0000F000L
26114 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26115 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26116 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26117 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26118 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26119 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26120 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26121 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26122 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK                                                                0x01000000L
26123 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26124 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26125 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26126 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26127 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26128 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26129 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26130 //CGTT_SX_CLK_CTRL1
26131 #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT                                                                    0x0
26132 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT                                                              0x4
26133 #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT                                                                    0xc
26134 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26135 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26136 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26137 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26138 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26139 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26140 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26141 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26142 #define CGTT_SX_CLK_CTRL1__DBG_EN__SHIFT                                                                      0x18
26143 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT                                                              0x19
26144 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26145 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26146 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26147 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26148 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26149 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26150 #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK                                                                      0x0000000FL
26151 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26152 #define CGTT_SX_CLK_CTRL1__RESERVED_MASK                                                                      0x0000F000L
26153 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26154 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26155 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26156 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26157 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26158 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26159 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26160 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26161 #define CGTT_SX_CLK_CTRL1__DBG_EN_MASK                                                                        0x01000000L
26162 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26163 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26164 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26165 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26166 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26167 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26168 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26169 //CGTT_SX_CLK_CTRL2
26170 #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT                                                                    0x0
26171 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT                                                              0x4
26172 #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT                                                                    0xd
26173 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26174 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26175 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26176 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26177 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26178 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26179 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26180 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26181 #define CGTT_SX_CLK_CTRL2__DBG_EN__SHIFT                                                                      0x18
26182 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT                                                              0x19
26183 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26184 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26185 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26186 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26187 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26188 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26189 #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK                                                                      0x0000000FL
26190 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26191 #define CGTT_SX_CLK_CTRL2__RESERVED_MASK                                                                      0x0000E000L
26192 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26193 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26194 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26195 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26196 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26197 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26198 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26199 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26200 #define CGTT_SX_CLK_CTRL2__DBG_EN_MASK                                                                        0x01000000L
26201 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26202 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26203 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26204 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26205 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26206 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26207 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26208 //CGTT_SX_CLK_CTRL3
26209 #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT                                                                    0x0
26210 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT                                                              0x4
26211 #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT                                                                    0xd
26212 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26213 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26214 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26215 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26216 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26217 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26218 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26219 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26220 #define CGTT_SX_CLK_CTRL3__DBG_EN__SHIFT                                                                      0x18
26221 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT                                                              0x19
26222 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26223 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26224 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26225 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26226 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26227 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26228 #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK                                                                      0x0000000FL
26229 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26230 #define CGTT_SX_CLK_CTRL3__RESERVED_MASK                                                                      0x0000E000L
26231 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26232 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26233 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26234 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26235 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26236 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26237 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26238 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26239 #define CGTT_SX_CLK_CTRL3__DBG_EN_MASK                                                                        0x01000000L
26240 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26241 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26242 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26243 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26244 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26245 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26246 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26247 //CGTT_SX_CLK_CTRL4
26248 #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT                                                                    0x0
26249 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT                                                              0x4
26250 #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT                                                                    0xc
26251 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26252 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26253 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26254 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26255 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26256 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26257 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26258 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26259 #define CGTT_SX_CLK_CTRL4__DBG_EN__SHIFT                                                                      0x18
26260 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT                                                              0x19
26261 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26262 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26263 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26264 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26265 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26266 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26267 #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK                                                                      0x0000000FL
26268 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26269 #define CGTT_SX_CLK_CTRL4__RESERVED_MASK                                                                      0x0000F000L
26270 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26271 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26272 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26273 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26274 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26275 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26276 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26277 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26278 #define CGTT_SX_CLK_CTRL4__DBG_EN_MASK                                                                        0x01000000L
26279 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26280 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26281 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26282 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26283 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26284 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26285 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26286 //TD_CGTT_CTRL
26287 #define TD_CGTT_CTRL__ON_DELAY__SHIFT                                                                         0x0
26288 #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT                                                                   0x4
26289 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                             0x10
26290 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                             0x11
26291 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                             0x12
26292 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                             0x13
26293 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                             0x14
26294 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                             0x15
26295 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                             0x16
26296 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                             0x17
26297 #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT                                                                   0x18
26298 #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT                                                                   0x19
26299 #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT                                                                   0x1a
26300 #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT                                                                   0x1b
26301 #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT                                                                   0x1c
26302 #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT                                                                   0x1d
26303 #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT                                                                   0x1e
26304 #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT                                                                   0x1f
26305 #define TD_CGTT_CTRL__ON_DELAY_MASK                                                                           0x0000000FL
26306 #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK                                                                     0x00000FF0L
26307 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                               0x00010000L
26308 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                               0x00020000L
26309 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                               0x00040000L
26310 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                               0x00080000L
26311 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                               0x00100000L
26312 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                               0x00200000L
26313 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                               0x00400000L
26314 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                               0x00800000L
26315 #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK                                                                     0x01000000L
26316 #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK                                                                     0x02000000L
26317 #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK                                                                     0x04000000L
26318 #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK                                                                     0x08000000L
26319 #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK                                                                     0x10000000L
26320 #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK                                                                     0x20000000L
26321 #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK                                                                     0x40000000L
26322 #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK                                                                     0x80000000L
26323 //TA_CGTT_CTRL
26324 #define TA_CGTT_CTRL__ON_DELAY__SHIFT                                                                         0x0
26325 #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT                                                                   0x4
26326 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                             0x10
26327 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                             0x11
26328 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                             0x12
26329 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                             0x13
26330 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                             0x14
26331 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                             0x15
26332 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                             0x16
26333 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                             0x17
26334 #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT                                                                   0x18
26335 #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT                                                                   0x19
26336 #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT                                                                   0x1a
26337 #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT                                                                   0x1b
26338 #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT                                                                   0x1c
26339 #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT                                                                   0x1d
26340 #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT                                                                   0x1e
26341 #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT                                                                   0x1f
26342 #define TA_CGTT_CTRL__ON_DELAY_MASK                                                                           0x0000000FL
26343 #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK                                                                     0x00000FF0L
26344 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                               0x00010000L
26345 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                               0x00020000L
26346 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                               0x00040000L
26347 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                               0x00080000L
26348 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                               0x00100000L
26349 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                               0x00200000L
26350 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                               0x00400000L
26351 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                               0x00800000L
26352 #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK                                                                     0x01000000L
26353 #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK                                                                     0x02000000L
26354 #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK                                                                     0x04000000L
26355 #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK                                                                     0x08000000L
26356 #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK                                                                     0x10000000L
26357 #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK                                                                     0x20000000L
26358 #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK                                                                     0x40000000L
26359 #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK                                                                     0x80000000L
26360 //CGTT_TCPI_CLK_CTRL
26361 #define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26362 #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26363 #define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT                                                                      0xc
26364 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26365 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26366 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26367 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26368 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26369 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26370 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26371 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26372 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
26373 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26374 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26375 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26376 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26377 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26378 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26379 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26380 #define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26381 #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26382 #define CGTT_TCPI_CLK_CTRL__SPARE_MASK                                                                        0x0000F000L
26383 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26384 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26385 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26386 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26387 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26388 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26389 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26390 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26391 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26392 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26393 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26394 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26395 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26396 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26397 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26398 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26399 //CGTT_TCI_CLK_CTRL
26400 #define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26401 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26402 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26403 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26404 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26405 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26406 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26407 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26408 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26409 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26410 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
26411 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
26412 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26413 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26414 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26415 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26416 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26417 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26418 #define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26419 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26420 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26421 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26422 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26423 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26424 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26425 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26426 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26427 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26428 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
26429 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26430 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26431 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26432 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26433 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26434 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26435 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26436 //CGTT_GDS_CLK_CTRL
26437 #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26438 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26439 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26440 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26441 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26442 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26443 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26444 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26445 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26446 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26447 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
26448 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
26449 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26450 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26451 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26452 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26453 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26454 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26455 #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26456 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26457 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26458 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26459 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26460 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26461 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26462 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26463 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26464 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26465 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
26466 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26467 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26468 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26469 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26470 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26471 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26472 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26473 //DB_CGTT_CLK_CTRL_0
26474 #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT                                                                   0x0
26475 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT                                                             0x4
26476 #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT                                                                   0xc
26477 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26478 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26479 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26480 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26481 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26482 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26483 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26484 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26485 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT                                                             0x18
26486 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT                                                             0x19
26487 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26488 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26489 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26490 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26491 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26492 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26493 #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK                                                                     0x0000000FL
26494 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26495 #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK                                                                     0x0000F000L
26496 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26497 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26498 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26499 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26500 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26501 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26502 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26503 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26504 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26505 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26506 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26507 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26508 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26509 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26510 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26511 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26512 //CB_CGTT_SCLK_CTRL
26513 #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26514 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26515 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26516 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26517 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26518 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26519 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26520 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26521 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26522 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26523 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
26524 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
26525 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26526 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26527 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26528 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26529 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26530 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26531 #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26532 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26533 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26534 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26535 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26536 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26537 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26538 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26539 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26540 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26541 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
26542 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26543 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26544 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26545 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26546 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26547 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26548 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26549 //TCC_CGTT_SCLK_CTRL
26550 #define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26551 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26552 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26553 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26554 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26555 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26556 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26557 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26558 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26559 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26560 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
26561 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26562 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26563 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26564 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26565 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26566 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26567 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26568 #define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26569 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26570 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26571 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26572 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26573 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26574 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26575 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26576 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26577 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26578 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26579 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26580 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26581 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26582 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26583 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26584 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26585 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26586 //TCA_CGTT_SCLK_CTRL
26587 #define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26588 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26589 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26590 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26591 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26592 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26593 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26594 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26595 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26596 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26597 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
26598 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26599 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26600 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26601 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26602 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26603 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26604 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26605 #define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26606 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26607 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26608 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26609 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26610 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26611 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26612 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26613 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26614 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26615 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26616 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26617 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26618 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26619 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26620 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26621 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26622 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26623 //CGTT_CP_CLK_CTRL
26624 #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
26625 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
26626 #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                                0xf
26627 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
26628 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
26629 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
26630 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
26631 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
26632 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
26633 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
26634 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
26635 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                        0x1d
26636 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                            0x1e
26637 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                            0x1f
26638 #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
26639 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
26640 #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                  0x00008000L
26641 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
26642 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
26643 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
26644 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
26645 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
26646 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
26647 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
26648 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
26649 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                          0x20000000L
26650 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                              0x40000000L
26651 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                              0x80000000L
26652 //CGTT_CPF_CLK_CTRL
26653 #define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26654 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26655 #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                               0xf
26656 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26657 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26658 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26659 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26660 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26661 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26662 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26663 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26664 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                       0x1d
26665 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
26666 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
26667 #define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26668 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26669 #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                 0x00008000L
26670 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26671 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26672 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26673 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26674 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26675 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26676 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26677 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26678 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                         0x20000000L
26679 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
26680 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
26681 //CGTT_CPC_CLK_CTRL
26682 #define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26683 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26684 #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                               0xf
26685 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26686 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26687 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26688 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26689 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26690 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26691 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26692 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26693 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                       0x1d
26694 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
26695 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
26696 #define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26697 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26698 #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                 0x00008000L
26699 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26700 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26701 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26702 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26703 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26704 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26705 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26706 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26707 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                         0x20000000L
26708 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
26709 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
26710 //CGTT_RLC_CLK_CTRL
26711 #define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26712 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26713 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26714 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26715 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26716 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26717 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26718 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26719 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26720 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26721 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
26722 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
26723 #define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26724 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26725 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26726 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26727 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26728 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26729 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26730 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26731 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26732 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26733 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
26734 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
26735 //RLC_GFX_RM_CNTL
26736 #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT                                                              0x0
26737 #define RLC_GFX_RM_CNTL__RESERVED__SHIFT                                                                      0x1
26738 #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK                                                                0x00000001L
26739 #define RLC_GFX_RM_CNTL__RESERVED_MASK                                                                        0xFFFFFFFEL
26740 //RMI_CGTT_SCLK_CTRL
26741 #define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26742 #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26743 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26744 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26745 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26746 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26747 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26748 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26749 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26750 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26751 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26752 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26753 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26754 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26755 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26756 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26757 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26758 #define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26759 #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26760 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26761 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26762 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26763 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26764 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26765 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26766 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26767 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26768 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26769 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26770 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26771 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26772 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26773 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26774 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26775 //CGTT_TCPF_CLK_CTRL
26776 #define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26777 #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26778 #define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT                                                                      0xc
26779 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26780 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26781 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26782 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26783 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26784 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26785 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26786 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26787 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
26788 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26789 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26790 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26791 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26792 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26793 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26794 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26795 #define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26796 #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26797 #define CGTT_TCPF_CLK_CTRL__SPARE_MASK                                                                        0x0000F000L
26798 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26799 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26800 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26801 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26802 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26803 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26804 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26805 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26806 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26807 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26808 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26809 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26810 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26811 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26812 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26813 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26814 
26815 
26816 // addressBlock: gc_ea_pwrdec
26817 //GCEA_CGTT_CLK_CTRL
26818 #define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26819 #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26820 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                        0x16
26821 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                       0x1e
26822 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                     0x1f
26823 #define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26824 #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26825 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                          0x00400000L
26826 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                         0x40000000L
26827 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                       0x80000000L
26828 
26829 
26830 // addressBlock: gc_utcl2_vmsharedhvdec
26831 //MC_VM_FB_SIZE_OFFSET_VF0
26832 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                                           0x0
26833 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                                         0x10
26834 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26835 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26836 //MC_VM_FB_SIZE_OFFSET_VF1
26837 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                                           0x0
26838 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                                         0x10
26839 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26840 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26841 //MC_VM_FB_SIZE_OFFSET_VF2
26842 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                                           0x0
26843 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                                         0x10
26844 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26845 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26846 //MC_VM_FB_SIZE_OFFSET_VF3
26847 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                                           0x0
26848 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                                         0x10
26849 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26850 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26851 //MC_VM_FB_SIZE_OFFSET_VF4
26852 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                                           0x0
26853 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                                         0x10
26854 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26855 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26856 //MC_VM_FB_SIZE_OFFSET_VF5
26857 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                                           0x0
26858 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                                         0x10
26859 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26860 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26861 //MC_VM_FB_SIZE_OFFSET_VF6
26862 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                                           0x0
26863 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                                         0x10
26864 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26865 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26866 //MC_VM_FB_SIZE_OFFSET_VF7
26867 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                                           0x0
26868 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                                         0x10
26869 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26870 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26871 //MC_VM_FB_SIZE_OFFSET_VF8
26872 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                                           0x0
26873 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                                         0x10
26874 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26875 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26876 //MC_VM_FB_SIZE_OFFSET_VF9
26877 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                                           0x0
26878 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                                         0x10
26879 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26880 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26881 //MC_VM_FB_SIZE_OFFSET_VF10
26882 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                                          0x0
26883 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                                        0x10
26884 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26885 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26886 //MC_VM_FB_SIZE_OFFSET_VF11
26887 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                                          0x0
26888 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                                        0x10
26889 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26890 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26891 //MC_VM_FB_SIZE_OFFSET_VF12
26892 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                                          0x0
26893 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                                        0x10
26894 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26895 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26896 //MC_VM_FB_SIZE_OFFSET_VF13
26897 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                                          0x0
26898 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                                        0x10
26899 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26900 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26901 //MC_VM_FB_SIZE_OFFSET_VF14
26902 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                                          0x0
26903 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                                        0x10
26904 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26905 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26906 //MC_VM_FB_SIZE_OFFSET_VF15
26907 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                                          0x0
26908 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                                        0x10
26909 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26910 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26911 //VM_IOMMU_MMIO_CNTRL_1
26912 #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                                 0x8
26913 #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                                   0x00000100L
26914 //MC_VM_MARC_BASE_LO_0
26915 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                                           0xc
26916 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                             0xFFFFF000L
26917 //MC_VM_MARC_BASE_LO_1
26918 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                                           0xc
26919 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                             0xFFFFF000L
26920 //MC_VM_MARC_BASE_LO_2
26921 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                                           0xc
26922 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                             0xFFFFF000L
26923 //MC_VM_MARC_BASE_LO_3
26924 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                                           0xc
26925 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                             0xFFFFF000L
26926 //MC_VM_MARC_BASE_HI_0
26927 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                                           0x0
26928 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                             0x000FFFFFL
26929 //MC_VM_MARC_BASE_HI_1
26930 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                                           0x0
26931 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                             0x000FFFFFL
26932 //MC_VM_MARC_BASE_HI_2
26933 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                                           0x0
26934 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                             0x000FFFFFL
26935 //MC_VM_MARC_BASE_HI_3
26936 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                                           0x0
26937 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                             0x000FFFFFL
26938 //MC_VM_MARC_RELOC_LO_0
26939 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                                           0x0
26940 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                                         0x1
26941 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                                         0xc
26942 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                             0x00000001L
26943 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                                           0x00000002L
26944 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                                           0xFFFFF000L
26945 //MC_VM_MARC_RELOC_LO_1
26946 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                                           0x0
26947 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                                         0x1
26948 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                                         0xc
26949 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                             0x00000001L
26950 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                                           0x00000002L
26951 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                                           0xFFFFF000L
26952 //MC_VM_MARC_RELOC_LO_2
26953 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                                           0x0
26954 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                                         0x1
26955 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                                         0xc
26956 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                             0x00000001L
26957 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                                           0x00000002L
26958 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                                           0xFFFFF000L
26959 //MC_VM_MARC_RELOC_LO_3
26960 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                                           0x0
26961 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                                         0x1
26962 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                                         0xc
26963 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                             0x00000001L
26964 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                                           0x00000002L
26965 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                                           0xFFFFF000L
26966 //MC_VM_MARC_RELOC_HI_0
26967 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                                         0x0
26968 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                                           0x000FFFFFL
26969 //MC_VM_MARC_RELOC_HI_1
26970 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                                         0x0
26971 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                                           0x000FFFFFL
26972 //MC_VM_MARC_RELOC_HI_2
26973 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                                         0x0
26974 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                                           0x000FFFFFL
26975 //MC_VM_MARC_RELOC_HI_3
26976 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                                         0x0
26977 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                                           0x000FFFFFL
26978 //MC_VM_MARC_LEN_LO_0
26979 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                             0xc
26980 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                               0xFFFFF000L
26981 //MC_VM_MARC_LEN_LO_1
26982 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                             0xc
26983 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                               0xFFFFF000L
26984 //MC_VM_MARC_LEN_LO_2
26985 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                             0xc
26986 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                               0xFFFFF000L
26987 //MC_VM_MARC_LEN_LO_3
26988 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                             0xc
26989 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                               0xFFFFF000L
26990 //MC_VM_MARC_LEN_HI_0
26991 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                             0x0
26992 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                               0x000FFFFFL
26993 //MC_VM_MARC_LEN_HI_1
26994 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                             0x0
26995 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                               0x000FFFFFL
26996 //MC_VM_MARC_LEN_HI_2
26997 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                             0x0
26998 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                               0x000FFFFFL
26999 //MC_VM_MARC_LEN_HI_3
27000 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                             0x0
27001 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                               0x000FFFFFL
27002 //VM_IOMMU_CONTROL_REGISTER
27003 #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                             0x0
27004 #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                               0x00000001L
27005 //VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
27006 #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                                  0xd
27007 #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                                    0x00002000L
27008 //VM_PCIE_ATS_CNTL
27009 #define VM_PCIE_ATS_CNTL__STU__SHIFT                                                                          0x10
27010 #define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                                   0x1f
27011 #define VM_PCIE_ATS_CNTL__STU_MASK                                                                            0x001F0000L
27012 #define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                                     0x80000000L
27013 //VM_PCIE_ATS_CNTL_VF_0
27014 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                              0x1f
27015 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                                0x80000000L
27016 //VM_PCIE_ATS_CNTL_VF_1
27017 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                              0x1f
27018 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                                0x80000000L
27019 //VM_PCIE_ATS_CNTL_VF_2
27020 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                              0x1f
27021 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                                0x80000000L
27022 //VM_PCIE_ATS_CNTL_VF_3
27023 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                              0x1f
27024 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                                0x80000000L
27025 //VM_PCIE_ATS_CNTL_VF_4
27026 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                              0x1f
27027 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                                0x80000000L
27028 //VM_PCIE_ATS_CNTL_VF_5
27029 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                              0x1f
27030 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                                0x80000000L
27031 //VM_PCIE_ATS_CNTL_VF_6
27032 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                              0x1f
27033 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                                0x80000000L
27034 //VM_PCIE_ATS_CNTL_VF_7
27035 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                              0x1f
27036 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                                0x80000000L
27037 //VM_PCIE_ATS_CNTL_VF_8
27038 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                              0x1f
27039 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                                0x80000000L
27040 //VM_PCIE_ATS_CNTL_VF_9
27041 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                              0x1f
27042 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                                0x80000000L
27043 //VM_PCIE_ATS_CNTL_VF_10
27044 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                             0x1f
27045 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                               0x80000000L
27046 //VM_PCIE_ATS_CNTL_VF_11
27047 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                             0x1f
27048 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                               0x80000000L
27049 //VM_PCIE_ATS_CNTL_VF_12
27050 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                             0x1f
27051 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                               0x80000000L
27052 //VM_PCIE_ATS_CNTL_VF_13
27053 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                             0x1f
27054 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                               0x80000000L
27055 //VM_PCIE_ATS_CNTL_VF_14
27056 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                             0x1f
27057 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                               0x80000000L
27058 //VM_PCIE_ATS_CNTL_VF_15
27059 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                             0x1f
27060 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                               0x80000000L
27061 //UTCL2_CGTT_CLK_CTRL
27062 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
27063 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
27064 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                                       0xc
27065 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                             0xf
27066 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                       0x10
27067 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                             0x18
27068 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
27069 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
27070 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                                         0x00007000L
27071 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                               0x00008000L
27072 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                         0x00FF0000L
27073 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                               0xFF000000L
27074 
27075 
27076 // addressBlock: gc_hypdec
27077 //CP_HYP_PFP_UCODE_ADDR
27078 #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
27079 #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x00003FFFL
27080 //CP_PFP_UCODE_ADDR
27081 #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                  0x0
27082 #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                                                                    0x00003FFFL
27083 //CP_HYP_PFP_UCODE_DATA
27084 #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
27085 #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
27086 //CP_PFP_UCODE_DATA
27087 #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT                                                                  0x0
27088 #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                                                                    0xFFFFFFFFL
27089 //CP_HYP_ME_UCODE_ADDR
27090 #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT                                                               0x0
27091 #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK                                                                 0x00001FFFL
27092 //CP_ME_RAM_RADDR
27093 #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT                                                                  0x0
27094 #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                                                                    0x00001FFFL
27095 //CP_ME_RAM_WADDR
27096 #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT                                                                  0x0
27097 #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                                                                    0x00001FFFL
27098 //CP_HYP_ME_UCODE_DATA
27099 #define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT                                                               0x0
27100 #define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK                                                                 0xFFFFFFFFL
27101 //CP_ME_RAM_DATA
27102 #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                                                                    0x0
27103 #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                                                                      0xFFFFFFFFL
27104 //CP_CE_UCODE_ADDR
27105 #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                   0x0
27106 #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK                                                                     0x00000FFFL
27107 //CP_HYP_CE_UCODE_ADDR
27108 #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                               0x0
27109 #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK                                                                 0x00000FFFL
27110 //CP_CE_UCODE_DATA
27111 #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT                                                                   0x0
27112 #define CP_CE_UCODE_DATA__UCODE_DATA_MASK                                                                     0xFFFFFFFFL
27113 //CP_HYP_CE_UCODE_DATA
27114 #define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT                                                               0x0
27115 #define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK                                                                 0xFFFFFFFFL
27116 //CP_HYP_MEC1_UCODE_ADDR
27117 #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
27118 #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x0001FFFFL
27119 //CP_MEC_ME1_UCODE_ADDR
27120 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
27121 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x0001FFFFL
27122 //CP_HYP_MEC1_UCODE_DATA
27123 #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
27124 #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
27125 //CP_MEC_ME1_UCODE_DATA
27126 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
27127 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
27128 //CP_HYP_MEC2_UCODE_ADDR
27129 #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
27130 #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x0001FFFFL
27131 //CP_MEC_ME2_UCODE_ADDR
27132 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
27133 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x0001FFFFL
27134 //CP_HYP_MEC2_UCODE_DATA
27135 #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
27136 #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
27137 //CP_MEC_ME2_UCODE_DATA
27138 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
27139 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
27140 //RLC_GPM_UCODE_ADDR
27141 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                 0x0
27142 #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT                                                                   0xe
27143 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK                                                                   0x00003FFFL
27144 #define RLC_GPM_UCODE_ADDR__RESERVED_MASK                                                                     0xFFFFC000L
27145 //RLC_GPM_UCODE_DATA
27146 #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT                                                                 0x0
27147 #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK                                                                   0xFFFFFFFFL
27148 //GRBM_GFX_INDEX_SR_SELECT
27149 #define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT                                                                0x0
27150 #define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK                                                                  0x00000007L
27151 //GRBM_GFX_INDEX_SR_DATA
27152 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT                                                         0x0
27153 #define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT                                                               0x8
27154 #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT                                                               0x10
27155 #define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT                                                    0x1d
27156 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT                                              0x1e
27157 #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT                                                    0x1f
27158 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK                                                           0x000000FFL
27159 #define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK                                                                 0x0000FF00L
27160 #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK                                                                 0x00FF0000L
27161 #define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK                                                      0x20000000L
27162 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK                                                0x40000000L
27163 #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK                                                      0x80000000L
27164 //GRBM_GFX_CNTL_SR_SELECT
27165 #define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT                                                                 0x0
27166 #define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK                                                                   0x00000007L
27167 //GRBM_GFX_CNTL_SR_DATA
27168 #define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT                                                                  0x0
27169 #define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT                                                                    0x2
27170 #define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT                                                                    0x4
27171 #define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT                                                                 0x8
27172 #define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK                                                                    0x00000003L
27173 #define GRBM_GFX_CNTL_SR_DATA__MEID_MASK                                                                      0x0000000CL
27174 #define GRBM_GFX_CNTL_SR_DATA__VMID_MASK                                                                      0x000000F0L
27175 #define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK                                                                   0x00000700L
27176 //GRBM_CAM_INDEX
27177 #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT                                                                      0x0
27178 #define GRBM_CAM_INDEX__CAM_INDEX_MASK                                                                        0x00000007L
27179 //GRBM_HYP_CAM_INDEX
27180 #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT                                                                  0x0
27181 #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK                                                                    0x00000007L
27182 //GRBM_CAM_DATA
27183 #define GRBM_CAM_DATA__CAM_ADDR__SHIFT                                                                        0x0
27184 #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT                                                                   0x10
27185 #define GRBM_CAM_DATA__CAM_ADDR_MASK                                                                          0x0000FFFFL
27186 #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK                                                                     0xFFFF0000L
27187 //GRBM_HYP_CAM_DATA
27188 #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT                                                                    0x0
27189 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT                                                               0x10
27190 #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK                                                                      0x0000FFFFL
27191 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK                                                                 0xFFFF0000L
27192 //RLC_GPU_IOV_VF_ENABLE
27193 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT                                                               0x0
27194 #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT                                                                0x1
27195 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT                                                                  0x10
27196 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK                                                                 0x00000001L
27197 #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK                                                                  0x0000FFFEL
27198 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK                                                                    0xFFFF0000L
27199 //RLC_GPU_IOV_CFG_REG6
27200 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT                                                               0x0
27201 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT                                                           0x7
27202 #define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT                                                                 0x8
27203 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT                                                             0xa
27204 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK                                                                 0x0000007FL
27205 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK                                                             0x00000080L
27206 #define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK                                                                   0x00000300L
27207 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK                                                               0xFFFFFC00L
27208 //RLC_GPU_IOV_CFG_REG8
27209 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT                                                           0x0
27210 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK                                                             0xFFFFFFFFL
27211 //RLC_RLCV_TIMER_INT_0
27212 #define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT                                                                    0x0
27213 #define RLC_RLCV_TIMER_INT_0__TIMER_MASK                                                                      0xFFFFFFFFL
27214 //RLC_RLCV_TIMER_CTRL
27215 #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                0x0
27216 #define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT                                                                  0x1
27217 #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK                                                                  0x00000001L
27218 #define RLC_RLCV_TIMER_CTRL__RESERVED_MASK                                                                    0xFFFFFFFEL
27219 //RLC_RLCV_TIMER_STAT
27220 #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT                                                              0x0
27221 #define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT                                                                  0x1
27222 #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK                                                                0x00000001L
27223 #define RLC_RLCV_TIMER_STAT__RESERVED_MASK                                                                    0xFFFFFFFEL
27224 //RLC_GPU_IOV_VF_DOORBELL_STATUS
27225 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT                                             0x0
27226 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT                                                       0x10
27227 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT                                             0x1f
27228 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK                                               0x0000FFFFL
27229 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK                                                         0x7FFF0000L
27230 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK                                               0x80000000L
27231 //RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
27232 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT                                     0x0
27233 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT                                                   0x10
27234 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT                                     0x1f
27235 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK                                       0x0000FFFFL
27236 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK                                                     0x7FFF0000L
27237 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK                                       0x80000000L
27238 //RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
27239 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT                                     0x0
27240 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT                                                   0x10
27241 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT                                     0x1f
27242 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK                                       0x0000FFFFL
27243 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK                                                     0x7FFF0000L
27244 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK                                       0x80000000L
27245 //RLC_GPU_IOV_VF_MASK
27246 #define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT                                                                   0x0
27247 #define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT                                                                  0x10
27248 #define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK                                                                     0x0000FFFFL
27249 #define RLC_GPU_IOV_VF_MASK__RESERVED_MASK                                                                    0xFFFF0000L
27250 //RLC_HYP_SEMAPHORE_2
27251 #define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT                                                                 0x0
27252 #define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT                                                                  0x5
27253 #define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK                                                                   0x0000001FL
27254 #define RLC_HYP_SEMAPHORE_2__RESERVED_MASK                                                                    0xFFFFFFE0L
27255 //RLC_HYP_SEMAPHORE_3
27256 #define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT                                                                 0x0
27257 #define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT                                                                  0x5
27258 #define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK                                                                   0x0000001FL
27259 #define RLC_HYP_SEMAPHORE_3__RESERVED_MASK                                                                    0xFFFFFFE0L
27260 //RLC_CLK_CNTL
27261 #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT                                                                 0x0
27262 #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT                                                                 0x1
27263 #define RLC_CLK_CNTL__RESERVED__SHIFT                                                                         0x2
27264 #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK                                                                   0x00000001L
27265 #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK                                                                   0x00000002L
27266 #define RLC_CLK_CNTL__RESERVED_MASK                                                                           0xFFFFFFFCL
27267 //RLC_GPU_IOV_SCH_BLOCK
27268 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT                                                            0x0
27269 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT                                                           0x4
27270 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT                                                          0x8
27271 #define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT                                                                0x10
27272 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK                                                              0x0000000FL
27273 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK                                                             0x000000F0L
27274 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK                                                            0x00007F00L
27275 #define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK                                                                  0x7FFF0000L
27276 //RLC_GPU_IOV_CFG_REG1
27277 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT                                                                 0x0
27278 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT                                                              0x4
27279 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT                                                      0x5
27280 #define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT                                                                 0x6
27281 #define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT                                                                   0x8
27282 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT                                                              0x10
27283 #define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT                                                                0x18
27284 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK                                                                   0x0000000FL
27285 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK                                                                0x00000010L
27286 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK                                                        0x00000020L
27287 #define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK                                                                   0x000000C0L
27288 #define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK                                                                     0x0000FF00L
27289 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK                                                                0x00FF0000L
27290 #define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK                                                                  0xFF000000L
27291 //RLC_GPU_IOV_CFG_REG2
27292 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT                                                               0x0
27293 #define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT                                                                 0x4
27294 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK                                                                 0x0000000FL
27295 #define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK                                                                   0xFFFFFFF0L
27296 //RLC_GPU_IOV_VM_BUSY_STATUS
27297 #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                     0x0
27298 #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                       0xFFFFFFFFL
27299 //RLC_GPU_IOV_SCH_0
27300 #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT                                                            0x0
27301 #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK                                                              0xFFFFFFFFL
27302 //RLC_GPU_IOV_ACTIVE_FCN_ID
27303 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT                                                               0x0
27304 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT                                                            0x4
27305 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT                                                               0x1f
27306 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK                                                                 0x0000000FL
27307 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK                                                              0x7FFFFFF0L
27308 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK                                                                 0x80000000L
27309 //RLC_GPU_IOV_SCH_3
27310 #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT                                                             0x0
27311 #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK                                                               0xFFFFFFFFL
27312 //RLC_GPU_IOV_SCH_1
27313 #define RLC_GPU_IOV_SCH_1__DATA__SHIFT                                                                        0x0
27314 #define RLC_GPU_IOV_SCH_1__DATA_MASK                                                                          0xFFFFFFFFL
27315 //RLC_GPU_IOV_SCH_2
27316 #define RLC_GPU_IOV_SCH_2__DATA__SHIFT                                                                        0x0
27317 #define RLC_GPU_IOV_SCH_2__DATA_MASK                                                                          0xFFFFFFFFL
27318 //RLC_GPU_IOV_UCODE_ADDR
27319 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
27320 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT                                                               0xc
27321 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x00000FFFL
27322 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK                                                                 0xFFFFF000L
27323 //RLC_GPU_IOV_UCODE_DATA
27324 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
27325 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
27326 //RLC_GPU_IOV_SCRATCH_ADDR
27327 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT                                                                 0x0
27328 #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT                                                             0x9
27329 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK                                                                   0x000001FFL
27330 #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK                                                               0xFFFFFE00L
27331 //RLC_GPU_IOV_SCRATCH_DATA
27332 #define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT                                                                 0x0
27333 #define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK                                                                   0xFFFFFFFFL
27334 //RLC_GPU_IOV_F32_CNTL
27335 #define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT                                                                   0x0
27336 #define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT                                                                 0x1
27337 #define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK                                                                     0x00000001L
27338 #define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK                                                                   0xFFFFFFFEL
27339 //RLC_GPU_IOV_F32_RESET
27340 #define RLC_GPU_IOV_F32_RESET__RESET__SHIFT                                                                   0x0
27341 #define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT                                                                0x1
27342 #define RLC_GPU_IOV_F32_RESET__RESET_MASK                                                                     0x00000001L
27343 #define RLC_GPU_IOV_F32_RESET__RESERVED_MASK                                                                  0xFFFFFFFEL
27344 //RLC_GPU_IOV_SDMA0_STATUS
27345 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT                                                            0x0
27346 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT                                                             0x1
27347 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT                                                                0x8
27348 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT                                                            0x9
27349 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT                                                             0xc
27350 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT                                                            0xd
27351 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK                                                              0x00000001L
27352 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK                                                               0x000000FEL
27353 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK                                                                  0x00000100L
27354 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK                                                              0x00000E00L
27355 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK                                                               0x00001000L
27356 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
27357 //RLC_GPU_IOV_SDMA1_STATUS
27358 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT                                                            0x0
27359 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT                                                             0x1
27360 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT                                                                0x8
27361 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT                                                            0x9
27362 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT                                                             0xc
27363 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT                                                            0xd
27364 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK                                                              0x00000001L
27365 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK                                                               0x000000FEL
27366 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK                                                                  0x00000100L
27367 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK                                                              0x00000E00L
27368 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK                                                               0x00001000L
27369 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
27370 //RLC_GPU_IOV_SMU_RESPONSE
27371 #define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT                                                                 0x0
27372 #define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
27373 //RLC_GPU_IOV_VIRT_RESET_REQ
27374 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT                                                             0x0
27375 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT                                                           0x10
27376 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT                                                        0x1f
27377 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK                                                               0x0000FFFFL
27378 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK                                                             0x7FFF0000L
27379 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK                                                          0x80000000L
27380 //RLC_GPU_IOV_RLC_RESPONSE
27381 #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT                                                                 0x0
27382 #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
27383 //RLC_GPU_IOV_INT_DISABLE
27384 #define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT                                                               0x0
27385 #define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK                                                                 0xFFFFFFFFL
27386 //RLC_GPU_IOV_INT_FORCE
27387 #define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT                                                                   0x0
27388 #define RLC_GPU_IOV_INT_FORCE__FORCE_MASK                                                                     0xFFFFFFFFL
27389 //RLC_GPU_IOV_SDMA0_BUSY_STATUS
27390 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
27391 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
27392 //RLC_GPU_IOV_SDMA1_BUSY_STATUS
27393 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
27394 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
27395 
27396 
27397 // addressBlock: gccacind
27398 //GC_CAC_CNTL
27399 #define GC_CAC_CNTL__CAC_ENABLE__SHIFT                                                                        0x0
27400 #define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT                                                                     0x1
27401 #define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT                                                                      0x11
27402 #define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT                                                                     0x17
27403 #define GC_CAC_CNTL__UNUSED_0__SHIFT                                                                          0x1f
27404 #define GC_CAC_CNTL__CAC_ENABLE_MASK                                                                          0x00000001L
27405 #define GC_CAC_CNTL__CAC_THRESHOLD_MASK                                                                       0x0001FFFEL
27406 #define GC_CAC_CNTL__CAC_BLOCK_ID_MASK                                                                        0x007E0000L
27407 #define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK                                                                       0x7F800000L
27408 #define GC_CAC_CNTL__UNUSED_0_MASK                                                                            0x80000000L
27409 //GC_CAC_OVR_SEL
27410 #define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT                                                                    0x0
27411 #define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK                                                                      0xFFFFFFFFL
27412 //GC_CAC_OVR_VAL
27413 #define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT                                                                    0x0
27414 #define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK                                                                      0xFFFFFFFFL
27415 //GC_CAC_WEIGHT_BCI_0
27416 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT                                                           0x0
27417 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT                                                           0x10
27418 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK                                                             0x0000FFFFL
27419 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK                                                             0xFFFF0000L
27420 //GC_CAC_WEIGHT_CB_0
27421 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT                                                             0x0
27422 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT                                                             0x10
27423 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK                                                               0x0000FFFFL
27424 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK                                                               0xFFFF0000L
27425 //GC_CAC_WEIGHT_CB_1
27426 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT                                                             0x0
27427 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT                                                             0x10
27428 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK                                                               0x0000FFFFL
27429 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK                                                               0xFFFF0000L
27430 //GC_CAC_WEIGHT_CBR_0
27431 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0__SHIFT                                                           0x0
27432 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1__SHIFT                                                           0x10
27433 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0_MASK                                                             0x0000FFFFL
27434 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1_MASK                                                             0xFFFF0000L
27435 //GC_CAC_WEIGHT_CBR_1
27436 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2__SHIFT                                                           0x0
27437 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3__SHIFT                                                           0x10
27438 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2_MASK                                                             0x0000FFFFL
27439 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3_MASK                                                             0xFFFF0000L
27440 //GC_CAC_WEIGHT_CP_0
27441 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT                                                             0x0
27442 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT                                                             0x10
27443 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK                                                               0x0000FFFFL
27444 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK                                                               0xFFFF0000L
27445 //GC_CAC_WEIGHT_CP_1
27446 #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT                                                             0x0
27447 #define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT                                                                   0x10
27448 #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK                                                               0x0000FFFFL
27449 #define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK                                                                     0xFFFF0000L
27450 //GC_CAC_WEIGHT_DB_0
27451 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT                                                             0x0
27452 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT                                                             0x10
27453 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK                                                               0x0000FFFFL
27454 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK                                                               0xFFFF0000L
27455 //GC_CAC_WEIGHT_DB_1
27456 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT                                                             0x0
27457 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT                                                             0x10
27458 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK                                                               0x0000FFFFL
27459 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK                                                               0xFFFF0000L
27460 //GC_CAC_WEIGHT_DBR_0
27461 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0__SHIFT                                                           0x0
27462 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1__SHIFT                                                           0x10
27463 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0_MASK                                                             0x0000FFFFL
27464 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1_MASK                                                             0xFFFF0000L
27465 //GC_CAC_WEIGHT_DBR_1
27466 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2__SHIFT                                                           0x0
27467 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3__SHIFT                                                           0x10
27468 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2_MASK                                                             0x0000FFFFL
27469 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3_MASK                                                             0xFFFF0000L
27470 //GC_CAC_WEIGHT_GDS_0
27471 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT                                                           0x0
27472 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT                                                           0x10
27473 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK                                                             0x0000FFFFL
27474 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK                                                             0xFFFF0000L
27475 //GC_CAC_WEIGHT_GDS_1
27476 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT                                                           0x0
27477 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT                                                           0x10
27478 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK                                                             0x0000FFFFL
27479 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK                                                             0xFFFF0000L
27480 //GC_CAC_WEIGHT_IA_0
27481 #define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT                                                             0x0
27482 #define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT                                                                   0x10
27483 #define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK                                                               0x0000FFFFL
27484 #define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27485 //GC_CAC_WEIGHT_LDS_0
27486 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT                                                           0x0
27487 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT                                                           0x10
27488 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK                                                             0x0000FFFFL
27489 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK                                                             0xFFFF0000L
27490 //GC_CAC_WEIGHT_LDS_1
27491 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT                                                           0x0
27492 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT                                                           0x10
27493 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK                                                             0x0000FFFFL
27494 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK                                                             0xFFFF0000L
27495 //GC_CAC_WEIGHT_PA_0
27496 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT                                                             0x0
27497 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT                                                             0x10
27498 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK                                                               0x0000FFFFL
27499 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK                                                               0xFFFF0000L
27500 //GC_CAC_WEIGHT_PC_0
27501 #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT                                                             0x0
27502 #define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT                                                                   0x10
27503 #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK                                                               0x0000FFFFL
27504 #define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27505 //GC_CAC_WEIGHT_SC_0
27506 #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT                                                             0x0
27507 #define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT                                                                   0x10
27508 #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK                                                               0x0000FFFFL
27509 #define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27510 //GC_CAC_WEIGHT_SPI_0
27511 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT                                                           0x0
27512 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT                                                           0x10
27513 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK                                                             0x0000FFFFL
27514 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK                                                             0xFFFF0000L
27515 //GC_CAC_WEIGHT_SPI_1
27516 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT                                                           0x0
27517 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT                                                           0x10
27518 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK                                                             0x0000FFFFL
27519 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK                                                             0xFFFF0000L
27520 //GC_CAC_WEIGHT_SPI_2
27521 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT                                                           0x0
27522 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT                                                           0x10
27523 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK                                                             0x0000FFFFL
27524 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK                                                             0xFFFF0000L
27525 //GC_CAC_WEIGHT_SQ_0
27526 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT                                                             0x0
27527 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT                                                             0x10
27528 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK                                                               0x0000FFFFL
27529 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK                                                               0xFFFF0000L
27530 //GC_CAC_WEIGHT_SQ_1
27531 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT                                                             0x0
27532 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT                                                             0x10
27533 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK                                                               0x0000FFFFL
27534 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK                                                               0xFFFF0000L
27535 //GC_CAC_WEIGHT_SQ_2
27536 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT                                                             0x0
27537 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT                                                             0x10
27538 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK                                                               0x0000FFFFL
27539 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK                                                               0xFFFF0000L
27540 //GC_CAC_WEIGHT_SQ_3
27541 #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT                                                             0x0
27542 #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT                                                             0x10
27543 #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK                                                               0x0000FFFFL
27544 #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK                                                               0xFFFF0000L
27545 //GC_CAC_WEIGHT_SQ_4
27546 #define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT                                                             0x0
27547 #define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT                                                                   0x10
27548 #define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK                                                               0x0000FFFFL
27549 #define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK                                                                     0xFFFF0000L
27550 //GC_CAC_WEIGHT_SX_0
27551 #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT                                                             0x0
27552 #define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT                                                                   0x10
27553 #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK                                                               0x0000FFFFL
27554 #define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27555 //GC_CAC_WEIGHT_SXRB_0
27556 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT                                                         0x0
27557 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT                                                         0x10
27558 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK                                                           0x0000FFFFL
27559 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK                                                           0xFFFF0000L
27560 //GC_CAC_WEIGHT_TA_0
27561 #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT                                                             0x0
27562 #define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT                                                                   0x10
27563 #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK                                                               0x0000FFFFL
27564 #define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27565 //GC_CAC_WEIGHT_TCC_0
27566 #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT                                                           0x0
27567 #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT                                                           0x10
27568 #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK                                                             0x0000FFFFL
27569 #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK                                                             0xFFFF0000L
27570 //GC_CAC_WEIGHT_TCC_1
27571 #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT                                                           0x0
27572 #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT                                                           0x10
27573 #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK                                                             0x0000FFFFL
27574 #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK                                                             0xFFFF0000L
27575 //GC_CAC_WEIGHT_TCC_2
27576 #define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT                                                           0x0
27577 #define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT                                                                  0x10
27578 #define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK                                                             0x0000FFFFL
27579 #define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK                                                                    0xFFFF0000L
27580 //GC_CAC_WEIGHT_TCP_0
27581 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT                                                           0x0
27582 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT                                                           0x10
27583 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK                                                             0x0000FFFFL
27584 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK                                                             0xFFFF0000L
27585 //GC_CAC_WEIGHT_TCP_1
27586 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT                                                           0x0
27587 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT                                                           0x10
27588 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK                                                             0x0000FFFFL
27589 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK                                                             0xFFFF0000L
27590 //GC_CAC_WEIGHT_TCP_2
27591 #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT                                                           0x0
27592 #define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT                                                                  0x10
27593 #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK                                                             0x0000FFFFL
27594 #define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK                                                                    0xFFFF0000L
27595 //GC_CAC_WEIGHT_TD_0
27596 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT                                                             0x0
27597 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT                                                             0x10
27598 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK                                                               0x0000FFFFL
27599 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK                                                               0xFFFF0000L
27600 //GC_CAC_WEIGHT_TD_1
27601 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT                                                             0x0
27602 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT                                                             0x10
27603 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK                                                               0x0000FFFFL
27604 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK                                                               0xFFFF0000L
27605 //GC_CAC_WEIGHT_TD_2
27606 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT                                                             0x0
27607 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT                                                             0x10
27608 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK                                                               0x0000FFFFL
27609 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK                                                               0xFFFF0000L
27610 //GC_CAC_WEIGHT_VGT_0
27611 #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT                                                           0x0
27612 #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT                                                           0x10
27613 #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK                                                             0x0000FFFFL
27614 #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK                                                             0xFFFF0000L
27615 //GC_CAC_WEIGHT_VGT_1
27616 #define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT                                                           0x0
27617 #define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT                                                                  0x10
27618 #define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK                                                             0x0000FFFFL
27619 #define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK                                                                    0xFFFF0000L
27620 //GC_CAC_WEIGHT_WD_0
27621 #define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT                                                             0x0
27622 #define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT                                                                   0x10
27623 #define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK                                                               0x0000FFFFL
27624 #define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27625 //GC_CAC_WEIGHT_CU_0
27626 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT                                                             0x0
27627 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT                                                             0x10
27628 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK                                                               0x0000FFFFL
27629 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK                                                               0xFFFF0000L
27630 //GC_CAC_WEIGHT_CU_1
27631 #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT                                                             0x0
27632 #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT                                                             0x10
27633 #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK                                                               0x0000FFFFL
27634 #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK                                                               0xFFFF0000L
27635 //GC_CAC_WEIGHT_CU_2
27636 #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT                                                             0x0
27637 #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT                                                             0x10
27638 #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK                                                               0x0000FFFFL
27639 #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK                                                               0xFFFF0000L
27640 //GC_CAC_WEIGHT_CU_3
27641 #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT                                                             0x0
27642 #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT                                                             0x10
27643 #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK                                                               0x0000FFFFL
27644 #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK                                                               0xFFFF0000L
27645 //GC_CAC_WEIGHT_CU_4
27646 #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT                                                             0x0
27647 #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT                                                             0x10
27648 #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK                                                               0x0000FFFFL
27649 #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK                                                               0xFFFF0000L
27650 //GC_CAC_WEIGHT_CU_5
27651 #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT                                                            0x0
27652 #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT                                                            0x10
27653 #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK                                                              0x0000FFFFL
27654 #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK                                                              0xFFFF0000L
27655 //GC_CAC_WEIGHT_CU_6
27656 #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12__SHIFT                                                            0x0
27657 #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13__SHIFT                                                            0x10
27658 #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12_MASK                                                              0x0000FFFFL
27659 #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13_MASK                                                              0xFFFF0000L
27660 //GC_CAC_WEIGHT_CU_7
27661 #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14__SHIFT                                                            0x0
27662 #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15__SHIFT                                                            0x10
27663 #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14_MASK                                                              0x0000FFFFL
27664 #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15_MASK                                                              0xFFFF0000L
27665 //GC_CAC_ACC_BCI0
27666 #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27667 #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27668 //GC_CAC_ACC_CB0
27669 #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27670 #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27671 //GC_CAC_ACC_CB1
27672 #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27673 #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27674 //GC_CAC_ACC_CB2
27675 #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT                                                               0x0
27676 #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27677 //GC_CAC_ACC_CB3
27678 #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT                                                               0x0
27679 #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27680 //GC_CAC_ACC_CBR0
27681 #define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27682 #define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27683 //GC_CAC_ACC_CBR1
27684 #define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27685 #define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27686 //GC_CAC_ACC_CBR2
27687 #define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27688 #define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27689 //GC_CAC_ACC_CBR3
27690 #define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27691 #define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27692 //GC_CAC_ACC_CP0
27693 #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27694 #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27695 //GC_CAC_ACC_CP1
27696 #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27697 #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27698 //GC_CAC_ACC_CP2
27699 #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT                                                               0x0
27700 #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27701 //GC_CAC_ACC_DB0
27702 #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27703 #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27704 //GC_CAC_ACC_DB1
27705 #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27706 #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27707 //GC_CAC_ACC_DB2
27708 #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT                                                               0x0
27709 #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27710 //GC_CAC_ACC_DB3
27711 #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT                                                               0x0
27712 #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27713 //GC_CAC_ACC_DBR0
27714 #define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27715 #define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27716 //GC_CAC_ACC_DBR1
27717 #define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27718 #define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27719 //GC_CAC_ACC_DBR2
27720 #define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27721 #define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27722 //GC_CAC_ACC_DBR3
27723 #define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27724 #define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27725 //GC_CAC_ACC_GDS0
27726 #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27727 #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27728 //GC_CAC_ACC_GDS1
27729 #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27730 #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27731 //GC_CAC_ACC_GDS2
27732 #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27733 #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27734 //GC_CAC_ACC_GDS3
27735 #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27736 #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27737 //GC_CAC_ACC_IA0
27738 #define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27739 #define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27740 //GC_CAC_ACC_LDS0
27741 #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27742 #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27743 //GC_CAC_ACC_LDS1
27744 #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27745 #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27746 //GC_CAC_ACC_LDS2
27747 #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27748 #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27749 //GC_CAC_ACC_LDS3
27750 #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27751 #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27752 //GC_CAC_ACC_PA0
27753 #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27754 #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27755 //GC_CAC_ACC_PA1
27756 #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27757 #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27758 //GC_CAC_ACC_PC0
27759 #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27760 #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27761 //GC_CAC_ACC_SC0
27762 #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27763 #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27764 //GC_CAC_ACC_SPI0
27765 #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27766 #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27767 //GC_CAC_ACC_SPI1
27768 #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27769 #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27770 //GC_CAC_ACC_SPI2
27771 #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27772 #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27773 //GC_CAC_ACC_SPI3
27774 #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27775 #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27776 //GC_CAC_ACC_SPI4
27777 #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT                                                              0x0
27778 #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27779 //GC_CAC_ACC_SPI5
27780 #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT                                                              0x0
27781 #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27782 //GC_CAC_WEIGHT_UTCL2_ATCL2_0
27783 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT                                           0x0
27784 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT                                           0x10
27785 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK                                             0x0000FFFFL
27786 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK                                             0xFFFF0000L
27787 //GC_CAC_ACC_EA0
27788 #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27789 #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27790 //GC_CAC_ACC_EA1
27791 #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27792 #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27793 //GC_CAC_ACC_EA2
27794 #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT                                                               0x0
27795 #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27796 //GC_CAC_ACC_EA3
27797 #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT                                                               0x0
27798 #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27799 //GC_CAC_ACC_UTCL2_ATCL20
27800 #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT                                                      0x0
27801 #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
27802 //GC_CAC_OVRD_EA
27803 #define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT                                                                   0x0
27804 #define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT                                                                    0x6
27805 #define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK                                                                     0x0000003FL
27806 #define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK                                                                      0x00000FC0L
27807 //GC_CAC_OVRD_UTCL2_ATCL2
27808 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT                                                          0x0
27809 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT                                                           0x5
27810 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK                                                            0x0000001FL
27811 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK                                                             0x000003E0L
27812 //GC_CAC_WEIGHT_EA_0
27813 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT                                                             0x0
27814 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT                                                             0x10
27815 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK                                                               0x0000FFFFL
27816 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK                                                               0xFFFF0000L
27817 //GC_CAC_WEIGHT_EA_1
27818 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT                                                             0x0
27819 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT                                                             0x10
27820 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK                                                               0x0000FFFFL
27821 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK                                                               0xFFFF0000L
27822 //GC_CAC_WEIGHT_RMI_0
27823 #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT                                                           0x0
27824 #define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT                                                                    0x10
27825 #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK                                                             0x0000FFFFL
27826 #define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK                                                                      0xFFFF0000L
27827 //GC_CAC_ACC_RMI0
27828 #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27829 #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27830 //GC_CAC_OVRD_RMI
27831 #define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT                                                                  0x0
27832 #define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT                                                                   0x1
27833 #define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK                                                                    0x00000001L
27834 #define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK                                                                     0x00000002L
27835 //GC_CAC_WEIGHT_UTCL2_ATCL2_1
27836 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT                                           0x0
27837 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT                                           0x10
27838 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK                                             0x0000FFFFL
27839 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK                                             0xFFFF0000L
27840 //GC_CAC_ACC_UTCL2_ATCL21
27841 #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT                                                      0x0
27842 #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
27843 //GC_CAC_ACC_UTCL2_ATCL22
27844 #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT                                                      0x0
27845 #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
27846 //GC_CAC_ACC_UTCL2_ATCL23
27847 #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT                                                      0x0
27848 #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
27849 //GC_CAC_ACC_EA4
27850 #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT                                                               0x0
27851 #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27852 //GC_CAC_ACC_EA5
27853 #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT                                                               0x0
27854 #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27855 //GC_CAC_WEIGHT_EA_2
27856 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT                                                             0x0
27857 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT                                                             0x10
27858 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK                                                               0x0000FFFFL
27859 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK                                                               0xFFFF0000L
27860 //GC_CAC_ACC_SQ0_LOWER
27861 #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27862 #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27863 //GC_CAC_ACC_SQ0_UPPER
27864 #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27865 #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT                                                                 0x8
27866 #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27867 #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27868 //GC_CAC_ACC_SQ1_LOWER
27869 #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27870 #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27871 //GC_CAC_ACC_SQ1_UPPER
27872 #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27873 #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT                                                                 0x8
27874 #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27875 #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27876 //GC_CAC_ACC_SQ2_LOWER
27877 #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27878 #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27879 //GC_CAC_ACC_SQ2_UPPER
27880 #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27881 #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT                                                                 0x8
27882 #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27883 #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27884 //GC_CAC_ACC_SQ3_LOWER
27885 #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27886 #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27887 //GC_CAC_ACC_SQ3_UPPER
27888 #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27889 #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT                                                                 0x8
27890 #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27891 #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27892 //GC_CAC_ACC_SQ4_LOWER
27893 #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27894 #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27895 //GC_CAC_ACC_SQ4_UPPER
27896 #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27897 #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT                                                                 0x8
27898 #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27899 #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27900 //GC_CAC_ACC_SQ5_LOWER
27901 #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27902 #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27903 //GC_CAC_ACC_SQ5_UPPER
27904 #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27905 #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT                                                                 0x8
27906 #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27907 #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27908 //GC_CAC_ACC_SQ6_LOWER
27909 #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27910 #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27911 //GC_CAC_ACC_SQ6_UPPER
27912 #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27913 #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT                                                                 0x8
27914 #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27915 #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27916 //GC_CAC_ACC_SQ7_LOWER
27917 #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27918 #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27919 //GC_CAC_ACC_SQ7_UPPER
27920 #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27921 #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT                                                                 0x8
27922 #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27923 #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27924 //GC_CAC_ACC_SQ8_LOWER
27925 #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27926 #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27927 //GC_CAC_ACC_SQ8_UPPER
27928 #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27929 #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT                                                                 0x8
27930 #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27931 #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27932 //GC_CAC_ACC_SX0
27933 #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27934 #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27935 //GC_CAC_ACC_SXRB0
27936 #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT                                                             0x0
27937 #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
27938 //GC_CAC_ACC_SXRB1
27939 #define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT                                                             0x0
27940 #define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
27941 //GC_CAC_ACC_TA0
27942 #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27943 #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27944 //GC_CAC_ACC_TCC0
27945 #define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27946 #define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27947 //GC_CAC_ACC_TCC1
27948 #define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27949 #define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27950 //GC_CAC_ACC_TCC2
27951 #define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27952 #define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27953 //GC_CAC_ACC_TCC3
27954 #define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27955 #define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27956 //GC_CAC_ACC_TCC4
27957 #define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT                                                              0x0
27958 #define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27959 //GC_CAC_ACC_TCP0
27960 #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27961 #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27962 //GC_CAC_ACC_TCP1
27963 #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27964 #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27965 //GC_CAC_ACC_TCP2
27966 #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27967 #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27968 //GC_CAC_ACC_TCP3
27969 #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27970 #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27971 //GC_CAC_ACC_TCP4
27972 #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT                                                              0x0
27973 #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27974 //GC_CAC_ACC_TD0
27975 #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27976 #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27977 //GC_CAC_ACC_TD1
27978 #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27979 #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27980 //GC_CAC_ACC_TD2
27981 #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT                                                               0x0
27982 #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27983 //GC_CAC_ACC_TD3
27984 #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT                                                               0x0
27985 #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27986 //GC_CAC_ACC_TD4
27987 #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT                                                               0x0
27988 #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27989 //GC_CAC_ACC_TD5
27990 #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT                                                               0x0
27991 #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27992 //GC_CAC_ACC_VGT0
27993 #define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27994 #define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27995 //GC_CAC_ACC_VGT1
27996 #define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27997 #define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27998 //GC_CAC_ACC_VGT2
27999 #define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT                                                              0x0
28000 #define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28001 //GC_CAC_ACC_WD0
28002 #define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT                                                               0x0
28003 #define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28004 //GC_CAC_ACC_CU0
28005 #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT                                                               0x0
28006 #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28007 //GC_CAC_ACC_CU1
28008 #define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT                                                               0x0
28009 #define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28010 //GC_CAC_ACC_CU2
28011 #define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT                                                               0x0
28012 #define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28013 //GC_CAC_ACC_CU3
28014 #define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT                                                               0x0
28015 #define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28016 //GC_CAC_ACC_CU4
28017 #define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT                                                               0x0
28018 #define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28019 //GC_CAC_ACC_CU5
28020 #define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT                                                               0x0
28021 #define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28022 //GC_CAC_ACC_CU6
28023 #define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT                                                               0x0
28024 #define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28025 //GC_CAC_ACC_CU7
28026 #define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT                                                               0x0
28027 #define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28028 //GC_CAC_ACC_CU8
28029 #define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT                                                               0x0
28030 #define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28031 //GC_CAC_ACC_CU9
28032 #define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT                                                               0x0
28033 #define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28034 //GC_CAC_ACC_CU10
28035 #define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT                                                              0x0
28036 #define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28037 //GC_CAC_ACC_CU11
28038 #define GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT                                                              0x0
28039 #define GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28040 //GC_CAC_ACC_CU12
28041 #define GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT                                                              0x0
28042 #define GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28043 //GC_CAC_ACC_CU13
28044 #define GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT                                                              0x0
28045 #define GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28046 //GC_CAC_ACC_CU14
28047 #define GC_CAC_ACC_CU14__ACCUMULATOR_31_0__SHIFT                                                              0x0
28048 #define GC_CAC_ACC_CU14__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28049 //GC_CAC_ACC_CU15
28050 #define GC_CAC_ACC_CU15__ACCUMULATOR_31_0__SHIFT                                                              0x0
28051 #define GC_CAC_ACC_CU15__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28052 //GC_CAC_OVRD_BCI
28053 #define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT                                                                  0x0
28054 #define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT                                                                   0x2
28055 #define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK                                                                    0x00000003L
28056 #define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK                                                                     0x0000000CL
28057 //GC_CAC_OVRD_CB
28058 #define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT                                                                   0x0
28059 #define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT                                                                    0x4
28060 #define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK                                                                     0x0000000FL
28061 #define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK                                                                      0x000000F0L
28062 //GC_CAC_OVRD_CBR
28063 #define GC_CAC_OVRD_CBR__OVRRD_SELECT__SHIFT                                                                  0x0
28064 #define GC_CAC_OVRD_CBR__OVRRD_VALUE__SHIFT                                                                   0x4
28065 #define GC_CAC_OVRD_CBR__OVRRD_SELECT_MASK                                                                    0x0000000FL
28066 #define GC_CAC_OVRD_CBR__OVRRD_VALUE_MASK                                                                     0x000000F0L
28067 //GC_CAC_OVRD_CP
28068 #define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT                                                                   0x0
28069 #define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT                                                                    0x3
28070 #define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK                                                                     0x00000007L
28071 #define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK                                                                      0x00000038L
28072 //GC_CAC_OVRD_DB
28073 #define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT                                                                   0x0
28074 #define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT                                                                    0x4
28075 #define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK                                                                     0x0000000FL
28076 #define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK                                                                      0x000000F0L
28077 //GC_CAC_OVRD_DBR
28078 #define GC_CAC_OVRD_DBR__OVRRD_SELECT__SHIFT                                                                  0x0
28079 #define GC_CAC_OVRD_DBR__OVRRD_VALUE__SHIFT                                                                   0x4
28080 #define GC_CAC_OVRD_DBR__OVRRD_SELECT_MASK                                                                    0x0000000FL
28081 #define GC_CAC_OVRD_DBR__OVRRD_VALUE_MASK                                                                     0x000000F0L
28082 //GC_CAC_OVRD_GDS
28083 #define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT                                                                  0x0
28084 #define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT                                                                   0x4
28085 #define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK                                                                    0x0000000FL
28086 #define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK                                                                     0x000000F0L
28087 //GC_CAC_OVRD_IA
28088 #define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT                                                                   0x0
28089 #define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT                                                                    0x1
28090 #define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK                                                                     0x00000001L
28091 #define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK                                                                      0x00000002L
28092 //GC_CAC_OVRD_LDS
28093 #define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT                                                                  0x0
28094 #define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT                                                                   0x4
28095 #define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK                                                                    0x0000000FL
28096 #define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK                                                                     0x000000F0L
28097 //GC_CAC_OVRD_PA
28098 #define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT                                                                   0x0
28099 #define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT                                                                    0x2
28100 #define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK                                                                     0x00000003L
28101 #define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK                                                                      0x0000000CL
28102 //GC_CAC_OVRD_PC
28103 #define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT                                                                   0x0
28104 #define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT                                                                    0x1
28105 #define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK                                                                     0x00000001L
28106 #define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK                                                                      0x00000002L
28107 //GC_CAC_OVRD_SC
28108 #define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT                                                                   0x0
28109 #define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT                                                                    0x1
28110 #define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK                                                                     0x00000001L
28111 #define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK                                                                      0x00000002L
28112 //GC_CAC_OVRD_SPI
28113 #define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT                                                                  0x0
28114 #define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT                                                                   0x6
28115 #define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK                                                                    0x0000003FL
28116 #define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK                                                                     0x00000FC0L
28117 //GC_CAC_OVRD_CU
28118 #define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT                                                                   0x0
28119 #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT                                                                    0x1
28120 #define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK                                                                     0x00000001L
28121 #define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK                                                                      0x00000002L
28122 //GC_CAC_OVRD_SQ
28123 #define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT                                                                   0x0
28124 #define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT                                                                    0x9
28125 #define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK                                                                     0x000001FFL
28126 #define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK                                                                      0x0003FE00L
28127 //GC_CAC_OVRD_SX
28128 #define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT                                                                   0x0
28129 #define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT                                                                    0x1
28130 #define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK                                                                     0x00000001L
28131 #define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK                                                                      0x00000002L
28132 //GC_CAC_OVRD_SXRB
28133 #define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT                                                                 0x0
28134 #define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT                                                                  0x1
28135 #define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK                                                                   0x00000001L
28136 #define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK                                                                    0x00000002L
28137 //GC_CAC_OVRD_TA
28138 #define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT                                                                   0x0
28139 #define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT                                                                    0x1
28140 #define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK                                                                     0x00000001L
28141 #define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK                                                                      0x00000002L
28142 //GC_CAC_OVRD_TCC
28143 #define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT                                                                  0x0
28144 #define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT                                                                   0x5
28145 #define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK                                                                    0x0000001FL
28146 #define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK                                                                     0x000003E0L
28147 //GC_CAC_OVRD_TCP
28148 #define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT                                                                  0x0
28149 #define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT                                                                   0x5
28150 #define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK                                                                    0x0000001FL
28151 #define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK                                                                     0x000003E0L
28152 //GC_CAC_OVRD_TD
28153 #define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT                                                                   0x0
28154 #define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT                                                                    0x6
28155 #define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK                                                                     0x0000003FL
28156 #define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK                                                                      0x00000FC0L
28157 //GC_CAC_OVRD_VGT
28158 #define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT                                                                  0x0
28159 #define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT                                                                   0x3
28160 #define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK                                                                    0x00000007L
28161 #define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK                                                                     0x00000038L
28162 //GC_CAC_OVRD_WD
28163 #define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT                                                                   0x0
28164 #define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT                                                                    0x1
28165 #define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK                                                                     0x00000001L
28166 #define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK                                                                      0x00000002L
28167 //GC_CAC_ACC_BCI1
28168 #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT                                                              0x0
28169 #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28170 //GC_CAC_WEIGHT_UTCL2_ATCL2_2
28171 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT                                           0x0
28172 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT                                           0x10
28173 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK                                             0x0000FFFFL
28174 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK                                             0xFFFF0000L
28175 //GC_CAC_WEIGHT_UTCL2_ROUTER_0
28176 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT                                         0x0
28177 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT                                         0x10
28178 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK                                           0x0000FFFFL
28179 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK                                           0xFFFF0000L
28180 //GC_CAC_WEIGHT_UTCL2_ROUTER_1
28181 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT                                         0x0
28182 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT                                         0x10
28183 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK                                           0x0000FFFFL
28184 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK                                           0xFFFF0000L
28185 //GC_CAC_WEIGHT_UTCL2_ROUTER_2
28186 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT                                         0x0
28187 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT                                         0x10
28188 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK                                           0x0000FFFFL
28189 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK                                           0xFFFF0000L
28190 //GC_CAC_WEIGHT_UTCL2_ROUTER_3
28191 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT                                         0x0
28192 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT                                         0x10
28193 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK                                           0x0000FFFFL
28194 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK                                           0xFFFF0000L
28195 //GC_CAC_WEIGHT_UTCL2_ROUTER_4
28196 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT                                         0x0
28197 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT                                         0x10
28198 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK                                           0x0000FFFFL
28199 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK                                           0xFFFF0000L
28200 //GC_CAC_WEIGHT_UTCL2_VML2_0
28201 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT                                             0x0
28202 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT                                             0x10
28203 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK                                               0x0000FFFFL
28204 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK                                               0xFFFF0000L
28205 //GC_CAC_WEIGHT_UTCL2_VML2_1
28206 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT                                             0x0
28207 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT                                             0x10
28208 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK                                               0x0000FFFFL
28209 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK                                               0xFFFF0000L
28210 //GC_CAC_WEIGHT_UTCL2_VML2_2
28211 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT                                             0x0
28212 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT                                             0x10
28213 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK                                               0x0000FFFFL
28214 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK                                               0xFFFF0000L
28215 //GC_CAC_ACC_UTCL2_ATCL24
28216 #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT                                                      0x0
28217 #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
28218 //GC_CAC_ACC_UTCL2_ROUTER0
28219 #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT                                                     0x0
28220 #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28221 //GC_CAC_ACC_UTCL2_ROUTER1
28222 #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT                                                     0x0
28223 #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28224 //GC_CAC_ACC_UTCL2_ROUTER2
28225 #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT                                                     0x0
28226 #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28227 //GC_CAC_ACC_UTCL2_ROUTER3
28228 #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT                                                     0x0
28229 #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28230 //GC_CAC_ACC_UTCL2_ROUTER4
28231 #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT                                                     0x0
28232 #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28233 //GC_CAC_ACC_UTCL2_ROUTER5
28234 #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT                                                     0x0
28235 #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28236 //GC_CAC_ACC_UTCL2_ROUTER6
28237 #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT                                                     0x0
28238 #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28239 //GC_CAC_ACC_UTCL2_ROUTER7
28240 #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT                                                     0x0
28241 #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28242 //GC_CAC_ACC_UTCL2_ROUTER8
28243 #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT                                                     0x0
28244 #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28245 //GC_CAC_ACC_UTCL2_ROUTER9
28246 #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT                                                     0x0
28247 #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28248 //GC_CAC_ACC_UTCL2_VML20
28249 #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT                                                       0x0
28250 #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28251 //GC_CAC_ACC_UTCL2_VML21
28252 #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT                                                       0x0
28253 #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28254 //GC_CAC_ACC_UTCL2_VML22
28255 #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT                                                       0x0
28256 #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28257 //GC_CAC_ACC_UTCL2_VML23
28258 #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT                                                       0x0
28259 #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28260 //GC_CAC_ACC_UTCL2_VML24
28261 #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT                                                       0x0
28262 #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28263 //GC_CAC_OVRD_UTCL2_ROUTER
28264 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT                                                         0x0
28265 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT                                                          0xa
28266 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK                                                           0x000003FFL
28267 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK                                                            0x000FFC00L
28268 //GC_CAC_OVRD_UTCL2_VML2
28269 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT                                                           0x0
28270 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT                                                            0x5
28271 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK                                                             0x0000001FL
28272 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK                                                              0x000003E0L
28273 //GC_CAC_WEIGHT_UTCL2_WALKER_0
28274 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT                                         0x0
28275 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT                                         0x10
28276 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK                                           0x0000FFFFL
28277 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK                                           0xFFFF0000L
28278 //GC_CAC_WEIGHT_UTCL2_WALKER_1
28279 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT                                         0x0
28280 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT                                         0x10
28281 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK                                           0x0000FFFFL
28282 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK                                           0xFFFF0000L
28283 //GC_CAC_WEIGHT_UTCL2_WALKER_2
28284 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT                                         0x0
28285 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT                                         0x10
28286 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK                                           0x0000FFFFL
28287 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK                                           0xFFFF0000L
28288 //GC_CAC_ACC_UTCL2_WALKER0
28289 #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT                                                     0x0
28290 #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28291 //GC_CAC_ACC_UTCL2_WALKER1
28292 #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT                                                     0x0
28293 #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28294 //GC_CAC_ACC_UTCL2_WALKER2
28295 #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT                                                     0x0
28296 #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28297 //GC_CAC_ACC_UTCL2_WALKER3
28298 #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT                                                     0x0
28299 #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28300 //GC_CAC_ACC_UTCL2_WALKER4
28301 #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT                                                     0x0
28302 #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28303 //GC_CAC_OVRD_UTCL2_WALKER
28304 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT                                                         0x0
28305 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT                                                          0x5
28306 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK                                                           0x0000001FL
28307 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK                                                            0x000003E0L
28308 
28309 
28310 // addressBlock: secacind
28311 //SE_CAC_CNTL
28312 #define SE_CAC_CNTL__CAC_ENABLE__SHIFT                                                                        0x0
28313 #define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT                                                                     0x1
28314 #define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT                                                                      0x11
28315 #define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT                                                                     0x17
28316 #define SE_CAC_CNTL__UNUSED_0__SHIFT                                                                          0x1f
28317 #define SE_CAC_CNTL__CAC_ENABLE_MASK                                                                          0x00000001L
28318 #define SE_CAC_CNTL__CAC_THRESHOLD_MASK                                                                       0x0001FFFEL
28319 #define SE_CAC_CNTL__CAC_BLOCK_ID_MASK                                                                        0x007E0000L
28320 #define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK                                                                       0x7F800000L
28321 #define SE_CAC_CNTL__UNUSED_0_MASK                                                                            0x80000000L
28322 //SE_CAC_OVR_SEL
28323 #define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT                                                                    0x0
28324 #define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK                                                                      0xFFFFFFFFL
28325 //SE_CAC_OVR_VAL
28326 #define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT                                                                    0x0
28327 #define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK                                                                      0xFFFFFFFFL
28328 
28329 
28330 // addressBlock: sqind
28331 //SQ_WAVE_MODE
28332 #define SQ_WAVE_MODE__FP_ROUND__SHIFT                                                                         0x0
28333 #define SQ_WAVE_MODE__FP_DENORM__SHIFT                                                                        0x4
28334 #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT                                                                       0x8
28335 #define SQ_WAVE_MODE__IEEE__SHIFT                                                                             0x9
28336 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT                                                                      0xa
28337 #define SQ_WAVE_MODE__DEBUG_EN__SHIFT                                                                         0xb
28338 #define SQ_WAVE_MODE__EXCP_EN__SHIFT                                                                          0xc
28339 #define SQ_WAVE_MODE__FP16_OVFL__SHIFT                                                                        0x17
28340 #define SQ_WAVE_MODE__POPS_PACKER0__SHIFT                                                                     0x18
28341 #define SQ_WAVE_MODE__POPS_PACKER1__SHIFT                                                                     0x19
28342 #define SQ_WAVE_MODE__DISABLE_PERF__SHIFT                                                                     0x1a
28343 #define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT                                                                       0x1b
28344 #define SQ_WAVE_MODE__VSKIP__SHIFT                                                                            0x1c
28345 #define SQ_WAVE_MODE__CSP__SHIFT                                                                              0x1d
28346 #define SQ_WAVE_MODE__FP_ROUND_MASK                                                                           0x0000000FL
28347 #define SQ_WAVE_MODE__FP_DENORM_MASK                                                                          0x000000F0L
28348 #define SQ_WAVE_MODE__DX10_CLAMP_MASK                                                                         0x00000100L
28349 #define SQ_WAVE_MODE__IEEE_MASK                                                                               0x00000200L
28350 #define SQ_WAVE_MODE__LOD_CLAMPED_MASK                                                                        0x00000400L
28351 #define SQ_WAVE_MODE__DEBUG_EN_MASK                                                                           0x00000800L
28352 #define SQ_WAVE_MODE__EXCP_EN_MASK                                                                            0x001FF000L
28353 #define SQ_WAVE_MODE__FP16_OVFL_MASK                                                                          0x00800000L
28354 #define SQ_WAVE_MODE__POPS_PACKER0_MASK                                                                       0x01000000L
28355 #define SQ_WAVE_MODE__POPS_PACKER1_MASK                                                                       0x02000000L
28356 #define SQ_WAVE_MODE__DISABLE_PERF_MASK                                                                       0x04000000L
28357 #define SQ_WAVE_MODE__GPR_IDX_EN_MASK                                                                         0x08000000L
28358 #define SQ_WAVE_MODE__VSKIP_MASK                                                                              0x10000000L
28359 #define SQ_WAVE_MODE__CSP_MASK                                                                                0xE0000000L
28360 //SQ_WAVE_STATUS
28361 #define SQ_WAVE_STATUS__SCC__SHIFT                                                                            0x0
28362 #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT                                                                       0x1
28363 #define SQ_WAVE_STATUS__USER_PRIO__SHIFT                                                                      0x3
28364 #define SQ_WAVE_STATUS__PRIV__SHIFT                                                                           0x5
28365 #define SQ_WAVE_STATUS__TRAP_EN__SHIFT                                                                        0x6
28366 #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT                                                                      0x7
28367 #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT                                                                     0x8
28368 #define SQ_WAVE_STATUS__EXECZ__SHIFT                                                                          0x9
28369 #define SQ_WAVE_STATUS__VCCZ__SHIFT                                                                           0xa
28370 #define SQ_WAVE_STATUS__IN_TG__SHIFT                                                                          0xb
28371 #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT                                                                     0xc
28372 #define SQ_WAVE_STATUS__HALT__SHIFT                                                                           0xd
28373 #define SQ_WAVE_STATUS__TRAP__SHIFT                                                                           0xe
28374 #define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT                                                                   0xf
28375 #define SQ_WAVE_STATUS__VALID__SHIFT                                                                          0x10
28376 #define SQ_WAVE_STATUS__ECC_ERR__SHIFT                                                                        0x11
28377 #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT                                                                    0x12
28378 #define SQ_WAVE_STATUS__PERF_EN__SHIFT                                                                        0x13
28379 #define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT                                                                  0x14
28380 #define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT                                                                   0x15
28381 #define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT                                                                   0x16
28382 #define SQ_WAVE_STATUS__FATAL_HALT__SHIFT                                                                     0x17
28383 #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT                                                                    0x1b
28384 #define SQ_WAVE_STATUS__SCC_MASK                                                                              0x00000001L
28385 #define SQ_WAVE_STATUS__SPI_PRIO_MASK                                                                         0x00000006L
28386 #define SQ_WAVE_STATUS__USER_PRIO_MASK                                                                        0x00000018L
28387 #define SQ_WAVE_STATUS__PRIV_MASK                                                                             0x00000020L
28388 #define SQ_WAVE_STATUS__TRAP_EN_MASK                                                                          0x00000040L
28389 #define SQ_WAVE_STATUS__TTRACE_EN_MASK                                                                        0x00000080L
28390 #define SQ_WAVE_STATUS__EXPORT_RDY_MASK                                                                       0x00000100L
28391 #define SQ_WAVE_STATUS__EXECZ_MASK                                                                            0x00000200L
28392 #define SQ_WAVE_STATUS__VCCZ_MASK                                                                             0x00000400L
28393 #define SQ_WAVE_STATUS__IN_TG_MASK                                                                            0x00000800L
28394 #define SQ_WAVE_STATUS__IN_BARRIER_MASK                                                                       0x00001000L
28395 #define SQ_WAVE_STATUS__HALT_MASK                                                                             0x00002000L
28396 #define SQ_WAVE_STATUS__TRAP_MASK                                                                             0x00004000L
28397 #define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK                                                                     0x00008000L
28398 #define SQ_WAVE_STATUS__VALID_MASK                                                                            0x00010000L
28399 #define SQ_WAVE_STATUS__ECC_ERR_MASK                                                                          0x00020000L
28400 #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK                                                                      0x00040000L
28401 #define SQ_WAVE_STATUS__PERF_EN_MASK                                                                          0x00080000L
28402 #define SQ_WAVE_STATUS__COND_DBG_USER_MASK                                                                    0x00100000L
28403 #define SQ_WAVE_STATUS__COND_DBG_SYS_MASK                                                                     0x00200000L
28404 #define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK                                                                     0x00400000L
28405 #define SQ_WAVE_STATUS__FATAL_HALT_MASK                                                                       0x00800000L
28406 #define SQ_WAVE_STATUS__MUST_EXPORT_MASK                                                                      0x08000000L
28407 //SQ_WAVE_TRAPSTS
28408 #define SQ_WAVE_TRAPSTS__EXCP__SHIFT                                                                          0x0
28409 #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT                                                                       0xa
28410 #define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT                                                                  0xb
28411 #define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT                                                                       0xc
28412 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT                                                                    0x10
28413 #define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT                                                                   0x1c
28414 #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT                                                                       0x1d
28415 #define SQ_WAVE_TRAPSTS__EXCP_MASK                                                                            0x000001FFL
28416 #define SQ_WAVE_TRAPSTS__SAVECTX_MASK                                                                         0x00000400L
28417 #define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK                                                                    0x00000800L
28418 #define SQ_WAVE_TRAPSTS__EXCP_HI_MASK                                                                         0x00007000L
28419 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK                                                                      0x003F0000L
28420 #define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK                                                                     0x10000000L
28421 #define SQ_WAVE_TRAPSTS__DP_RATE_MASK                                                                         0xE0000000L
28422 //SQ_WAVE_HW_ID
28423 #define SQ_WAVE_HW_ID__WAVE_ID__SHIFT                                                                         0x0
28424 #define SQ_WAVE_HW_ID__SIMD_ID__SHIFT                                                                         0x4
28425 #define SQ_WAVE_HW_ID__PIPE_ID__SHIFT                                                                         0x6
28426 #define SQ_WAVE_HW_ID__CU_ID__SHIFT                                                                           0x8
28427 #define SQ_WAVE_HW_ID__SH_ID__SHIFT                                                                           0xc
28428 #define SQ_WAVE_HW_ID__SE_ID__SHIFT                                                                           0xd
28429 #define SQ_WAVE_HW_ID__TG_ID__SHIFT                                                                           0x10
28430 #define SQ_WAVE_HW_ID__VM_ID__SHIFT                                                                           0x14
28431 #define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT                                                                        0x18
28432 #define SQ_WAVE_HW_ID__STATE_ID__SHIFT                                                                        0x1b
28433 #define SQ_WAVE_HW_ID__ME_ID__SHIFT                                                                           0x1e
28434 #define SQ_WAVE_HW_ID__WAVE_ID_MASK                                                                           0x0000000FL
28435 #define SQ_WAVE_HW_ID__SIMD_ID_MASK                                                                           0x00000030L
28436 #define SQ_WAVE_HW_ID__PIPE_ID_MASK                                                                           0x000000C0L
28437 #define SQ_WAVE_HW_ID__CU_ID_MASK                                                                             0x00000F00L
28438 #define SQ_WAVE_HW_ID__SH_ID_MASK                                                                             0x00001000L
28439 #define SQ_WAVE_HW_ID__SE_ID_MASK                                                                             0x00006000L
28440 #define SQ_WAVE_HW_ID__TG_ID_MASK                                                                             0x000F0000L
28441 #define SQ_WAVE_HW_ID__VM_ID_MASK                                                                             0x00F00000L
28442 #define SQ_WAVE_HW_ID__QUEUE_ID_MASK                                                                          0x07000000L
28443 #define SQ_WAVE_HW_ID__STATE_ID_MASK                                                                          0x38000000L
28444 #define SQ_WAVE_HW_ID__ME_ID_MASK                                                                             0xC0000000L
28445 //SQ_WAVE_GPR_ALLOC
28446 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT                                                                   0x0
28447 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT                                                                   0x8
28448 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT                                                                   0x10
28449 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT                                                                   0x18
28450 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK                                                                     0x0000003FL
28451 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK                                                                     0x00003F00L
28452 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK                                                                     0x003F0000L
28453 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK                                                                     0x0F000000L
28454 //SQ_WAVE_LDS_ALLOC
28455 #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT                                                                    0x0
28456 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT                                                                    0xc
28457 #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK                                                                      0x000000FFL
28458 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK                                                                      0x001FF000L
28459 //SQ_WAVE_IB_STS
28460 #define SQ_WAVE_IB_STS__VM_CNT__SHIFT                                                                         0x0
28461 #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT                                                                        0x4
28462 #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT                                                                       0x8
28463 #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT                                                                       0xc
28464 #define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT                                                                   0xf
28465 #define SQ_WAVE_IB_STS__RCNT__SHIFT                                                                           0x10
28466 #define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT                                                                      0x16
28467 #define SQ_WAVE_IB_STS__VM_CNT_MASK                                                                           0x0000000FL
28468 #define SQ_WAVE_IB_STS__EXP_CNT_MASK                                                                          0x00000070L
28469 #define SQ_WAVE_IB_STS__LGKM_CNT_MASK                                                                         0x00000F00L
28470 #define SQ_WAVE_IB_STS__VALU_CNT_MASK                                                                         0x00007000L
28471 #define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK                                                                     0x00008000L
28472 #define SQ_WAVE_IB_STS__RCNT_MASK                                                                             0x001F0000L
28473 #define SQ_WAVE_IB_STS__VM_CNT_HI_MASK                                                                        0x00C00000L
28474 //SQ_WAVE_PC_LO
28475 #define SQ_WAVE_PC_LO__PC_LO__SHIFT                                                                           0x0
28476 #define SQ_WAVE_PC_LO__PC_LO_MASK                                                                             0xFFFFFFFFL
28477 //SQ_WAVE_PC_HI
28478 #define SQ_WAVE_PC_HI__PC_HI__SHIFT                                                                           0x0
28479 #define SQ_WAVE_PC_HI__PC_HI_MASK                                                                             0x0000FFFFL
28480 //SQ_WAVE_INST_DW0
28481 #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT                                                                     0x0
28482 #define SQ_WAVE_INST_DW0__INST_DW0_MASK                                                                       0xFFFFFFFFL
28483 //SQ_WAVE_INST_DW1
28484 #define SQ_WAVE_INST_DW1__INST_DW1__SHIFT                                                                     0x0
28485 #define SQ_WAVE_INST_DW1__INST_DW1_MASK                                                                       0xFFFFFFFFL
28486 //SQ_WAVE_IB_DBG0
28487 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT                                                                       0x0
28488 #define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT                                                                    0x3
28489 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT                                                                  0x4
28490 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT                                                               0x5
28491 #define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT                                                                     0x8
28492 #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT                                                                     0xa
28493 #define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT                                                                   0x10
28494 #define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT                                                                        0x18
28495 #define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT                                                                        0x1a
28496 #define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT                                                                       0x1b
28497 #define SQ_WAVE_IB_DBG0__KILL__SHIFT                                                                          0x1d
28498 #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT                                                              0x1e
28499 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT                                                            0x1f
28500 #define SQ_WAVE_IB_DBG0__IBUF_ST_MASK                                                                         0x00000007L
28501 #define SQ_WAVE_IB_DBG0__PC_INVALID_MASK                                                                      0x00000008L
28502 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK                                                                    0x00000010L
28503 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK                                                                 0x000000E0L
28504 #define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK                                                                       0x00000300L
28505 #define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK                                                                       0x00000C00L
28506 #define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK                                                                     0x000F0000L
28507 #define SQ_WAVE_IB_DBG0__ECC_ST_MASK                                                                          0x03000000L
28508 #define SQ_WAVE_IB_DBG0__IS_HYB_MASK                                                                          0x04000000L
28509 #define SQ_WAVE_IB_DBG0__HYB_CNT_MASK                                                                         0x18000000L
28510 #define SQ_WAVE_IB_DBG0__KILL_MASK                                                                            0x20000000L
28511 #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK                                                                0x40000000L
28512 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK                                                              0x80000000L
28513 //SQ_WAVE_IB_DBG1
28514 #define SQ_WAVE_IB_DBG1__IXNACK__SHIFT                                                                        0x0
28515 #define SQ_WAVE_IB_DBG1__XNACK__SHIFT                                                                         0x1
28516 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT                                                                 0x2
28517 #define SQ_WAVE_IB_DBG1__XCNT__SHIFT                                                                          0x4
28518 #define SQ_WAVE_IB_DBG1__QCNT__SHIFT                                                                          0xb
28519 #define SQ_WAVE_IB_DBG1__RCNT__SHIFT                                                                          0x12
28520 #define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT                                                                      0x19
28521 #define SQ_WAVE_IB_DBG1__IXNACK_MASK                                                                          0x00000001L
28522 #define SQ_WAVE_IB_DBG1__XNACK_MASK                                                                           0x00000002L
28523 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK                                                                   0x00000004L
28524 #define SQ_WAVE_IB_DBG1__XCNT_MASK                                                                            0x000001F0L
28525 #define SQ_WAVE_IB_DBG1__QCNT_MASK                                                                            0x0000F800L
28526 #define SQ_WAVE_IB_DBG1__RCNT_MASK                                                                            0x007C0000L
28527 #define SQ_WAVE_IB_DBG1__MISC_CNT_MASK                                                                        0xFE000000L
28528 //SQ_WAVE_FLUSH_IB
28529 #define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT                                                                       0x0
28530 #define SQ_WAVE_FLUSH_IB__UNUSED_MASK                                                                         0xFFFFFFFFL
28531 //SQ_WAVE_TTMP0
28532 #define SQ_WAVE_TTMP0__DATA__SHIFT                                                                            0x0
28533 #define SQ_WAVE_TTMP0__DATA_MASK                                                                              0xFFFFFFFFL
28534 //SQ_WAVE_TTMP1
28535 #define SQ_WAVE_TTMP1__DATA__SHIFT                                                                            0x0
28536 #define SQ_WAVE_TTMP1__DATA_MASK                                                                              0xFFFFFFFFL
28537 //SQ_WAVE_TTMP2
28538 #define SQ_WAVE_TTMP2__DATA__SHIFT                                                                            0x0
28539 #define SQ_WAVE_TTMP2__DATA_MASK                                                                              0xFFFFFFFFL
28540 //SQ_WAVE_TTMP3
28541 #define SQ_WAVE_TTMP3__DATA__SHIFT                                                                            0x0
28542 #define SQ_WAVE_TTMP3__DATA_MASK                                                                              0xFFFFFFFFL
28543 //SQ_WAVE_TTMP4
28544 #define SQ_WAVE_TTMP4__DATA__SHIFT                                                                            0x0
28545 #define SQ_WAVE_TTMP4__DATA_MASK                                                                              0xFFFFFFFFL
28546 //SQ_WAVE_TTMP5
28547 #define SQ_WAVE_TTMP5__DATA__SHIFT                                                                            0x0
28548 #define SQ_WAVE_TTMP5__DATA_MASK                                                                              0xFFFFFFFFL
28549 //SQ_WAVE_TTMP6
28550 #define SQ_WAVE_TTMP6__DATA__SHIFT                                                                            0x0
28551 #define SQ_WAVE_TTMP6__DATA_MASK                                                                              0xFFFFFFFFL
28552 //SQ_WAVE_TTMP7
28553 #define SQ_WAVE_TTMP7__DATA__SHIFT                                                                            0x0
28554 #define SQ_WAVE_TTMP7__DATA_MASK                                                                              0xFFFFFFFFL
28555 //SQ_WAVE_TTMP8
28556 #define SQ_WAVE_TTMP8__DATA__SHIFT                                                                            0x0
28557 #define SQ_WAVE_TTMP8__DATA_MASK                                                                              0xFFFFFFFFL
28558 //SQ_WAVE_TTMP9
28559 #define SQ_WAVE_TTMP9__DATA__SHIFT                                                                            0x0
28560 #define SQ_WAVE_TTMP9__DATA_MASK                                                                              0xFFFFFFFFL
28561 //SQ_WAVE_TTMP10
28562 #define SQ_WAVE_TTMP10__DATA__SHIFT                                                                           0x0
28563 #define SQ_WAVE_TTMP10__DATA_MASK                                                                             0xFFFFFFFFL
28564 //SQ_WAVE_TTMP11
28565 #define SQ_WAVE_TTMP11__DATA__SHIFT                                                                           0x0
28566 #define SQ_WAVE_TTMP11__DATA_MASK                                                                             0xFFFFFFFFL
28567 //SQ_WAVE_TTMP12
28568 #define SQ_WAVE_TTMP12__DATA__SHIFT                                                                           0x0
28569 #define SQ_WAVE_TTMP12__DATA_MASK                                                                             0xFFFFFFFFL
28570 //SQ_WAVE_TTMP13
28571 #define SQ_WAVE_TTMP13__DATA__SHIFT                                                                           0x0
28572 #define SQ_WAVE_TTMP13__DATA_MASK                                                                             0xFFFFFFFFL
28573 //SQ_WAVE_TTMP14
28574 #define SQ_WAVE_TTMP14__DATA__SHIFT                                                                           0x0
28575 #define SQ_WAVE_TTMP14__DATA_MASK                                                                             0xFFFFFFFFL
28576 //SQ_WAVE_TTMP15
28577 #define SQ_WAVE_TTMP15__DATA__SHIFT                                                                           0x0
28578 #define SQ_WAVE_TTMP15__DATA_MASK                                                                             0xFFFFFFFFL
28579 //SQ_WAVE_M0
28580 #define SQ_WAVE_M0__M0__SHIFT                                                                                 0x0
28581 #define SQ_WAVE_M0__M0_MASK                                                                                   0xFFFFFFFFL
28582 //SQ_WAVE_EXEC_LO
28583 #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT                                                                       0x0
28584 #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK                                                                         0xFFFFFFFFL
28585 //SQ_WAVE_EXEC_HI
28586 #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT                                                                       0x0
28587 #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK                                                                         0xFFFFFFFFL
28588 //SQ_INTERRUPT_WORD_AUTO_CTXID
28589 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT                                                     0x0
28590 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT                                                              0x1
28591 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT                                            0x2
28592 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT                                                    0x3
28593 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT                                                    0x4
28594 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT                                                0x5
28595 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT                                                0x6
28596 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT                                                   0x7
28597 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT                                           0x8
28598 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT                                                            0x18
28599 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT                                                         0x1a
28600 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK                                                       0x0000001L
28601 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK                                                                0x0000002L
28602 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK                                              0x0000004L
28603 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK                                                      0x0000008L
28604 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK                                                      0x0000010L
28605 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK                                                  0x0000020L
28606 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK                                                  0x0000040L
28607 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK                                                     0x0000080L
28608 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK                                             0x0000100L
28609 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK                                                              0x3000000L
28610 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK                                                           0xC000000L
28611 //SQ_INTERRUPT_WORD_AUTO_HI
28612 #define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT                                                               0x8
28613 #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT                                                            0xa
28614 #define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK                                                                 0x300L
28615 #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK                                                              0xC00L
28616 //SQ_INTERRUPT_WORD_AUTO_LO
28617 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT                                                        0x0
28618 #define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT                                                                 0x1
28619 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT                                               0x2
28620 #define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT                                                       0x3
28621 #define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT                                                       0x4
28622 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT                                                   0x5
28623 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT                                                   0x6
28624 #define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT                                                      0x7
28625 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT                                              0x8
28626 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK                                                          0x001L
28627 #define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK                                                                   0x002L
28628 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK                                                 0x004L
28629 #define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK                                                         0x008L
28630 #define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK                                                         0x010L
28631 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK                                                     0x020L
28632 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK                                                     0x040L
28633 #define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK                                                        0x080L
28634 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK                                                0x100L
28635 //SQ_INTERRUPT_WORD_CMN_CTXID
28636 #define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT                                                             0x18
28637 #define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT                                                          0x1a
28638 #define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK                                                               0x3000000L
28639 #define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK                                                            0xC000000L
28640 //SQ_INTERRUPT_WORD_CMN_HI
28641 #define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT                                                                0x8
28642 #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT                                                             0xa
28643 #define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK                                                                  0x300L
28644 #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK                                                               0xC00L
28645 //SQ_INTERRUPT_WORD_WAVE_CTXID
28646 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT                                                             0x0
28647 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT                                                            0xc
28648 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT                                                             0xd
28649 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT                                                          0xe
28650 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT                                                          0x12
28651 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT                                                            0x14
28652 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT                                                            0x18
28653 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT                                                         0x1a
28654 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK                                                               0x0000FFFL
28655 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK                                                              0x0001000L
28656 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK                                                               0x0002000L
28657 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK                                                            0x003C000L
28658 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK                                                            0x00C0000L
28659 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK                                                              0x0F00000L
28660 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK                                                              0x3000000L
28661 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK                                                           0xC000000L
28662 //SQ_INTERRUPT_WORD_WAVE_HI
28663 #define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT                                                               0x0
28664 #define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT                                                               0x4
28665 #define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT                                                               0x8
28666 #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT                                                            0xa
28667 #define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK                                                                 0x00FL
28668 #define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK                                                                 0x0F0L
28669 #define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK                                                                 0x300L
28670 #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK                                                              0xC00L
28671 //SQ_INTERRUPT_WORD_WAVE_LO
28672 #define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT                                                                0x0
28673 #define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT                                                               0x18
28674 #define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT                                                                0x19
28675 #define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT                                                             0x1a
28676 #define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT                                                             0x1e
28677 #define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK                                                                  0x00FFFFFFL
28678 #define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK                                                                 0x01000000L
28679 #define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK                                                                  0x02000000L
28680 #define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK                                                               0x3C000000L
28681 #define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK                                                               0xC0000000L
28682 
28683 
28684 // addressBlock: didtind
28685 //DIDT_SQ_CTRL0
28686 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
28687 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
28688 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
28689 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
28690 #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
28691 #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
28692 #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
28693 #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
28694 #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
28695 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
28696 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
28697 #define DIDT_SQ_CTRL0__UNUSED_0__SHIFT                                                                        0x1b
28698 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
28699 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
28700 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
28701 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
28702 #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
28703 #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
28704 #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
28705 #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
28706 #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
28707 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
28708 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
28709 #define DIDT_SQ_CTRL0__UNUSED_0_MASK                                                                          0xF8000000L
28710 //DIDT_SQ_CTRL1
28711 #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT                                                                       0x0
28712 #define DIDT_SQ_CTRL1__MAX_POWER__SHIFT                                                                       0x10
28713 #define DIDT_SQ_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
28714 #define DIDT_SQ_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
28715 //DIDT_SQ_CTRL2
28716 #define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
28717 #define DIDT_SQ_CTRL2__UNUSED_0__SHIFT                                                                        0xe
28718 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
28719 #define DIDT_SQ_CTRL2__UNUSED_1__SHIFT                                                                        0x1a
28720 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
28721 #define DIDT_SQ_CTRL2__UNUSED_2__SHIFT                                                                        0x1f
28722 #define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
28723 #define DIDT_SQ_CTRL2__UNUSED_0_MASK                                                                          0x0000C000L
28724 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
28725 #define DIDT_SQ_CTRL2__UNUSED_1_MASK                                                                          0x04000000L
28726 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
28727 #define DIDT_SQ_CTRL2__UNUSED_2_MASK                                                                          0x80000000L
28728 //DIDT_SQ_STALL_CTRL
28729 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
28730 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
28731 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
28732 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
28733 #define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT                                                                   0x18
28734 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
28735 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
28736 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
28737 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
28738 #define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK                                                                     0xFF000000L
28739 //DIDT_SQ_TUNING_CTRL
28740 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
28741 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
28742 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
28743 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
28744 //DIDT_SQ_STALL_AUTO_RELEASE_CTRL
28745 #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
28746 #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
28747 //DIDT_SQ_CTRL3
28748 #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
28749 #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
28750 #define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
28751 #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
28752 #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
28753 #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
28754 #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
28755 #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
28756 #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
28757 #define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
28758 #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
28759 #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
28760 #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
28761 #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
28762 #define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
28763 #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
28764 #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
28765 #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
28766 #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
28767 #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
28768 #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
28769 #define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
28770 #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
28771 #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
28772 //DIDT_SQ_STALL_PATTERN_1_2
28773 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
28774 #define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                            0xf
28775 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
28776 #define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                            0x1f
28777 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
28778 #define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK                                                              0x00008000L
28779 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
28780 #define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK                                                              0x80000000L
28781 //DIDT_SQ_STALL_PATTERN_3_4
28782 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
28783 #define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                            0xf
28784 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
28785 #define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                            0x1f
28786 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
28787 #define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK                                                              0x00008000L
28788 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
28789 #define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK                                                              0x80000000L
28790 //DIDT_SQ_STALL_PATTERN_5_6
28791 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
28792 #define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                            0xf
28793 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
28794 #define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                            0x1f
28795 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
28796 #define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK                                                              0x00008000L
28797 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
28798 #define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK                                                              0x80000000L
28799 //DIDT_SQ_STALL_PATTERN_7
28800 #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
28801 #define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT                                                              0xf
28802 #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
28803 #define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK                                                                0xFFFF8000L
28804 //DIDT_SQ_WEIGHT0_3
28805 #define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
28806 #define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
28807 #define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
28808 #define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
28809 #define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
28810 #define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
28811 #define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
28812 #define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
28813 //DIDT_SQ_WEIGHT4_7
28814 #define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
28815 #define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
28816 #define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
28817 #define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
28818 #define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
28819 #define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
28820 #define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
28821 #define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
28822 //DIDT_SQ_WEIGHT8_11
28823 #define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
28824 #define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
28825 #define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
28826 #define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
28827 #define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
28828 #define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
28829 #define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
28830 #define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
28831 //DIDT_SQ_EDC_CTRL
28832 #define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
28833 #define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
28834 #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
28835 #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
28836 #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
28837 #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
28838 #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
28839 #define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
28840 #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
28841 #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
28842 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
28843 #define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT                                                                     0x17
28844 #define DIDT_SQ_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
28845 #define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
28846 #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
28847 #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
28848 #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
28849 #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
28850 #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
28851 #define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
28852 #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
28853 #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
28854 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
28855 #define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK                                                                       0xFF800000L
28856 //DIDT_SQ_EDC_THRESHOLD
28857 #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
28858 #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
28859 //DIDT_SQ_EDC_STALL_PATTERN_1_2
28860 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
28861 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                        0xf
28862 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
28863 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                        0x1f
28864 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
28865 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                          0x00008000L
28866 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
28867 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                          0x80000000L
28868 //DIDT_SQ_EDC_STALL_PATTERN_3_4
28869 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
28870 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                        0xf
28871 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
28872 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                        0x1f
28873 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
28874 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                          0x00008000L
28875 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
28876 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                          0x80000000L
28877 //DIDT_SQ_EDC_STALL_PATTERN_5_6
28878 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
28879 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                        0xf
28880 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
28881 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                        0x1f
28882 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
28883 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                          0x00008000L
28884 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
28885 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                          0x80000000L
28886 //DIDT_SQ_EDC_STALL_PATTERN_7
28887 #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
28888 #define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                          0xf
28889 #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
28890 #define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                            0xFFFF8000L
28891 //DIDT_SQ_EDC_STATUS
28892 #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
28893 #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
28894 #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
28895 #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
28896 //DIDT_SQ_EDC_STALL_DELAY_1
28897 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT                                                 0x0
28898 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT                                                 0x8
28899 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT                                                 0x10
28900 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT                                                 0x18
28901 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK                                                   0x000000FFL
28902 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK                                                   0x0000FF00L
28903 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK                                                   0x00FF0000L
28904 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK                                                   0xFF000000L
28905 //DIDT_SQ_EDC_STALL_DELAY_2
28906 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT                                                 0x0
28907 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT                                                 0x8
28908 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT                                                 0x10
28909 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT                                                 0x18
28910 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK                                                   0x000000FFL
28911 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK                                                   0x0000FF00L
28912 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK                                                   0x00FF0000L
28913 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK                                                   0xFF000000L
28914 //DIDT_SQ_EDC_STALL_DELAY_3
28915 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT                                                 0x0
28916 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT                                                 0x8
28917 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT                                                0x10
28918 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT                                                0x18
28919 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK                                                   0x000000FFL
28920 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK                                                   0x0000FF00L
28921 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK                                                  0x00FF0000L
28922 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK                                                  0xFF000000L
28923 //DIDT_SQ_EDC_STALL_DELAY_4
28924 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT                                                0x0
28925 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT                                                0x8
28926 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT                                                0x10
28927 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT                                                0x18
28928 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK                                                  0x000000FFL
28929 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13_MASK                                                  0x0000FF00L
28930 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK                                                  0x00FF0000L
28931 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK                                                  0xFF000000L
28932 //DIDT_SQ_EDC_OVERFLOW
28933 #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
28934 #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
28935 #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
28936 #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
28937 //DIDT_SQ_EDC_ROLLING_POWER_DELTA
28938 #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
28939 #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
28940 //DIDT_DB_CTRL0
28941 #define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
28942 #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
28943 #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
28944 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
28945 #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
28946 #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
28947 #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
28948 #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
28949 #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
28950 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
28951 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
28952 #define DIDT_DB_CTRL0__UNUSED_0__SHIFT                                                                        0x1b
28953 #define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
28954 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
28955 #define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
28956 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
28957 #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
28958 #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
28959 #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
28960 #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
28961 #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
28962 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
28963 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
28964 #define DIDT_DB_CTRL0__UNUSED_0_MASK                                                                          0xF8000000L
28965 //DIDT_DB_CTRL1
28966 #define DIDT_DB_CTRL1__MIN_POWER__SHIFT                                                                       0x0
28967 #define DIDT_DB_CTRL1__MAX_POWER__SHIFT                                                                       0x10
28968 #define DIDT_DB_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
28969 #define DIDT_DB_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
28970 //DIDT_DB_CTRL2
28971 #define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
28972 #define DIDT_DB_CTRL2__UNUSED_0__SHIFT                                                                        0xe
28973 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
28974 #define DIDT_DB_CTRL2__UNUSED_1__SHIFT                                                                        0x1a
28975 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
28976 #define DIDT_DB_CTRL2__UNUSED_2__SHIFT                                                                        0x1f
28977 #define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
28978 #define DIDT_DB_CTRL2__UNUSED_0_MASK                                                                          0x0000C000L
28979 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
28980 #define DIDT_DB_CTRL2__UNUSED_1_MASK                                                                          0x04000000L
28981 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
28982 #define DIDT_DB_CTRL2__UNUSED_2_MASK                                                                          0x80000000L
28983 //DIDT_DB_STALL_CTRL
28984 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
28985 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
28986 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
28987 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
28988 #define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT                                                                   0x18
28989 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
28990 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
28991 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
28992 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
28993 #define DIDT_DB_STALL_CTRL__UNUSED_0_MASK                                                                     0xFF000000L
28994 //DIDT_DB_TUNING_CTRL
28995 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
28996 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
28997 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
28998 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
28999 //DIDT_DB_STALL_AUTO_RELEASE_CTRL
29000 #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
29001 #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
29002 //DIDT_DB_CTRL3
29003 #define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
29004 #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
29005 #define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
29006 #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
29007 #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
29008 #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
29009 #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
29010 #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
29011 #define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
29012 #define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
29013 #define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
29014 #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
29015 #define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
29016 #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
29017 #define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
29018 #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
29019 #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
29020 #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
29021 #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
29022 #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
29023 #define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
29024 #define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
29025 #define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
29026 #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
29027 //DIDT_DB_STALL_PATTERN_1_2
29028 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
29029 #define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                            0xf
29030 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
29031 #define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                            0x1f
29032 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
29033 #define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK                                                              0x00008000L
29034 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
29035 #define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK                                                              0x80000000L
29036 //DIDT_DB_STALL_PATTERN_3_4
29037 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
29038 #define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                            0xf
29039 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
29040 #define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                            0x1f
29041 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
29042 #define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK                                                              0x00008000L
29043 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
29044 #define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK                                                              0x80000000L
29045 //DIDT_DB_STALL_PATTERN_5_6
29046 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
29047 #define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                            0xf
29048 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
29049 #define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                            0x1f
29050 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
29051 #define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK                                                              0x00008000L
29052 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
29053 #define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK                                                              0x80000000L
29054 //DIDT_DB_STALL_PATTERN_7
29055 #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
29056 #define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT                                                              0xf
29057 #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
29058 #define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK                                                                0xFFFF8000L
29059 //DIDT_DB_WEIGHT0_3
29060 #define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
29061 #define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
29062 #define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
29063 #define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
29064 #define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
29065 #define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
29066 #define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
29067 #define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
29068 //DIDT_DB_WEIGHT4_7
29069 #define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
29070 #define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
29071 #define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
29072 #define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
29073 #define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
29074 #define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
29075 #define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
29076 #define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
29077 //DIDT_DB_WEIGHT8_11
29078 #define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
29079 #define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
29080 #define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
29081 #define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
29082 #define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
29083 #define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
29084 #define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
29085 #define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
29086 //DIDT_DB_EDC_CTRL
29087 #define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
29088 #define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
29089 #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
29090 #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
29091 #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
29092 #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
29093 #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
29094 #define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
29095 #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
29096 #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
29097 #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
29098 #define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT                                                                     0x17
29099 #define DIDT_DB_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
29100 #define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
29101 #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
29102 #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
29103 #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
29104 #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
29105 #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
29106 #define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
29107 #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
29108 #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
29109 #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
29110 #define DIDT_DB_EDC_CTRL__UNUSED_0_MASK                                                                       0xFF800000L
29111 //DIDT_DB_EDC_THRESHOLD
29112 #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
29113 #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
29114 //DIDT_DB_EDC_STALL_PATTERN_1_2
29115 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
29116 #define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                        0xf
29117 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
29118 #define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                        0x1f
29119 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
29120 #define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                          0x00008000L
29121 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
29122 #define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                          0x80000000L
29123 //DIDT_DB_EDC_STALL_PATTERN_3_4
29124 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
29125 #define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                        0xf
29126 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
29127 #define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                        0x1f
29128 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
29129 #define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                          0x00008000L
29130 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
29131 #define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                          0x80000000L
29132 //DIDT_DB_EDC_STALL_PATTERN_5_6
29133 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
29134 #define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                        0xf
29135 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
29136 #define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                        0x1f
29137 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
29138 #define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                          0x00008000L
29139 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
29140 #define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                          0x80000000L
29141 //DIDT_DB_EDC_STALL_PATTERN_7
29142 #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
29143 #define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                          0xf
29144 #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
29145 #define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                            0xFFFF8000L
29146 //DIDT_DB_EDC_STATUS
29147 #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
29148 #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
29149 #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
29150 #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
29151 //DIDT_DB_EDC_STALL_DELAY_1
29152 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT                                                 0x0
29153 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT                                                 0x6
29154 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT                                                 0xc
29155 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT                                                 0x12
29156 #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                              0x18
29157 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK                                                   0x0000003FL
29158 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK                                                   0x00000FC0L
29159 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK                                                   0x0003F000L
29160 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK                                                   0x00FC0000L
29161 #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK                                                                0xFF000000L
29162 //DIDT_DB_EDC_OVERFLOW
29163 #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
29164 #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
29165 #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
29166 #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
29167 //DIDT_DB_EDC_ROLLING_POWER_DELTA
29168 #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
29169 #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
29170 //DIDT_TD_CTRL0
29171 #define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
29172 #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
29173 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
29174 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
29175 #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
29176 #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
29177 #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
29178 #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
29179 #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
29180 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
29181 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
29182 #define DIDT_TD_CTRL0__UNUSED_0__SHIFT                                                                        0x1b
29183 #define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
29184 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
29185 #define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
29186 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
29187 #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
29188 #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
29189 #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
29190 #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
29191 #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
29192 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
29193 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
29194 #define DIDT_TD_CTRL0__UNUSED_0_MASK                                                                          0xF8000000L
29195 //DIDT_TD_CTRL1
29196 #define DIDT_TD_CTRL1__MIN_POWER__SHIFT                                                                       0x0
29197 #define DIDT_TD_CTRL1__MAX_POWER__SHIFT                                                                       0x10
29198 #define DIDT_TD_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
29199 #define DIDT_TD_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
29200 //DIDT_TD_CTRL2
29201 #define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
29202 #define DIDT_TD_CTRL2__UNUSED_0__SHIFT                                                                        0xe
29203 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
29204 #define DIDT_TD_CTRL2__UNUSED_1__SHIFT                                                                        0x1a
29205 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
29206 #define DIDT_TD_CTRL2__UNUSED_2__SHIFT                                                                        0x1f
29207 #define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
29208 #define DIDT_TD_CTRL2__UNUSED_0_MASK                                                                          0x0000C000L
29209 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
29210 #define DIDT_TD_CTRL2__UNUSED_1_MASK                                                                          0x04000000L
29211 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
29212 #define DIDT_TD_CTRL2__UNUSED_2_MASK                                                                          0x80000000L
29213 //DIDT_TD_STALL_CTRL
29214 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
29215 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
29216 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
29217 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
29218 #define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT                                                                   0x18
29219 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
29220 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
29221 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
29222 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
29223 #define DIDT_TD_STALL_CTRL__UNUSED_0_MASK                                                                     0xFF000000L
29224 //DIDT_TD_TUNING_CTRL
29225 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
29226 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
29227 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
29228 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
29229 //DIDT_TD_STALL_AUTO_RELEASE_CTRL
29230 #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
29231 #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
29232 //DIDT_TD_CTRL3
29233 #define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
29234 #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
29235 #define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
29236 #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
29237 #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
29238 #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
29239 #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
29240 #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
29241 #define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
29242 #define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
29243 #define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
29244 #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
29245 #define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
29246 #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
29247 #define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
29248 #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
29249 #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
29250 #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
29251 #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
29252 #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
29253 #define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
29254 #define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
29255 #define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
29256 #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
29257 //DIDT_TD_STALL_PATTERN_1_2
29258 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
29259 #define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                            0xf
29260 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
29261 #define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                            0x1f
29262 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
29263 #define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK                                                              0x00008000L
29264 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
29265 #define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK                                                              0x80000000L
29266 //DIDT_TD_STALL_PATTERN_3_4
29267 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
29268 #define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                            0xf
29269 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
29270 #define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                            0x1f
29271 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
29272 #define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK                                                              0x00008000L
29273 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
29274 #define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK                                                              0x80000000L
29275 //DIDT_TD_STALL_PATTERN_5_6
29276 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
29277 #define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                            0xf
29278 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
29279 #define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                            0x1f
29280 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
29281 #define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK                                                              0x00008000L
29282 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
29283 #define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK                                                              0x80000000L
29284 //DIDT_TD_STALL_PATTERN_7
29285 #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
29286 #define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT                                                              0xf
29287 #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
29288 #define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK                                                                0xFFFF8000L
29289 //DIDT_TD_WEIGHT0_3
29290 #define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
29291 #define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
29292 #define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
29293 #define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
29294 #define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
29295 #define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
29296 #define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
29297 #define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
29298 //DIDT_TD_WEIGHT4_7
29299 #define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
29300 #define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
29301 #define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
29302 #define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
29303 #define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
29304 #define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
29305 #define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
29306 #define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
29307 //DIDT_TD_WEIGHT8_11
29308 #define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
29309 #define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
29310 #define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
29311 #define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
29312 #define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
29313 #define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
29314 #define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
29315 #define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
29316 //DIDT_TD_EDC_CTRL
29317 #define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
29318 #define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
29319 #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
29320 #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
29321 #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
29322 #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
29323 #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
29324 #define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
29325 #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
29326 #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
29327 #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
29328 #define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT                                                                     0x17
29329 #define DIDT_TD_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
29330 #define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
29331 #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
29332 #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
29333 #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
29334 #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
29335 #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
29336 #define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
29337 #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
29338 #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
29339 #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
29340 #define DIDT_TD_EDC_CTRL__UNUSED_0_MASK                                                                       0xFF800000L
29341 //DIDT_TD_EDC_THRESHOLD
29342 #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
29343 #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
29344 //DIDT_TD_EDC_STALL_PATTERN_1_2
29345 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
29346 #define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                        0xf
29347 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
29348 #define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                        0x1f
29349 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
29350 #define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                          0x00008000L
29351 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
29352 #define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                          0x80000000L
29353 //DIDT_TD_EDC_STALL_PATTERN_3_4
29354 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
29355 #define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                        0xf
29356 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
29357 #define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                        0x1f
29358 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
29359 #define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                          0x00008000L
29360 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
29361 #define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                          0x80000000L
29362 //DIDT_TD_EDC_STALL_PATTERN_5_6
29363 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
29364 #define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                        0xf
29365 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
29366 #define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                        0x1f
29367 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
29368 #define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                          0x00008000L
29369 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
29370 #define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                          0x80000000L
29371 //DIDT_TD_EDC_STALL_PATTERN_7
29372 #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
29373 #define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                          0xf
29374 #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
29375 #define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                            0xFFFF8000L
29376 //DIDT_TD_EDC_STATUS
29377 #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
29378 #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
29379 #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
29380 #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
29381 //DIDT_TD_EDC_STALL_DELAY_1
29382 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT                                                 0x0
29383 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT                                                 0x8
29384 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT                                                 0x10
29385 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT                                                 0x18
29386 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK                                                   0x000000FFL
29387 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK                                                   0x0000FF00L
29388 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK                                                   0x00FF0000L
29389 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK                                                   0xFF000000L
29390 //DIDT_TD_EDC_STALL_DELAY_2
29391 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT                                                 0x0
29392 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT                                                 0x8
29393 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT                                                 0x10
29394 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT                                                 0x18
29395 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK                                                   0x000000FFL
29396 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK                                                   0x0000FF00L
29397 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK                                                   0x00FF0000L
29398 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK                                                   0xFF000000L
29399 //DIDT_TD_EDC_STALL_DELAY_3
29400 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT                                                 0x0
29401 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT                                                 0x8
29402 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT                                                0x10
29403 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11__SHIFT                                                0x18
29404 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK                                                   0x000000FFL
29405 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK                                                   0x0000FF00L
29406 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK                                                  0x00FF0000L
29407 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11_MASK                                                  0xFF000000L
29408 //DIDT_TD_EDC_STALL_DELAY_4
29409 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12__SHIFT                                                0x0
29410 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13__SHIFT                                                0x8
29411 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14__SHIFT                                                0x10
29412 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15__SHIFT                                                0x18
29413 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12_MASK                                                  0x000000FFL
29414 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13_MASK                                                  0x0000FF00L
29415 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14_MASK                                                  0x00FF0000L
29416 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15_MASK                                                  0xFF000000L
29417 //DIDT_TD_EDC_OVERFLOW
29418 #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
29419 #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
29420 #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
29421 #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
29422 //DIDT_TD_EDC_ROLLING_POWER_DELTA
29423 #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
29424 #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
29425 //DIDT_TCP_CTRL0
29426 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT                                                                   0x0
29427 #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
29428 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT                                                                  0x3
29429 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                           0x4
29430 #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                             0x5
29431 #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                            0x6
29432 #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                     0x7
29433 #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                        0x8
29434 #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                               0x18
29435 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                            0x19
29436 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                 0x1a
29437 #define DIDT_TCP_CTRL0__UNUSED_0__SHIFT                                                                       0x1b
29438 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK                                                                     0x00000001L
29439 #define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK                                                                     0x00000006L
29440 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK                                                                    0x00000008L
29441 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                             0x00000010L
29442 #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                               0x00000020L
29443 #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                              0x00000040L
29444 #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                       0x00000080L
29445 #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                          0x00FFFF00L
29446 #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                 0x01000000L
29447 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                              0x02000000L
29448 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                   0x04000000L
29449 #define DIDT_TCP_CTRL0__UNUSED_0_MASK                                                                         0xF8000000L
29450 //DIDT_TCP_CTRL1
29451 #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT                                                                      0x0
29452 #define DIDT_TCP_CTRL1__MAX_POWER__SHIFT                                                                      0x10
29453 #define DIDT_TCP_CTRL1__MIN_POWER_MASK                                                                        0x0000FFFFL
29454 #define DIDT_TCP_CTRL1__MAX_POWER_MASK                                                                        0xFFFF0000L
29455 //DIDT_TCP_CTRL2
29456 #define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT                                                                0x0
29457 #define DIDT_TCP_CTRL2__UNUSED_0__SHIFT                                                                       0xe
29458 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                       0x10
29459 #define DIDT_TCP_CTRL2__UNUSED_1__SHIFT                                                                       0x1a
29460 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                       0x1b
29461 #define DIDT_TCP_CTRL2__UNUSED_2__SHIFT                                                                       0x1f
29462 #define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK                                                                  0x00003FFFL
29463 #define DIDT_TCP_CTRL2__UNUSED_0_MASK                                                                         0x0000C000L
29464 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                         0x03FF0000L
29465 #define DIDT_TCP_CTRL2__UNUSED_1_MASK                                                                         0x04000000L
29466 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                         0x78000000L
29467 #define DIDT_TCP_CTRL2__UNUSED_2_MASK                                                                         0x80000000L
29468 //DIDT_TCP_STALL_CTRL
29469 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                       0x0
29470 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                       0x6
29471 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                0xc
29472 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                0x12
29473 #define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT                                                                  0x18
29474 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                         0x0000003FL
29475 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                         0x00000FC0L
29476 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                  0x0003F000L
29477 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                  0x00FC0000L
29478 #define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK                                                                    0xFF000000L
29479 //DIDT_TCP_TUNING_CTRL
29480 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                       0x0
29481 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                       0xe
29482 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                         0x00003FFFL
29483 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                         0x0FFFC000L
29484 //DIDT_TCP_STALL_AUTO_RELEASE_CTRL
29485 #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                 0x0
29486 #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                   0x00FFFFFFL
29487 //DIDT_TCP_CTRL3
29488 #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                 0x0
29489 #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                        0x1
29490 #define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT                                                                0x2
29491 #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                   0x4
29492 #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                        0x9
29493 #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                    0xe
29494 #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x16
29495 #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x17
29496 #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT                                                               0x18
29497 #define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT                                                                 0x19
29498 #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT                                                               0x1b
29499 #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                            0x1c
29500 #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK                                                                   0x00000001L
29501 #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                          0x00000002L
29502 #define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK                                                                  0x0000000CL
29503 #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                     0x000001F0L
29504 #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                          0x00003E00L
29505 #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                      0x003FC000L
29506 #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                            0x00400000L
29507 #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                            0x00800000L
29508 #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK                                                                 0x01000000L
29509 #define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK                                                                   0x06000000L
29510 #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK                                                                 0x08000000L
29511 #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                              0x10000000L
29512 //DIDT_TCP_STALL_PATTERN_1_2
29513 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                               0x0
29514 #define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                           0xf
29515 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                               0x10
29516 #define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                           0x1f
29517 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                 0x00007FFFL
29518 #define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK                                                             0x00008000L
29519 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                 0x7FFF0000L
29520 #define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK                                                             0x80000000L
29521 //DIDT_TCP_STALL_PATTERN_3_4
29522 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                               0x0
29523 #define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                           0xf
29524 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                               0x10
29525 #define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                           0x1f
29526 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                 0x00007FFFL
29527 #define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK                                                             0x00008000L
29528 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                 0x7FFF0000L
29529 #define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK                                                             0x80000000L
29530 //DIDT_TCP_STALL_PATTERN_5_6
29531 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                               0x0
29532 #define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                           0xf
29533 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                               0x10
29534 #define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                           0x1f
29535 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                 0x00007FFFL
29536 #define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK                                                             0x00008000L
29537 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                 0x7FFF0000L
29538 #define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK                                                             0x80000000L
29539 //DIDT_TCP_STALL_PATTERN_7
29540 #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                 0x0
29541 #define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT                                                             0xf
29542 #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                   0x00007FFFL
29543 #define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK                                                               0xFFFF8000L
29544 //DIDT_TCP_WEIGHT0_3
29545 #define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT                                                                    0x0
29546 #define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT                                                                    0x8
29547 #define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT                                                                    0x10
29548 #define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT                                                                    0x18
29549 #define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK                                                                      0x000000FFL
29550 #define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK                                                                      0x0000FF00L
29551 #define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK                                                                      0x00FF0000L
29552 #define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK                                                                      0xFF000000L
29553 //DIDT_TCP_WEIGHT4_7
29554 #define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT                                                                    0x0
29555 #define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT                                                                    0x8
29556 #define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT                                                                    0x10
29557 #define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT                                                                    0x18
29558 #define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK                                                                      0x000000FFL
29559 #define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK                                                                      0x0000FF00L
29560 #define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK                                                                      0x00FF0000L
29561 #define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK                                                                      0xFF000000L
29562 //DIDT_TCP_WEIGHT8_11
29563 #define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT                                                                   0x0
29564 #define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT                                                                   0x8
29565 #define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT                                                                  0x10
29566 #define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT                                                                  0x18
29567 #define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK                                                                     0x000000FFL
29568 #define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK                                                                     0x0000FF00L
29569 #define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK                                                                    0x00FF0000L
29570 #define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK                                                                    0xFF000000L
29571 //DIDT_TCP_EDC_CTRL
29572 #define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT                                                                      0x0
29573 #define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT                                                                  0x1
29574 #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                         0x2
29575 #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                             0x3
29576 #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                 0x4
29577 #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                  0x9
29578 #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                    0x11
29579 #define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT                                                                   0x12
29580 #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                         0x13
29581 #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                        0x15
29582 #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                        0x16
29583 #define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT                                                                    0x17
29584 #define DIDT_TCP_EDC_CTRL__EDC_EN_MASK                                                                        0x00000001L
29585 #define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK                                                                    0x00000002L
29586 #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                           0x00000004L
29587 #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK                                                               0x00000008L
29588 #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                   0x000001F0L
29589 #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                    0x0001FE00L
29590 #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                      0x00020000L
29591 #define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK                                                                     0x00040000L
29592 #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                           0x00180000L
29593 #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                          0x00200000L
29594 #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                          0x00400000L
29595 #define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK                                                                      0xFF800000L
29596 //DIDT_TCP_EDC_THRESHOLD
29597 #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                          0x0
29598 #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                            0xFFFFFFFFL
29599 //DIDT_TCP_EDC_STALL_PATTERN_1_2
29600 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                            0x0
29601 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                       0xf
29602 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                            0x10
29603 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                       0x1f
29604 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                              0x00007FFFL
29605 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                         0x00008000L
29606 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                              0x7FFF0000L
29607 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                         0x80000000L
29608 //DIDT_TCP_EDC_STALL_PATTERN_3_4
29609 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                            0x0
29610 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                       0xf
29611 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                            0x10
29612 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                       0x1f
29613 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                              0x00007FFFL
29614 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                         0x00008000L
29615 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                              0x7FFF0000L
29616 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                         0x80000000L
29617 //DIDT_TCP_EDC_STALL_PATTERN_5_6
29618 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                            0x0
29619 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                       0xf
29620 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                            0x10
29621 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                       0x1f
29622 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                              0x00007FFFL
29623 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                         0x00008000L
29624 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                              0x7FFF0000L
29625 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                         0x80000000L
29626 //DIDT_TCP_EDC_STALL_PATTERN_7
29627 #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                              0x0
29628 #define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                         0xf
29629 #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                0x00007FFFL
29630 #define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                           0xFFFF8000L
29631 //DIDT_TCP_EDC_STATUS
29632 #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                             0x0
29633 #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                        0x1
29634 #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK                                                               0x00000001L
29635 #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                          0x0000000EL
29636 //DIDT_TCP_EDC_STALL_DELAY_1
29637 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT                                               0x0
29638 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT                                               0x8
29639 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT                                               0x10
29640 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT                                               0x18
29641 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK                                                 0x000000FFL
29642 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK                                                 0x0000FF00L
29643 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK                                                 0x00FF0000L
29644 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK                                                 0xFF000000L
29645 //DIDT_TCP_EDC_STALL_DELAY_2
29646 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT                                               0x0
29647 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT                                               0x8
29648 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT                                               0x10
29649 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT                                               0x18
29650 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK                                                 0x000000FFL
29651 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK                                                 0x0000FF00L
29652 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK                                                 0x00FF0000L
29653 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK                                                 0xFF000000L
29654 //DIDT_TCP_EDC_STALL_DELAY_3
29655 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT                                               0x0
29656 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT                                               0x8
29657 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT                                              0x10
29658 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11__SHIFT                                              0x18
29659 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK                                                 0x000000FFL
29660 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK                                                 0x0000FF00L
29661 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK                                                0x00FF0000L
29662 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11_MASK                                                0xFF000000L
29663 //DIDT_TCP_EDC_STALL_DELAY_4
29664 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12__SHIFT                                              0x0
29665 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13__SHIFT                                              0x8
29666 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14__SHIFT                                              0x10
29667 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15__SHIFT                                              0x18
29668 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12_MASK                                                0x000000FFL
29669 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13_MASK                                                0x0000FF00L
29670 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14_MASK                                                0x00FF0000L
29671 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15_MASK                                                0xFF000000L
29672 //DIDT_TCP_EDC_OVERFLOW
29673 #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                        0x0
29674 #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                     0x1
29675 #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                          0x00000001L
29676 #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                       0x0001FFFEL
29677 //DIDT_TCP_EDC_ROLLING_POWER_DELTA
29678 #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                      0x0
29679 #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                        0xFFFFFFFFL
29680 //DIDT_DBR_CTRL0
29681 #define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT                                                                   0x0
29682 #define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
29683 #define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT                                                                  0x3
29684 #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                           0x4
29685 #define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                             0x5
29686 #define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                            0x6
29687 #define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                     0x7
29688 #define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                        0x8
29689 #define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                               0x18
29690 #define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                            0x19
29691 #define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                 0x1a
29692 #define DIDT_DBR_CTRL0__UNUSED_0__SHIFT                                                                       0x1b
29693 #define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK                                                                     0x00000001L
29694 #define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK                                                                     0x00000006L
29695 #define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK                                                                    0x00000008L
29696 #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                             0x00000010L
29697 #define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                               0x00000020L
29698 #define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                              0x00000040L
29699 #define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                       0x00000080L
29700 #define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                          0x00FFFF00L
29701 #define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                 0x01000000L
29702 #define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                              0x02000000L
29703 #define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                   0x04000000L
29704 #define DIDT_DBR_CTRL0__UNUSED_0_MASK                                                                         0xF8000000L
29705 //DIDT_DBR_CTRL1
29706 #define DIDT_DBR_CTRL1__MIN_POWER__SHIFT                                                                      0x0
29707 #define DIDT_DBR_CTRL1__MAX_POWER__SHIFT                                                                      0x10
29708 #define DIDT_DBR_CTRL1__MIN_POWER_MASK                                                                        0x0000FFFFL
29709 #define DIDT_DBR_CTRL1__MAX_POWER_MASK                                                                        0xFFFF0000L
29710 //DIDT_DBR_CTRL2
29711 #define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT                                                                0x0
29712 #define DIDT_DBR_CTRL2__UNUSED_0__SHIFT                                                                       0xe
29713 #define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                       0x10
29714 #define DIDT_DBR_CTRL2__UNUSED_1__SHIFT                                                                       0x1a
29715 #define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                       0x1b
29716 #define DIDT_DBR_CTRL2__UNUSED_2__SHIFT                                                                       0x1f
29717 #define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK                                                                  0x00003FFFL
29718 #define DIDT_DBR_CTRL2__UNUSED_0_MASK                                                                         0x0000C000L
29719 #define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                         0x03FF0000L
29720 #define DIDT_DBR_CTRL2__UNUSED_1_MASK                                                                         0x04000000L
29721 #define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                         0x78000000L
29722 #define DIDT_DBR_CTRL2__UNUSED_2_MASK                                                                         0x80000000L
29723 //DIDT_DBR_STALL_CTRL
29724 #define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                       0x0
29725 #define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                       0x6
29726 #define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                0xc
29727 #define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                0x12
29728 #define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT                                                                  0x18
29729 #define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                         0x0000003FL
29730 #define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                         0x00000FC0L
29731 #define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                  0x0003F000L
29732 #define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                  0x00FC0000L
29733 #define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK                                                                    0xFF000000L
29734 //DIDT_DBR_TUNING_CTRL
29735 #define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                       0x0
29736 #define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                       0xe
29737 #define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                         0x00003FFFL
29738 #define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                         0x0FFFC000L
29739 //DIDT_DBR_STALL_AUTO_RELEASE_CTRL
29740 #define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                 0x0
29741 #define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                   0x00FFFFFFL
29742 //DIDT_DBR_CTRL3
29743 #define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                 0x0
29744 #define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                        0x1
29745 #define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT                                                                0x2
29746 #define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                   0x4
29747 #define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                        0x9
29748 #define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                    0xe
29749 #define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x16
29750 #define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x17
29751 #define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT                                                               0x18
29752 #define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT                                                                 0x19
29753 #define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT                                                               0x1b
29754 #define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                            0x1c
29755 #define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK                                                                   0x00000001L
29756 #define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                          0x00000002L
29757 #define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK                                                                  0x0000000CL
29758 #define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                     0x000001F0L
29759 #define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                          0x00003E00L
29760 #define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                      0x003FC000L
29761 #define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                            0x00400000L
29762 #define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                            0x00800000L
29763 #define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK                                                                 0x01000000L
29764 #define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK                                                                   0x06000000L
29765 #define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK                                                                 0x08000000L
29766 #define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                              0x10000000L
29767 //DIDT_DBR_STALL_PATTERN_1_2
29768 #define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                               0x0
29769 #define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                           0xf
29770 #define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                               0x10
29771 #define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                           0x1f
29772 #define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                 0x00007FFFL
29773 #define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK                                                             0x00008000L
29774 #define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                 0x7FFF0000L
29775 #define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK                                                             0x80000000L
29776 //DIDT_DBR_STALL_PATTERN_3_4
29777 #define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                               0x0
29778 #define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                           0xf
29779 #define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                               0x10
29780 #define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                           0x1f
29781 #define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                 0x00007FFFL
29782 #define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK                                                             0x00008000L
29783 #define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                 0x7FFF0000L
29784 #define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK                                                             0x80000000L
29785 //DIDT_DBR_STALL_PATTERN_5_6
29786 #define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                               0x0
29787 #define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                           0xf
29788 #define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                               0x10
29789 #define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                           0x1f
29790 #define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                 0x00007FFFL
29791 #define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK                                                             0x00008000L
29792 #define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                 0x7FFF0000L
29793 #define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK                                                             0x80000000L
29794 //DIDT_DBR_STALL_PATTERN_7
29795 #define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                 0x0
29796 #define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT                                                             0xf
29797 #define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                   0x00007FFFL
29798 #define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK                                                               0xFFFF8000L
29799 //DIDT_DBR_WEIGHT0_3
29800 #define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT                                                                    0x0
29801 #define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT                                                                    0x8
29802 #define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT                                                                    0x10
29803 #define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT                                                                    0x18
29804 #define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK                                                                      0x000000FFL
29805 #define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK                                                                      0x0000FF00L
29806 #define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK                                                                      0x00FF0000L
29807 #define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK                                                                      0xFF000000L
29808 //DIDT_DBR_WEIGHT4_7
29809 #define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT                                                                    0x0
29810 #define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT                                                                    0x8
29811 #define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT                                                                    0x10
29812 #define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT                                                                    0x18
29813 #define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK                                                                      0x000000FFL
29814 #define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK                                                                      0x0000FF00L
29815 #define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK                                                                      0x00FF0000L
29816 #define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK                                                                      0xFF000000L
29817 //DIDT_DBR_WEIGHT8_11
29818 #define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT                                                                   0x0
29819 #define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT                                                                   0x8
29820 #define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT                                                                  0x10
29821 #define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT                                                                  0x18
29822 #define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK                                                                     0x000000FFL
29823 #define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK                                                                     0x0000FF00L
29824 #define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK                                                                    0x00FF0000L
29825 #define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK                                                                    0xFF000000L
29826 //DIDT_DBR_EDC_CTRL
29827 #define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT                                                                      0x0
29828 #define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT                                                                  0x1
29829 #define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                         0x2
29830 #define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                             0x3
29831 #define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                 0x4
29832 #define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                  0x9
29833 #define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                    0x11
29834 #define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT                                                                   0x12
29835 #define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                         0x13
29836 #define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                        0x15
29837 #define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                        0x16
29838 #define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT                                                                    0x17
29839 #define DIDT_DBR_EDC_CTRL__EDC_EN_MASK                                                                        0x00000001L
29840 #define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK                                                                    0x00000002L
29841 #define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                           0x00000004L
29842 #define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK                                                               0x00000008L
29843 #define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                   0x000001F0L
29844 #define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                    0x0001FE00L
29845 #define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                      0x00020000L
29846 #define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK                                                                     0x00040000L
29847 #define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                           0x00180000L
29848 #define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                          0x00200000L
29849 #define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                          0x00400000L
29850 #define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK                                                                      0xFF800000L
29851 //DIDT_DBR_EDC_THRESHOLD
29852 #define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                          0x0
29853 #define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                            0xFFFFFFFFL
29854 //DIDT_DBR_EDC_STALL_PATTERN_1_2
29855 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                            0x0
29856 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                       0xf
29857 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                            0x10
29858 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                       0x1f
29859 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                              0x00007FFFL
29860 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                         0x00008000L
29861 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                              0x7FFF0000L
29862 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                         0x80000000L
29863 //DIDT_DBR_EDC_STALL_PATTERN_3_4
29864 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                            0x0
29865 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                       0xf
29866 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                            0x10
29867 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                       0x1f
29868 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                              0x00007FFFL
29869 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                         0x00008000L
29870 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                              0x7FFF0000L
29871 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                         0x80000000L
29872 //DIDT_DBR_EDC_STALL_PATTERN_5_6
29873 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                            0x0
29874 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                       0xf
29875 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                            0x10
29876 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                       0x1f
29877 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                              0x00007FFFL
29878 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                         0x00008000L
29879 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                              0x7FFF0000L
29880 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                         0x80000000L
29881 //DIDT_DBR_EDC_STALL_PATTERN_7
29882 #define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                              0x0
29883 #define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                         0xf
29884 #define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                0x00007FFFL
29885 #define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                           0xFFFF8000L
29886 //DIDT_DBR_EDC_STATUS
29887 #define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                             0x0
29888 #define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                        0x1
29889 #define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT                                                                  0x4
29890 #define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK                                                               0x00000001L
29891 #define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                          0x0000000EL
29892 #define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK                                                                    0xFFFFFFF0L
29893 //DIDT_DBR_EDC_STALL_DELAY_1
29894 #define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT                                               0x0
29895 #define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1__SHIFT                                               0x3
29896 #define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                             0x6
29897 #define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK                                                 0x00000007L
29898 #define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1_MASK                                                 0x00000038L
29899 #define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK                                                               0xFFFFFFC0L
29900 //DIDT_DBR_EDC_OVERFLOW
29901 #define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                        0x0
29902 #define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                     0x1
29903 #define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                          0x00000001L
29904 #define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                       0x0001FFFEL
29905 //DIDT_DBR_EDC_ROLLING_POWER_DELTA
29906 #define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                      0x0
29907 #define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                        0xFFFFFFFFL
29908 //DIDT_SQ_STALL_EVENT_COUNTER
29909 #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
29910 #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
29911 //DIDT_DB_STALL_EVENT_COUNTER
29912 #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
29913 #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
29914 //DIDT_TD_STALL_EVENT_COUNTER
29915 #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
29916 #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
29917 //DIDT_TCP_STALL_EVENT_COUNTER
29918 #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                         0x0
29919 #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                           0xFFFFFFFFL
29920 //DIDT_DBR_STALL_EVENT_COUNTER
29921 #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                         0x0
29922 #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                           0xFFFFFFFFL
29923 
29924 //TA_EDC_CNT
29925 #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT                                                              0x0
29926 #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT                                                              0x2
29927 #define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT__SHIFT                                                              0x4
29928 #define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT__SHIFT                                                              0x6
29929 #define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT__SHIFT                                                              0x8
29930 #define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT__SHIFT                                                              0xa
29931 #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK                                                                0x00000003L
29932 #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK                                                                0x0000000CL
29933 #define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT_MASK                                                                0x00000030L
29934 #define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT_MASK                                                                0x000000C0L
29935 #define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT_MASK                                                                0x00000300L
29936 #define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT_MASK                                                                0x00000C00L
29937 
29938 //TCI_EDC_CNT
29939 #define TCI_EDC_CNT__WRITE_RAM_SED_COUNT__SHIFT                                                               0x0
29940 #define TCI_EDC_CNT__WRITE_RAM_SED_COUNT_MASK                                                                 0x00000003L
29941 
29942 //TCP_EDC_CNT_NEW
29943 #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT                                                           0x0
29944 #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT                                                           0x2
29945 #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT                                                           0x4
29946 #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT                                                           0x6
29947 #define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT__SHIFT                                                            0x8
29948 #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT                                                             0xa
29949 #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT                                                             0xc
29950 #define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT                                                              0xe
29951 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT                                                        0x10
29952 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT                                                        0x12
29953 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT                                                        0x14
29954 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT                                                        0x16
29955 #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK                                                             0x00000003L
29956 #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK                                                             0x0000000CL
29957 #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK                                                             0x00000030L
29958 #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK                                                             0x000000C0L
29959 #define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT_MASK                                                              0x00000300L
29960 #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK                                                               0x00000C00L
29961 #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK                                                               0x00003000L
29962 #define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK                                                                0x0000C000L
29963 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK                                                          0x00030000L
29964 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK                                                          0x000C0000L
29965 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK                                                          0x00300000L
29966 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK                                                          0x00C00000L
29967 
29968 //TD_EDC_CNT
29969 #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT                                                               0x0
29970 #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT                                                               0x2
29971 #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT                                                               0x4
29972 #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT                                                               0x6
29973 #define TD_EDC_CNT__CS_FIFO_SED_COUNT__SHIFT                                                                  0x8
29974 #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK                                                                 0x00000003L
29975 #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK                                                                 0x0000000CL
29976 #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK                                                                 0x00000030L
29977 #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK                                                                 0x000000C0L
29978 #define TD_EDC_CNT__CS_FIFO_SED_COUNT_MASK                                                                    0x00000300L
29979 
29980 #endif