root/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h

INCLUDED FROM

   1 /*
   2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _dce_12_0_OFFSET_HEADER
  22 #define _dce_12_0_OFFSET_HEADER
  23 
  24 
  25 
  26 // addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
  27 // base address: 0x48
  28 #define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR                                                              0x0012
  29 #define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                     0
  30 
  31 
  32 // addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
  33 // base address: 0x4c
  34 #define mmdispdec_VGA_MEM_READ_PAGE_ADDR                                                               0x0014
  35 #define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                      0
  36 
  37 
  38 // addressBlock: dce_dc_dc_perfmon0_dispdec
  39 // base address: 0x0
  40 #define mmDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0020
  41 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
  42 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0021
  43 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
  44 #define mmDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0022
  45 #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
  46 #define mmDC_PERFMON0_PERFMON_CNTL                                                                     0x0023
  47 #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
  48 #define mmDC_PERFMON0_PERFMON_CNTL2                                                                    0x0024
  49 #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
  50 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0025
  51 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
  52 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0026
  53 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
  54 #define mmDC_PERFMON0_PERFMON_HI                                                                       0x0027
  55 #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
  56 #define mmDC_PERFMON0_PERFMON_LOW                                                                      0x0028
  57 #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
  58 
  59 
  60 // addressBlock: dce_dc_dc_perfmon13_dispdec
  61 // base address: 0x30
  62 #define mmDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x002c
  63 #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
  64 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x002d
  65 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
  66 #define mmDC_PERFMON13_PERFCOUNTER_STATE                                                               0x002e
  67 #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
  68 #define mmDC_PERFMON13_PERFMON_CNTL                                                                    0x002f
  69 #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
  70 #define mmDC_PERFMON13_PERFMON_CNTL2                                                                   0x0030
  71 #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
  72 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x0031
  73 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
  74 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x0032
  75 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
  76 #define mmDC_PERFMON13_PERFMON_HI                                                                      0x0033
  77 #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
  78 #define mmDC_PERFMON13_PERFMON_LOW                                                                     0x0034
  79 #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
  80 
  81 
  82 // addressBlock: dce_dc_dc_displaypllregs_dispdec
  83 // base address: 0x0
  84 #define mmPPLL_VREG_CFG                                                                                0x0038
  85 #define mmPPLL_VREG_CFG_BASE_IDX                                                                       2
  86 #define mmPPLL_MODE_CNTL                                                                               0x0039
  87 #define mmPPLL_MODE_CNTL_BASE_IDX                                                                      2
  88 #define mmPPLL_FREQ_CTRL0                                                                              0x003a
  89 #define mmPPLL_FREQ_CTRL0_BASE_IDX                                                                     2
  90 #define mmPPLL_FREQ_CTRL1                                                                              0x003b
  91 #define mmPPLL_FREQ_CTRL1_BASE_IDX                                                                     2
  92 #define mmPPLL_FREQ_CTRL2                                                                              0x003c
  93 #define mmPPLL_FREQ_CTRL2_BASE_IDX                                                                     2
  94 #define mmPPLL_FREQ_CTRL3                                                                              0x003d
  95 #define mmPPLL_FREQ_CTRL3_BASE_IDX                                                                     2
  96 #define mmPPLL_BW_CTRL_COARSE                                                                          0x003e
  97 #define mmPPLL_BW_CTRL_COARSE_BASE_IDX                                                                 2
  98 #define mmPPLL_BW_CTRL_FINE                                                                            0x0040
  99 #define mmPPLL_BW_CTRL_FINE_BASE_IDX                                                                   2
 100 #define mmPPLL_CAL_CTRL                                                                                0x0041
 101 #define mmPPLL_CAL_CTRL_BASE_IDX                                                                       2
 102 #define mmPPLL_LOOP_CTRL                                                                               0x0042
 103 #define mmPPLL_LOOP_CTRL_BASE_IDX                                                                      2
 104 #define mmPPLL_REFCLK_CNTL                                                                             0x0050
 105 #define mmPPLL_REFCLK_CNTL_BASE_IDX                                                                    2
 106 #define mmPPLL_CLKOUT_CNTL                                                                             0x0051
 107 #define mmPPLL_CLKOUT_CNTL_BASE_IDX                                                                    2
 108 #define mmPPLL_DFT_CNTL                                                                                0x0052
 109 #define mmPPLL_DFT_CNTL_BASE_IDX                                                                       2
 110 #define mmPPLL_ANALOG_CNTL                                                                             0x0053
 111 #define mmPPLL_ANALOG_CNTL_BASE_IDX                                                                    2
 112 #define mmPPLL_POSTDIV                                                                                 0x0054
 113 #define mmPPLL_POSTDIV_BASE_IDX                                                                        2
 114 #define mmPPLL_OBSERVE0                                                                                0x0059
 115 #define mmPPLL_OBSERVE0_BASE_IDX                                                                       2
 116 #define mmPPLL_OBSERVE1                                                                                0x005a
 117 #define mmPPLL_OBSERVE1_BASE_IDX                                                                       2
 118 #define mmPPLL_UPDATE_CNTL                                                                             0x005c
 119 #define mmPPLL_UPDATE_CNTL_BASE_IDX                                                                    2
 120 #define mmPPLL_OBSERVE0_OUT                                                                            0x005d
 121 #define mmPPLL_OBSERVE0_OUT_BASE_IDX                                                                   2
 122 
 123 
 124 // addressBlock: dce_dc_dccg_pll0_dispdec
 125 // base address: 0x0
 126 #define mmPLL_MACRO_CNTL_RESERVED0                                                                     0x0038
 127 #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX                                                            2
 128 #define mmPLL_MACRO_CNTL_RESERVED1                                                                     0x0039
 129 #define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX                                                            2
 130 #define mmPLL_MACRO_CNTL_RESERVED2                                                                     0x003a
 131 #define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX                                                            2
 132 #define mmPLL_MACRO_CNTL_RESERVED3                                                                     0x003b
 133 #define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX                                                            2
 134 #define mmPLL_MACRO_CNTL_RESERVED4                                                                     0x003c
 135 #define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX                                                            2
 136 #define mmPLL_MACRO_CNTL_RESERVED5                                                                     0x003d
 137 #define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX                                                            2
 138 #define mmPLL_MACRO_CNTL_RESERVED6                                                                     0x003e
 139 #define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX                                                            2
 140 #define mmPLL_MACRO_CNTL_RESERVED7                                                                     0x003f
 141 #define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX                                                            2
 142 #define mmPLL_MACRO_CNTL_RESERVED8                                                                     0x0040
 143 #define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX                                                            2
 144 #define mmPLL_MACRO_CNTL_RESERVED9                                                                     0x0041
 145 #define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX                                                            2
 146 #define mmPLL_MACRO_CNTL_RESERVED10                                                                    0x0042
 147 #define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX                                                           2
 148 #define mmPLL_MACRO_CNTL_RESERVED11                                                                    0x0043
 149 #define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX                                                           2
 150 #define mmPLL_MACRO_CNTL_RESERVED12                                                                    0x0044
 151 #define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX                                                           2
 152 #define mmPLL_MACRO_CNTL_RESERVED13                                                                    0x0045
 153 #define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX                                                           2
 154 #define mmPLL_MACRO_CNTL_RESERVED14                                                                    0x0046
 155 #define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX                                                           2
 156 #define mmPLL_MACRO_CNTL_RESERVED15                                                                    0x0047
 157 #define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX                                                           2
 158 #define mmPLL_MACRO_CNTL_RESERVED16                                                                    0x0048
 159 #define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX                                                           2
 160 #define mmPLL_MACRO_CNTL_RESERVED17                                                                    0x0049
 161 #define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX                                                           2
 162 #define mmPLL_MACRO_CNTL_RESERVED18                                                                    0x004a
 163 #define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX                                                           2
 164 #define mmPLL_MACRO_CNTL_RESERVED19                                                                    0x004b
 165 #define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX                                                           2
 166 #define mmPLL_MACRO_CNTL_RESERVED20                                                                    0x004c
 167 #define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX                                                           2
 168 #define mmPLL_MACRO_CNTL_RESERVED21                                                                    0x004d
 169 #define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX                                                           2
 170 #define mmPLL_MACRO_CNTL_RESERVED22                                                                    0x004e
 171 #define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX                                                           2
 172 #define mmPLL_MACRO_CNTL_RESERVED23                                                                    0x004f
 173 #define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX                                                           2
 174 #define mmPLL_MACRO_CNTL_RESERVED24                                                                    0x0050
 175 #define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX                                                           2
 176 #define mmPLL_MACRO_CNTL_RESERVED25                                                                    0x0051
 177 #define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX                                                           2
 178 #define mmPLL_MACRO_CNTL_RESERVED26                                                                    0x0052
 179 #define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX                                                           2
 180 #define mmPLL_MACRO_CNTL_RESERVED27                                                                    0x0053
 181 #define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX                                                           2
 182 #define mmPLL_MACRO_CNTL_RESERVED28                                                                    0x0054
 183 #define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX                                                           2
 184 #define mmPLL_MACRO_CNTL_RESERVED29                                                                    0x0055
 185 #define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX                                                           2
 186 #define mmPLL_MACRO_CNTL_RESERVED30                                                                    0x0056
 187 #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX                                                           2
 188 #define mmPLL_MACRO_CNTL_RESERVED31                                                                    0x0057
 189 #define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX                                                           2
 190 #define mmPLL_MACRO_CNTL_RESERVED32                                                                    0x0058
 191 #define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX                                                           2
 192 #define mmPLL_MACRO_CNTL_RESERVED33                                                                    0x0059
 193 #define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX                                                           2
 194 #define mmPLL_MACRO_CNTL_RESERVED34                                                                    0x005a
 195 #define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX                                                           2
 196 #define mmPLL_MACRO_CNTL_RESERVED35                                                                    0x005b
 197 #define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX                                                           2
 198 #define mmPLL_MACRO_CNTL_RESERVED36                                                                    0x005c
 199 #define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX                                                           2
 200 #define mmPLL_MACRO_CNTL_RESERVED37                                                                    0x005d
 201 #define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX                                                           2
 202 #define mmPLL_MACRO_CNTL_RESERVED38                                                                    0x005e
 203 #define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX                                                           2
 204 #define mmPLL_MACRO_CNTL_RESERVED39                                                                    0x005f
 205 #define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX                                                           2
 206 #define mmPLL_MACRO_CNTL_RESERVED40                                                                    0x0060
 207 #define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX                                                           2
 208 #define mmPLL_MACRO_CNTL_RESERVED41                                                                    0x0061
 209 #define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX                                                           2
 210 
 211 
 212 // addressBlock: dce_dc_dc_perfmon1_dispdec
 213 // base address: 0x598
 214 #define mmDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x0186
 215 #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
 216 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x0187
 217 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
 218 #define mmDC_PERFMON1_PERFCOUNTER_STATE                                                                0x0188
 219 #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
 220 #define mmDC_PERFMON1_PERFMON_CNTL                                                                     0x0189
 221 #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
 222 #define mmDC_PERFMON1_PERFMON_CNTL2                                                                    0x018a
 223 #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
 224 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x018b
 225 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
 226 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x018c
 227 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
 228 #define mmDC_PERFMON1_PERFMON_HI                                                                       0x018d
 229 #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
 230 #define mmDC_PERFMON1_PERFMON_LOW                                                                      0x018e
 231 #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
 232 
 233 
 234 // addressBlock: dce_dc_mcif_wb0_dispdec
 235 // base address: 0x0
 236 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x0272
 237 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
 238 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x0273
 239 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
 240 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS                                                               0x0274
 241 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
 242 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH                                                                   0x0275
 243 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
 244 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS                                                                0x0276
 245 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
 246 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2                                                               0x0277
 247 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
 248 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS                                                                0x0278
 249 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
 250 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2                                                               0x0279
 251 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
 252 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS                                                                0x027a
 253 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
 254 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2                                                               0x027b
 255 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
 256 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS                                                                0x027c
 257 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
 258 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2                                                               0x027d
 259 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
 260 #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL                                                         0x027e
 261 #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
 262 #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE                                                                 0x027f
 263 #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
 264 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y                                                                0x0282
 265 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
 266 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x0283
 267 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
 268 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C                                                                0x0284
 269 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
 270 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x0285
 271 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
 272 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y                                                                0x0286
 273 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
 274 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x0287
 275 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
 276 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C                                                                0x0288
 277 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
 278 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x0289
 279 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
 280 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y                                                                0x028a
 281 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
 282 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x028b
 283 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
 284 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C                                                                0x028c
 285 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
 286 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x028d
 287 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
 288 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y                                                                0x028e
 289 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
 290 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x028f
 291 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
 292 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C                                                                0x0290
 293 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
 294 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x0291
 295 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
 296 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x0292
 297 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
 298 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x0293
 299 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
 300 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL                                                           0x0294
 301 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
 302 #define mmMCIF_WB0_MCIF_WB_WATERMARK                                                                   0x0295
 303 #define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX                                                          2
 304 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x0296
 305 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
 306 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL                                                                0x0297
 307 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
 308 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x0298
 309 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
 310 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL                                                                0x0299
 311 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
 312 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE                                                               0x029b
 313 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
 314 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE                                                             0x029c
 315 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
 316 
 317 
 318 // addressBlock: dce_dc_mcif_wb1_dispdec
 319 // base address: 0x100
 320 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02b2
 321 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
 322 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x02b3
 323 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
 324 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS                                                               0x02b4
 325 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
 326 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH                                                                   0x02b5
 327 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
 328 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS                                                                0x02b6
 329 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
 330 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2                                                               0x02b7
 331 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
 332 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS                                                                0x02b8
 333 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
 334 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2                                                               0x02b9
 335 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
 336 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS                                                                0x02ba
 337 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
 338 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2                                                               0x02bb
 339 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
 340 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS                                                                0x02bc
 341 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
 342 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2                                                               0x02bd
 343 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
 344 #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL                                                         0x02be
 345 #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
 346 #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE                                                                 0x02bf
 347 #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
 348 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y                                                                0x02c2
 349 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
 350 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x02c3
 351 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
 352 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C                                                                0x02c4
 353 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
 354 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x02c5
 355 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
 356 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y                                                                0x02c6
 357 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
 358 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x02c7
 359 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
 360 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C                                                                0x02c8
 361 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
 362 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x02c9
 363 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
 364 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y                                                                0x02ca
 365 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
 366 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x02cb
 367 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
 368 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C                                                                0x02cc
 369 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
 370 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x02cd
 371 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
 372 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y                                                                0x02ce
 373 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
 374 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x02cf
 375 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
 376 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C                                                                0x02d0
 377 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
 378 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x02d1
 379 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
 380 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x02d2
 381 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
 382 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x02d3
 383 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
 384 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL                                                           0x02d4
 385 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
 386 #define mmMCIF_WB1_MCIF_WB_WATERMARK                                                                   0x02d5
 387 #define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX                                                          2
 388 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x02d6
 389 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
 390 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL                                                                0x02d7
 391 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
 392 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x02d8
 393 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
 394 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL                                                                0x02d9
 395 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
 396 #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE                                                               0x02db
 397 #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
 398 #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE                                                             0x02dc
 399 #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
 400 
 401 
 402 // addressBlock: dce_dc_mcif_wb2_dispdec
 403 // base address: 0x200
 404 #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02f2
 405 #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
 406 #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x02f3
 407 #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
 408 #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS                                                               0x02f4
 409 #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
 410 #define mmMCIF_WB2_MCIF_WB_BUF_PITCH                                                                   0x02f5
 411 #define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
 412 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS                                                                0x02f6
 413 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
 414 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2                                                               0x02f7
 415 #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
 416 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS                                                                0x02f8
 417 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
 418 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2                                                               0x02f9
 419 #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
 420 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS                                                                0x02fa
 421 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
 422 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2                                                               0x02fb
 423 #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
 424 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS                                                                0x02fc
 425 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
 426 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2                                                               0x02fd
 427 #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
 428 #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL                                                         0x02fe
 429 #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
 430 #define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE                                                                 0x02ff
 431 #define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
 432 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y                                                                0x0302
 433 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
 434 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x0303
 435 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
 436 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C                                                                0x0304
 437 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
 438 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x0305
 439 #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
 440 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y                                                                0x0306
 441 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
 442 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x0307
 443 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
 444 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C                                                                0x0308
 445 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
 446 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x0309
 447 #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
 448 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y                                                                0x030a
 449 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
 450 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x030b
 451 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
 452 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C                                                                0x030c
 453 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
 454 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x030d
 455 #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
 456 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y                                                                0x030e
 457 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
 458 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x030f
 459 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
 460 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C                                                                0x0310
 461 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
 462 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x0311
 463 #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
 464 #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x0312
 465 #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
 466 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x0313
 467 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
 468 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL                                                           0x0314
 469 #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
 470 #define mmMCIF_WB2_MCIF_WB_WATERMARK                                                                   0x0315
 471 #define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX                                                          2
 472 #define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x0316
 473 #define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
 474 #define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL                                                                0x0317
 475 #define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
 476 #define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x0318
 477 #define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
 478 #define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL                                                                0x0319
 479 #define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
 480 #define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE                                                               0x031b
 481 #define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
 482 #define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE                                                             0x031c
 483 #define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
 484 
 485 
 486 // addressBlock: dce_dc_cwb0_dispdec
 487 // base address: 0x0
 488 #define mmCWB0_CWB_CTRL                                                                                0x0332
 489 #define mmCWB0_CWB_CTRL_BASE_IDX                                                                       2
 490 #define mmCWB0_CWB_FENCE_PAR0                                                                          0x0334
 491 #define mmCWB0_CWB_FENCE_PAR0_BASE_IDX                                                                 2
 492 #define mmCWB0_CWB_FENCE_PAR1                                                                          0x0335
 493 #define mmCWB0_CWB_FENCE_PAR1_BASE_IDX                                                                 2
 494 #define mmCWB0_CWB_CRC_CTRL                                                                            0x0339
 495 #define mmCWB0_CWB_CRC_CTRL_BASE_IDX                                                                   2
 496 #define mmCWB0_CWB_CRC_RED_GREEN_MASK                                                                  0x033a
 497 #define mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX                                                         2
 498 #define mmCWB0_CWB_CRC_BLUE_MASK                                                                       0x033b
 499 #define mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX                                                              2
 500 #define mmCWB0_CWB_CRC_RED_GREEN_RESULT                                                                0x033c
 501 #define mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX                                                       2
 502 #define mmCWB0_CWB_CRC_BLUE_RESULT                                                                     0x033d
 503 #define mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX                                                            2
 504 
 505 
 506 // addressBlock: dce_dc_cwb1_dispdec
 507 // base address: 0x60
 508 #define mmCWB1_CWB_CTRL                                                                                0x034a
 509 #define mmCWB1_CWB_CTRL_BASE_IDX                                                                       2
 510 #define mmCWB1_CWB_FENCE_PAR0                                                                          0x034c
 511 #define mmCWB1_CWB_FENCE_PAR0_BASE_IDX                                                                 2
 512 #define mmCWB1_CWB_FENCE_PAR1                                                                          0x034d
 513 #define mmCWB1_CWB_FENCE_PAR1_BASE_IDX                                                                 2
 514 #define mmCWB1_CWB_CRC_CTRL                                                                            0x0351
 515 #define mmCWB1_CWB_CRC_CTRL_BASE_IDX                                                                   2
 516 #define mmCWB1_CWB_CRC_RED_GREEN_MASK                                                                  0x0352
 517 #define mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX                                                         2
 518 #define mmCWB1_CWB_CRC_BLUE_MASK                                                                       0x0353
 519 #define mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX                                                              2
 520 #define mmCWB1_CWB_CRC_RED_GREEN_RESULT                                                                0x0354
 521 #define mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX                                                       2
 522 #define mmCWB1_CWB_CRC_BLUE_RESULT                                                                     0x0355
 523 #define mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX                                                            2
 524 
 525 
 526 // addressBlock: dce_dc_dc_perfmon9_dispdec
 527 // base address: 0xd08
 528 #define mmDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0362
 529 #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
 530 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0363
 531 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
 532 #define mmDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0364
 533 #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
 534 #define mmDC_PERFMON9_PERFMON_CNTL                                                                     0x0365
 535 #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
 536 #define mmDC_PERFMON9_PERFMON_CNTL2                                                                    0x0366
 537 #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
 538 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x0367
 539 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
 540 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x0368
 541 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
 542 #define mmDC_PERFMON9_PERFMON_HI                                                                       0x0369
 543 #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
 544 #define mmDC_PERFMON9_PERFMON_LOW                                                                      0x036a
 545 #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
 546 
 547 
 548 // addressBlock: dce_dc_dispdec
 549 // base address: 0x0
 550 #define mmVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
 551 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
 552 #define mmVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
 553 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
 554 #define mmVGA_RENDER_CONTROL                                                                           0x0000
 555 #define mmVGA_RENDER_CONTROL_BASE_IDX                                                                  1
 556 #define mmVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
 557 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
 558 #define mmVGA_MODE_CONTROL                                                                             0x0002
 559 #define mmVGA_MODE_CONTROL_BASE_IDX                                                                    1
 560 #define mmVGA_SURFACE_PITCH_SELECT                                                                     0x0003
 561 #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
 562 #define mmVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
 563 #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
 564 #define mmVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
 565 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
 566 #define mmVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
 567 #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
 568 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
 569 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
 570 #define mmVGA_HDP_CONTROL                                                                              0x000a
 571 #define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
 572 #define mmVGA_CACHE_CONTROL                                                                            0x000b
 573 #define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
 574 #define mmD1VGA_CONTROL                                                                                0x000c
 575 #define mmD1VGA_CONTROL_BASE_IDX                                                                       1
 576 #define mmD2VGA_CONTROL                                                                                0x000e
 577 #define mmD2VGA_CONTROL_BASE_IDX                                                                       1
 578 #define mmVGA_STATUS                                                                                   0x0010
 579 #define mmVGA_STATUS_BASE_IDX                                                                          1
 580 #define mmVGA_INTERRUPT_CONTROL                                                                        0x0011
 581 #define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
 582 #define mmVGA_STATUS_CLEAR                                                                             0x0012
 583 #define mmVGA_STATUS_CLEAR_BASE_IDX                                                                    1
 584 #define mmVGA_INTERRUPT_STATUS                                                                         0x0013
 585 #define mmVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
 586 #define mmVGA_MAIN_CONTROL                                                                             0x0014
 587 #define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
 588 #define mmVGA_TEST_CONTROL                                                                             0x0015
 589 #define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
 590 #define mmVGA_QOS_CTRL                                                                                 0x0018
 591 #define mmVGA_QOS_CTRL_BASE_IDX                                                                        1
 592 #define mmCRTC8_IDX                                                                                    0x002d
 593 #define mmCRTC8_IDX_BASE_IDX                                                                           1
 594 #define mmCRTC8_DATA                                                                                   0x002d
 595 #define mmCRTC8_DATA_BASE_IDX                                                                          1
 596 #define mmGENFC_WT                                                                                     0x002e
 597 #define mmGENFC_WT_BASE_IDX                                                                            1
 598 #define mmGENS1                                                                                        0x002e
 599 #define mmGENS1_BASE_IDX                                                                               1
 600 #define mmATTRDW                                                                                       0x0030
 601 #define mmATTRDW_BASE_IDX                                                                              1
 602 #define mmATTRX                                                                                        0x0030
 603 #define mmATTRX_BASE_IDX                                                                               1
 604 #define mmATTRDR                                                                                       0x0030
 605 #define mmATTRDR_BASE_IDX                                                                              1
 606 #define mmGENMO_WT                                                                                     0x0030
 607 #define mmGENMO_WT_BASE_IDX                                                                            1
 608 #define mmGENS0                                                                                        0x0030
 609 #define mmGENS0_BASE_IDX                                                                               1
 610 #define mmGENENB                                                                                       0x0030
 611 #define mmGENENB_BASE_IDX                                                                              1
 612 #define mmSEQ8_IDX                                                                                     0x0031
 613 #define mmSEQ8_IDX_BASE_IDX                                                                            1
 614 #define mmSEQ8_DATA                                                                                    0x0031
 615 #define mmSEQ8_DATA_BASE_IDX                                                                           1
 616 #define mmDAC_MASK                                                                                     0x0031
 617 #define mmDAC_MASK_BASE_IDX                                                                            1
 618 #define mmDAC_R_INDEX                                                                                  0x0031
 619 #define mmDAC_R_INDEX_BASE_IDX                                                                         1
 620 #define mmDAC_W_INDEX                                                                                  0x0032
 621 #define mmDAC_W_INDEX_BASE_IDX                                                                         1
 622 #define mmDAC_DATA                                                                                     0x0032
 623 #define mmDAC_DATA_BASE_IDX                                                                            1
 624 #define mmGENFC_RD                                                                                     0x0032
 625 #define mmGENFC_RD_BASE_IDX                                                                            1
 626 #define mmGENMO_RD                                                                                     0x0033
 627 #define mmGENMO_RD_BASE_IDX                                                                            1
 628 #define mmGRPH8_IDX                                                                                    0x0033
 629 #define mmGRPH8_IDX_BASE_IDX                                                                           1
 630 #define mmGRPH8_DATA                                                                                   0x0033
 631 #define mmGRPH8_DATA_BASE_IDX                                                                          1
 632 #define mmCRTC8_IDX_1                                                                                  0x0035
 633 #define mmCRTC8_IDX_1_BASE_IDX                                                                         1
 634 #define mmCRTC8_DATA_1                                                                                 0x0035
 635 #define mmCRTC8_DATA_1_BASE_IDX                                                                        1
 636 #define mmGENFC_WT_1                                                                                   0x0036
 637 #define mmGENFC_WT_1_BASE_IDX                                                                          1
 638 #define mmGENS1_1                                                                                      0x0036
 639 #define mmGENS1_1_BASE_IDX                                                                             1
 640 #define mmD3VGA_CONTROL                                                                                0x0038
 641 #define mmD3VGA_CONTROL_BASE_IDX                                                                       1
 642 #define mmD4VGA_CONTROL                                                                                0x0039
 643 #define mmD4VGA_CONTROL_BASE_IDX                                                                       1
 644 #define mmD5VGA_CONTROL                                                                                0x003a
 645 #define mmD5VGA_CONTROL_BASE_IDX                                                                       1
 646 #define mmD6VGA_CONTROL                                                                                0x003b
 647 #define mmD6VGA_CONTROL_BASE_IDX                                                                       1
 648 #define mmVGA_SOURCE_SELECT                                                                            0x003c
 649 #define mmVGA_SOURCE_SELECT_BASE_IDX                                                                   1
 650 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
 651 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 652 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
 653 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 654 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
 655 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 656 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
 657 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 658 #define mmDCFEV0_CRTC_PIXEL_RATE_CNTL                                                                  0x0044
 659 #define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX                                                         1
 660 #define mmDCFEV1_CRTC_PIXEL_RATE_CNTL                                                                  0x0045
 661 #define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX                                                         1
 662 #define mmSYMCLKLPA_CLOCK_ENABLE                                                                       0x0046
 663 #define mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX                                                              1
 664 #define mmSYMCLKLPB_CLOCK_ENABLE                                                                       0x0047
 665 #define mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX                                                              1
 666 #define mmDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
 667 #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
 668 #define mmREFCLK_CNTL                                                                                  0x0049
 669 #define mmREFCLK_CNTL_BASE_IDX                                                                         1
 670 #define mmMIPI_CLK_CNTL                                                                                0x004a
 671 #define mmMIPI_CLK_CNTL_BASE_IDX                                                                       1
 672 #define mmREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
 673 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
 674 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
 675 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 676 #define mmDCCG_PERFMON_CNTL2                                                                           0x004e
 677 #define mmDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
 678 #define mmDSICLK_CGTT_BLK_CTRL_REG                                                                     0x004f
 679 #define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
 680 #define mmDCCG_CBUS_WRCMD_DELAY                                                                        0x0050
 681 #define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX                                                               1
 682 #define mmDCCG_DS_DTO_INCR                                                                             0x0053
 683 #define mmDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
 684 #define mmDCCG_DS_DTO_MODULO                                                                           0x0054
 685 #define mmDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
 686 #define mmDCCG_DS_CNTL                                                                                 0x0055
 687 #define mmDCCG_DS_CNTL_BASE_IDX                                                                        1
 688 #define mmDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
 689 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
 690 #define mmSYMCLKG_CLOCK_ENABLE                                                                         0x0057
 691 #define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX                                                                1
 692 #define mmDPREFCLK_CNTL                                                                                0x0058
 693 #define mmDPREFCLK_CNTL_BASE_IDX                                                                       1
 694 #define mmAOMCLK0_CNTL                                                                                 0x0059
 695 #define mmAOMCLK0_CNTL_BASE_IDX                                                                        1
 696 #define mmAOMCLK1_CNTL                                                                                 0x005a
 697 #define mmAOMCLK1_CNTL_BASE_IDX                                                                        1
 698 #define mmAOMCLK2_CNTL                                                                                 0x005b
 699 #define mmAOMCLK2_CNTL_BASE_IDX                                                                        1
 700 #define mmDCCG_AUDIO_DTO2_PHASE                                                                        0x005c
 701 #define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX                                                               1
 702 #define mmDCCG_AUDIO_DTO2_MODULO                                                                       0x005d
 703 #define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX                                                              1
 704 #define mmDCE_VERSION                                                                                  0x005e
 705 #define mmDCE_VERSION_BASE_IDX                                                                         1
 706 #define mmPHYPLLG_PIXCLK_RESYNC_CNTL                                                                   0x005f
 707 #define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 708 #define mmDCCG_GTC_CNTL                                                                                0x0060
 709 #define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
 710 #define mmDCCG_GTC_DTO_INCR                                                                            0x0061
 711 #define mmDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
 712 #define mmDCCG_GTC_DTO_MODULO                                                                          0x0062
 713 #define mmDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
 714 #define mmDCCG_GTC_CURRENT                                                                             0x0063
 715 #define mmDCCG_GTC_CURRENT_BASE_IDX                                                                    1
 716 #define mmDENTIST_DISPCLK_CNTL                                                                         0x0064
 717 #define mmDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
 718 #define mmMIPI_DTO_CNTL                                                                                0x0065
 719 #define mmMIPI_DTO_CNTL_BASE_IDX                                                                       1
 720 #define mmMIPI_DTO_PHASE                                                                               0x0066
 721 #define mmMIPI_DTO_PHASE_BASE_IDX                                                                      1
 722 #define mmMIPI_DTO_MODULO                                                                              0x0067
 723 #define mmMIPI_DTO_MODULO_BASE_IDX                                                                     1
 724 #define mmDAC_CLK_ENABLE                                                                               0x0068
 725 #define mmDAC_CLK_ENABLE_BASE_IDX                                                                      1
 726 #define mmDVO_CLK_ENABLE                                                                               0x0069
 727 #define mmDVO_CLK_ENABLE_BASE_IDX                                                                      1
 728 #define mmAVSYNC_COUNTER_WRITE                                                                         0x006a
 729 #define mmAVSYNC_COUNTER_WRITE_BASE_IDX                                                                1
 730 #define mmAVSYNC_COUNTER_CONTROL                                                                       0x006b
 731 #define mmAVSYNC_COUNTER_CONTROL_BASE_IDX                                                              1
 732 #define mmDMCU_SMU_INTERRUPT_CNTL                                                                      0x006c
 733 #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             1
 734 #define mmSMU_CONTROL                                                                                  0x006d
 735 #define mmSMU_CONTROL_BASE_IDX                                                                         1
 736 #define mmSMU_INTERRUPT_CONTROL                                                                        0x006e
 737 #define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               1
 738 #define mmAVSYNC_COUNTER_READ                                                                          0x006f
 739 #define mmAVSYNC_COUNTER_READ_BASE_IDX                                                                 1
 740 #define mmMILLISECOND_TIME_BASE_DIV                                                                    0x0070
 741 #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
 742 #define mmDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
 743 #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
 744 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
 745 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
 746 #define mmDCCG_PERFMON_CNTL                                                                            0x0073
 747 #define mmDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
 748 #define mmDCCG_GATE_DISABLE_CNTL                                                                       0x0074
 749 #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
 750 #define mmDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
 751 #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
 752 #define mmSCLK_CGTT_BLK_CTRL_REG                                                                       0x0076
 753 #define mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                              1
 754 #define mmDCCG_CAC_STATUS                                                                              0x0077
 755 #define mmDCCG_CAC_STATUS_BASE_IDX                                                                     1
 756 #define mmPIXCLK1_RESYNC_CNTL                                                                          0x0078
 757 #define mmPIXCLK1_RESYNC_CNTL_BASE_IDX                                                                 1
 758 #define mmPIXCLK2_RESYNC_CNTL                                                                          0x0079
 759 #define mmPIXCLK2_RESYNC_CNTL_BASE_IDX                                                                 1
 760 #define mmPIXCLK0_RESYNC_CNTL                                                                          0x007a
 761 #define mmPIXCLK0_RESYNC_CNTL_BASE_IDX                                                                 1
 762 #define mmMICROSECOND_TIME_BASE_DIV                                                                    0x007b
 763 #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
 764 #define mmDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
 765 #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
 766 #define mmSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
 767 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
 768 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL                                                                   0x007e
 769 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
 770 #define mmDCCG_DISP_CNTL_REG                                                                           0x007f
 771 #define mmDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
 772 #define mmCRTC0_PIXEL_RATE_CNTL                                                                        0x0080
 773 #define mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX                                                               1
 774 #define mmDP_DTO0_PHASE                                                                                0x0081
 775 #define mmDP_DTO0_PHASE_BASE_IDX                                                                       1
 776 #define mmDP_DTO0_MODULO                                                                               0x0082
 777 #define mmDP_DTO0_MODULO_BASE_IDX                                                                      1
 778 #define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL                                                                 0x0083
 779 #define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                        1
 780 #define mmCRTC1_PIXEL_RATE_CNTL                                                                        0x0084
 781 #define mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX                                                               1
 782 #define mmDP_DTO1_PHASE                                                                                0x0085
 783 #define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
 784 #define mmDP_DTO1_MODULO                                                                               0x0086
 785 #define mmDP_DTO1_MODULO_BASE_IDX                                                                      1
 786 #define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL                                                                 0x0087
 787 #define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                        1
 788 #define mmCRTC2_PIXEL_RATE_CNTL                                                                        0x0088
 789 #define mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX                                                               1
 790 #define mmDP_DTO2_PHASE                                                                                0x0089
 791 #define mmDP_DTO2_PHASE_BASE_IDX                                                                       1
 792 #define mmDP_DTO2_MODULO                                                                               0x008a
 793 #define mmDP_DTO2_MODULO_BASE_IDX                                                                      1
 794 #define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL                                                                 0x008b
 795 #define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                        1
 796 #define mmCRTC3_PIXEL_RATE_CNTL                                                                        0x008c
 797 #define mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX                                                               1
 798 #define mmDP_DTO3_PHASE                                                                                0x008d
 799 #define mmDP_DTO3_PHASE_BASE_IDX                                                                       1
 800 #define mmDP_DTO3_MODULO                                                                               0x008e
 801 #define mmDP_DTO3_MODULO_BASE_IDX                                                                      1
 802 #define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL                                                                 0x008f
 803 #define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                        1
 804 #define mmCRTC4_PIXEL_RATE_CNTL                                                                        0x0090
 805 #define mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX                                                               1
 806 #define mmDP_DTO4_PHASE                                                                                0x0091
 807 #define mmDP_DTO4_PHASE_BASE_IDX                                                                       1
 808 #define mmDP_DTO4_MODULO                                                                               0x0092
 809 #define mmDP_DTO4_MODULO_BASE_IDX                                                                      1
 810 #define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL                                                                 0x0093
 811 #define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                        1
 812 #define mmCRTC5_PIXEL_RATE_CNTL                                                                        0x0094
 813 #define mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX                                                               1
 814 #define mmDP_DTO5_PHASE                                                                                0x0095
 815 #define mmDP_DTO5_PHASE_BASE_IDX                                                                       1
 816 #define mmDP_DTO5_MODULO                                                                               0x0096
 817 #define mmDP_DTO5_MODULO_BASE_IDX                                                                      1
 818 #define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL                                                                 0x0097
 819 #define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                        1
 820 #define mmDCCG_SOFT_RESET                                                                              0x009f
 821 #define mmDCCG_SOFT_RESET_BASE_IDX                                                                     1
 822 #define mmSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
 823 #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
 824 #define mmSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
 825 #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
 826 #define mmSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
 827 #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
 828 #define mmSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
 829 #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
 830 #define mmSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
 831 #define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
 832 #define mmSYMCLKF_CLOCK_ENABLE                                                                         0x00a5
 833 #define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX                                                                1
 834 #define mmDVOACLKD_CNTL                                                                                0x00a8
 835 #define mmDVOACLKD_CNTL_BASE_IDX                                                                       1
 836 #define mmDVOACLKC_MVP_CNTL                                                                            0x00a9
 837 #define mmDVOACLKC_MVP_CNTL_BASE_IDX                                                                   1
 838 #define mmDVOACLKC_CNTL                                                                                0x00aa
 839 #define mmDVOACLKC_CNTL_BASE_IDX                                                                       1
 840 #define mmDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
 841 #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
 842 #define mmDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
 843 #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
 844 #define mmDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
 845 #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
 846 #define mmDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
 847 #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
 848 #define mmDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
 849 #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
 850 #define mmDCCG_TEST_CLK_SEL                                                                            0x00be
 851 #define mmDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1
 852 #define mmFBC_CNTL                                                                                     0x0062
 853 #define mmFBC_CNTL_BASE_IDX                                                                            2
 854 #define mmFBC_IDLE_FORCE_CLEAR_MASK                                                                    0x0064
 855 #define mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX                                                           2
 856 #define mmFBC_START_STOP_DELAY                                                                         0x0065
 857 #define mmFBC_START_STOP_DELAY_BASE_IDX                                                                2
 858 #define mmFBC_COMP_CNTL                                                                                0x0066
 859 #define mmFBC_COMP_CNTL_BASE_IDX                                                                       2
 860 #define mmFBC_COMP_MODE                                                                                0x0067
 861 #define mmFBC_COMP_MODE_BASE_IDX                                                                       2
 862 #define mmFBC_IND_LUT0                                                                                 0x006b
 863 #define mmFBC_IND_LUT0_BASE_IDX                                                                        2
 864 #define mmFBC_IND_LUT1                                                                                 0x006c
 865 #define mmFBC_IND_LUT1_BASE_IDX                                                                        2
 866 #define mmFBC_IND_LUT2                                                                                 0x006d
 867 #define mmFBC_IND_LUT2_BASE_IDX                                                                        2
 868 #define mmFBC_IND_LUT3                                                                                 0x006e
 869 #define mmFBC_IND_LUT3_BASE_IDX                                                                        2
 870 #define mmFBC_IND_LUT4                                                                                 0x006f
 871 #define mmFBC_IND_LUT4_BASE_IDX                                                                        2
 872 #define mmFBC_IND_LUT5                                                                                 0x0070
 873 #define mmFBC_IND_LUT5_BASE_IDX                                                                        2
 874 #define mmFBC_IND_LUT6                                                                                 0x0071
 875 #define mmFBC_IND_LUT6_BASE_IDX                                                                        2
 876 #define mmFBC_IND_LUT7                                                                                 0x0072
 877 #define mmFBC_IND_LUT7_BASE_IDX                                                                        2
 878 #define mmFBC_IND_LUT8                                                                                 0x0073
 879 #define mmFBC_IND_LUT8_BASE_IDX                                                                        2
 880 #define mmFBC_IND_LUT9                                                                                 0x0074
 881 #define mmFBC_IND_LUT9_BASE_IDX                                                                        2
 882 #define mmFBC_IND_LUT10                                                                                0x0075
 883 #define mmFBC_IND_LUT10_BASE_IDX                                                                       2
 884 #define mmFBC_IND_LUT11                                                                                0x0076
 885 #define mmFBC_IND_LUT11_BASE_IDX                                                                       2
 886 #define mmFBC_IND_LUT12                                                                                0x0077
 887 #define mmFBC_IND_LUT12_BASE_IDX                                                                       2
 888 #define mmFBC_IND_LUT13                                                                                0x0078
 889 #define mmFBC_IND_LUT13_BASE_IDX                                                                       2
 890 #define mmFBC_IND_LUT14                                                                                0x0079
 891 #define mmFBC_IND_LUT14_BASE_IDX                                                                       2
 892 #define mmFBC_IND_LUT15                                                                                0x007a
 893 #define mmFBC_IND_LUT15_BASE_IDX                                                                       2
 894 #define mmFBC_CSM_REGION_OFFSET_01                                                                     0x007b
 895 #define mmFBC_CSM_REGION_OFFSET_01_BASE_IDX                                                            2
 896 #define mmFBC_CSM_REGION_OFFSET_23                                                                     0x007c
 897 #define mmFBC_CSM_REGION_OFFSET_23_BASE_IDX                                                            2
 898 #define mmFBC_CLIENT_REGION_MASK                                                                       0x007d
 899 #define mmFBC_CLIENT_REGION_MASK_BASE_IDX                                                              2
 900 #define mmFBC_DEBUG_COMP                                                                               0x007e
 901 #define mmFBC_DEBUG_COMP_BASE_IDX                                                                      2
 902 #define mmFBC_MISC                                                                                     0x0084
 903 #define mmFBC_MISC_BASE_IDX                                                                            2
 904 #define mmFBC_STATUS                                                                                   0x0085
 905 #define mmFBC_STATUS_BASE_IDX                                                                          2
 906 #define mmFBC_ALPHA_CNTL                                                                               0x0088
 907 #define mmFBC_ALPHA_CNTL_BASE_IDX                                                                      2
 908 #define mmFBC_ALPHA_RGB_OVERRIDE                                                                       0x0089
 909 #define mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX                                                              2
 910 #define mmPIPE0_PG_CONFIG                                                                              0x008e
 911 #define mmPIPE0_PG_CONFIG_BASE_IDX                                                                     2
 912 #define mmPIPE0_PG_ENABLE                                                                              0x008f
 913 #define mmPIPE0_PG_ENABLE_BASE_IDX                                                                     2
 914 #define mmPIPE0_PG_STATUS                                                                              0x0090
 915 #define mmPIPE0_PG_STATUS_BASE_IDX                                                                     2
 916 #define mmPIPE1_PG_CONFIG                                                                              0x0091
 917 #define mmPIPE1_PG_CONFIG_BASE_IDX                                                                     2
 918 #define mmPIPE1_PG_ENABLE                                                                              0x0092
 919 #define mmPIPE1_PG_ENABLE_BASE_IDX                                                                     2
 920 #define mmPIPE1_PG_STATUS                                                                              0x0093
 921 #define mmPIPE1_PG_STATUS_BASE_IDX                                                                     2
 922 #define mmPIPE2_PG_CONFIG                                                                              0x0094
 923 #define mmPIPE2_PG_CONFIG_BASE_IDX                                                                     2
 924 #define mmPIPE2_PG_ENABLE                                                                              0x0095
 925 #define mmPIPE2_PG_ENABLE_BASE_IDX                                                                     2
 926 #define mmPIPE2_PG_STATUS                                                                              0x0096
 927 #define mmPIPE2_PG_STATUS_BASE_IDX                                                                     2
 928 #define mmPIPE3_PG_CONFIG                                                                              0x0097
 929 #define mmPIPE3_PG_CONFIG_BASE_IDX                                                                     2
 930 #define mmPIPE3_PG_ENABLE                                                                              0x0098
 931 #define mmPIPE3_PG_ENABLE_BASE_IDX                                                                     2
 932 #define mmPIPE3_PG_STATUS                                                                              0x0099
 933 #define mmPIPE3_PG_STATUS_BASE_IDX                                                                     2
 934 #define mmPIPE4_PG_CONFIG                                                                              0x009a
 935 #define mmPIPE4_PG_CONFIG_BASE_IDX                                                                     2
 936 #define mmPIPE4_PG_ENABLE                                                                              0x009b
 937 #define mmPIPE4_PG_ENABLE_BASE_IDX                                                                     2
 938 #define mmPIPE4_PG_STATUS                                                                              0x009c
 939 #define mmPIPE4_PG_STATUS_BASE_IDX                                                                     2
 940 #define mmPIPE5_PG_CONFIG                                                                              0x009d
 941 #define mmPIPE5_PG_CONFIG_BASE_IDX                                                                     2
 942 #define mmPIPE5_PG_ENABLE                                                                              0x009e
 943 #define mmPIPE5_PG_ENABLE_BASE_IDX                                                                     2
 944 #define mmPIPE5_PG_STATUS                                                                              0x009f
 945 #define mmPIPE5_PG_STATUS_BASE_IDX                                                                     2
 946 #define mmDSI_PG_CONFIG                                                                                0x00a0
 947 #define mmDSI_PG_CONFIG_BASE_IDX                                                                       2
 948 #define mmDSI_PG_ENABLE                                                                                0x00a1
 949 #define mmDSI_PG_ENABLE_BASE_IDX                                                                       2
 950 #define mmDSI_PG_STATUS                                                                                0x00a2
 951 #define mmDSI_PG_STATUS_BASE_IDX                                                                       2
 952 #define mmDCFEV0_PG_CONFIG                                                                             0x00a3
 953 #define mmDCFEV0_PG_CONFIG_BASE_IDX                                                                    2
 954 #define mmDCFEV0_PG_ENABLE                                                                             0x00a4
 955 #define mmDCFEV0_PG_ENABLE_BASE_IDX                                                                    2
 956 #define mmDCFEV0_PG_STATUS                                                                             0x00a5
 957 #define mmDCFEV0_PG_STATUS_BASE_IDX                                                                    2
 958 #define mmDCPG_INTERRUPT_STATUS                                                                        0x00a6
 959 #define mmDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
 960 #define mmDCPG_INTERRUPT_CONTROL                                                                       0x00a7
 961 #define mmDCPG_INTERRUPT_CONTROL_BASE_IDX                                                              2
 962 #define mmDCPG_INTERRUPT_CONTROL2                                                                      0x00a8
 963 #define mmDCPG_INTERRUPT_CONTROL2_BASE_IDX                                                             2
 964 #define mmDCFEV1_PG_CONFIG                                                                             0x00a9
 965 #define mmDCFEV1_PG_CONFIG_BASE_IDX                                                                    2
 966 #define mmDCFEV1_PG_ENABLE                                                                             0x00aa
 967 #define mmDCFEV1_PG_ENABLE_BASE_IDX                                                                    2
 968 #define mmDCFEV1_PG_STATUS                                                                             0x00ab
 969 #define mmDCFEV1_PG_STATUS_BASE_IDX                                                                    2
 970 #define mmDC_IP_REQUEST_CNTL                                                                           0x00ac
 971 #define mmDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
 972 #define mmDC_PGCNTL_STATUS_REG                                                                         0x00ad
 973 #define mmDC_PGCNTL_STATUS_REG_BASE_IDX                                                                2
 974 #define mmDMIFV_STATUS                                                                                 0x00c3
 975 #define mmDMIFV_STATUS_BASE_IDX                                                                        2
 976 #define mmDMIF_CONTROL                                                                                 0x00c4
 977 #define mmDMIF_CONTROL_BASE_IDX                                                                        2
 978 #define mmDMIF_STATUS                                                                                  0x00c5
 979 #define mmDMIF_STATUS_BASE_IDX                                                                         2
 980 #define mmDMIF_ARBITRATION_CONTROL                                                                     0x00c7
 981 #define mmDMIF_ARBITRATION_CONTROL_BASE_IDX                                                            2
 982 #define mmPIPE0_ARBITRATION_CONTROL3                                                                   0x00c8
 983 #define mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX                                                          2
 984 #define mmPIPE1_ARBITRATION_CONTROL3                                                                   0x00c9
 985 #define mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX                                                          2
 986 #define mmPIPE2_ARBITRATION_CONTROL3                                                                   0x00ca
 987 #define mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX                                                          2
 988 #define mmPIPE3_ARBITRATION_CONTROL3                                                                   0x00cb
 989 #define mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX                                                          2
 990 #define mmPIPE4_ARBITRATION_CONTROL3                                                                   0x00cc
 991 #define mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX                                                          2
 992 #define mmPIPE5_ARBITRATION_CONTROL3                                                                   0x00cd
 993 #define mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX                                                          2
 994 #define mmDMIF_P_VMID                                                                                  0x00ce
 995 #define mmDMIF_P_VMID_BASE_IDX                                                                         2
 996 #define mmDMIF_ADDR_CALC                                                                               0x00d1
 997 #define mmDMIF_ADDR_CALC_BASE_IDX                                                                      2
 998 #define mmDMIF_STATUS2                                                                                 0x00d2
 999 #define mmDMIF_STATUS2_BASE_IDX                                                                        2
1000 #define mmPIPE0_MAX_REQUESTS                                                                           0x00d3
1001 #define mmPIPE0_MAX_REQUESTS_BASE_IDX                                                                  2
1002 #define mmPIPE1_MAX_REQUESTS                                                                           0x00d4
1003 #define mmPIPE1_MAX_REQUESTS_BASE_IDX                                                                  2
1004 #define mmPIPE2_MAX_REQUESTS                                                                           0x00d5
1005 #define mmPIPE2_MAX_REQUESTS_BASE_IDX                                                                  2
1006 #define mmPIPE3_MAX_REQUESTS                                                                           0x00d6
1007 #define mmPIPE3_MAX_REQUESTS_BASE_IDX                                                                  2
1008 #define mmPIPE4_MAX_REQUESTS                                                                           0x00d7
1009 #define mmPIPE4_MAX_REQUESTS_BASE_IDX                                                                  2
1010 #define mmPIPE5_MAX_REQUESTS                                                                           0x00d8
1011 #define mmPIPE5_MAX_REQUESTS_BASE_IDX                                                                  2
1012 #define mmLOW_POWER_TILING_CONTROL                                                                     0x00d9
1013 #define mmLOW_POWER_TILING_CONTROL_BASE_IDX                                                            2
1014 #define mmMCIF_CONTROL                                                                                 0x00da
1015 #define mmMCIF_CONTROL_BASE_IDX                                                                        2
1016 #define mmMCIF_WRITE_COMBINE_CONTROL                                                                   0x00db
1017 #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
1018 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x00de
1019 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1020 #define mmCC_DC_PIPE_DIS                                                                               0x00e0
1021 #define mmCC_DC_PIPE_DIS_BASE_IDX                                                                      2
1022 #define mmSMU_WM_CONTROL                                                                               0x00e1
1023 #define mmSMU_WM_CONTROL_BASE_IDX                                                                      2
1024 #define mmRBBMIF_TIMEOUT                                                                               0x00e2
1025 #define mmRBBMIF_TIMEOUT_BASE_IDX                                                                      2
1026 #define mmRBBMIF_STATUS                                                                                0x00e3
1027 #define mmRBBMIF_STATUS_BASE_IDX                                                                       2
1028 #define mmRBBMIF_TIMEOUT_DIS                                                                           0x00e4
1029 #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
1030 #define mmDCI_MEM_PWR_STATUS                                                                           0x00e5
1031 #define mmDCI_MEM_PWR_STATUS_BASE_IDX                                                                  2
1032 #define mmDCI_MEM_PWR_STATUS2                                                                          0x00e6
1033 #define mmDCI_MEM_PWR_STATUS2_BASE_IDX                                                                 2
1034 #define mmDCI_CLK_CNTL                                                                                 0x00e7
1035 #define mmDCI_CLK_CNTL_BASE_IDX                                                                        2
1036 #define mmDCI_CLK_CNTL2                                                                                0x00e8
1037 #define mmDCI_CLK_CNTL2_BASE_IDX                                                                       2
1038 #define mmDCI_MEM_PWR_CNTL                                                                             0x00e9
1039 #define mmDCI_MEM_PWR_CNTL_BASE_IDX                                                                    2
1040 #define mmDCI_MEM_PWR_CNTL2                                                                            0x00ea
1041 #define mmDCI_MEM_PWR_CNTL2_BASE_IDX                                                                   2
1042 #define mmDCI_MEM_PWR_CNTL3                                                                            0x00eb
1043 #define mmDCI_MEM_PWR_CNTL3_BASE_IDX                                                                   2
1044 #define mmPIPE0_DMIF_BUFFER_CONTROL                                                                    0x00ef
1045 #define mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX                                                           2
1046 #define mmPIPE1_DMIF_BUFFER_CONTROL                                                                    0x00f0
1047 #define mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX                                                           2
1048 #define mmPIPE2_DMIF_BUFFER_CONTROL                                                                    0x00f1
1049 #define mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX                                                           2
1050 #define mmPIPE3_DMIF_BUFFER_CONTROL                                                                    0x00f2
1051 #define mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX                                                           2
1052 #define mmPIPE4_DMIF_BUFFER_CONTROL                                                                    0x00f3
1053 #define mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX                                                           2
1054 #define mmPIPE5_DMIF_BUFFER_CONTROL                                                                    0x00f4
1055 #define mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX                                                           2
1056 #define mmRBBMIF_STATUS_FLAG                                                                           0x00f5
1057 #define mmRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
1058 #define mmDCI_SOFT_RESET                                                                               0x00f6
1059 #define mmDCI_SOFT_RESET_BASE_IDX                                                                      2
1060 #define mmDMIF_URG_OVERRIDE                                                                            0x00f7
1061 #define mmDMIF_URG_OVERRIDE_BASE_IDX                                                                   2
1062 #define mmPIPE6_ARBITRATION_CONTROL3                                                                   0x00f8
1063 #define mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX                                                          2
1064 #define mmPIPE7_ARBITRATION_CONTROL3                                                                   0x00f9
1065 #define mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX                                                          2
1066 #define mmPIPE6_MAX_REQUESTS                                                                           0x00fa
1067 #define mmPIPE6_MAX_REQUESTS_BASE_IDX                                                                  2
1068 #define mmPIPE7_MAX_REQUESTS                                                                           0x00fb
1069 #define mmPIPE7_MAX_REQUESTS_BASE_IDX                                                                  2
1070 #define mmDVMM_REG_RD_STATUS                                                                           0x00fc
1071 #define mmDVMM_REG_RD_STATUS_BASE_IDX                                                                  2
1072 #define mmDVMM_REG_RD_DATA                                                                             0x00fd
1073 #define mmDVMM_REG_RD_DATA_BASE_IDX                                                                    2
1074 #define mmDVMM_PTE_REQ                                                                                 0x00fe
1075 #define mmDVMM_PTE_REQ_BASE_IDX                                                                        2
1076 #define mmDVMM_CNTL                                                                                    0x00ff
1077 #define mmDVMM_CNTL_BASE_IDX                                                                           2
1078 #define mmDVMM_FAULT_STATUS                                                                            0x0100
1079 #define mmDVMM_FAULT_STATUS_BASE_IDX                                                                   2
1080 #define mmDVMM_FAULT_ADDR                                                                              0x0101
1081 #define mmDVMM_FAULT_ADDR_BASE_IDX                                                                     2
1082 #define mmFMON_CTRL                                                                                    0x0102
1083 #define mmFMON_CTRL_BASE_IDX                                                                           2
1084 #define mmDVMM_PTE_PGMEM_CONTROL                                                                       0x0103
1085 #define mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX                                                              2
1086 #define mmDVMM_PTE_PGMEM_STATE                                                                         0x0104
1087 #define mmDVMM_PTE_PGMEM_STATE_BASE_IDX                                                                2
1088 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x0105
1089 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1090 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0106
1091 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
1092 #define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER                                                           0x0107
1093 #define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                  2
1094 #define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER                                                           0x0108
1095 #define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                  2
1096 #define mmDCI_MEM_PWR_CNTL4                                                                            0x0109
1097 #define mmDCI_MEM_PWR_CNTL4_BASE_IDX                                                                   2
1098 #define mmMCIF_WB_MISC_CTRL                                                                            0x010a
1099 #define mmMCIF_WB_MISC_CTRL_BASE_IDX                                                                   2
1100 #define mmDCI_MEM_PWR_STATUS3                                                                          0x010b
1101 #define mmDCI_MEM_PWR_STATUS3_BASE_IDX                                                                 2
1102 #define mmDMIF_CURSOR_CONTROL                                                                          0x010c
1103 #define mmDMIF_CURSOR_CONTROL_BASE_IDX                                                                 2
1104 #define mmDMIF_CURSOR_MEM_CONTROL                                                                      0x010d
1105 #define mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX                                                             2
1106 #define mmDCHUB_FB_LOCATION                                                                            0x0126
1107 #define mmDCHUB_FB_LOCATION_BASE_IDX                                                                   2
1108 #define mmDCHUB_FB_OFFSET                                                                              0x0127
1109 #define mmDCHUB_FB_OFFSET_BASE_IDX                                                                     2
1110 #define mmDCHUB_AGP_BASE                                                                               0x0128
1111 #define mmDCHUB_AGP_BASE_BASE_IDX                                                                      2
1112 #define mmDCHUB_AGP_BOT                                                                                0x0129
1113 #define mmDCHUB_AGP_BOT_BASE_IDX                                                                       2
1114 #define mmDCHUB_AGP_TOP                                                                                0x012a
1115 #define mmDCHUB_AGP_TOP_BASE_IDX                                                                       2
1116 #define mmDCHUB_DRAM_APER_BASE                                                                         0x012b
1117 #define mmDCHUB_DRAM_APER_BASE_BASE_IDX                                                                2
1118 #define mmDCHUB_DRAM_APER_DEF                                                                          0x012c
1119 #define mmDCHUB_DRAM_APER_DEF_BASE_IDX                                                                 2
1120 #define mmDCHUB_DRAM_APER_TOP                                                                          0x012d
1121 #define mmDCHUB_DRAM_APER_TOP_BASE_IDX                                                                 2
1122 #define mmDCHUB_CONTROL_STATUS                                                                         0x012e
1123 #define mmDCHUB_CONTROL_STATUS_BASE_IDX                                                                2
1124 #define mmWB_ENABLE                                                                                    0x0212
1125 #define mmWB_ENABLE_BASE_IDX                                                                           2
1126 #define mmWB_EC_CONFIG                                                                                 0x0213
1127 #define mmWB_EC_CONFIG_BASE_IDX                                                                        2
1128 #define mmCNV_MODE                                                                                     0x0214
1129 #define mmCNV_MODE_BASE_IDX                                                                            2
1130 #define mmCNV_WINDOW_START                                                                             0x0215
1131 #define mmCNV_WINDOW_START_BASE_IDX                                                                    2
1132 #define mmCNV_WINDOW_SIZE                                                                              0x0216
1133 #define mmCNV_WINDOW_SIZE_BASE_IDX                                                                     2
1134 #define mmCNV_UPDATE                                                                                   0x0217
1135 #define mmCNV_UPDATE_BASE_IDX                                                                          2
1136 #define mmCNV_SOURCE_SIZE                                                                              0x0218
1137 #define mmCNV_SOURCE_SIZE_BASE_IDX                                                                     2
1138 #define mmCNV_CSC_CONTROL                                                                              0x0219
1139 #define mmCNV_CSC_CONTROL_BASE_IDX                                                                     2
1140 #define mmCNV_CSC_C11_C12                                                                              0x021a
1141 #define mmCNV_CSC_C11_C12_BASE_IDX                                                                     2
1142 #define mmCNV_CSC_C13_C14                                                                              0x021b
1143 #define mmCNV_CSC_C13_C14_BASE_IDX                                                                     2
1144 #define mmCNV_CSC_C21_C22                                                                              0x021c
1145 #define mmCNV_CSC_C21_C22_BASE_IDX                                                                     2
1146 #define mmCNV_CSC_C23_C24                                                                              0x021d
1147 #define mmCNV_CSC_C23_C24_BASE_IDX                                                                     2
1148 #define mmCNV_CSC_C31_C32                                                                              0x021e
1149 #define mmCNV_CSC_C31_C32_BASE_IDX                                                                     2
1150 #define mmCNV_CSC_C33_C34                                                                              0x021f
1151 #define mmCNV_CSC_C33_C34_BASE_IDX                                                                     2
1152 #define mmCNV_CSC_ROUND_OFFSET_R                                                                       0x0220
1153 #define mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX                                                              2
1154 #define mmCNV_CSC_ROUND_OFFSET_G                                                                       0x0221
1155 #define mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX                                                              2
1156 #define mmCNV_CSC_ROUND_OFFSET_B                                                                       0x0222
1157 #define mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX                                                              2
1158 #define mmCNV_CSC_CLAMP_R                                                                              0x0223
1159 #define mmCNV_CSC_CLAMP_R_BASE_IDX                                                                     2
1160 #define mmCNV_CSC_CLAMP_G                                                                              0x0224
1161 #define mmCNV_CSC_CLAMP_G_BASE_IDX                                                                     2
1162 #define mmCNV_CSC_CLAMP_B                                                                              0x0225
1163 #define mmCNV_CSC_CLAMP_B_BASE_IDX                                                                     2
1164 #define mmCNV_TEST_CNTL                                                                                0x0226
1165 #define mmCNV_TEST_CNTL_BASE_IDX                                                                       2
1166 #define mmCNV_TEST_CRC_RED                                                                             0x0227
1167 #define mmCNV_TEST_CRC_RED_BASE_IDX                                                                    2
1168 #define mmCNV_TEST_CRC_GREEN                                                                           0x0228
1169 #define mmCNV_TEST_CRC_GREEN_BASE_IDX                                                                  2
1170 #define mmCNV_TEST_CRC_BLUE                                                                            0x0229
1171 #define mmCNV_TEST_CRC_BLUE_BASE_IDX                                                                   2
1172 #define mmCNV_INPUT_SELECT                                                                             0x022d
1173 #define mmCNV_INPUT_SELECT_BASE_IDX                                                                    2
1174 #define mmWB_SOFT_RESET                                                                                0x0230
1175 #define mmWB_SOFT_RESET_BASE_IDX                                                                       2
1176 #define mmWB_WARM_UP_MODE_CTL1                                                                         0x0231
1177 #define mmWB_WARM_UP_MODE_CTL1_BASE_IDX                                                                2
1178 #define mmWB_WARM_UP_MODE_CTL2                                                                         0x0232
1179 #define mmWB_WARM_UP_MODE_CTL2_BASE_IDX                                                                2
1180 #define mmWBSCL_COEF_RAM_SELECT                                                                        0x0242
1181 #define mmWBSCL_COEF_RAM_SELECT_BASE_IDX                                                               2
1182 #define mmWBSCL_COEF_RAM_TAP_DATA                                                                      0x0243
1183 #define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX                                                             2
1184 #define mmWBSCL_MODE                                                                                   0x0244
1185 #define mmWBSCL_MODE_BASE_IDX                                                                          2
1186 #define mmWBSCL_TAP_CONTROL                                                                            0x0245
1187 #define mmWBSCL_TAP_CONTROL_BASE_IDX                                                                   2
1188 #define mmWBSCL_DEST_SIZE                                                                              0x0246
1189 #define mmWBSCL_DEST_SIZE_BASE_IDX                                                                     2
1190 #define mmWBSCL_HORZ_FILTER_SCALE_RATIO                                                                0x0247
1191 #define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                       2
1192 #define mmWBSCL_HORZ_FILTER_INIT_Y_RGB                                                                 0x0248
1193 #define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX                                                        2
1194 #define mmWBSCL_HORZ_FILTER_INIT_CBCR                                                                  0x0249
1195 #define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX                                                         2
1196 #define mmWBSCL_VERT_FILTER_SCALE_RATIO                                                                0x024a
1197 #define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                       2
1198 #define mmWBSCL_VERT_FILTER_INIT_Y_RGB                                                                 0x024b
1199 #define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX                                                        2
1200 #define mmWBSCL_VERT_FILTER_INIT_CBCR                                                                  0x024c
1201 #define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX                                                         2
1202 #define mmWBSCL_ROUND_OFFSET                                                                           0x024d
1203 #define mmWBSCL_ROUND_OFFSET_BASE_IDX                                                                  2
1204 #define mmWBSCL_CLAMP                                                                                  0x024e
1205 #define mmWBSCL_CLAMP_BASE_IDX                                                                         2
1206 #define mmWBSCL_OVERFLOW_STATUS                                                                        0x024f
1207 #define mmWBSCL_OVERFLOW_STATUS_BASE_IDX                                                               2
1208 #define mmWBSCL_COEF_RAM_CONFLICT_STATUS                                                               0x0250
1209 #define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                      2
1210 #define mmWBSCL_OUTSIDE_PIX_STRATEGY                                                                   0x0251
1211 #define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX                                                          2
1212 #define mmWBSCL_TEST_CNTL                                                                              0x0252
1213 #define mmWBSCL_TEST_CNTL_BASE_IDX                                                                     2
1214 #define mmWBSCL_TEST_CRC_RED                                                                           0x0253
1215 #define mmWBSCL_TEST_CRC_RED_BASE_IDX                                                                  2
1216 #define mmWBSCL_TEST_CRC_GREEN                                                                         0x0254
1217 #define mmWBSCL_TEST_CRC_GREEN_BASE_IDX                                                                2
1218 #define mmWBSCL_TEST_CRC_BLUE                                                                          0x0255
1219 #define mmWBSCL_TEST_CRC_BLUE_BASE_IDX                                                                 2
1220 #define mmWBSCL_BACKPRESSURE_CNT_EN                                                                    0x0256
1221 #define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX                                                           2
1222 #define mmWB_MCIF_BACKPRESSURE_CNT                                                                     0x0257
1223 #define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX                                                            2
1224 #define mmWBSCL_RAM_SHUTDOWN                                                                           0x025a
1225 #define mmWBSCL_RAM_SHUTDOWN_BASE_IDX                                                                  2
1226 #define mmDMCU_CTRL                                                                                    0x03b6
1227 #define mmDMCU_CTRL_BASE_IDX                                                                           2
1228 #define mmDMCU_STATUS                                                                                  0x03b7
1229 #define mmDMCU_STATUS_BASE_IDX                                                                         2
1230 #define mmDMCU_PC_START_ADDR                                                                           0x03b8
1231 #define mmDMCU_PC_START_ADDR_BASE_IDX                                                                  2
1232 #define mmDMCU_FW_START_ADDR                                                                           0x03b9
1233 #define mmDMCU_FW_START_ADDR_BASE_IDX                                                                  2
1234 #define mmDMCU_FW_END_ADDR                                                                             0x03ba
1235 #define mmDMCU_FW_END_ADDR_BASE_IDX                                                                    2
1236 #define mmDMCU_FW_ISR_START_ADDR                                                                       0x03bb
1237 #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
1238 #define mmDMCU_FW_CS_HI                                                                                0x03bc
1239 #define mmDMCU_FW_CS_HI_BASE_IDX                                                                       2
1240 #define mmDMCU_FW_CS_LO                                                                                0x03bd
1241 #define mmDMCU_FW_CS_LO_BASE_IDX                                                                       2
1242 #define mmDMCU_RAM_ACCESS_CTRL                                                                         0x03be
1243 #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
1244 #define mmDMCU_ERAM_WR_CTRL                                                                            0x03bf
1245 #define mmDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
1246 #define mmDMCU_ERAM_WR_DATA                                                                            0x03c0
1247 #define mmDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
1248 #define mmDMCU_ERAM_RD_CTRL                                                                            0x03c1
1249 #define mmDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
1250 #define mmDMCU_ERAM_RD_DATA                                                                            0x03c2
1251 #define mmDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
1252 #define mmDMCU_IRAM_WR_CTRL                                                                            0x03c3
1253 #define mmDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
1254 #define mmDMCU_IRAM_WR_DATA                                                                            0x03c4
1255 #define mmDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
1256 #define mmDMCU_IRAM_RD_CTRL                                                                            0x03c5
1257 #define mmDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
1258 #define mmDMCU_IRAM_RD_DATA                                                                            0x03c6
1259 #define mmDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
1260 #define mmDMCU_EVENT_TRIGGER                                                                           0x03c7
1261 #define mmDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
1262 #define mmDMCU_UC_INTERNAL_INT_STATUS                                                                  0x03c8
1263 #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
1264 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x03c9
1265 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
1266 #define mmDMCU_INTERRUPT_STATUS                                                                        0x03ca
1267 #define mmDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
1268 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x03cb
1269 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
1270 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x03cc
1271 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
1272 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x03cd
1273 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
1274 #define mmDC_DMCU_SCRATCH                                                                              0x03ce
1275 #define mmDC_DMCU_SCRATCH_BASE_IDX                                                                     2
1276 #define mmDMCU_INT_CNT                                                                                 0x03cf
1277 #define mmDMCU_INT_CNT_BASE_IDX                                                                        2
1278 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x03d0
1279 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
1280 #define mmDMCU_UC_CLK_GATING_CNTL                                                                      0x03d1
1281 #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
1282 #define mmMASTER_COMM_DATA_REG1                                                                        0x03d2
1283 #define mmMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
1284 #define mmMASTER_COMM_DATA_REG2                                                                        0x03d3
1285 #define mmMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
1286 #define mmMASTER_COMM_DATA_REG3                                                                        0x03d4
1287 #define mmMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
1288 #define mmMASTER_COMM_CMD_REG                                                                          0x03d5
1289 #define mmMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
1290 #define mmMASTER_COMM_CNTL_REG                                                                         0x03d6
1291 #define mmMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
1292 #define mmSLAVE_COMM_DATA_REG1                                                                         0x03d7
1293 #define mmSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
1294 #define mmSLAVE_COMM_DATA_REG2                                                                         0x03d8
1295 #define mmSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
1296 #define mmSLAVE_COMM_DATA_REG3                                                                         0x03d9
1297 #define mmSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
1298 #define mmSLAVE_COMM_CMD_REG                                                                           0x03da
1299 #define mmSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
1300 #define mmSLAVE_COMM_CNTL_REG                                                                          0x03db
1301 #define mmSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
1302 #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                                                  0x03de
1303 #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                         2
1304 #define mmBL1_PWM_USER_LEVEL                                                                           0x03df
1305 #define mmBL1_PWM_USER_LEVEL_BASE_IDX                                                                  2
1306 #define mmBL1_PWM_TARGET_ABM_LEVEL                                                                     0x03e0
1307 #define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                            2
1308 #define mmBL1_PWM_CURRENT_ABM_LEVEL                                                                    0x03e1
1309 #define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                           2
1310 #define mmBL1_PWM_FINAL_DUTY_CYCLE                                                                     0x03e2
1311 #define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                            2
1312 #define mmBL1_PWM_MINIMUM_DUTY_CYCLE                                                                   0x03e3
1313 #define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                          2
1314 #define mmBL1_PWM_ABM_CNTL                                                                             0x03e4
1315 #define mmBL1_PWM_ABM_CNTL_BASE_IDX                                                                    2
1316 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                                                0x03e5
1317 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                       2
1318 #define mmBL1_PWM_GRP2_REG_LOCK                                                                        0x03e6
1319 #define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                               2
1320 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x03e7
1321 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
1322 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x03e8
1323 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
1324 #define mmDMCU_INTERRUPT_STATUS_1                                                                      0x03e9
1325 #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
1326 #define mmDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x03ea
1327 #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
1328 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x03eb
1329 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
1330 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x03ec
1331 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
1332 #define mmDC_ABM1_CNTL                                                                                 0x03ee
1333 #define mmDC_ABM1_CNTL_BASE_IDX                                                                        2
1334 #define mmDC_ABM1_IPCSC_COEFF_SEL                                                                      0x03ef
1335 #define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                             2
1336 #define mmDC_ABM1_ACE_OFFSET_SLOPE_0                                                                   0x03f0
1337 #define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                          2
1338 #define mmDC_ABM1_ACE_OFFSET_SLOPE_1                                                                   0x03f1
1339 #define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                          2
1340 #define mmDC_ABM1_ACE_OFFSET_SLOPE_2                                                                   0x03f2
1341 #define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                          2
1342 #define mmDC_ABM1_ACE_OFFSET_SLOPE_3                                                                   0x03f3
1343 #define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                          2
1344 #define mmDC_ABM1_ACE_OFFSET_SLOPE_4                                                                   0x03f4
1345 #define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                          2
1346 #define mmDC_ABM1_ACE_THRES_12                                                                         0x03f5
1347 #define mmDC_ABM1_ACE_THRES_12_BASE_IDX                                                                2
1348 #define mmDC_ABM1_ACE_THRES_34                                                                         0x03f6
1349 #define mmDC_ABM1_ACE_THRES_34_BASE_IDX                                                                2
1350 #define mmDC_ABM1_ACE_CNTL_MISC                                                                        0x03f7
1351 #define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                               2
1352 #define mmDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x03f8
1353 #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
1354 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x03f9
1355 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
1356 #define mmDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x03fa
1357 #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
1358 #define mmDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x03fb
1359 #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
1360 #define mmDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x03fc
1361 #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
1362 #define mmDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x03fd
1363 #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
1364 #define mmDC_ABM1_HGLS_REG_READ_PROGRESS                                                               0x0400
1365 #define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                      2
1366 #define mmDC_ABM1_HG_MISC_CTRL                                                                         0x0401
1367 #define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX                                                                2
1368 #define mmDC_ABM1_LS_SUM_OF_LUMA                                                                       0x0402
1369 #define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                              2
1370 #define mmDC_ABM1_LS_MIN_MAX_LUMA                                                                      0x0403
1371 #define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                             2
1372 #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                             0x0404
1373 #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                                    2
1374 #define mmDC_ABM1_LS_PIXEL_COUNT                                                                       0x0405
1375 #define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                              2
1376 #define mmDC_ABM1_LS_OVR_SCAN_BIN                                                                      0x0406
1377 #define mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX                                                             2
1378 #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                         0x0407
1379 #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                                2
1380 #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                             0x0408
1381 #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                                    2
1382 #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                             0x0409
1383 #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                                    2
1384 #define mmDC_ABM1_HG_SAMPLE_RATE                                                                       0x040a
1385 #define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                              2
1386 #define mmDC_ABM1_LS_SAMPLE_RATE                                                                       0x040b
1387 #define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                              2
1388 #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                               0x040c
1389 #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                      2
1390 #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                               0x040d
1391 #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                      2
1392 #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                              0x040e
1393 #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                     2
1394 #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                             0x040f
1395 #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                                    2
1396 #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                             0x0410
1397 #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                                    2
1398 #define mmDC_ABM1_HG_RESULT_1                                                                          0x0411
1399 #define mmDC_ABM1_HG_RESULT_1_BASE_IDX                                                                 2
1400 #define mmDC_ABM1_HG_RESULT_2                                                                          0x0412
1401 #define mmDC_ABM1_HG_RESULT_2_BASE_IDX                                                                 2
1402 #define mmDC_ABM1_HG_RESULT_3                                                                          0x0413
1403 #define mmDC_ABM1_HG_RESULT_3_BASE_IDX                                                                 2
1404 #define mmDC_ABM1_HG_RESULT_4                                                                          0x0414
1405 #define mmDC_ABM1_HG_RESULT_4_BASE_IDX                                                                 2
1406 #define mmDC_ABM1_HG_RESULT_5                                                                          0x0415
1407 #define mmDC_ABM1_HG_RESULT_5_BASE_IDX                                                                 2
1408 #define mmDC_ABM1_HG_RESULT_6                                                                          0x0416
1409 #define mmDC_ABM1_HG_RESULT_6_BASE_IDX                                                                 2
1410 #define mmDC_ABM1_HG_RESULT_7                                                                          0x0417
1411 #define mmDC_ABM1_HG_RESULT_7_BASE_IDX                                                                 2
1412 #define mmDC_ABM1_HG_RESULT_8                                                                          0x0418
1413 #define mmDC_ABM1_HG_RESULT_8_BASE_IDX                                                                 2
1414 #define mmDC_ABM1_HG_RESULT_9                                                                          0x0419
1415 #define mmDC_ABM1_HG_RESULT_9_BASE_IDX                                                                 2
1416 #define mmDC_ABM1_HG_RESULT_10                                                                         0x041a
1417 #define mmDC_ABM1_HG_RESULT_10_BASE_IDX                                                                2
1418 #define mmDC_ABM1_HG_RESULT_11                                                                         0x041b
1419 #define mmDC_ABM1_HG_RESULT_11_BASE_IDX                                                                2
1420 #define mmDC_ABM1_HG_RESULT_12                                                                         0x041c
1421 #define mmDC_ABM1_HG_RESULT_12_BASE_IDX                                                                2
1422 #define mmDC_ABM1_HG_RESULT_13                                                                         0x041d
1423 #define mmDC_ABM1_HG_RESULT_13_BASE_IDX                                                                2
1424 #define mmDC_ABM1_HG_RESULT_14                                                                         0x041e
1425 #define mmDC_ABM1_HG_RESULT_14_BASE_IDX                                                                2
1426 #define mmDC_ABM1_HG_RESULT_15                                                                         0x041f
1427 #define mmDC_ABM1_HG_RESULT_15_BASE_IDX                                                                2
1428 #define mmDC_ABM1_HG_RESULT_16                                                                         0x0420
1429 #define mmDC_ABM1_HG_RESULT_16_BASE_IDX                                                                2
1430 #define mmDC_ABM1_HG_RESULT_17                                                                         0x0421
1431 #define mmDC_ABM1_HG_RESULT_17_BASE_IDX                                                                2
1432 #define mmDC_ABM1_HG_RESULT_18                                                                         0x0422
1433 #define mmDC_ABM1_HG_RESULT_18_BASE_IDX                                                                2
1434 #define mmDC_ABM1_HG_RESULT_19                                                                         0x0423
1435 #define mmDC_ABM1_HG_RESULT_19_BASE_IDX                                                                2
1436 #define mmDC_ABM1_HG_RESULT_20                                                                         0x0424
1437 #define mmDC_ABM1_HG_RESULT_20_BASE_IDX                                                                2
1438 #define mmDC_ABM1_HG_RESULT_21                                                                         0x0425
1439 #define mmDC_ABM1_HG_RESULT_21_BASE_IDX                                                                2
1440 #define mmDC_ABM1_HG_RESULT_22                                                                         0x0426
1441 #define mmDC_ABM1_HG_RESULT_22_BASE_IDX                                                                2
1442 #define mmDC_ABM1_HG_RESULT_23                                                                         0x0427
1443 #define mmDC_ABM1_HG_RESULT_23_BASE_IDX                                                                2
1444 #define mmDC_ABM1_HG_RESULT_24                                                                         0x0428
1445 #define mmDC_ABM1_HG_RESULT_24_BASE_IDX                                                                2
1446 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0429
1447 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
1448 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x042a
1449 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
1450 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x042b
1451 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
1452 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x042c
1453 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
1454 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x042d
1455 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
1456 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x042e
1457 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
1458 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x042f
1459 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
1460 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0430
1461 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
1462 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0431
1463 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
1464 #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE                                                                 0x0451
1465 #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX                                                        2
1466 #define mmDC_ABM1_BL_MASTER_LOCK                                                                       0x0452
1467 #define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                              2
1468 #define mmAZALIA_CONTROLLER_CLOCK_GATING                                                               0x04bc
1469 #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
1470 #define mmAZALIA_AUDIO_DTO                                                                             0x04bd
1471 #define mmAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
1472 #define mmAZALIA_AUDIO_DTO_CONTROL                                                                     0x04be
1473 #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
1474 #define mmAZALIA_SOCCLK_CONTROL                                                                        0x04bf
1475 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
1476 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x04c0
1477 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
1478 #define mmAZALIA_DATA_DMA_CONTROL                                                                      0x04c1
1479 #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
1480 #define mmAZALIA_BDL_DMA_CONTROL                                                                       0x04c2
1481 #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
1482 #define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x04c3
1483 #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
1484 #define mmAZALIA_CORB_DMA_CONTROL                                                                      0x04c4
1485 #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
1486 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x04cb
1487 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
1488 #define mmAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x04cc
1489 #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
1490 #define mmAZALIA_GLOBAL_CAPABILITIES                                                                   0x04cd
1491 #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
1492 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x04ce
1493 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
1494 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x04cf
1495 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
1496 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x04d0
1497 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
1498 #define mmAZALIA_INPUT_CRC0_CONTROL0                                                                   0x04d3
1499 #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
1500 #define mmAZALIA_INPUT_CRC0_CONTROL1                                                                   0x04d4
1501 #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
1502 #define mmAZALIA_INPUT_CRC0_CONTROL2                                                                   0x04d5
1503 #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
1504 #define mmAZALIA_INPUT_CRC0_CONTROL3                                                                   0x04d6
1505 #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
1506 #define mmAZALIA_INPUT_CRC0_RESULT                                                                     0x04d7
1507 #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
1508 #define mmAZALIA_INPUT_CRC1_CONTROL0                                                                   0x04d8
1509 #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
1510 #define mmAZALIA_INPUT_CRC1_CONTROL1                                                                   0x04d9
1511 #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
1512 #define mmAZALIA_INPUT_CRC1_CONTROL2                                                                   0x04da
1513 #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
1514 #define mmAZALIA_INPUT_CRC1_CONTROL3                                                                   0x04db
1515 #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
1516 #define mmAZALIA_INPUT_CRC1_RESULT                                                                     0x04dc
1517 #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
1518 #define mmAZALIA_CRC0_CONTROL0                                                                         0x04dd
1519 #define mmAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
1520 #define mmAZALIA_CRC0_CONTROL1                                                                         0x04de
1521 #define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
1522 #define mmAZALIA_CRC0_CONTROL2                                                                         0x04df
1523 #define mmAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
1524 #define mmAZALIA_CRC0_CONTROL3                                                                         0x04e0
1525 #define mmAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
1526 #define mmAZALIA_CRC0_RESULT                                                                           0x04e1
1527 #define mmAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
1528 #define mmAZALIA_CRC1_CONTROL0                                                                         0x04e2
1529 #define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
1530 #define mmAZALIA_CRC1_CONTROL1                                                                         0x04e3
1531 #define mmAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
1532 #define mmAZALIA_CRC1_CONTROL2                                                                         0x04e4
1533 #define mmAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
1534 #define mmAZALIA_CRC1_CONTROL3                                                                         0x04e5
1535 #define mmAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
1536 #define mmAZALIA_CRC1_RESULT                                                                           0x04e6
1537 #define mmAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
1538 #define mmAZALIA_MEM_PWR_CTRL                                                                          0x04e8
1539 #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
1540 #define mmAZALIA_MEM_PWR_STATUS                                                                        0x04e9
1541 #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
1542 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0500
1543 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
1544 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0501
1545 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
1546 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0502
1547 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
1548 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0503
1549 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
1550 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x0504
1551 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
1552 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x0505
1553 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
1554 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x0506
1555 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
1556 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x0507
1557 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
1558 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x0508
1559 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
1560 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x0509
1561 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
1562 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x050a
1563 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
1564 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x050b
1565 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
1566 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x050c
1567 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
1568 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x050d
1569 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
1570 #define mmAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x050f
1571 #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
1572 #define mmAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0510
1573 #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
1574 #define mmAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0511
1575 #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
1576 #define mmAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0512
1577 #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
1578 #define mmAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0513
1579 #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
1580 #define mmAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x0514
1581 #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
1582 #define mmAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x0515
1583 #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
1584 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x0516
1585 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
1586 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x0517
1587 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
1588 #define mmDAC_ENABLE                                                                                   0x155a
1589 #define mmDAC_ENABLE_BASE_IDX                                                                          2
1590 #define mmDAC_SOURCE_SELECT                                                                            0x155b
1591 #define mmDAC_SOURCE_SELECT_BASE_IDX                                                                   2
1592 #define mmDAC_CRC_EN                                                                                   0x155c
1593 #define mmDAC_CRC_EN_BASE_IDX                                                                          2
1594 #define mmDAC_CRC_CONTROL                                                                              0x155d
1595 #define mmDAC_CRC_CONTROL_BASE_IDX                                                                     2
1596 #define mmDAC_CRC_SIG_RGB_MASK                                                                         0x155e
1597 #define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX                                                                2
1598 #define mmDAC_CRC_SIG_CONTROL_MASK                                                                     0x155f
1599 #define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX                                                            2
1600 #define mmDAC_CRC_SIG_RGB                                                                              0x1560
1601 #define mmDAC_CRC_SIG_RGB_BASE_IDX                                                                     2
1602 #define mmDAC_CRC_SIG_CONTROL                                                                          0x1561
1603 #define mmDAC_CRC_SIG_CONTROL_BASE_IDX                                                                 2
1604 #define mmDAC_SYNC_TRISTATE_CONTROL                                                                    0x1562
1605 #define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX                                                           2
1606 #define mmDAC_STEREOSYNC_SELECT                                                                        0x1563
1607 #define mmDAC_STEREOSYNC_SELECT_BASE_IDX                                                               2
1608 #define mmDAC_AUTODETECT_CONTROL                                                                       0x1564
1609 #define mmDAC_AUTODETECT_CONTROL_BASE_IDX                                                              2
1610 #define mmDAC_AUTODETECT_CONTROL2                                                                      0x1565
1611 #define mmDAC_AUTODETECT_CONTROL2_BASE_IDX                                                             2
1612 #define mmDAC_AUTODETECT_CONTROL3                                                                      0x1566
1613 #define mmDAC_AUTODETECT_CONTROL3_BASE_IDX                                                             2
1614 #define mmDAC_AUTODETECT_STATUS                                                                        0x1567
1615 #define mmDAC_AUTODETECT_STATUS_BASE_IDX                                                               2
1616 #define mmDAC_AUTODETECT_INT_CONTROL                                                                   0x1568
1617 #define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX                                                          2
1618 #define mmDAC_FORCE_OUTPUT_CNTL                                                                        0x1569
1619 #define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX                                                               2
1620 #define mmDAC_FORCE_DATA                                                                               0x156a
1621 #define mmDAC_FORCE_DATA_BASE_IDX                                                                      2
1622 #define mmDAC_POWERDOWN                                                                                0x156b
1623 #define mmDAC_POWERDOWN_BASE_IDX                                                                       2
1624 #define mmDAC_CONTROL                                                                                  0x156c
1625 #define mmDAC_CONTROL_BASE_IDX                                                                         2
1626 #define mmDAC_COMPARATOR_ENABLE                                                                        0x156d
1627 #define mmDAC_COMPARATOR_ENABLE_BASE_IDX                                                               2
1628 #define mmDAC_COMPARATOR_OUTPUT                                                                        0x156e
1629 #define mmDAC_COMPARATOR_OUTPUT_BASE_IDX                                                               2
1630 #define mmDAC_PWR_CNTL                                                                                 0x156f
1631 #define mmDAC_PWR_CNTL_BASE_IDX                                                                        2
1632 #define mmDAC_DFT_CONFIG                                                                               0x1570
1633 #define mmDAC_DFT_CONFIG_BASE_IDX                                                                      2
1634 #define mmDAC_FIFO_STATUS                                                                              0x1571
1635 #define mmDAC_FIFO_STATUS_BASE_IDX                                                                     2
1636 #define mmDC_I2C_CONTROL                                                                               0x1584
1637 #define mmDC_I2C_CONTROL_BASE_IDX                                                                      2
1638 #define mmDC_I2C_ARBITRATION                                                                           0x1585
1639 #define mmDC_I2C_ARBITRATION_BASE_IDX                                                                  2
1640 #define mmDC_I2C_INTERRUPT_CONTROL                                                                     0x1586
1641 #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
1642 #define mmDC_I2C_SW_STATUS                                                                             0x1587
1643 #define mmDC_I2C_SW_STATUS_BASE_IDX                                                                    2
1644 #define mmDC_I2C_DDC1_HW_STATUS                                                                        0x1588
1645 #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
1646 #define mmDC_I2C_DDC2_HW_STATUS                                                                        0x1589
1647 #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
1648 #define mmDC_I2C_DDC3_HW_STATUS                                                                        0x158a
1649 #define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
1650 #define mmDC_I2C_DDC4_HW_STATUS                                                                        0x158b
1651 #define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
1652 #define mmDC_I2C_DDC5_HW_STATUS                                                                        0x158c
1653 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
1654 #define mmDC_I2C_DDC6_HW_STATUS                                                                        0x158d
1655 #define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX                                                               2
1656 #define mmDC_I2C_DDC1_SPEED                                                                            0x158e
1657 #define mmDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
1658 #define mmDC_I2C_DDC1_SETUP                                                                            0x158f
1659 #define mmDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
1660 #define mmDC_I2C_DDC2_SPEED                                                                            0x1590
1661 #define mmDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
1662 #define mmDC_I2C_DDC2_SETUP                                                                            0x1591
1663 #define mmDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
1664 #define mmDC_I2C_DDC3_SPEED                                                                            0x1592
1665 #define mmDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
1666 #define mmDC_I2C_DDC3_SETUP                                                                            0x1593
1667 #define mmDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
1668 #define mmDC_I2C_DDC4_SPEED                                                                            0x1594
1669 #define mmDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
1670 #define mmDC_I2C_DDC4_SETUP                                                                            0x1595
1671 #define mmDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
1672 #define mmDC_I2C_DDC5_SPEED                                                                            0x1596
1673 #define mmDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
1674 #define mmDC_I2C_DDC5_SETUP                                                                            0x1597
1675 #define mmDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
1676 #define mmDC_I2C_DDC6_SPEED                                                                            0x1598
1677 #define mmDC_I2C_DDC6_SPEED_BASE_IDX                                                                   2
1678 #define mmDC_I2C_DDC6_SETUP                                                                            0x1599
1679 #define mmDC_I2C_DDC6_SETUP_BASE_IDX                                                                   2
1680 #define mmDC_I2C_TRANSACTION0                                                                          0x159a
1681 #define mmDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
1682 #define mmDC_I2C_TRANSACTION1                                                                          0x159b
1683 #define mmDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
1684 #define mmDC_I2C_TRANSACTION2                                                                          0x159c
1685 #define mmDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
1686 #define mmDC_I2C_TRANSACTION3                                                                          0x159d
1687 #define mmDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
1688 #define mmDC_I2C_DATA                                                                                  0x159e
1689 #define mmDC_I2C_DATA_BASE_IDX                                                                         2
1690 #define mmDC_I2C_DDCVGA_HW_STATUS                                                                      0x159f
1691 #define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX                                                             2
1692 #define mmDC_I2C_DDCVGA_SPEED                                                                          0x15a0
1693 #define mmDC_I2C_DDCVGA_SPEED_BASE_IDX                                                                 2
1694 #define mmDC_I2C_DDCVGA_SETUP                                                                          0x15a1
1695 #define mmDC_I2C_DDCVGA_SETUP_BASE_IDX                                                                 2
1696 #define mmDC_I2C_EDID_DETECT_CTRL                                                                      0x15a2
1697 #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
1698 #define mmDC_I2C_READ_REQUEST_INTERRUPT                                                                0x15a3
1699 #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
1700 #define mmGENERIC_I2C_CONTROL                                                                          0x15a4
1701 #define mmGENERIC_I2C_CONTROL_BASE_IDX                                                                 2
1702 #define mmGENERIC_I2C_INTERRUPT_CONTROL                                                                0x15a5
1703 #define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                       2
1704 #define mmGENERIC_I2C_STATUS                                                                           0x15a6
1705 #define mmGENERIC_I2C_STATUS_BASE_IDX                                                                  2
1706 #define mmGENERIC_I2C_SPEED                                                                            0x15a7
1707 #define mmGENERIC_I2C_SPEED_BASE_IDX                                                                   2
1708 #define mmGENERIC_I2C_SETUP                                                                            0x15a8
1709 #define mmGENERIC_I2C_SETUP_BASE_IDX                                                                   2
1710 #define mmGENERIC_I2C_TRANSACTION                                                                      0x15a9
1711 #define mmGENERIC_I2C_TRANSACTION_BASE_IDX                                                             2
1712 #define mmGENERIC_I2C_DATA                                                                             0x15aa
1713 #define mmGENERIC_I2C_DATA_BASE_IDX                                                                    2
1714 #define mmGENERIC_I2C_PIN_SELECTION                                                                    0x15ab
1715 #define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX                                                           2
1716 #define mmDCO_SCRATCH0                                                                                 0x15b6
1717 #define mmDCO_SCRATCH0_BASE_IDX                                                                        2
1718 #define mmDCO_SCRATCH1                                                                                 0x15b7
1719 #define mmDCO_SCRATCH1_BASE_IDX                                                                        2
1720 #define mmDCO_SCRATCH2                                                                                 0x15b8
1721 #define mmDCO_SCRATCH2_BASE_IDX                                                                        2
1722 #define mmDCO_SCRATCH3                                                                                 0x15b9
1723 #define mmDCO_SCRATCH3_BASE_IDX                                                                        2
1724 #define mmDCO_SCRATCH4                                                                                 0x15ba
1725 #define mmDCO_SCRATCH4_BASE_IDX                                                                        2
1726 #define mmDCO_SCRATCH5                                                                                 0x15bb
1727 #define mmDCO_SCRATCH5_BASE_IDX                                                                        2
1728 #define mmDCO_SCRATCH6                                                                                 0x15bc
1729 #define mmDCO_SCRATCH6_BASE_IDX                                                                        2
1730 #define mmDCO_SCRATCH7                                                                                 0x15bd
1731 #define mmDCO_SCRATCH7_BASE_IDX                                                                        2
1732 #define mmDCE_VCE_CONTROL                                                                              0x15be
1733 #define mmDCE_VCE_CONTROL_BASE_IDX                                                                     2
1734 #define mmDISP_INTERRUPT_STATUS                                                                        0x15bf
1735 #define mmDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
1736 #define mmDISP_INTERRUPT_STATUS_CONTINUE                                                               0x15c0
1737 #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
1738 #define mmDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x15c1
1739 #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
1740 #define mmDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x15c2
1741 #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
1742 #define mmDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x15c3
1743 #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
1744 #define mmDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x15c4
1745 #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
1746 #define mmDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x15c5
1747 #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
1748 #define mmDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x15c6
1749 #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
1750 #define mmDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x15c7
1751 #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
1752 #define mmDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x15c8
1753 #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
1754 #define mmDCO_MEM_PWR_STATUS                                                                           0x15c9
1755 #define mmDCO_MEM_PWR_STATUS_BASE_IDX                                                                  2
1756 #define mmDCO_MEM_PWR_CTRL                                                                             0x15ca
1757 #define mmDCO_MEM_PWR_CTRL_BASE_IDX                                                                    2
1758 #define mmDCO_MEM_PWR_CTRL2                                                                            0x15cb
1759 #define mmDCO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
1760 #define mmDCO_CLK_CNTL                                                                                 0x15cc
1761 #define mmDCO_CLK_CNTL_BASE_IDX                                                                        2
1762 #define mmDCO_POWER_MANAGEMENT_CNTL                                                                    0x15d0
1763 #define mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
1764 #define mmDIG_SOFT_RESET_2                                                                             0x15d2
1765 #define mmDIG_SOFT_RESET_2_BASE_IDX                                                                    2
1766 #define mmDCO_STEREOSYNC_SEL                                                                           0x15d6
1767 #define mmDCO_STEREOSYNC_SEL_BASE_IDX                                                                  2
1768 #define mmDCO_SOFT_RESET                                                                               0x15d9
1769 #define mmDCO_SOFT_RESET_BASE_IDX                                                                      2
1770 #define mmDIG_SOFT_RESET                                                                               0x15da
1771 #define mmDIG_SOFT_RESET_BASE_IDX                                                                      2
1772 #define mmDCO_MEM_PWR_STATUS1                                                                          0x15dc
1773 #define mmDCO_MEM_PWR_STATUS1_BASE_IDX                                                                 2
1774 #define mmDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x15dd
1775 #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
1776 #define mmDCO_CLK_CNTL2                                                                                0x15de
1777 #define mmDCO_CLK_CNTL2_BASE_IDX                                                                       2
1778 #define mmDCO_CLK_CNTL3                                                                                0x15df
1779 #define mmDCO_CLK_CNTL3_BASE_IDX                                                                       2
1780 #define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x15eb
1781 #define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
1782 #define mmDCO_PSP_INTERRUPT_STATUS                                                                     0x15ec
1783 #define mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX                                                            2
1784 #define mmDCO_PSP_INTERRUPT_CLEAR                                                                      0x15ed
1785 #define mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX                                                             2
1786 #define mmDCO_GENERIC_INTERRUPT_MESSAGE                                                                0x15ee
1787 #define mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
1788 #define mmDCO_GENERIC_INTERRUPT_CLEAR                                                                  0x15ef
1789 #define mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
1790 #define mmFMT_MEMORY0_CONTROL                                                                          0x15f0
1791 #define mmFMT_MEMORY0_CONTROL_BASE_IDX                                                                 2
1792 #define mmFMT_MEMORY1_CONTROL                                                                          0x15f1
1793 #define mmFMT_MEMORY1_CONTROL_BASE_IDX                                                                 2
1794 #define mmFMT_MEMORY2_CONTROL                                                                          0x15f2
1795 #define mmFMT_MEMORY2_CONTROL_BASE_IDX                                                                 2
1796 #define mmFMT_MEMORY3_CONTROL                                                                          0x15f3
1797 #define mmFMT_MEMORY3_CONTROL_BASE_IDX                                                                 2
1798 #define mmFMT_MEMORY4_CONTROL                                                                          0x15f4
1799 #define mmFMT_MEMORY4_CONTROL_BASE_IDX                                                                 2
1800 #define mmFMT_MEMORY5_CONTROL                                                                          0x15f5
1801 #define mmFMT_MEMORY5_CONTROL_BASE_IDX                                                                 2
1802 #define mmDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x15f6
1803 #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
1804 #define mmDC_GENERICA                                                                                  0x207e
1805 #define mmDC_GENERICA_BASE_IDX                                                                         2
1806 #define mmDC_GENERICB                                                                                  0x207f
1807 #define mmDC_GENERICB_BASE_IDX                                                                         2
1808 #define mmDC_PAD_EXTERN_SIG                                                                            0x2080
1809 #define mmDC_PAD_EXTERN_SIG_BASE_IDX                                                                   2
1810 #define mmDC_REF_CLK_CNTL                                                                              0x2081
1811 #define mmDC_REF_CLK_CNTL_BASE_IDX                                                                     2
1812 #define mmDC_GPIO_DEBUG                                                                                0x2082
1813 #define mmDC_GPIO_DEBUG_BASE_IDX                                                                       2
1814 #define mmUNIPHYA_LINK_CNTL                                                                            0x2083
1815 #define mmUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
1816 #define mmUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x2084
1817 #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
1818 #define mmUNIPHYB_LINK_CNTL                                                                            0x2085
1819 #define mmUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
1820 #define mmUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2086
1821 #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
1822 #define mmUNIPHYC_LINK_CNTL                                                                            0x2087
1823 #define mmUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
1824 #define mmUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2088
1825 #define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
1826 #define mmUNIPHYD_LINK_CNTL                                                                            0x2089
1827 #define mmUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
1828 #define mmUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x208a
1829 #define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
1830 #define mmUNIPHYE_LINK_CNTL                                                                            0x208b
1831 #define mmUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
1832 #define mmUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x208c
1833 #define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
1834 #define mmUNIPHYF_LINK_CNTL                                                                            0x208d
1835 #define mmUNIPHYF_LINK_CNTL_BASE_IDX                                                                   2
1836 #define mmUNIPHYF_CHANNEL_XBAR_CNTL                                                                    0x208e
1837 #define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
1838 #define mmUNIPHYG_LINK_CNTL                                                                            0x208f
1839 #define mmUNIPHYG_LINK_CNTL_BASE_IDX                                                                   2
1840 #define mmUNIPHYG_CHANNEL_XBAR_CNTL                                                                    0x2090
1841 #define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
1842 #define mmDCIO_WRCMD_DELAY                                                                             0x2094
1843 #define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
1844 #define mmDC_PINSTRAPS                                                                                 0x2096
1845 #define mmDC_PINSTRAPS_BASE_IDX                                                                        2
1846 #define mmCC_DC_MISC_STRAPS                                                                            0x2097
1847 #define mmCC_DC_MISC_STRAPS_BASE_IDX                                                                   2
1848 #define mmDC_DVODATA_CONFIG                                                                            0x2098
1849 #define mmDC_DVODATA_CONFIG_BASE_IDX                                                                   2
1850 #define mmLVTMA_PWRSEQ_CNTL                                                                            0x2099
1851 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX                                                                   2
1852 #define mmLVTMA_PWRSEQ_STATE                                                                           0x209a
1853 #define mmLVTMA_PWRSEQ_STATE_BASE_IDX                                                                  2
1854 #define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x209b
1855 #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2
1856 #define mmLVTMA_PWRSEQ_DELAY1                                                                          0x209c
1857 #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2
1858 #define mmLVTMA_PWRSEQ_DELAY2                                                                          0x209d
1859 #define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX                                                                 2
1860 #define mmBL_PWM_CNTL                                                                                  0x209e
1861 #define mmBL_PWM_CNTL_BASE_IDX                                                                         2
1862 #define mmBL_PWM_CNTL2                                                                                 0x209f
1863 #define mmBL_PWM_CNTL2_BASE_IDX                                                                        2
1864 #define mmBL_PWM_PERIOD_CNTL                                                                           0x20a0
1865 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
1866 #define mmBL_PWM_GRP1_REG_LOCK                                                                         0x20a1
1867 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
1868 #define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x20a2
1869 #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
1870 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x20a3
1871 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
1872 #define mmDCIO_GSL0_CNTL                                                                               0x20a4
1873 #define mmDCIO_GSL0_CNTL_BASE_IDX                                                                      2
1874 #define mmDCIO_GSL1_CNTL                                                                               0x20a5
1875 #define mmDCIO_GSL1_CNTL_BASE_IDX                                                                      2
1876 #define mmDCIO_GSL2_CNTL                                                                               0x20a6
1877 #define mmDCIO_GSL2_CNTL_BASE_IDX                                                                      2
1878 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x20a7
1879 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
1880 #define mmDC_GPU_TIMER_START_POSITION_P_FLIP                                                           0x20a8
1881 #define mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX                                                  2
1882 #define mmDC_GPU_TIMER_READ                                                                            0x20a9
1883 #define mmDC_GPU_TIMER_READ_BASE_IDX                                                                   2
1884 #define mmDC_GPU_TIMER_READ_CNTL                                                                       0x20aa
1885 #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
1886 #define mmDCIO_CLOCK_CNTL                                                                              0x20ab
1887 #define mmDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
1888 #define mmDCO_DCFE_EXT_VSYNC_CNTL                                                                      0x20ae
1889 #define mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX                                                             2
1890 #define mmDCIO_SOFT_RESET                                                                              0x20b4
1891 #define mmDCIO_SOFT_RESET_BASE_IDX                                                                     2
1892 #define mmDCIO_DPHY_SEL                                                                                0x20b5
1893 #define mmDCIO_DPHY_SEL_BASE_IDX                                                                       2
1894 #define mmUNIPHY_IMPCAL_LINKA                                                                          0x20b6
1895 #define mmUNIPHY_IMPCAL_LINKA_BASE_IDX                                                                 2
1896 #define mmUNIPHY_IMPCAL_LINKB                                                                          0x20b7
1897 #define mmUNIPHY_IMPCAL_LINKB_BASE_IDX                                                                 2
1898 #define mmUNIPHY_IMPCAL_PERIOD                                                                         0x20b8
1899 #define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX                                                                2
1900 #define mmAUXP_IMPCAL                                                                                  0x20b9
1901 #define mmAUXP_IMPCAL_BASE_IDX                                                                         2
1902 #define mmAUXN_IMPCAL                                                                                  0x20ba
1903 #define mmAUXN_IMPCAL_BASE_IDX                                                                         2
1904 #define mmDCIO_IMPCAL_CNTL                                                                             0x20bb
1905 #define mmDCIO_IMPCAL_CNTL_BASE_IDX                                                                    2
1906 #define mmUNIPHY_IMPCAL_PSW_AB                                                                         0x20bc
1907 #define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX                                                                2
1908 #define mmUNIPHY_IMPCAL_LINKC                                                                          0x20bd
1909 #define mmUNIPHY_IMPCAL_LINKC_BASE_IDX                                                                 2
1910 #define mmUNIPHY_IMPCAL_LINKD                                                                          0x20be
1911 #define mmUNIPHY_IMPCAL_LINKD_BASE_IDX                                                                 2
1912 #define mmDCIO_IMPCAL_CNTL_CD                                                                          0x20bf
1913 #define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX                                                                 2
1914 #define mmUNIPHY_IMPCAL_PSW_CD                                                                         0x20c0
1915 #define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX                                                                2
1916 #define mmUNIPHY_IMPCAL_LINKE                                                                          0x20c1
1917 #define mmUNIPHY_IMPCAL_LINKE_BASE_IDX                                                                 2
1918 #define mmUNIPHY_IMPCAL_LINKF                                                                          0x20c2
1919 #define mmUNIPHY_IMPCAL_LINKF_BASE_IDX                                                                 2
1920 #define mmDCIO_IMPCAL_CNTL_EF                                                                          0x20c3
1921 #define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX                                                                 2
1922 #define mmUNIPHY_IMPCAL_PSW_EF                                                                         0x20c4
1923 #define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX                                                                2
1924 #define mmUNIPHYLPA_LINK_CNTL                                                                          0x20c5
1925 #define mmUNIPHYLPA_LINK_CNTL_BASE_IDX                                                                 2
1926 #define mmUNIPHYLPB_LINK_CNTL                                                                          0x20c6
1927 #define mmUNIPHYLPB_LINK_CNTL_BASE_IDX                                                                 2
1928 #define mmUNIPHYLPA_CHANNEL_XBAR_CNTL                                                                  0x20c7
1929 #define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX                                                         2
1930 #define mmUNIPHYLPB_CHANNEL_XBAR_CNTL                                                                  0x20c8
1931 #define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX                                                         2
1932 #define mmDCIO_DPCS_TX_INTERRUPT                                                                       0x20c9
1933 #define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX                                                              2
1934 #define mmDCIO_DPCS_RX_INTERRUPT                                                                       0x20ca
1935 #define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX                                                              2
1936 #define mmDCIO_SEMAPHORE0                                                                              0x20cb
1937 #define mmDCIO_SEMAPHORE0_BASE_IDX                                                                     2
1938 #define mmDCIO_SEMAPHORE1                                                                              0x20cc
1939 #define mmDCIO_SEMAPHORE1_BASE_IDX                                                                     2
1940 #define mmDCIO_SEMAPHORE2                                                                              0x20cd
1941 #define mmDCIO_SEMAPHORE2_BASE_IDX                                                                     2
1942 #define mmDCIO_SEMAPHORE3                                                                              0x20ce
1943 #define mmDCIO_SEMAPHORE3_BASE_IDX                                                                     2
1944 #define mmDCIO_SEMAPHORE4                                                                              0x20cf
1945 #define mmDCIO_SEMAPHORE4_BASE_IDX                                                                     2
1946 #define mmDCIO_SEMAPHORE5                                                                              0x20d0
1947 #define mmDCIO_SEMAPHORE5_BASE_IDX                                                                     2
1948 #define mmDCIO_SEMAPHORE6                                                                              0x20d1
1949 #define mmDCIO_SEMAPHORE6_BASE_IDX                                                                     2
1950 #define mmDCIO_SEMAPHORE7                                                                              0x20d2
1951 #define mmDCIO_SEMAPHORE7_BASE_IDX                                                                     2
1952 #define mmDC_GPIO_GENERIC_MASK                                                                         0x20de
1953 #define mmDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
1954 #define mmDC_GPIO_GENERIC_A                                                                            0x20df
1955 #define mmDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
1956 #define mmDC_GPIO_GENERIC_EN                                                                           0x20e0
1957 #define mmDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
1958 #define mmDC_GPIO_GENERIC_Y                                                                            0x20e1
1959 #define mmDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
1960 #define mmDC_GPIO_DVODATA_MASK                                                                         0x20e2
1961 #define mmDC_GPIO_DVODATA_MASK_BASE_IDX                                                                2
1962 #define mmDC_GPIO_DVODATA_A                                                                            0x20e3
1963 #define mmDC_GPIO_DVODATA_A_BASE_IDX                                                                   2
1964 #define mmDC_GPIO_DVODATA_EN                                                                           0x20e4
1965 #define mmDC_GPIO_DVODATA_EN_BASE_IDX                                                                  2
1966 #define mmDC_GPIO_DVODATA_Y                                                                            0x20e5
1967 #define mmDC_GPIO_DVODATA_Y_BASE_IDX                                                                   2
1968 #define mmDC_GPIO_DDC1_MASK                                                                            0x20e6
1969 #define mmDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
1970 #define mmDC_GPIO_DDC1_A                                                                               0x20e7
1971 #define mmDC_GPIO_DDC1_A_BASE_IDX                                                                      2
1972 #define mmDC_GPIO_DDC1_EN                                                                              0x20e8
1973 #define mmDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
1974 #define mmDC_GPIO_DDC1_Y                                                                               0x20e9
1975 #define mmDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
1976 #define mmDC_GPIO_DDC2_MASK                                                                            0x20ea
1977 #define mmDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
1978 #define mmDC_GPIO_DDC2_A                                                                               0x20eb
1979 #define mmDC_GPIO_DDC2_A_BASE_IDX                                                                      2
1980 #define mmDC_GPIO_DDC2_EN                                                                              0x20ec
1981 #define mmDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
1982 #define mmDC_GPIO_DDC2_Y                                                                               0x20ed
1983 #define mmDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
1984 #define mmDC_GPIO_DDC3_MASK                                                                            0x20ee
1985 #define mmDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
1986 #define mmDC_GPIO_DDC3_A                                                                               0x20ef
1987 #define mmDC_GPIO_DDC3_A_BASE_IDX                                                                      2
1988 #define mmDC_GPIO_DDC3_EN                                                                              0x20f0
1989 #define mmDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
1990 #define mmDC_GPIO_DDC3_Y                                                                               0x20f1
1991 #define mmDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
1992 #define mmDC_GPIO_DDC4_MASK                                                                            0x20f2
1993 #define mmDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
1994 #define mmDC_GPIO_DDC4_A                                                                               0x20f3
1995 #define mmDC_GPIO_DDC4_A_BASE_IDX                                                                      2
1996 #define mmDC_GPIO_DDC4_EN                                                                              0x20f4
1997 #define mmDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
1998 #define mmDC_GPIO_DDC4_Y                                                                               0x20f5
1999 #define mmDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
2000 #define mmDC_GPIO_DDC5_MASK                                                                            0x20f6
2001 #define mmDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
2002 #define mmDC_GPIO_DDC5_A                                                                               0x20f7
2003 #define mmDC_GPIO_DDC5_A_BASE_IDX                                                                      2
2004 #define mmDC_GPIO_DDC5_EN                                                                              0x20f8
2005 #define mmDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
2006 #define mmDC_GPIO_DDC5_Y                                                                               0x20f9
2007 #define mmDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
2008 #define mmDC_GPIO_DDC6_MASK                                                                            0x20fa
2009 #define mmDC_GPIO_DDC6_MASK_BASE_IDX                                                                   2
2010 #define mmDC_GPIO_DDC6_A                                                                               0x20fb
2011 #define mmDC_GPIO_DDC6_A_BASE_IDX                                                                      2
2012 #define mmDC_GPIO_DDC6_EN                                                                              0x20fc
2013 #define mmDC_GPIO_DDC6_EN_BASE_IDX                                                                     2
2014 #define mmDC_GPIO_DDC6_Y                                                                               0x20fd
2015 #define mmDC_GPIO_DDC6_Y_BASE_IDX                                                                      2
2016 #define mmDC_GPIO_DDCVGA_MASK                                                                          0x20fe
2017 #define mmDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
2018 #define mmDC_GPIO_DDCVGA_A                                                                             0x20ff
2019 #define mmDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
2020 #define mmDC_GPIO_DDCVGA_EN                                                                            0x2100
2021 #define mmDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
2022 #define mmDC_GPIO_DDCVGA_Y                                                                             0x2101
2023 #define mmDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
2024 #define mmDC_GPIO_SYNCA_MASK                                                                           0x2102
2025 #define mmDC_GPIO_SYNCA_MASK_BASE_IDX                                                                  2
2026 #define mmDC_GPIO_SYNCA_A                                                                              0x2103
2027 #define mmDC_GPIO_SYNCA_A_BASE_IDX                                                                     2
2028 #define mmDC_GPIO_SYNCA_EN                                                                             0x2104
2029 #define mmDC_GPIO_SYNCA_EN_BASE_IDX                                                                    2
2030 #define mmDC_GPIO_SYNCA_Y                                                                              0x2105
2031 #define mmDC_GPIO_SYNCA_Y_BASE_IDX                                                                     2
2032 #define mmDC_GPIO_GENLK_MASK                                                                           0x2106
2033 #define mmDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
2034 #define mmDC_GPIO_GENLK_A                                                                              0x2107
2035 #define mmDC_GPIO_GENLK_A_BASE_IDX                                                                     2
2036 #define mmDC_GPIO_GENLK_EN                                                                             0x2108
2037 #define mmDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
2038 #define mmDC_GPIO_GENLK_Y                                                                              0x2109
2039 #define mmDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
2040 #define mmDC_GPIO_HPD_MASK                                                                             0x210a
2041 #define mmDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
2042 #define mmDC_GPIO_HPD_A                                                                                0x210b
2043 #define mmDC_GPIO_HPD_A_BASE_IDX                                                                       2
2044 #define mmDC_GPIO_HPD_EN                                                                               0x210c
2045 #define mmDC_GPIO_HPD_EN_BASE_IDX                                                                      2
2046 #define mmDC_GPIO_HPD_Y                                                                                0x210d
2047 #define mmDC_GPIO_HPD_Y_BASE_IDX                                                                       2
2048 #define mmDC_GPIO_PWRSEQ_MASK                                                                          0x210e
2049 #define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
2050 #define mmDC_GPIO_PWRSEQ_A                                                                             0x210f
2051 #define mmDC_GPIO_PWRSEQ_A_BASE_IDX                                                                    2
2052 #define mmDC_GPIO_PWRSEQ_EN                                                                            0x2110
2053 #define mmDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
2054 #define mmDC_GPIO_PWRSEQ_Y                                                                             0x2111
2055 #define mmDC_GPIO_PWRSEQ_Y_BASE_IDX                                                                    2
2056 #define mmDC_GPIO_PAD_STRENGTH_1                                                                       0x2112
2057 #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
2058 #define mmDC_GPIO_PAD_STRENGTH_2                                                                       0x2113
2059 #define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
2060 #define mmPHY_AUX_CNTL                                                                                 0x2115
2061 #define mmPHY_AUX_CNTL_BASE_IDX                                                                        2
2062 #define mmDC_GPIO_I2CPAD_MASK                                                                          0x2116
2063 #define mmDC_GPIO_I2CPAD_MASK_BASE_IDX                                                                 2
2064 #define mmDC_GPIO_I2CPAD_A                                                                             0x2117
2065 #define mmDC_GPIO_I2CPAD_A_BASE_IDX                                                                    2
2066 #define mmDC_GPIO_I2CPAD_EN                                                                            0x2118
2067 #define mmDC_GPIO_I2CPAD_EN_BASE_IDX                                                                   2
2068 #define mmDC_GPIO_I2CPAD_Y                                                                             0x2119
2069 #define mmDC_GPIO_I2CPAD_Y_BASE_IDX                                                                    2
2070 #define mmDC_GPIO_I2CPAD_STRENGTH                                                                      0x211a
2071 #define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX                                                             2
2072 #define mmDVO_STRENGTH_CONTROL                                                                         0x211b
2073 #define mmDVO_STRENGTH_CONTROL_BASE_IDX                                                                2
2074 #define mmDVO_VREF_CONTROL                                                                             0x211c
2075 #define mmDVO_VREF_CONTROL_BASE_IDX                                                                    2
2076 #define mmDVO_SKEW_ADJUST                                                                              0x211d
2077 #define mmDVO_SKEW_ADJUST_BASE_IDX                                                                     2
2078 #define mmDC_GPIO_I2S_SPDIF_MASK                                                                       0x2126
2079 #define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX                                                              2
2080 #define mmDC_GPIO_I2S_SPDIF_A                                                                          0x2127
2081 #define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX                                                                 2
2082 #define mmDC_GPIO_I2S_SPDIF_EN                                                                         0x2128
2083 #define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX                                                                2
2084 #define mmDC_GPIO_I2S_SPDIF_Y                                                                          0x2129
2085 #define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX                                                                 2
2086 #define mmDC_GPIO_I2S_SPDIF_STRENGTH                                                                   0x212a
2087 #define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX                                                          2
2088 #define mmDC_GPIO_TX12_EN                                                                              0x212b
2089 #define mmDC_GPIO_TX12_EN_BASE_IDX                                                                     2
2090 #define mmDC_GPIO_AUX_CTRL_0                                                                           0x212c
2091 #define mmDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
2092 #define mmDC_GPIO_AUX_CTRL_1                                                                           0x212d
2093 #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
2094 #define mmDC_GPIO_AUX_CTRL_2                                                                           0x212e
2095 #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
2096 #define mmDC_GPIO_RXEN                                                                                 0x212f
2097 #define mmDC_GPIO_RXEN_BASE_IDX                                                                        2
2098 #define mmDC_GPIO_AUX_CTRL_3                                                                           0x2130
2099 #define mmDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
2100 #define mmDC_GPIO_AUX_CTRL_4                                                                           0x2131
2101 #define mmDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
2102 #define mmDC_GPIO_AUX_CTRL_5                                                                           0x2132
2103 #define mmDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
2104 #define mmAUXI2C_PAD_ALL_PWR_OK                                                                        0x2133
2105 #define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
2106 #define mmDC_GPIO_PULLUPEN                                                                             0x2134
2107 #define mmDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
2108 #define mmDC_GPIO_AUX_CTRL_6                                                                           0x2135
2109 #define mmDC_GPIO_AUX_CTRL_6_BASE_IDX                                                                  2
2110 #define mmBPHYC_DAC_MACRO_CNTL                                                                         0x2136
2111 #define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX                                                                2
2112 #define mmDAC_MACRO_CNTL_RESERVED0                                                                     0x2136
2113 #define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX                                                            2
2114 #define mmBPHYC_DAC_AUTO_CALIB_CONTROL                                                                 0x2137
2115 #define mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX                                                        2
2116 #define mmDAC_MACRO_CNTL_RESERVED1                                                                     0x2137
2117 #define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX                                                            2
2118 #define mmDAC_MACRO_CNTL_RESERVED2                                                                     0x2138
2119 #define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX                                                            2
2120 #define mmDAC_MACRO_CNTL_RESERVED3                                                                     0x2139
2121 #define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX                                                            2
2122 #define mmDISP_DSI_DUAL_CTRL                                                                           0x277e
2123 #define mmDISP_DSI_DUAL_CTRL_BASE_IDX                                                                  2
2124 #define mmDPHY_MACRO_CNTL_RESERVED0                                                                    0x283e
2125 #define mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                                           2
2126 #define mmDPHY_MACRO_CNTL_RESERVED1                                                                    0x283f
2127 #define mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                                           2
2128 #define mmDPHY_MACRO_CNTL_RESERVED2                                                                    0x2840
2129 #define mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                                           2
2130 #define mmDPHY_MACRO_CNTL_RESERVED3                                                                    0x2841
2131 #define mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                                           2
2132 #define mmDPHY_MACRO_CNTL_RESERVED4                                                                    0x2842
2133 #define mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                                           2
2134 #define mmDPHY_MACRO_CNTL_RESERVED5                                                                    0x2843
2135 #define mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                                           2
2136 #define mmDPHY_MACRO_CNTL_RESERVED6                                                                    0x2844
2137 #define mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                                           2
2138 #define mmDPHY_MACRO_CNTL_RESERVED7                                                                    0x2845
2139 #define mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                                           2
2140 #define mmDPHY_MACRO_CNTL_RESERVED8                                                                    0x2846
2141 #define mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                                           2
2142 #define mmDPHY_MACRO_CNTL_RESERVED9                                                                    0x2847
2143 #define mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                                           2
2144 #define mmDPHY_MACRO_CNTL_RESERVED10                                                                   0x2848
2145 #define mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                                          2
2146 #define mmDPHY_MACRO_CNTL_RESERVED11                                                                   0x2849
2147 #define mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                                          2
2148 #define mmDPHY_MACRO_CNTL_RESERVED12                                                                   0x284a
2149 #define mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                                          2
2150 #define mmDPHY_MACRO_CNTL_RESERVED13                                                                   0x284b
2151 #define mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                                          2
2152 #define mmDPHY_MACRO_CNTL_RESERVED14                                                                   0x284c
2153 #define mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                                          2
2154 #define mmDPHY_MACRO_CNTL_RESERVED15                                                                   0x284d
2155 #define mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                                          2
2156 #define mmDPHY_MACRO_CNTL_RESERVED16                                                                   0x284e
2157 #define mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                                          2
2158 #define mmDPHY_MACRO_CNTL_RESERVED17                                                                   0x284f
2159 #define mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                                          2
2160 #define mmDPHY_MACRO_CNTL_RESERVED18                                                                   0x2850
2161 #define mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                                          2
2162 #define mmDPHY_MACRO_CNTL_RESERVED19                                                                   0x2851
2163 #define mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                                          2
2164 #define mmDPHY_MACRO_CNTL_RESERVED20                                                                   0x2852
2165 #define mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                                          2
2166 #define mmDPHY_MACRO_CNTL_RESERVED21                                                                   0x2853
2167 #define mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                                          2
2168 #define mmDPHY_MACRO_CNTL_RESERVED22                                                                   0x2854
2169 #define mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                                          2
2170 #define mmDPHY_MACRO_CNTL_RESERVED23                                                                   0x2855
2171 #define mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                                          2
2172 #define mmDPHY_MACRO_CNTL_RESERVED24                                                                   0x2856
2173 #define mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                                          2
2174 #define mmDPHY_MACRO_CNTL_RESERVED25                                                                   0x2857
2175 #define mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                                          2
2176 #define mmDPHY_MACRO_CNTL_RESERVED26                                                                   0x2858
2177 #define mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                                          2
2178 #define mmDPHY_MACRO_CNTL_RESERVED27                                                                   0x2859
2179 #define mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                                          2
2180 #define mmDPHY_MACRO_CNTL_RESERVED28                                                                   0x285a
2181 #define mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                                          2
2182 #define mmDPHY_MACRO_CNTL_RESERVED29                                                                   0x285b
2183 #define mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                                          2
2184 #define mmDPHY_MACRO_CNTL_RESERVED30                                                                   0x285c
2185 #define mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                                          2
2186 #define mmDPHY_MACRO_CNTL_RESERVED31                                                                   0x285d
2187 #define mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                                          2
2188 #define mmDPHY_MACRO_CNTL_RESERVED32                                                                   0x285e
2189 #define mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                                          2
2190 #define mmDPHY_MACRO_CNTL_RESERVED33                                                                   0x285f
2191 #define mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                                          2
2192 #define mmDPHY_MACRO_CNTL_RESERVED34                                                                   0x2860
2193 #define mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                                          2
2194 #define mmDPHY_MACRO_CNTL_RESERVED35                                                                   0x2861
2195 #define mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                                          2
2196 #define mmDPHY_MACRO_CNTL_RESERVED36                                                                   0x2862
2197 #define mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                                          2
2198 #define mmDPHY_MACRO_CNTL_RESERVED37                                                                   0x2863
2199 #define mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                                          2
2200 #define mmDPHY_MACRO_CNTL_RESERVED38                                                                   0x2864
2201 #define mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                                          2
2202 #define mmDPHY_MACRO_CNTL_RESERVED39                                                                   0x2865
2203 #define mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                                          2
2204 #define mmDPHY_MACRO_CNTL_RESERVED40                                                                   0x2866
2205 #define mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                                          2
2206 #define mmDPHY_MACRO_CNTL_RESERVED41                                                                   0x2867
2207 #define mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                                          2
2208 #define mmDPHY_MACRO_CNTL_RESERVED42                                                                   0x2868
2209 #define mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                                          2
2210 #define mmDPHY_MACRO_CNTL_RESERVED43                                                                   0x2869
2211 #define mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                                          2
2212 #define mmDPHY_MACRO_CNTL_RESERVED44                                                                   0x286a
2213 #define mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                                          2
2214 #define mmDPHY_MACRO_CNTL_RESERVED45                                                                   0x286b
2215 #define mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                                          2
2216 #define mmDPHY_MACRO_CNTL_RESERVED46                                                                   0x286c
2217 #define mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                                          2
2218 #define mmDPHY_MACRO_CNTL_RESERVED47                                                                   0x286d
2219 #define mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                                          2
2220 #define mmDPHY_MACRO_CNTL_RESERVED48                                                                   0x286e
2221 #define mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                                          2
2222 #define mmDPHY_MACRO_CNTL_RESERVED49                                                                   0x286f
2223 #define mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                                          2
2224 #define mmDPHY_MACRO_CNTL_RESERVED50                                                                   0x2870
2225 #define mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                                          2
2226 #define mmDPHY_MACRO_CNTL_RESERVED51                                                                   0x2871
2227 #define mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                                          2
2228 #define mmDPHY_MACRO_CNTL_RESERVED52                                                                   0x2872
2229 #define mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                                          2
2230 #define mmDPHY_MACRO_CNTL_RESERVED53                                                                   0x2873
2231 #define mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                                          2
2232 #define mmDPHY_MACRO_CNTL_RESERVED54                                                                   0x2874
2233 #define mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                                          2
2234 #define mmDPHY_MACRO_CNTL_RESERVED55                                                                   0x2875
2235 #define mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                                          2
2236 #define mmDPHY_MACRO_CNTL_RESERVED56                                                                   0x2876
2237 #define mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                                          2
2238 #define mmDPHY_MACRO_CNTL_RESERVED57                                                                   0x2877
2239 #define mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                                          2
2240 #define mmDPHY_MACRO_CNTL_RESERVED58                                                                   0x2878
2241 #define mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX                                                          2
2242 #define mmDPHY_MACRO_CNTL_RESERVED59                                                                   0x2879
2243 #define mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX                                                          2
2244 #define mmDPHY_MACRO_CNTL_RESERVED60                                                                   0x287a
2245 #define mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX                                                          2
2246 #define mmDPHY_MACRO_CNTL_RESERVED61                                                                   0x287b
2247 #define mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX                                                          2
2248 #define mmDPHY_MACRO_CNTL_RESERVED62                                                                   0x287c
2249 #define mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX                                                          2
2250 #define mmDPHY_MACRO_CNTL_RESERVED63                                                                   0x287d
2251 #define mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX                                                          2
2252 #define mmDPRX_AUX_REFERENCE_PULSE_DIV                                                                 0x2a7e
2253 #define mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX                                                        2
2254 #define mmDPRX_AUX_CONTROL                                                                             0x2a7f
2255 #define mmDPRX_AUX_CONTROL_BASE_IDX                                                                    2
2256 #define mmDPRX_AUX_HPD_CONTROL1                                                                        0x2a80
2257 #define mmDPRX_AUX_HPD_CONTROL1_BASE_IDX                                                               2
2258 #define mmDPRX_AUX_HPD_CONTROL2                                                                        0x2a81
2259 #define mmDPRX_AUX_HPD_CONTROL2_BASE_IDX                                                               2
2260 #define mmDPRX_AUX_RX_STATUS                                                                           0x2a82
2261 #define mmDPRX_AUX_RX_STATUS_BASE_IDX                                                                  2
2262 #define mmDPRX_AUX_RX_ERROR_MASK                                                                       0x2a83
2263 #define mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX                                                              2
2264 #define mmDPRX_AUX_DPHY_TX_REF_CONTROL                                                                 0x2a84
2265 #define mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                        2
2266 #define mmDPRX_AUX_DPHY_TX_CONTROL                                                                     0x2a85
2267 #define mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX                                                            2
2268 #define mmDPRX_AUX_DPHY_RX_CONTROL0                                                                    0x2a86
2269 #define mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                           2
2270 #define mmDPRX_AUX_DPHY_RX_CONTROL1                                                                    0x2a87
2271 #define mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                           2
2272 #define mmDPRX_AUX_DPHY_TX_STATUS                                                                      0x2a88
2273 #define mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX                                                             2
2274 #define mmDPRX_AUX_DPHY_RX_STATUS                                                                      0x2a89
2275 #define mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX                                                             2
2276 #define mmDPRX_AUX_DMCU_HW_INT_STATUS                                                                  0x2a8a
2277 #define mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX                                                         2
2278 #define mmDPRX_AUX_DMCU_HW_INT_ACK                                                                     0x2a8b
2279 #define mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX                                                            2
2280 #define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1                                                              0x2a8c
2281 #define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX                                                     2
2282 #define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2                                                              0x2a8d
2283 #define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX                                                     2
2284 #define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1                                                              0x2a8e
2285 #define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX                                                     2
2286 #define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2                                                              0x2a8f
2287 #define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX                                                     2
2288 #define mmDPRX_AUX_AUX_BUF_INDEX                                                                       0x2a90
2289 #define mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX                                                              2
2290 #define mmDPRX_AUX_AUX_BUF_DATA                                                                        0x2a91
2291 #define mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX                                                               2
2292 #define mmDPRX_AUX_EDID_INDEX                                                                          0x2a92
2293 #define mmDPRX_AUX_EDID_INDEX_BASE_IDX                                                                 2
2294 #define mmDPRX_AUX_EDID_DATA                                                                           0x2a93
2295 #define mmDPRX_AUX_EDID_DATA_BASE_IDX                                                                  2
2296 #define mmDPRX_AUX_DPCD_INDEX1                                                                         0x2a94
2297 #define mmDPRX_AUX_DPCD_INDEX1_BASE_IDX                                                                2
2298 #define mmDPRX_AUX_DPCD_DATA1                                                                          0x2a95
2299 #define mmDPRX_AUX_DPCD_DATA1_BASE_IDX                                                                 2
2300 #define mmDPRX_AUX_DPCD_INDEX2                                                                         0x2a96
2301 #define mmDPRX_AUX_DPCD_INDEX2_BASE_IDX                                                                2
2302 #define mmDPRX_AUX_DPCD_DATA2                                                                          0x2a97
2303 #define mmDPRX_AUX_DPCD_DATA2_BASE_IDX                                                                 2
2304 #define mmDPRX_AUX_MSG_INDEX1                                                                          0x2a98
2305 #define mmDPRX_AUX_MSG_INDEX1_BASE_IDX                                                                 2
2306 #define mmDPRX_AUX_MSG_DATA1                                                                           0x2a99
2307 #define mmDPRX_AUX_MSG_DATA1_BASE_IDX                                                                  2
2308 #define mmDPRX_AUX_MSG_INDEX2                                                                          0x2a9a
2309 #define mmDPRX_AUX_MSG_INDEX2_BASE_IDX                                                                 2
2310 #define mmDPRX_AUX_MSG_DATA2                                                                           0x2a9b
2311 #define mmDPRX_AUX_MSG_DATA2_BASE_IDX                                                                  2
2312 #define mmDPRX_AUX_KSV_INDEX1                                                                          0x2a9c
2313 #define mmDPRX_AUX_KSV_INDEX1_BASE_IDX                                                                 2
2314 #define mmDPRX_AUX_KSV_DATA1                                                                           0x2a9d
2315 #define mmDPRX_AUX_KSV_DATA1_BASE_IDX                                                                  2
2316 #define mmDPRX_AUX_KSV_INDEX2                                                                          0x2a9e
2317 #define mmDPRX_AUX_KSV_INDEX2_BASE_IDX                                                                 2
2318 #define mmDPRX_AUX_KSV_DATA2                                                                           0x2a9f
2319 #define mmDPRX_AUX_KSV_DATA2_BASE_IDX                                                                  2
2320 #define mmDPRX_AUX_MSG_TIMEOUT_CONTROL                                                                 0x2aa0
2321 #define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX                                                        2
2322 #define mmDPRX_AUX_MSG_BUF_CONTROL1                                                                    0x2aa1
2323 #define mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX                                                           2
2324 #define mmDPRX_AUX_MSG_BUF_CONTROL2                                                                    0x2aa2
2325 #define mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX                                                           2
2326 #define mmDPRX_AUX_SCRATCH1                                                                            0x2aa3
2327 #define mmDPRX_AUX_SCRATCH1_BASE_IDX                                                                   2
2328 #define mmDPRX_AUX_SCRATCH2                                                                            0x2aa4
2329 #define mmDPRX_AUX_SCRATCH2_BASE_IDX                                                                   2
2330 #define mmDPRX_AUX_MSG1_PENDING                                                                        0x2aa5
2331 #define mmDPRX_AUX_MSG1_PENDING_BASE_IDX                                                               2
2332 #define mmDPRX_AUX_MSG2_PENDING                                                                        0x2aa6
2333 #define mmDPRX_AUX_MSG2_PENDING_BASE_IDX                                                               2
2334 #define mmDPRX_AUX_MSG3_PENDING                                                                        0x2aa7
2335 #define mmDPRX_AUX_MSG3_PENDING_BASE_IDX                                                               2
2336 #define mmDPRX_AUX_MSG4_PENDING                                                                        0x2aa8
2337 #define mmDPRX_AUX_MSG4_PENDING_BASE_IDX                                                               2
2338 #define mmDPRX_DPHY_DPCD_LANE_COUNT_SET                                                                0x2afe
2339 #define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX                                                       2
2340 #define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET                                                          0x2aff
2341 #define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX                                                 2
2342 #define mmDPRX_DPHY_DPCD_MSTM_CTRL                                                                     0x2b00
2343 #define mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX                                                            2
2344 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET                                                           0x2b01
2345 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX                                                  2
2346 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS                                                        0x2b02
2347 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX                                               2
2348 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET                                                           0x2b03
2349 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX                                                  2
2350 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS                                                        0x2b04
2351 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX                                               2
2352 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET                                                           0x2b05
2353 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX                                                  2
2354 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS                                                        0x2b06
2355 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX                                               2
2356 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET                                                           0x2b07
2357 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX                                                  2
2358 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS                                                        0x2b08
2359 #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX                                               2
2360 #define mmDPRX_DPHY_READY                                                                              0x2b09
2361 #define mmDPRX_DPHY_READY_BASE_IDX                                                                     2
2362 #define mmDPRX_DPHY_COMMA_STATUS                                                                       0x2b0b
2363 #define mmDPRX_DPHY_COMMA_STATUS_BASE_IDX                                                              2
2364 #define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED                                                    0x2b0c
2365 #define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX                                           2
2366 #define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED                                                          0x2b0d
2367 #define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX                                                 2
2368 #define mmDPRX_DPHY_ERROR_THRESH_A_LANE0                                                               0x2b0f
2369 #define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX                                                      2
2370 #define mmDPRX_DPHY_ERROR_COUNT_A_LANE0                                                                0x2b11
2371 #define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX                                                       2
2372 #define mmDPRX_DPHY_ERROR_COUNT_B_LANE0                                                                0x2b12
2373 #define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX                                                       2
2374 #define mmDPRX_DPHY_ERROR_COUNT_C_LANE0                                                                0x2b13
2375 #define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX                                                       2
2376 #define mmDPRX_DPHY_ERROR_THRESH_A_LANE1                                                               0x2b14
2377 #define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX                                                      2
2378 #define mmDPRX_DPHY_ERROR_COUNT_A_LANE1                                                                0x2b16
2379 #define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX                                                       2
2380 #define mmDPRX_DPHY_ERROR_COUNT_B_LANE1                                                                0x2b17
2381 #define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX                                                       2
2382 #define mmDPRX_DPHY_ERROR_COUNT_C_LANE1                                                                0x2b18
2383 #define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX                                                       2
2384 #define mmDPRX_DPHY_ERROR_THRESH_A_LANE2                                                               0x2b19
2385 #define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX                                                      2
2386 #define mmDPRX_DPHY_ERROR_COUNT_A_LANE2                                                                0x2b1b
2387 #define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX                                                       2
2388 #define mmDPRX_DPHY_ERROR_COUNT_B_LANE2                                                                0x2b1c
2389 #define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX                                                       2
2390 #define mmDPRX_DPHY_ERROR_COUNT_C_LANE2                                                                0x2b1d
2391 #define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX                                                       2
2392 #define mmDPRX_DPHY_ERROR_THRESH_A_LANE3                                                               0x2b1e
2393 #define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX                                                      2
2394 #define mmDPRX_DPHY_ERROR_COUNT_A_LANE3                                                                0x2b20
2395 #define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX                                                       2
2396 #define mmDPRX_DPHY_ERROR_COUNT_B_LANE3                                                                0x2b21
2397 #define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX                                                       2
2398 #define mmDPRX_DPHY_ERROR_COUNT_C_LANE3                                                                0x2b22
2399 #define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX                                                       2
2400 #define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL                                                             0x2b24
2401 #define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX                                                    2
2402 #define mmDPRX_DPHY_SR_ERROR_COUNT_A                                                                   0x2b25
2403 #define mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX                                                          2
2404 #define mmDPRX_DPHY_BS_ERROR_COUNT_A                                                                   0x2b27
2405 #define mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX                                                          2
2406 #define mmDPRX_DPHY_BS_ERROR_COUNT_B                                                                   0x2b28
2407 #define mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX                                                          2
2408 #define mmDPRX_DPHY_LANESETUP0                                                                         0x2b2d
2409 #define mmDPRX_DPHY_LANESETUP0_BASE_IDX                                                                2
2410 #define mmDPRX_DPHY_LANESETUP1                                                                         0x2b2e
2411 #define mmDPRX_DPHY_LANESETUP1_BASE_IDX                                                                2
2412 #define mmDPRX_DPHY_LFSRADV                                                                            0x2b31
2413 #define mmDPRX_DPHY_LFSRADV_BASE_IDX                                                                   2
2414 #define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT                                                     0x2b32
2415 #define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX                                            2
2416 #define mmDPRX_DPHY_SET_ENABLE                                                                         0x2b33
2417 #define mmDPRX_DPHY_SET_ENABLE_BASE_IDX                                                                2
2418 #define mmDPRX_DPHY_ECF_LSB                                                                            0x2b34
2419 #define mmDPRX_DPHY_ECF_LSB_BASE_IDX                                                                   2
2420 #define mmDPRX_DPHY_ECF_MSB                                                                            0x2b35
2421 #define mmDPRX_DPHY_ECF_MSB_BASE_IDX                                                                   2
2422 #define mmDPRX_DPHY_ENHANCED_FRAME_EN                                                                  0x2b36
2423 #define mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX                                                         2
2424 #define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE                                                             0x2b3c
2425 #define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX                                                    2
2426 #define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA                                                                0x2b3d
2427 #define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX                                                       2
2428 #define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL                                                             0x2b3e
2429 #define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX                                                    2
2430 #define mmDPRX_DPHY_BYPASS                                                                             0x2b3f
2431 #define mmDPRX_DPHY_BYPASS_BASE_IDX                                                                    2
2432 #define mmDPRX_DPHY_INT_RESET                                                                          0x2b40
2433 #define mmDPRX_DPHY_INT_RESET_BASE_IDX                                                                 2
2434 #define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS                                           0x2b41
2435 #define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX                                  2
2436 #define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS                                                0x2b43
2437 #define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX                                       2
2438 #define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS                                             0x2b44
2439 #define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX                                    2
2440 #define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS                                          0x2b46
2441 #define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX                                 2
2442 #define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS                                                              0x2b48
2443 #define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX                                                     2
2444 #define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS                                                               0x2b49
2445 #define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX                                                      2
2446 #define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS                                                              0x2b4a
2447 #define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX                                                     2
2448 #define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS                                                             0x2b4b
2449 #define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX                                                    2
2450 #define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS                                                        0x2b4c
2451 #define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX                                               2
2452 #define mmDPRX_DPHY_SPARE                                                                              0x2b4d
2453 #define mmDPRX_DPHY_SPARE_BASE_IDX                                                                     2
2454 #define mmDCRX_GATE_DISABLE_CNTL                                                                       0x2b6e
2455 #define mmDCRX_GATE_DISABLE_CNTL_BASE_IDX                                                              2
2456 #define mmDCRX_SOFT_RESET                                                                              0x2b6f
2457 #define mmDCRX_SOFT_RESET_BASE_IDX                                                                     2
2458 #define mmDCRX_LIGHT_SLEEP_CNTL                                                                        0x2b70
2459 #define mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX                                                               2
2460 #define mmDCRX_DISPCLK_GATE_CNTL                                                                       0x2b73
2461 #define mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX                                                              2
2462 #define mmDCRX_CLK_CNTL                                                                                0x2b74
2463 #define mmDCRX_CLK_CNTL_BASE_IDX                                                                       2
2464 #define mmDCRX_TEST_CLK_CNTL                                                                           0x2b75
2465 #define mmDCRX_TEST_CLK_CNTL_BASE_IDX                                                                  2
2466 #define mmDCRX_PHY_MACRO_CNTL_RESERVED0                                                                0x2c06
2467 #define mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX                                                       2
2468 #define mmDCRX_PHY_MACRO_CNTL_RESERVED1                                                                0x2c07
2469 #define mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX                                                       2
2470 #define mmDCRX_PHY_MACRO_CNTL_RESERVED2                                                                0x2c08
2471 #define mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX                                                       2
2472 #define mmDCRX_PHY_MACRO_CNTL_RESERVED3                                                                0x2c09
2473 #define mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX                                                       2
2474 #define mmDCRX_PHY_MACRO_CNTL_RESERVED4                                                                0x2c0a
2475 #define mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX                                                       2
2476 #define mmDCRX_PHY_MACRO_CNTL_RESERVED5                                                                0x2c0b
2477 #define mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX                                                       2
2478 #define mmDCRX_PHY_MACRO_CNTL_RESERVED6                                                                0x2c0c
2479 #define mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX                                                       2
2480 #define mmDCRX_PHY_MACRO_CNTL_RESERVED7                                                                0x2c0d
2481 #define mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX                                                       2
2482 #define mmDCRX_PHY_MACRO_CNTL_RESERVED8                                                                0x2c0e
2483 #define mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX                                                       2
2484 #define mmDCRX_PHY_MACRO_CNTL_RESERVED9                                                                0x2c0f
2485 #define mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX                                                       2
2486 #define mmDCRX_PHY_MACRO_CNTL_RESERVED10                                                               0x2c10
2487 #define mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX                                                      2
2488 #define mmDCRX_PHY_MACRO_CNTL_RESERVED11                                                               0x2c11
2489 #define mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX                                                      2
2490 #define mmDCRX_PHY_MACRO_CNTL_RESERVED12                                                               0x2c12
2491 #define mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX                                                      2
2492 #define mmDCRX_PHY_MACRO_CNTL_RESERVED13                                                               0x2c13
2493 #define mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX                                                      2
2494 #define mmDCRX_PHY_MACRO_CNTL_RESERVED14                                                               0x2c14
2495 #define mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX                                                      2
2496 #define mmDCRX_PHY_MACRO_CNTL_RESERVED15                                                               0x2c15
2497 #define mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX                                                      2
2498 #define mmDCRX_PHY_MACRO_CNTL_RESERVED16                                                               0x2c16
2499 #define mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX                                                      2
2500 #define mmDCRX_PHY_MACRO_CNTL_RESERVED17                                                               0x2c17
2501 #define mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX                                                      2
2502 #define mmDCRX_PHY_MACRO_CNTL_RESERVED18                                                               0x2c18
2503 #define mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX                                                      2
2504 #define mmDCRX_PHY_MACRO_CNTL_RESERVED19                                                               0x2c19
2505 #define mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX                                                      2
2506 #define mmDCRX_PHY_MACRO_CNTL_RESERVED20                                                               0x2c1a
2507 #define mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX                                                      2
2508 #define mmDCRX_PHY_MACRO_CNTL_RESERVED21                                                               0x2c1b
2509 #define mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX                                                      2
2510 #define mmDCRX_PHY_MACRO_CNTL_RESERVED22                                                               0x2c1c
2511 #define mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX                                                      2
2512 #define mmDCRX_PHY_MACRO_CNTL_RESERVED23                                                               0x2c1d
2513 #define mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX                                                      2
2514 #define mmDCRX_PHY_MACRO_CNTL_RESERVED24                                                               0x2c1e
2515 #define mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX                                                      2
2516 #define mmDCRX_PHY_MACRO_CNTL_RESERVED25                                                               0x2c1f
2517 #define mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX                                                      2
2518 #define mmDCRX_PHY_MACRO_CNTL_RESERVED26                                                               0x2c20
2519 #define mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX                                                      2
2520 #define mmDCRX_PHY_MACRO_CNTL_RESERVED27                                                               0x2c21
2521 #define mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX                                                      2
2522 #define mmDCRX_PHY_MACRO_CNTL_RESERVED28                                                               0x2c22
2523 #define mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX                                                      2
2524 #define mmDCRX_PHY_MACRO_CNTL_RESERVED29                                                               0x2c23
2525 #define mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX                                                      2
2526 #define mmDCRX_PHY_MACRO_CNTL_RESERVED30                                                               0x2c24
2527 #define mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX                                                      2
2528 #define mmDCRX_PHY_MACRO_CNTL_RESERVED31                                                               0x2c25
2529 #define mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX                                                      2
2530 #define mmDCRX_PHY_MACRO_CNTL_RESERVED32                                                               0x2c26
2531 #define mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX                                                      2
2532 #define mmDCRX_PHY_MACRO_CNTL_RESERVED33                                                               0x2c27
2533 #define mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX                                                      2
2534 #define mmDCRX_PHY_MACRO_CNTL_RESERVED34                                                               0x2c28
2535 #define mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX                                                      2
2536 #define mmDCRX_PHY_MACRO_CNTL_RESERVED35                                                               0x2c29
2537 #define mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX                                                      2
2538 #define mmDCRX_PHY_MACRO_CNTL_RESERVED36                                                               0x2c2a
2539 #define mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX                                                      2
2540 #define mmDCRX_PHY_MACRO_CNTL_RESERVED37                                                               0x2c2b
2541 #define mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX                                                      2
2542 #define mmDCRX_PHY_MACRO_CNTL_RESERVED38                                                               0x2c2c
2543 #define mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX                                                      2
2544 #define mmDCRX_PHY_MACRO_CNTL_RESERVED39                                                               0x2c2d
2545 #define mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX                                                      2
2546 #define mmDCRX_PHY_MACRO_CNTL_RESERVED40                                                               0x2c2e
2547 #define mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX                                                      2
2548 #define mmDCRX_PHY_MACRO_CNTL_RESERVED41                                                               0x2c2f
2549 #define mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX                                                      2
2550 #define mmDCRX_PHY_MACRO_CNTL_RESERVED42                                                               0x2c30
2551 #define mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX                                                      2
2552 #define mmDCRX_PHY_MACRO_CNTL_RESERVED43                                                               0x2c31
2553 #define mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX                                                      2
2554 #define mmDCRX_PHY_MACRO_CNTL_RESERVED44                                                               0x2c32
2555 #define mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX                                                      2
2556 #define mmDCRX_PHY_MACRO_CNTL_RESERVED45                                                               0x2c33
2557 #define mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX                                                      2
2558 #define mmDCRX_PHY_MACRO_CNTL_RESERVED46                                                               0x2c34
2559 #define mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX                                                      2
2560 #define mmDCRX_PHY_MACRO_CNTL_RESERVED47                                                               0x2c35
2561 #define mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX                                                      2
2562 #define mmDCRX_PHY_MACRO_CNTL_RESERVED48                                                               0x2c36
2563 #define mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX                                                      2
2564 #define mmDCRX_PHY_MACRO_CNTL_RESERVED49                                                               0x2c37
2565 #define mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX                                                      2
2566 #define mmDCRX_PHY_MACRO_CNTL_RESERVED50                                                               0x2c38
2567 #define mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX                                                      2
2568 #define mmDCRX_PHY_MACRO_CNTL_RESERVED51                                                               0x2c39
2569 #define mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX                                                      2
2570 #define mmDCRX_PHY_MACRO_CNTL_RESERVED52                                                               0x2c3a
2571 #define mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX                                                      2
2572 #define mmDCRX_PHY_MACRO_CNTL_RESERVED53                                                               0x2c3b
2573 #define mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX                                                      2
2574 #define mmDCRX_PHY_MACRO_CNTL_RESERVED54                                                               0x2c3c
2575 #define mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX                                                      2
2576 #define mmDCRX_PHY_MACRO_CNTL_RESERVED55                                                               0x2c3d
2577 #define mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX                                                      2
2578 #define mmDCRX_PHY_MACRO_CNTL_RESERVED56                                                               0x2c3e
2579 #define mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX                                                      2
2580 #define mmDCRX_PHY_MACRO_CNTL_RESERVED57                                                               0x2c3f
2581 #define mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX                                                      2
2582 #define mmDCRX_PHY_MACRO_CNTL_RESERVED58                                                               0x2c40
2583 #define mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX                                                      2
2584 #define mmDCRX_PHY_MACRO_CNTL_RESERVED59                                                               0x2c41
2585 #define mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX                                                      2
2586 #define mmDCRX_PHY_MACRO_CNTL_RESERVED60                                                               0x2c42
2587 #define mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX                                                      2
2588 #define mmDCRX_PHY_MACRO_CNTL_RESERVED61                                                               0x2c43
2589 #define mmDCRX_PHY_MACRO_CNTL_RESERVED61_BASE_IDX                                                      2
2590 #define mmDCRX_PHY_MACRO_CNTL_RESERVED62                                                               0x2c44
2591 #define mmDCRX_PHY_MACRO_CNTL_RESERVED62_BASE_IDX                                                      2
2592 #define mmDCRX_PHY_MACRO_CNTL_RESERVED63                                                               0x2c45
2593 #define mmDCRX_PHY_MACRO_CNTL_RESERVED63_BASE_IDX                                                      2
2594 #define mmDCRX_PHY_MACRO_CNTL_RESERVED64                                                               0x2c46
2595 #define mmDCRX_PHY_MACRO_CNTL_RESERVED64_BASE_IDX                                                      2
2596 #define mmDCRX_PHY_MACRO_CNTL_RESERVED65                                                               0x2c47
2597 #define mmDCRX_PHY_MACRO_CNTL_RESERVED65_BASE_IDX                                                      2
2598 #define mmDCRX_PHY_MACRO_CNTL_RESERVED66                                                               0x2c48
2599 #define mmDCRX_PHY_MACRO_CNTL_RESERVED66_BASE_IDX                                                      2
2600 #define mmDCRX_PHY_MACRO_CNTL_RESERVED67                                                               0x2c49
2601 #define mmDCRX_PHY_MACRO_CNTL_RESERVED67_BASE_IDX                                                      2
2602 #define mmDCRX_PHY_MACRO_CNTL_RESERVED68                                                               0x2c4a
2603 #define mmDCRX_PHY_MACRO_CNTL_RESERVED68_BASE_IDX                                                      2
2604 #define mmDCRX_PHY_MACRO_CNTL_RESERVED69                                                               0x2c4b
2605 #define mmDCRX_PHY_MACRO_CNTL_RESERVED69_BASE_IDX                                                      2
2606 #define mmDCRX_PHY_MACRO_CNTL_RESERVED70                                                               0x2c4c
2607 #define mmDCRX_PHY_MACRO_CNTL_RESERVED70_BASE_IDX                                                      2
2608 #define mmDCRX_PHY_MACRO_CNTL_RESERVED71                                                               0x2c4d
2609 #define mmDCRX_PHY_MACRO_CNTL_RESERVED71_BASE_IDX                                                      2
2610 #define mmDCRX_PHY_MACRO_CNTL_RESERVED72                                                               0x2c4e
2611 #define mmDCRX_PHY_MACRO_CNTL_RESERVED72_BASE_IDX                                                      2
2612 #define mmDCRX_PHY_MACRO_CNTL_RESERVED73                                                               0x2c4f
2613 #define mmDCRX_PHY_MACRO_CNTL_RESERVED73_BASE_IDX                                                      2
2614 #define mmDCRX_PHY_MACRO_CNTL_RESERVED74                                                               0x2c50
2615 #define mmDCRX_PHY_MACRO_CNTL_RESERVED74_BASE_IDX                                                      2
2616 #define mmDCRX_PHY_MACRO_CNTL_RESERVED75                                                               0x2c51
2617 #define mmDCRX_PHY_MACRO_CNTL_RESERVED75_BASE_IDX                                                      2
2618 #define mmDCRX_PHY_MACRO_CNTL_RESERVED76                                                               0x2c52
2619 #define mmDCRX_PHY_MACRO_CNTL_RESERVED76_BASE_IDX                                                      2
2620 #define mmDCRX_PHY_MACRO_CNTL_RESERVED77                                                               0x2c53
2621 #define mmDCRX_PHY_MACRO_CNTL_RESERVED77_BASE_IDX                                                      2
2622 #define mmDCRX_PHY_MACRO_CNTL_RESERVED78                                                               0x2c54
2623 #define mmDCRX_PHY_MACRO_CNTL_RESERVED78_BASE_IDX                                                      2
2624 #define mmDCRX_PHY_MACRO_CNTL_RESERVED79                                                               0x2c55
2625 #define mmDCRX_PHY_MACRO_CNTL_RESERVED79_BASE_IDX                                                      2
2626 #define mmDCRX_PHY_MACRO_CNTL_RESERVED80                                                               0x2c56
2627 #define mmDCRX_PHY_MACRO_CNTL_RESERVED80_BASE_IDX                                                      2
2628 #define mmDCRX_PHY_MACRO_CNTL_RESERVED81                                                               0x2c57
2629 #define mmDCRX_PHY_MACRO_CNTL_RESERVED81_BASE_IDX                                                      2
2630 #define mmDCRX_PHY_MACRO_CNTL_RESERVED82                                                               0x2c58
2631 #define mmDCRX_PHY_MACRO_CNTL_RESERVED82_BASE_IDX                                                      2
2632 #define mmDCRX_PHY_MACRO_CNTL_RESERVED83                                                               0x2c59
2633 #define mmDCRX_PHY_MACRO_CNTL_RESERVED83_BASE_IDX                                                      2
2634 #define mmDCRX_PHY_MACRO_CNTL_RESERVED84                                                               0x2c5a
2635 #define mmDCRX_PHY_MACRO_CNTL_RESERVED84_BASE_IDX                                                      2
2636 #define mmDCRX_PHY_MACRO_CNTL_RESERVED85                                                               0x2c5b
2637 #define mmDCRX_PHY_MACRO_CNTL_RESERVED85_BASE_IDX                                                      2
2638 #define mmDCRX_PHY_MACRO_CNTL_RESERVED86                                                               0x2c5c
2639 #define mmDCRX_PHY_MACRO_CNTL_RESERVED86_BASE_IDX                                                      2
2640 #define mmDCRX_PHY_MACRO_CNTL_RESERVED87                                                               0x2c5d
2641 #define mmDCRX_PHY_MACRO_CNTL_RESERVED87_BASE_IDX                                                      2
2642 #define mmDCRX_PHY_MACRO_CNTL_RESERVED88                                                               0x2c5e
2643 #define mmDCRX_PHY_MACRO_CNTL_RESERVED88_BASE_IDX                                                      2
2644 #define mmDCRX_PHY_MACRO_CNTL_RESERVED89                                                               0x2c5f
2645 #define mmDCRX_PHY_MACRO_CNTL_RESERVED89_BASE_IDX                                                      2
2646 #define mmDCRX_PHY_MACRO_CNTL_RESERVED90                                                               0x2c60
2647 #define mmDCRX_PHY_MACRO_CNTL_RESERVED90_BASE_IDX                                                      2
2648 #define mmDCRX_PHY_MACRO_CNTL_RESERVED91                                                               0x2c61
2649 #define mmDCRX_PHY_MACRO_CNTL_RESERVED91_BASE_IDX                                                      2
2650 #define mmDCRX_PHY_MACRO_CNTL_RESERVED92                                                               0x2c62
2651 #define mmDCRX_PHY_MACRO_CNTL_RESERVED92_BASE_IDX                                                      2
2652 #define mmDCRX_PHY_MACRO_CNTL_RESERVED93                                                               0x2c63
2653 #define mmDCRX_PHY_MACRO_CNTL_RESERVED93_BASE_IDX                                                      2
2654 #define mmDCRX_PHY_MACRO_CNTL_RESERVED94                                                               0x2c64
2655 #define mmDCRX_PHY_MACRO_CNTL_RESERVED94_BASE_IDX                                                      2
2656 #define mmDCRX_PHY_MACRO_CNTL_RESERVED95                                                               0x2c65
2657 #define mmDCRX_PHY_MACRO_CNTL_RESERVED95_BASE_IDX                                                      2
2658 #define mmDCRX_PHY_MACRO_CNTL_RESERVED96                                                               0x2c66
2659 #define mmDCRX_PHY_MACRO_CNTL_RESERVED96_BASE_IDX                                                      2
2660 #define mmDCRX_PHY_MACRO_CNTL_RESERVED97                                                               0x2c67
2661 #define mmDCRX_PHY_MACRO_CNTL_RESERVED97_BASE_IDX                                                      2
2662 #define mmDCRX_PHY_MACRO_CNTL_RESERVED98                                                               0x2c68
2663 #define mmDCRX_PHY_MACRO_CNTL_RESERVED98_BASE_IDX                                                      2
2664 #define mmDCRX_PHY_MACRO_CNTL_RESERVED99                                                               0x2c69
2665 #define mmDCRX_PHY_MACRO_CNTL_RESERVED99_BASE_IDX                                                      2
2666 #define mmDCRX_PHY_MACRO_CNTL_RESERVED100                                                              0x2c6a
2667 #define mmDCRX_PHY_MACRO_CNTL_RESERVED100_BASE_IDX                                                     2
2668 #define mmDCRX_PHY_MACRO_CNTL_RESERVED101                                                              0x2c6b
2669 #define mmDCRX_PHY_MACRO_CNTL_RESERVED101_BASE_IDX                                                     2
2670 #define mmDCRX_PHY_MACRO_CNTL_RESERVED102                                                              0x2c6c
2671 #define mmDCRX_PHY_MACRO_CNTL_RESERVED102_BASE_IDX                                                     2
2672 #define mmDCRX_PHY_MACRO_CNTL_RESERVED103                                                              0x2c6d
2673 #define mmDCRX_PHY_MACRO_CNTL_RESERVED103_BASE_IDX                                                     2
2674 #define mmDCRX_PHY_MACRO_CNTL_RESERVED104                                                              0x2c6e
2675 #define mmDCRX_PHY_MACRO_CNTL_RESERVED104_BASE_IDX                                                     2
2676 #define mmDCRX_PHY_MACRO_CNTL_RESERVED105                                                              0x2c6f
2677 #define mmDCRX_PHY_MACRO_CNTL_RESERVED105_BASE_IDX                                                     2
2678 #define mmDCRX_PHY_MACRO_CNTL_RESERVED106                                                              0x2c70
2679 #define mmDCRX_PHY_MACRO_CNTL_RESERVED106_BASE_IDX                                                     2
2680 #define mmDCRX_PHY_MACRO_CNTL_RESERVED107                                                              0x2c71
2681 #define mmDCRX_PHY_MACRO_CNTL_RESERVED107_BASE_IDX                                                     2
2682 #define mmDCRX_PHY_MACRO_CNTL_RESERVED108                                                              0x2c72
2683 #define mmDCRX_PHY_MACRO_CNTL_RESERVED108_BASE_IDX                                                     2
2684 #define mmDCRX_PHY_MACRO_CNTL_RESERVED109                                                              0x2c73
2685 #define mmDCRX_PHY_MACRO_CNTL_RESERVED109_BASE_IDX                                                     2
2686 #define mmDCRX_PHY_MACRO_CNTL_RESERVED110                                                              0x2c74
2687 #define mmDCRX_PHY_MACRO_CNTL_RESERVED110_BASE_IDX                                                     2
2688 #define mmDCRX_PHY_MACRO_CNTL_RESERVED111                                                              0x2c75
2689 #define mmDCRX_PHY_MACRO_CNTL_RESERVED111_BASE_IDX                                                     2
2690 #define mmDCRX_PHY_MACRO_CNTL_RESERVED112                                                              0x2c76
2691 #define mmDCRX_PHY_MACRO_CNTL_RESERVED112_BASE_IDX                                                     2
2692 #define mmDCRX_PHY_MACRO_CNTL_RESERVED113                                                              0x2c77
2693 #define mmDCRX_PHY_MACRO_CNTL_RESERVED113_BASE_IDX                                                     2
2694 #define mmDCRX_PHY_MACRO_CNTL_RESERVED114                                                              0x2c78
2695 #define mmDCRX_PHY_MACRO_CNTL_RESERVED114_BASE_IDX                                                     2
2696 #define mmDCRX_PHY_MACRO_CNTL_RESERVED115                                                              0x2c79
2697 #define mmDCRX_PHY_MACRO_CNTL_RESERVED115_BASE_IDX                                                     2
2698 #define mmDCRX_PHY_MACRO_CNTL_RESERVED116                                                              0x2c7a
2699 #define mmDCRX_PHY_MACRO_CNTL_RESERVED116_BASE_IDX                                                     2
2700 #define mmDCRX_PHY_MACRO_CNTL_RESERVED117                                                              0x2c7b
2701 #define mmDCRX_PHY_MACRO_CNTL_RESERVED117_BASE_IDX                                                     2
2702 #define mmDCRX_PHY_MACRO_CNTL_RESERVED118                                                              0x2c7c
2703 #define mmDCRX_PHY_MACRO_CNTL_RESERVED118_BASE_IDX                                                     2
2704 #define mmDCRX_PHY_MACRO_CNTL_RESERVED119                                                              0x2c7d
2705 #define mmDCRX_PHY_MACRO_CNTL_RESERVED119_BASE_IDX                                                     2
2706 #define mmDCRX_PHY_MACRO_CNTL_RESERVED120                                                              0x2c7e
2707 #define mmDCRX_PHY_MACRO_CNTL_RESERVED120_BASE_IDX                                                     2
2708 #define mmDCRX_PHY_MACRO_CNTL_RESERVED121                                                              0x2c7f
2709 #define mmDCRX_PHY_MACRO_CNTL_RESERVED121_BASE_IDX                                                     2
2710 #define mmDCRX_PHY_MACRO_CNTL_RESERVED122                                                              0x2c80
2711 #define mmDCRX_PHY_MACRO_CNTL_RESERVED122_BASE_IDX                                                     2
2712 #define mmDCRX_PHY_MACRO_CNTL_RESERVED123                                                              0x2c81
2713 #define mmDCRX_PHY_MACRO_CNTL_RESERVED123_BASE_IDX                                                     2
2714 #define mmDCRX_PHY_MACRO_CNTL_RESERVED124                                                              0x2c82
2715 #define mmDCRX_PHY_MACRO_CNTL_RESERVED124_BASE_IDX                                                     2
2716 #define mmDCRX_PHY_MACRO_CNTL_RESERVED125                                                              0x2c83
2717 #define mmDCRX_PHY_MACRO_CNTL_RESERVED125_BASE_IDX                                                     2
2718 #define mmDCRX_PHY_MACRO_CNTL_RESERVED126                                                              0x2c84
2719 #define mmDCRX_PHY_MACRO_CNTL_RESERVED126_BASE_IDX                                                     2
2720 #define mmDCRX_PHY_MACRO_CNTL_RESERVED127                                                              0x2c85
2721 #define mmDCRX_PHY_MACRO_CNTL_RESERVED127_BASE_IDX                                                     2
2722 #define mmDCRX_PHY_MACRO_CNTL_RESERVED128                                                              0x2c86
2723 #define mmDCRX_PHY_MACRO_CNTL_RESERVED128_BASE_IDX                                                     2
2724 #define mmDCRX_PHY_MACRO_CNTL_RESERVED129                                                              0x2c87
2725 #define mmDCRX_PHY_MACRO_CNTL_RESERVED129_BASE_IDX                                                     2
2726 #define mmDCRX_PHY_MACRO_CNTL_RESERVED130                                                              0x2c88
2727 #define mmDCRX_PHY_MACRO_CNTL_RESERVED130_BASE_IDX                                                     2
2728 #define mmDCRX_PHY_MACRO_CNTL_RESERVED131                                                              0x2c89
2729 #define mmDCRX_PHY_MACRO_CNTL_RESERVED131_BASE_IDX                                                     2
2730 #define mmDCRX_PHY_MACRO_CNTL_RESERVED132                                                              0x2c8a
2731 #define mmDCRX_PHY_MACRO_CNTL_RESERVED132_BASE_IDX                                                     2
2732 #define mmDCRX_PHY_MACRO_CNTL_RESERVED133                                                              0x2c8b
2733 #define mmDCRX_PHY_MACRO_CNTL_RESERVED133_BASE_IDX                                                     2
2734 #define mmDCRX_PHY_MACRO_CNTL_RESERVED134                                                              0x2c8c
2735 #define mmDCRX_PHY_MACRO_CNTL_RESERVED134_BASE_IDX                                                     2
2736 #define mmDCRX_PHY_MACRO_CNTL_RESERVED135                                                              0x2c8d
2737 #define mmDCRX_PHY_MACRO_CNTL_RESERVED135_BASE_IDX                                                     2
2738 #define mmDCRX_PHY_MACRO_CNTL_RESERVED136                                                              0x2c8e
2739 #define mmDCRX_PHY_MACRO_CNTL_RESERVED136_BASE_IDX                                                     2
2740 #define mmDCRX_PHY_MACRO_CNTL_RESERVED137                                                              0x2c8f
2741 #define mmDCRX_PHY_MACRO_CNTL_RESERVED137_BASE_IDX                                                     2
2742 #define mmDCRX_PHY_MACRO_CNTL_RESERVED138                                                              0x2c90
2743 #define mmDCRX_PHY_MACRO_CNTL_RESERVED138_BASE_IDX                                                     2
2744 #define mmDCRX_PHY_MACRO_CNTL_RESERVED139                                                              0x2c91
2745 #define mmDCRX_PHY_MACRO_CNTL_RESERVED139_BASE_IDX                                                     2
2746 #define mmDCRX_PHY_MACRO_CNTL_RESERVED140                                                              0x2c92
2747 #define mmDCRX_PHY_MACRO_CNTL_RESERVED140_BASE_IDX                                                     2
2748 #define mmDCRX_PHY_MACRO_CNTL_RESERVED141                                                              0x2c93
2749 #define mmDCRX_PHY_MACRO_CNTL_RESERVED141_BASE_IDX                                                     2
2750 #define mmDCRX_PHY_MACRO_CNTL_RESERVED142                                                              0x2c94
2751 #define mmDCRX_PHY_MACRO_CNTL_RESERVED142_BASE_IDX                                                     2
2752 #define mmDCRX_PHY_MACRO_CNTL_RESERVED143                                                              0x2c95
2753 #define mmDCRX_PHY_MACRO_CNTL_RESERVED143_BASE_IDX                                                     2
2754 #define mmDCRX_PHY_MACRO_CNTL_RESERVED144                                                              0x2c96
2755 #define mmDCRX_PHY_MACRO_CNTL_RESERVED144_BASE_IDX                                                     2
2756 #define mmDCRX_PHY_MACRO_CNTL_RESERVED145                                                              0x2c97
2757 #define mmDCRX_PHY_MACRO_CNTL_RESERVED145_BASE_IDX                                                     2
2758 #define mmDCRX_PHY_MACRO_CNTL_RESERVED146                                                              0x2c98
2759 #define mmDCRX_PHY_MACRO_CNTL_RESERVED146_BASE_IDX                                                     2
2760 #define mmDCRX_PHY_MACRO_CNTL_RESERVED147                                                              0x2c99
2761 #define mmDCRX_PHY_MACRO_CNTL_RESERVED147_BASE_IDX                                                     2
2762 #define mmDCRX_PHY_MACRO_CNTL_RESERVED148                                                              0x2c9a
2763 #define mmDCRX_PHY_MACRO_CNTL_RESERVED148_BASE_IDX                                                     2
2764 #define mmDCRX_PHY_MACRO_CNTL_RESERVED149                                                              0x2c9b
2765 #define mmDCRX_PHY_MACRO_CNTL_RESERVED149_BASE_IDX                                                     2
2766 #define mmDCRX_PHY_MACRO_CNTL_RESERVED150                                                              0x2c9c
2767 #define mmDCRX_PHY_MACRO_CNTL_RESERVED150_BASE_IDX                                                     2
2768 #define mmDCRX_PHY_MACRO_CNTL_RESERVED151                                                              0x2c9d
2769 #define mmDCRX_PHY_MACRO_CNTL_RESERVED151_BASE_IDX                                                     2
2770 #define mmDCRX_PHY_MACRO_CNTL_RESERVED152                                                              0x2c9e
2771 #define mmDCRX_PHY_MACRO_CNTL_RESERVED152_BASE_IDX                                                     2
2772 #define mmDCRX_PHY_MACRO_CNTL_RESERVED153                                                              0x2c9f
2773 #define mmDCRX_PHY_MACRO_CNTL_RESERVED153_BASE_IDX                                                     2
2774 #define mmDCRX_PHY_MACRO_CNTL_RESERVED154                                                              0x2ca0
2775 #define mmDCRX_PHY_MACRO_CNTL_RESERVED154_BASE_IDX                                                     2
2776 #define mmDCRX_PHY_MACRO_CNTL_RESERVED155                                                              0x2ca1
2777 #define mmDCRX_PHY_MACRO_CNTL_RESERVED155_BASE_IDX                                                     2
2778 #define mmDCRX_PHY_MACRO_CNTL_RESERVED156                                                              0x2ca2
2779 #define mmDCRX_PHY_MACRO_CNTL_RESERVED156_BASE_IDX                                                     2
2780 #define mmDCRX_PHY_MACRO_CNTL_RESERVED157                                                              0x2ca3
2781 #define mmDCRX_PHY_MACRO_CNTL_RESERVED157_BASE_IDX                                                     2
2782 #define mmDCRX_PHY_MACRO_CNTL_RESERVED158                                                              0x2ca4
2783 #define mmDCRX_PHY_MACRO_CNTL_RESERVED158_BASE_IDX                                                     2
2784 #define mmDCRX_PHY_MACRO_CNTL_RESERVED159                                                              0x2ca5
2785 #define mmDCRX_PHY_MACRO_CNTL_RESERVED159_BASE_IDX                                                     2
2786 #define mmDCRX_PHY_MACRO_CNTL_RESERVED160                                                              0x2ca6
2787 #define mmDCRX_PHY_MACRO_CNTL_RESERVED160_BASE_IDX                                                     2
2788 #define mmDCRX_PHY_MACRO_CNTL_RESERVED161                                                              0x2ca7
2789 #define mmDCRX_PHY_MACRO_CNTL_RESERVED161_BASE_IDX                                                     2
2790 #define mmDCRX_PHY_MACRO_CNTL_RESERVED162                                                              0x2ca8
2791 #define mmDCRX_PHY_MACRO_CNTL_RESERVED162_BASE_IDX                                                     2
2792 #define mmDCRX_PHY_MACRO_CNTL_RESERVED163                                                              0x2ca9
2793 #define mmDCRX_PHY_MACRO_CNTL_RESERVED163_BASE_IDX                                                     2
2794 #define mmDCRX_PHY_MACRO_CNTL_RESERVED164                                                              0x2caa
2795 #define mmDCRX_PHY_MACRO_CNTL_RESERVED164_BASE_IDX                                                     2
2796 #define mmDCRX_PHY_MACRO_CNTL_RESERVED165                                                              0x2cab
2797 #define mmDCRX_PHY_MACRO_CNTL_RESERVED165_BASE_IDX                                                     2
2798 #define mmDCRX_PHY_MACRO_CNTL_RESERVED166                                                              0x2cac
2799 #define mmDCRX_PHY_MACRO_CNTL_RESERVED166_BASE_IDX                                                     2
2800 #define mmDCRX_PHY_MACRO_CNTL_RESERVED167                                                              0x2cad
2801 #define mmDCRX_PHY_MACRO_CNTL_RESERVED167_BASE_IDX                                                     2
2802 #define mmDCRX_PHY_MACRO_CNTL_RESERVED168                                                              0x2cae
2803 #define mmDCRX_PHY_MACRO_CNTL_RESERVED168_BASE_IDX                                                     2
2804 #define mmDCRX_PHY_MACRO_CNTL_RESERVED169                                                              0x2caf
2805 #define mmDCRX_PHY_MACRO_CNTL_RESERVED169_BASE_IDX                                                     2
2806 #define mmDCRX_PHY_MACRO_CNTL_RESERVED170                                                              0x2cb0
2807 #define mmDCRX_PHY_MACRO_CNTL_RESERVED170_BASE_IDX                                                     2
2808 #define mmDCRX_PHY_MACRO_CNTL_RESERVED171                                                              0x2cb1
2809 #define mmDCRX_PHY_MACRO_CNTL_RESERVED171_BASE_IDX                                                     2
2810 #define mmDCRX_PHY_MACRO_CNTL_RESERVED172                                                              0x2cb2
2811 #define mmDCRX_PHY_MACRO_CNTL_RESERVED172_BASE_IDX                                                     2
2812 #define mmDCRX_PHY_MACRO_CNTL_RESERVED173                                                              0x2cb3
2813 #define mmDCRX_PHY_MACRO_CNTL_RESERVED173_BASE_IDX                                                     2
2814 #define mmDCRX_PHY_MACRO_CNTL_RESERVED174                                                              0x2cb4
2815 #define mmDCRX_PHY_MACRO_CNTL_RESERVED174_BASE_IDX                                                     2
2816 #define mmDCRX_PHY_MACRO_CNTL_RESERVED175                                                              0x2cb5
2817 #define mmDCRX_PHY_MACRO_CNTL_RESERVED175_BASE_IDX                                                     2
2818 #define mmDCRX_PHY_MACRO_CNTL_RESERVED176                                                              0x2cb6
2819 #define mmDCRX_PHY_MACRO_CNTL_RESERVED176_BASE_IDX                                                     2
2820 #define mmDCRX_PHY_MACRO_CNTL_RESERVED177                                                              0x2cb7
2821 #define mmDCRX_PHY_MACRO_CNTL_RESERVED177_BASE_IDX                                                     2
2822 #define mmDCRX_PHY_MACRO_CNTL_RESERVED178                                                              0x2cb8
2823 #define mmDCRX_PHY_MACRO_CNTL_RESERVED178_BASE_IDX                                                     2
2824 #define mmDCRX_PHY_MACRO_CNTL_RESERVED179                                                              0x2cb9
2825 #define mmDCRX_PHY_MACRO_CNTL_RESERVED179_BASE_IDX                                                     2
2826 #define mmDCRX_PHY_MACRO_CNTL_RESERVED180                                                              0x2cba
2827 #define mmDCRX_PHY_MACRO_CNTL_RESERVED180_BASE_IDX                                                     2
2828 #define mmDCRX_PHY_MACRO_CNTL_RESERVED181                                                              0x2cbb
2829 #define mmDCRX_PHY_MACRO_CNTL_RESERVED181_BASE_IDX                                                     2
2830 #define mmDCRX_PHY_MACRO_CNTL_RESERVED182                                                              0x2cbc
2831 #define mmDCRX_PHY_MACRO_CNTL_RESERVED182_BASE_IDX                                                     2
2832 #define mmDCRX_PHY_MACRO_CNTL_RESERVED183                                                              0x2cbd
2833 #define mmDCRX_PHY_MACRO_CNTL_RESERVED183_BASE_IDX                                                     2
2834 #define mmDCRX_PHY_MACRO_CNTL_RESERVED184                                                              0x2cbe
2835 #define mmDCRX_PHY_MACRO_CNTL_RESERVED184_BASE_IDX                                                     2
2836 #define mmDCRX_PHY_MACRO_CNTL_RESERVED185                                                              0x2cbf
2837 #define mmDCRX_PHY_MACRO_CNTL_RESERVED185_BASE_IDX                                                     2
2838 #define mmDCRX_PHY_MACRO_CNTL_RESERVED186                                                              0x2cc0
2839 #define mmDCRX_PHY_MACRO_CNTL_RESERVED186_BASE_IDX                                                     2
2840 #define mmDCRX_PHY_MACRO_CNTL_RESERVED187                                                              0x2cc1
2841 #define mmDCRX_PHY_MACRO_CNTL_RESERVED187_BASE_IDX                                                     2
2842 #define mmDCRX_PHY_MACRO_CNTL_RESERVED188                                                              0x2cc2
2843 #define mmDCRX_PHY_MACRO_CNTL_RESERVED188_BASE_IDX                                                     2
2844 #define mmDCRX_PHY_MACRO_CNTL_RESERVED189                                                              0x2cc3
2845 #define mmDCRX_PHY_MACRO_CNTL_RESERVED189_BASE_IDX                                                     2
2846 #define mmDCRX_PHY_MACRO_CNTL_RESERVED190                                                              0x2cc4
2847 #define mmDCRX_PHY_MACRO_CNTL_RESERVED190_BASE_IDX                                                     2
2848 #define mmDCRX_PHY_MACRO_CNTL_RESERVED191                                                              0x2cc5
2849 #define mmDCRX_PHY_MACRO_CNTL_RESERVED191_BASE_IDX                                                     2
2850 #define mmDCRX_PHY_MACRO_CNTL_RESERVED192                                                              0x2cc6
2851 #define mmDCRX_PHY_MACRO_CNTL_RESERVED192_BASE_IDX                                                     2
2852 #define mmDCRX_PHY_MACRO_CNTL_RESERVED193                                                              0x2cc7
2853 #define mmDCRX_PHY_MACRO_CNTL_RESERVED193_BASE_IDX                                                     2
2854 #define mmDCRX_PHY_MACRO_CNTL_RESERVED194                                                              0x2cc8
2855 #define mmDCRX_PHY_MACRO_CNTL_RESERVED194_BASE_IDX                                                     2
2856 #define mmDCRX_PHY_MACRO_CNTL_RESERVED195                                                              0x2cc9
2857 #define mmDCRX_PHY_MACRO_CNTL_RESERVED195_BASE_IDX                                                     2
2858 #define mmDCRX_PHY_MACRO_CNTL_RESERVED196                                                              0x2cca
2859 #define mmDCRX_PHY_MACRO_CNTL_RESERVED196_BASE_IDX                                                     2
2860 #define mmDCRX_PHY_MACRO_CNTL_RESERVED197                                                              0x2ccb
2861 #define mmDCRX_PHY_MACRO_CNTL_RESERVED197_BASE_IDX                                                     2
2862 #define mmDCRX_PHY_MACRO_CNTL_RESERVED198                                                              0x2ccc
2863 #define mmDCRX_PHY_MACRO_CNTL_RESERVED198_BASE_IDX                                                     2
2864 #define mmDCRX_PHY_MACRO_CNTL_RESERVED199                                                              0x2ccd
2865 #define mmDCRX_PHY_MACRO_CNTL_RESERVED199_BASE_IDX                                                     2
2866 #define mmDCRX_PHY_MACRO_CNTL_RESERVED200                                                              0x2cce
2867 #define mmDCRX_PHY_MACRO_CNTL_RESERVED200_BASE_IDX                                                     2
2868 #define mmDCRX_PHY_MACRO_CNTL_RESERVED201                                                              0x2ccf
2869 #define mmDCRX_PHY_MACRO_CNTL_RESERVED201_BASE_IDX                                                     2
2870 #define mmDCRX_PHY_MACRO_CNTL_RESERVED202                                                              0x2cd0
2871 #define mmDCRX_PHY_MACRO_CNTL_RESERVED202_BASE_IDX                                                     2
2872 #define mmDCRX_PHY_MACRO_CNTL_RESERVED203                                                              0x2cd1
2873 #define mmDCRX_PHY_MACRO_CNTL_RESERVED203_BASE_IDX                                                     2
2874 #define mmDCRX_PHY_MACRO_CNTL_RESERVED204                                                              0x2cd2
2875 #define mmDCRX_PHY_MACRO_CNTL_RESERVED204_BASE_IDX                                                     2
2876 #define mmDCRX_PHY_MACRO_CNTL_RESERVED205                                                              0x2cd3
2877 #define mmDCRX_PHY_MACRO_CNTL_RESERVED205_BASE_IDX                                                     2
2878 #define mmDCRX_PHY_MACRO_CNTL_RESERVED206                                                              0x2cd4
2879 #define mmDCRX_PHY_MACRO_CNTL_RESERVED206_BASE_IDX                                                     2
2880 #define mmDCRX_PHY_MACRO_CNTL_RESERVED207                                                              0x2cd5
2881 #define mmDCRX_PHY_MACRO_CNTL_RESERVED207_BASE_IDX                                                     2
2882 #define mmDCRX_PHY_MACRO_CNTL_RESERVED208                                                              0x2cd6
2883 #define mmDCRX_PHY_MACRO_CNTL_RESERVED208_BASE_IDX                                                     2
2884 #define mmDCRX_PHY_MACRO_CNTL_RESERVED209                                                              0x2cd7
2885 #define mmDCRX_PHY_MACRO_CNTL_RESERVED209_BASE_IDX                                                     2
2886 #define mmDCRX_PHY_MACRO_CNTL_RESERVED210                                                              0x2cd8
2887 #define mmDCRX_PHY_MACRO_CNTL_RESERVED210_BASE_IDX                                                     2
2888 #define mmDCRX_PHY_MACRO_CNTL_RESERVED211                                                              0x2cd9
2889 #define mmDCRX_PHY_MACRO_CNTL_RESERVED211_BASE_IDX                                                     2
2890 #define mmDCRX_PHY_MACRO_CNTL_RESERVED212                                                              0x2cda
2891 #define mmDCRX_PHY_MACRO_CNTL_RESERVED212_BASE_IDX                                                     2
2892 #define mmDCRX_PHY_MACRO_CNTL_RESERVED213                                                              0x2cdb
2893 #define mmDCRX_PHY_MACRO_CNTL_RESERVED213_BASE_IDX                                                     2
2894 #define mmDCRX_PHY_MACRO_CNTL_RESERVED214                                                              0x2cdc
2895 #define mmDCRX_PHY_MACRO_CNTL_RESERVED214_BASE_IDX                                                     2
2896 #define mmDCRX_PHY_MACRO_CNTL_RESERVED215                                                              0x2cdd
2897 #define mmDCRX_PHY_MACRO_CNTL_RESERVED215_BASE_IDX                                                     2
2898 #define mmDCRX_PHY_MACRO_CNTL_RESERVED216                                                              0x2cde
2899 #define mmDCRX_PHY_MACRO_CNTL_RESERVED216_BASE_IDX                                                     2
2900 #define mmDCRX_PHY_MACRO_CNTL_RESERVED217                                                              0x2cdf
2901 #define mmDCRX_PHY_MACRO_CNTL_RESERVED217_BASE_IDX                                                     2
2902 #define mmDCRX_PHY_MACRO_CNTL_RESERVED218                                                              0x2ce0
2903 #define mmDCRX_PHY_MACRO_CNTL_RESERVED218_BASE_IDX                                                     2
2904 #define mmDCRX_PHY_MACRO_CNTL_RESERVED219                                                              0x2ce1
2905 #define mmDCRX_PHY_MACRO_CNTL_RESERVED219_BASE_IDX                                                     2
2906 #define mmDCRX_PHY_MACRO_CNTL_RESERVED220                                                              0x2ce2
2907 #define mmDCRX_PHY_MACRO_CNTL_RESERVED220_BASE_IDX                                                     2
2908 #define mmDCRX_PHY_MACRO_CNTL_RESERVED221                                                              0x2ce3
2909 #define mmDCRX_PHY_MACRO_CNTL_RESERVED221_BASE_IDX                                                     2
2910 #define mmDCRX_PHY_MACRO_CNTL_RESERVED222                                                              0x2ce4
2911 #define mmDCRX_PHY_MACRO_CNTL_RESERVED222_BASE_IDX                                                     2
2912 #define mmDCRX_PHY_MACRO_CNTL_RESERVED223                                                              0x2ce5
2913 #define mmDCRX_PHY_MACRO_CNTL_RESERVED223_BASE_IDX                                                     2
2914 #define mmDCRX_PHY_MACRO_CNTL_RESERVED224                                                              0x2ce6
2915 #define mmDCRX_PHY_MACRO_CNTL_RESERVED224_BASE_IDX                                                     2
2916 #define mmDCRX_PHY_MACRO_CNTL_RESERVED225                                                              0x2ce7
2917 #define mmDCRX_PHY_MACRO_CNTL_RESERVED225_BASE_IDX                                                     2
2918 #define mmDCRX_PHY_MACRO_CNTL_RESERVED226                                                              0x2ce8
2919 #define mmDCRX_PHY_MACRO_CNTL_RESERVED226_BASE_IDX                                                     2
2920 #define mmDCRX_PHY_MACRO_CNTL_RESERVED227                                                              0x2ce9
2921 #define mmDCRX_PHY_MACRO_CNTL_RESERVED227_BASE_IDX                                                     2
2922 #define mmDCRX_PHY_MACRO_CNTL_RESERVED228                                                              0x2cea
2923 #define mmDCRX_PHY_MACRO_CNTL_RESERVED228_BASE_IDX                                                     2
2924 #define mmDCRX_PHY_MACRO_CNTL_RESERVED229                                                              0x2ceb
2925 #define mmDCRX_PHY_MACRO_CNTL_RESERVED229_BASE_IDX                                                     2
2926 #define mmDCRX_PHY_MACRO_CNTL_RESERVED230                                                              0x2cec
2927 #define mmDCRX_PHY_MACRO_CNTL_RESERVED230_BASE_IDX                                                     2
2928 #define mmDCRX_PHY_MACRO_CNTL_RESERVED231                                                              0x2ced
2929 #define mmDCRX_PHY_MACRO_CNTL_RESERVED231_BASE_IDX                                                     2
2930 #define mmDCRX_PHY_MACRO_CNTL_RESERVED232                                                              0x2cee
2931 #define mmDCRX_PHY_MACRO_CNTL_RESERVED232_BASE_IDX                                                     2
2932 #define mmDCRX_PHY_MACRO_CNTL_RESERVED233                                                              0x2cef
2933 #define mmDCRX_PHY_MACRO_CNTL_RESERVED233_BASE_IDX                                                     2
2934 #define mmDCRX_PHY_MACRO_CNTL_RESERVED234                                                              0x2cf0
2935 #define mmDCRX_PHY_MACRO_CNTL_RESERVED234_BASE_IDX                                                     2
2936 #define mmDCRX_PHY_MACRO_CNTL_RESERVED235                                                              0x2cf1
2937 #define mmDCRX_PHY_MACRO_CNTL_RESERVED235_BASE_IDX                                                     2
2938 #define mmDCRX_PHY_MACRO_CNTL_RESERVED236                                                              0x2cf2
2939 #define mmDCRX_PHY_MACRO_CNTL_RESERVED236_BASE_IDX                                                     2
2940 #define mmDCRX_PHY_MACRO_CNTL_RESERVED237                                                              0x2cf3
2941 #define mmDCRX_PHY_MACRO_CNTL_RESERVED237_BASE_IDX                                                     2
2942 #define mmDCRX_PHY_MACRO_CNTL_RESERVED238                                                              0x2cf4
2943 #define mmDCRX_PHY_MACRO_CNTL_RESERVED238_BASE_IDX                                                     2
2944 #define mmDCRX_PHY_MACRO_CNTL_RESERVED239                                                              0x2cf5
2945 #define mmDCRX_PHY_MACRO_CNTL_RESERVED239_BASE_IDX                                                     2
2946 #define mmDCRX_PHY_MACRO_CNTL_RESERVED240                                                              0x2cf6
2947 #define mmDCRX_PHY_MACRO_CNTL_RESERVED240_BASE_IDX                                                     2
2948 #define mmDCRX_PHY_MACRO_CNTL_RESERVED241                                                              0x2cf7
2949 #define mmDCRX_PHY_MACRO_CNTL_RESERVED241_BASE_IDX                                                     2
2950 #define mmDCRX_PHY_MACRO_CNTL_RESERVED242                                                              0x2cf8
2951 #define mmDCRX_PHY_MACRO_CNTL_RESERVED242_BASE_IDX                                                     2
2952 #define mmDCRX_PHY_MACRO_CNTL_RESERVED243                                                              0x2cf9
2953 #define mmDCRX_PHY_MACRO_CNTL_RESERVED243_BASE_IDX                                                     2
2954 #define mmDCRX_PHY_MACRO_CNTL_RESERVED244                                                              0x2cfa
2955 #define mmDCRX_PHY_MACRO_CNTL_RESERVED244_BASE_IDX                                                     2
2956 #define mmDCRX_PHY_MACRO_CNTL_RESERVED245                                                              0x2cfb
2957 #define mmDCRX_PHY_MACRO_CNTL_RESERVED245_BASE_IDX                                                     2
2958 #define mmDCRX_PHY_MACRO_CNTL_RESERVED246                                                              0x2cfc
2959 #define mmDCRX_PHY_MACRO_CNTL_RESERVED246_BASE_IDX                                                     2
2960 #define mmDCRX_PHY_MACRO_CNTL_RESERVED247                                                              0x2cfd
2961 #define mmDCRX_PHY_MACRO_CNTL_RESERVED247_BASE_IDX                                                     2
2962 #define mmDCRX_PHY_MACRO_CNTL_RESERVED248                                                              0x2cfe
2963 #define mmDCRX_PHY_MACRO_CNTL_RESERVED248_BASE_IDX                                                     2
2964 #define mmDCRX_PHY_MACRO_CNTL_RESERVED249                                                              0x2cff
2965 #define mmDCRX_PHY_MACRO_CNTL_RESERVED249_BASE_IDX                                                     2
2966 #define mmDCRX_PHY_MACRO_CNTL_RESERVED250                                                              0x2d00
2967 #define mmDCRX_PHY_MACRO_CNTL_RESERVED250_BASE_IDX                                                     2
2968 #define mmDCRX_PHY_MACRO_CNTL_RESERVED251                                                              0x2d01
2969 #define mmDCRX_PHY_MACRO_CNTL_RESERVED251_BASE_IDX                                                     2
2970 #define mmDCRX_PHY_MACRO_CNTL_RESERVED252                                                              0x2d02
2971 #define mmDCRX_PHY_MACRO_CNTL_RESERVED252_BASE_IDX                                                     2
2972 #define mmDCRX_PHY_MACRO_CNTL_RESERVED253                                                              0x2d03
2973 #define mmDCRX_PHY_MACRO_CNTL_RESERVED253_BASE_IDX                                                     2
2974 #define mmDCRX_PHY_MACRO_CNTL_RESERVED254                                                              0x2d04
2975 #define mmDCRX_PHY_MACRO_CNTL_RESERVED254_BASE_IDX                                                     2
2976 #define mmDCRX_PHY_MACRO_CNTL_RESERVED255                                                              0x2d05
2977 #define mmDCRX_PHY_MACRO_CNTL_RESERVED255_BASE_IDX                                                     2
2978 #define mmDCRX_PHY_MACRO_CNTL_RESERVED256                                                              0x2d06
2979 #define mmDCRX_PHY_MACRO_CNTL_RESERVED256_BASE_IDX                                                     2
2980 #define mmDCRX_PHY_MACRO_CNTL_RESERVED257                                                              0x2d07
2981 #define mmDCRX_PHY_MACRO_CNTL_RESERVED257_BASE_IDX                                                     2
2982 #define mmDCRX_PHY_MACRO_CNTL_RESERVED258                                                              0x2d08
2983 #define mmDCRX_PHY_MACRO_CNTL_RESERVED258_BASE_IDX                                                     2
2984 #define mmDCRX_PHY_MACRO_CNTL_RESERVED259                                                              0x2d09
2985 #define mmDCRX_PHY_MACRO_CNTL_RESERVED259_BASE_IDX                                                     2
2986 #define mmDCRX_PHY_MACRO_CNTL_RESERVED260                                                              0x2d0a
2987 #define mmDCRX_PHY_MACRO_CNTL_RESERVED260_BASE_IDX                                                     2
2988 #define mmDCRX_PHY_MACRO_CNTL_RESERVED261                                                              0x2d0b
2989 #define mmDCRX_PHY_MACRO_CNTL_RESERVED261_BASE_IDX                                                     2
2990 #define mmDCRX_PHY_MACRO_CNTL_RESERVED262                                                              0x2d0c
2991 #define mmDCRX_PHY_MACRO_CNTL_RESERVED262_BASE_IDX                                                     2
2992 #define mmDCRX_PHY_MACRO_CNTL_RESERVED263                                                              0x2d0d
2993 #define mmDCRX_PHY_MACRO_CNTL_RESERVED263_BASE_IDX                                                     2
2994 #define mmDCRX_PHY_MACRO_CNTL_RESERVED264                                                              0x2d0e
2995 #define mmDCRX_PHY_MACRO_CNTL_RESERVED264_BASE_IDX                                                     2
2996 #define mmDCRX_PHY_MACRO_CNTL_RESERVED265                                                              0x2d0f
2997 #define mmDCRX_PHY_MACRO_CNTL_RESERVED265_BASE_IDX                                                     2
2998 #define mmDCRX_PHY_MACRO_CNTL_RESERVED266                                                              0x2d10
2999 #define mmDCRX_PHY_MACRO_CNTL_RESERVED266_BASE_IDX                                                     2
3000 #define mmDCRX_PHY_MACRO_CNTL_RESERVED267                                                              0x2d11
3001 #define mmDCRX_PHY_MACRO_CNTL_RESERVED267_BASE_IDX                                                     2
3002 #define mmDCRX_PHY_MACRO_CNTL_RESERVED268                                                              0x2d12
3003 #define mmDCRX_PHY_MACRO_CNTL_RESERVED268_BASE_IDX                                                     2
3004 #define mmDCRX_PHY_MACRO_CNTL_RESERVED269                                                              0x2d13
3005 #define mmDCRX_PHY_MACRO_CNTL_RESERVED269_BASE_IDX                                                     2
3006 #define mmDCRX_PHY_MACRO_CNTL_RESERVED270                                                              0x2d14
3007 #define mmDCRX_PHY_MACRO_CNTL_RESERVED270_BASE_IDX                                                     2
3008 #define mmDCRX_PHY_MACRO_CNTL_RESERVED271                                                              0x2d15
3009 #define mmDCRX_PHY_MACRO_CNTL_RESERVED271_BASE_IDX                                                     2
3010 #define mmDCRX_PHY_MACRO_CNTL_RESERVED272                                                              0x2d16
3011 #define mmDCRX_PHY_MACRO_CNTL_RESERVED272_BASE_IDX                                                     2
3012 #define mmDCRX_PHY_MACRO_CNTL_RESERVED273                                                              0x2d17
3013 #define mmDCRX_PHY_MACRO_CNTL_RESERVED273_BASE_IDX                                                     2
3014 #define mmDCRX_PHY_MACRO_CNTL_RESERVED274                                                              0x2d18
3015 #define mmDCRX_PHY_MACRO_CNTL_RESERVED274_BASE_IDX                                                     2
3016 #define mmDCRX_PHY_MACRO_CNTL_RESERVED275                                                              0x2d19
3017 #define mmDCRX_PHY_MACRO_CNTL_RESERVED275_BASE_IDX                                                     2
3018 #define mmDCRX_PHY_MACRO_CNTL_RESERVED276                                                              0x2d1a
3019 #define mmDCRX_PHY_MACRO_CNTL_RESERVED276_BASE_IDX                                                     2
3020 #define mmDCRX_PHY_MACRO_CNTL_RESERVED277                                                              0x2d1b
3021 #define mmDCRX_PHY_MACRO_CNTL_RESERVED277_BASE_IDX                                                     2
3022 #define mmDCRX_PHY_MACRO_CNTL_RESERVED278                                                              0x2d1c
3023 #define mmDCRX_PHY_MACRO_CNTL_RESERVED278_BASE_IDX                                                     2
3024 #define mmDCRX_PHY_MACRO_CNTL_RESERVED279                                                              0x2d1d
3025 #define mmDCRX_PHY_MACRO_CNTL_RESERVED279_BASE_IDX                                                     2
3026 #define mmDCRX_PHY_MACRO_CNTL_RESERVED280                                                              0x2d1e
3027 #define mmDCRX_PHY_MACRO_CNTL_RESERVED280_BASE_IDX                                                     2
3028 #define mmDCRX_PHY_MACRO_CNTL_RESERVED281                                                              0x2d1f
3029 #define mmDCRX_PHY_MACRO_CNTL_RESERVED281_BASE_IDX                                                     2
3030 #define mmDCRX_PHY_MACRO_CNTL_RESERVED282                                                              0x2d20
3031 #define mmDCRX_PHY_MACRO_CNTL_RESERVED282_BASE_IDX                                                     2
3032 #define mmDCRX_PHY_MACRO_CNTL_RESERVED283                                                              0x2d21
3033 #define mmDCRX_PHY_MACRO_CNTL_RESERVED283_BASE_IDX                                                     2
3034 #define mmDCRX_PHY_MACRO_CNTL_RESERVED284                                                              0x2d22
3035 #define mmDCRX_PHY_MACRO_CNTL_RESERVED284_BASE_IDX                                                     2
3036 #define mmDCRX_PHY_MACRO_CNTL_RESERVED285                                                              0x2d23
3037 #define mmDCRX_PHY_MACRO_CNTL_RESERVED285_BASE_IDX                                                     2
3038 #define mmDCRX_PHY_MACRO_CNTL_RESERVED286                                                              0x2d24
3039 #define mmDCRX_PHY_MACRO_CNTL_RESERVED286_BASE_IDX                                                     2
3040 #define mmDCRX_PHY_MACRO_CNTL_RESERVED287                                                              0x2d25
3041 #define mmDCRX_PHY_MACRO_CNTL_RESERVED287_BASE_IDX                                                     2
3042 #define mmDCRX_PHY_MACRO_CNTL_RESERVED288                                                              0x2d26
3043 #define mmDCRX_PHY_MACRO_CNTL_RESERVED288_BASE_IDX                                                     2
3044 #define mmDCRX_PHY_MACRO_CNTL_RESERVED289                                                              0x2d27
3045 #define mmDCRX_PHY_MACRO_CNTL_RESERVED289_BASE_IDX                                                     2
3046 #define mmDCRX_PHY_MACRO_CNTL_RESERVED290                                                              0x2d28
3047 #define mmDCRX_PHY_MACRO_CNTL_RESERVED290_BASE_IDX                                                     2
3048 #define mmDCRX_PHY_MACRO_CNTL_RESERVED291                                                              0x2d29
3049 #define mmDCRX_PHY_MACRO_CNTL_RESERVED291_BASE_IDX                                                     2
3050 #define mmDCRX_PHY_MACRO_CNTL_RESERVED292                                                              0x2d2a
3051 #define mmDCRX_PHY_MACRO_CNTL_RESERVED292_BASE_IDX                                                     2
3052 #define mmDCRX_PHY_MACRO_CNTL_RESERVED293                                                              0x2d2b
3053 #define mmDCRX_PHY_MACRO_CNTL_RESERVED293_BASE_IDX                                                     2
3054 #define mmDCRX_PHY_MACRO_CNTL_RESERVED294                                                              0x2d2c
3055 #define mmDCRX_PHY_MACRO_CNTL_RESERVED294_BASE_IDX                                                     2
3056 #define mmDCRX_PHY_MACRO_CNTL_RESERVED295                                                              0x2d2d
3057 #define mmDCRX_PHY_MACRO_CNTL_RESERVED295_BASE_IDX                                                     2
3058 #define mmDCRX_PHY_MACRO_CNTL_RESERVED296                                                              0x2d2e
3059 #define mmDCRX_PHY_MACRO_CNTL_RESERVED296_BASE_IDX                                                     2
3060 #define mmDCRX_PHY_MACRO_CNTL_RESERVED297                                                              0x2d2f
3061 #define mmDCRX_PHY_MACRO_CNTL_RESERVED297_BASE_IDX                                                     2
3062 #define mmDCRX_PHY_MACRO_CNTL_RESERVED298                                                              0x2d30
3063 #define mmDCRX_PHY_MACRO_CNTL_RESERVED298_BASE_IDX                                                     2
3064 #define mmDCRX_PHY_MACRO_CNTL_RESERVED299                                                              0x2d31
3065 #define mmDCRX_PHY_MACRO_CNTL_RESERVED299_BASE_IDX                                                     2
3066 #define mmDCRX_PHY_MACRO_CNTL_RESERVED300                                                              0x2d32
3067 #define mmDCRX_PHY_MACRO_CNTL_RESERVED300_BASE_IDX                                                     2
3068 #define mmDCRX_PHY_MACRO_CNTL_RESERVED301                                                              0x2d33
3069 #define mmDCRX_PHY_MACRO_CNTL_RESERVED301_BASE_IDX                                                     2
3070 #define mmDCRX_PHY_MACRO_CNTL_RESERVED302                                                              0x2d34
3071 #define mmDCRX_PHY_MACRO_CNTL_RESERVED302_BASE_IDX                                                     2
3072 #define mmDCRX_PHY_MACRO_CNTL_RESERVED303                                                              0x2d35
3073 #define mmDCRX_PHY_MACRO_CNTL_RESERVED303_BASE_IDX                                                     2
3074 #define mmDCRX_PHY_MACRO_CNTL_RESERVED304                                                              0x2d36
3075 #define mmDCRX_PHY_MACRO_CNTL_RESERVED304_BASE_IDX                                                     2
3076 #define mmDCRX_PHY_MACRO_CNTL_RESERVED305                                                              0x2d37
3077 #define mmDCRX_PHY_MACRO_CNTL_RESERVED305_BASE_IDX                                                     2
3078 #define mmDCRX_PHY_MACRO_CNTL_RESERVED306                                                              0x2d38
3079 #define mmDCRX_PHY_MACRO_CNTL_RESERVED306_BASE_IDX                                                     2
3080 #define mmDCRX_PHY_MACRO_CNTL_RESERVED307                                                              0x2d39
3081 #define mmDCRX_PHY_MACRO_CNTL_RESERVED307_BASE_IDX                                                     2
3082 #define mmDCRX_PHY_MACRO_CNTL_RESERVED308                                                              0x2d3a
3083 #define mmDCRX_PHY_MACRO_CNTL_RESERVED308_BASE_IDX                                                     2
3084 #define mmDCRX_PHY_MACRO_CNTL_RESERVED309                                                              0x2d3b
3085 #define mmDCRX_PHY_MACRO_CNTL_RESERVED309_BASE_IDX                                                     2
3086 #define mmDCRX_PHY_MACRO_CNTL_RESERVED310                                                              0x2d3c
3087 #define mmDCRX_PHY_MACRO_CNTL_RESERVED310_BASE_IDX                                                     2
3088 #define mmDCRX_PHY_MACRO_CNTL_RESERVED311                                                              0x2d3d
3089 #define mmDCRX_PHY_MACRO_CNTL_RESERVED311_BASE_IDX                                                     2
3090 #define mmDCRX_PHY_MACRO_CNTL_RESERVED312                                                              0x2d3e
3091 #define mmDCRX_PHY_MACRO_CNTL_RESERVED312_BASE_IDX                                                     2
3092 #define mmDCRX_PHY_MACRO_CNTL_RESERVED313                                                              0x2d3f
3093 #define mmDCRX_PHY_MACRO_CNTL_RESERVED313_BASE_IDX                                                     2
3094 #define mmDCRX_PHY_MACRO_CNTL_RESERVED314                                                              0x2d40
3095 #define mmDCRX_PHY_MACRO_CNTL_RESERVED314_BASE_IDX                                                     2
3096 #define mmDCRX_PHY_MACRO_CNTL_RESERVED315                                                              0x2d41
3097 #define mmDCRX_PHY_MACRO_CNTL_RESERVED315_BASE_IDX                                                     2
3098 #define mmDCRX_PHY_MACRO_CNTL_RESERVED316                                                              0x2d42
3099 #define mmDCRX_PHY_MACRO_CNTL_RESERVED316_BASE_IDX                                                     2
3100 #define mmDCRX_PHY_MACRO_CNTL_RESERVED317                                                              0x2d43
3101 #define mmDCRX_PHY_MACRO_CNTL_RESERVED317_BASE_IDX                                                     2
3102 #define mmDCRX_PHY_MACRO_CNTL_RESERVED318                                                              0x2d44
3103 #define mmDCRX_PHY_MACRO_CNTL_RESERVED318_BASE_IDX                                                     2
3104 #define mmDCRX_PHY_MACRO_CNTL_RESERVED319                                                              0x2d45
3105 #define mmDCRX_PHY_MACRO_CNTL_RESERVED319_BASE_IDX                                                     2
3106 #define mmDCRX_PHY_MACRO_CNTL_RESERVED320                                                              0x2d46
3107 #define mmDCRX_PHY_MACRO_CNTL_RESERVED320_BASE_IDX                                                     2
3108 #define mmDCRX_PHY_MACRO_CNTL_RESERVED321                                                              0x2d47
3109 #define mmDCRX_PHY_MACRO_CNTL_RESERVED321_BASE_IDX                                                     2
3110 #define mmDCRX_PHY_MACRO_CNTL_RESERVED322                                                              0x2d48
3111 #define mmDCRX_PHY_MACRO_CNTL_RESERVED322_BASE_IDX                                                     2
3112 #define mmDCRX_PHY_MACRO_CNTL_RESERVED323                                                              0x2d49
3113 #define mmDCRX_PHY_MACRO_CNTL_RESERVED323_BASE_IDX                                                     2
3114 #define mmDCRX_PHY_MACRO_CNTL_RESERVED324                                                              0x2d4a
3115 #define mmDCRX_PHY_MACRO_CNTL_RESERVED324_BASE_IDX                                                     2
3116 #define mmDCRX_PHY_MACRO_CNTL_RESERVED325                                                              0x2d4b
3117 #define mmDCRX_PHY_MACRO_CNTL_RESERVED325_BASE_IDX                                                     2
3118 #define mmDCRX_PHY_MACRO_CNTL_RESERVED326                                                              0x2d4c
3119 #define mmDCRX_PHY_MACRO_CNTL_RESERVED326_BASE_IDX                                                     2
3120 #define mmDCRX_PHY_MACRO_CNTL_RESERVED327                                                              0x2d4d
3121 #define mmDCRX_PHY_MACRO_CNTL_RESERVED327_BASE_IDX                                                     2
3122 #define mmDCRX_PHY_MACRO_CNTL_RESERVED328                                                              0x2d4e
3123 #define mmDCRX_PHY_MACRO_CNTL_RESERVED328_BASE_IDX                                                     2
3124 #define mmDCRX_PHY_MACRO_CNTL_RESERVED329                                                              0x2d4f
3125 #define mmDCRX_PHY_MACRO_CNTL_RESERVED329_BASE_IDX                                                     2
3126 #define mmDCRX_PHY_MACRO_CNTL_RESERVED330                                                              0x2d50
3127 #define mmDCRX_PHY_MACRO_CNTL_RESERVED330_BASE_IDX                                                     2
3128 #define mmDCRX_PHY_MACRO_CNTL_RESERVED331                                                              0x2d51
3129 #define mmDCRX_PHY_MACRO_CNTL_RESERVED331_BASE_IDX                                                     2
3130 #define mmDCRX_PHY_MACRO_CNTL_RESERVED332                                                              0x2d52
3131 #define mmDCRX_PHY_MACRO_CNTL_RESERVED332_BASE_IDX                                                     2
3132 #define mmDCRX_PHY_MACRO_CNTL_RESERVED333                                                              0x2d53
3133 #define mmDCRX_PHY_MACRO_CNTL_RESERVED333_BASE_IDX                                                     2
3134 #define mmDCRX_PHY_MACRO_CNTL_RESERVED334                                                              0x2d54
3135 #define mmDCRX_PHY_MACRO_CNTL_RESERVED334_BASE_IDX                                                     2
3136 #define mmDCRX_PHY_MACRO_CNTL_RESERVED335                                                              0x2d55
3137 #define mmDCRX_PHY_MACRO_CNTL_RESERVED335_BASE_IDX                                                     2
3138 #define mmDCRX_PHY_MACRO_CNTL_RESERVED336                                                              0x2d56
3139 #define mmDCRX_PHY_MACRO_CNTL_RESERVED336_BASE_IDX                                                     2
3140 #define mmDCRX_PHY_MACRO_CNTL_RESERVED337                                                              0x2d57
3141 #define mmDCRX_PHY_MACRO_CNTL_RESERVED337_BASE_IDX                                                     2
3142 #define mmDCRX_PHY_MACRO_CNTL_RESERVED338                                                              0x2d58
3143 #define mmDCRX_PHY_MACRO_CNTL_RESERVED338_BASE_IDX                                                     2
3144 #define mmDCRX_PHY_MACRO_CNTL_RESERVED339                                                              0x2d59
3145 #define mmDCRX_PHY_MACRO_CNTL_RESERVED339_BASE_IDX                                                     2
3146 #define mmDCRX_PHY_MACRO_CNTL_RESERVED340                                                              0x2d5a
3147 #define mmDCRX_PHY_MACRO_CNTL_RESERVED340_BASE_IDX                                                     2
3148 #define mmDCRX_PHY_MACRO_CNTL_RESERVED341                                                              0x2d5b
3149 #define mmDCRX_PHY_MACRO_CNTL_RESERVED341_BASE_IDX                                                     2
3150 #define mmDCRX_PHY_MACRO_CNTL_RESERVED342                                                              0x2d5c
3151 #define mmDCRX_PHY_MACRO_CNTL_RESERVED342_BASE_IDX                                                     2
3152 #define mmDCRX_PHY_MACRO_CNTL_RESERVED343                                                              0x2d5d
3153 #define mmDCRX_PHY_MACRO_CNTL_RESERVED343_BASE_IDX                                                     2
3154 #define mmDCRX_PHY_MACRO_CNTL_RESERVED344                                                              0x2d5e
3155 #define mmDCRX_PHY_MACRO_CNTL_RESERVED344_BASE_IDX                                                     2
3156 #define mmDCRX_PHY_MACRO_CNTL_RESERVED345                                                              0x2d5f
3157 #define mmDCRX_PHY_MACRO_CNTL_RESERVED345_BASE_IDX                                                     2
3158 #define mmDCRX_PHY_MACRO_CNTL_RESERVED346                                                              0x2d60
3159 #define mmDCRX_PHY_MACRO_CNTL_RESERVED346_BASE_IDX                                                     2
3160 #define mmDCRX_PHY_MACRO_CNTL_RESERVED347                                                              0x2d61
3161 #define mmDCRX_PHY_MACRO_CNTL_RESERVED347_BASE_IDX                                                     2
3162 #define mmDCRX_PHY_MACRO_CNTL_RESERVED348                                                              0x2d62
3163 #define mmDCRX_PHY_MACRO_CNTL_RESERVED348_BASE_IDX                                                     2
3164 #define mmDCRX_PHY_MACRO_CNTL_RESERVED349                                                              0x2d63
3165 #define mmDCRX_PHY_MACRO_CNTL_RESERVED349_BASE_IDX                                                     2
3166 #define mmDCRX_PHY_MACRO_CNTL_RESERVED350                                                              0x2d64
3167 #define mmDCRX_PHY_MACRO_CNTL_RESERVED350_BASE_IDX                                                     2
3168 #define mmDCRX_PHY_MACRO_CNTL_RESERVED351                                                              0x2d65
3169 #define mmDCRX_PHY_MACRO_CNTL_RESERVED351_BASE_IDX                                                     2
3170 #define mmDCRX_PHY_MACRO_CNTL_RESERVED352                                                              0x2d66
3171 #define mmDCRX_PHY_MACRO_CNTL_RESERVED352_BASE_IDX                                                     2
3172 #define mmDCRX_PHY_MACRO_CNTL_RESERVED353                                                              0x2d67
3173 #define mmDCRX_PHY_MACRO_CNTL_RESERVED353_BASE_IDX                                                     2
3174 #define mmDCRX_PHY_MACRO_CNTL_RESERVED354                                                              0x2d68
3175 #define mmDCRX_PHY_MACRO_CNTL_RESERVED354_BASE_IDX                                                     2
3176 #define mmDCRX_PHY_MACRO_CNTL_RESERVED355                                                              0x2d69
3177 #define mmDCRX_PHY_MACRO_CNTL_RESERVED355_BASE_IDX                                                     2
3178 #define mmDCRX_PHY_MACRO_CNTL_RESERVED356                                                              0x2d6a
3179 #define mmDCRX_PHY_MACRO_CNTL_RESERVED356_BASE_IDX                                                     2
3180 #define mmDCRX_PHY_MACRO_CNTL_RESERVED357                                                              0x2d6b
3181 #define mmDCRX_PHY_MACRO_CNTL_RESERVED357_BASE_IDX                                                     2
3182 #define mmDCRX_PHY_MACRO_CNTL_RESERVED358                                                              0x2d6c
3183 #define mmDCRX_PHY_MACRO_CNTL_RESERVED358_BASE_IDX                                                     2
3184 #define mmDCRX_PHY_MACRO_CNTL_RESERVED359                                                              0x2d6d
3185 #define mmDCRX_PHY_MACRO_CNTL_RESERVED359_BASE_IDX                                                     2
3186 #define mmDCRX_PHY_MACRO_CNTL_RESERVED360                                                              0x2d6e
3187 #define mmDCRX_PHY_MACRO_CNTL_RESERVED360_BASE_IDX                                                     2
3188 #define mmDCRX_PHY_MACRO_CNTL_RESERVED361                                                              0x2d6f
3189 #define mmDCRX_PHY_MACRO_CNTL_RESERVED361_BASE_IDX                                                     2
3190 #define mmDCRX_PHY_MACRO_CNTL_RESERVED362                                                              0x2d70
3191 #define mmDCRX_PHY_MACRO_CNTL_RESERVED362_BASE_IDX                                                     2
3192 #define mmDCRX_PHY_MACRO_CNTL_RESERVED363                                                              0x2d71
3193 #define mmDCRX_PHY_MACRO_CNTL_RESERVED363_BASE_IDX                                                     2
3194 #define mmDCRX_PHY_MACRO_CNTL_RESERVED364                                                              0x2d72
3195 #define mmDCRX_PHY_MACRO_CNTL_RESERVED364_BASE_IDX                                                     2
3196 #define mmDCRX_PHY_MACRO_CNTL_RESERVED365                                                              0x2d73
3197 #define mmDCRX_PHY_MACRO_CNTL_RESERVED365_BASE_IDX                                                     2
3198 #define mmDCRX_PHY_MACRO_CNTL_RESERVED366                                                              0x2d74
3199 #define mmDCRX_PHY_MACRO_CNTL_RESERVED366_BASE_IDX                                                     2
3200 #define mmDCRX_PHY_MACRO_CNTL_RESERVED367                                                              0x2d75
3201 #define mmDCRX_PHY_MACRO_CNTL_RESERVED367_BASE_IDX                                                     2
3202 #define mmDCRX_PHY_MACRO_CNTL_RESERVED368                                                              0x2d76
3203 #define mmDCRX_PHY_MACRO_CNTL_RESERVED368_BASE_IDX                                                     2
3204 #define mmDCRX_PHY_MACRO_CNTL_RESERVED369                                                              0x2d77
3205 #define mmDCRX_PHY_MACRO_CNTL_RESERVED369_BASE_IDX                                                     2
3206 #define mmDCRX_PHY_MACRO_CNTL_RESERVED370                                                              0x2d78
3207 #define mmDCRX_PHY_MACRO_CNTL_RESERVED370_BASE_IDX                                                     2
3208 #define mmDCRX_PHY_MACRO_CNTL_RESERVED371                                                              0x2d79
3209 #define mmDCRX_PHY_MACRO_CNTL_RESERVED371_BASE_IDX                                                     2
3210 #define mmDCRX_PHY_MACRO_CNTL_RESERVED372                                                              0x2d7a
3211 #define mmDCRX_PHY_MACRO_CNTL_RESERVED372_BASE_IDX                                                     2
3212 #define mmDCRX_PHY_MACRO_CNTL_RESERVED373                                                              0x2d7b
3213 #define mmDCRX_PHY_MACRO_CNTL_RESERVED373_BASE_IDX                                                     2
3214 #define mmDCRX_PHY_MACRO_CNTL_RESERVED374                                                              0x2d7c
3215 #define mmDCRX_PHY_MACRO_CNTL_RESERVED374_BASE_IDX                                                     2
3216 #define mmDCRX_PHY_MACRO_CNTL_RESERVED375                                                              0x2d7d
3217 #define mmDCRX_PHY_MACRO_CNTL_RESERVED375_BASE_IDX                                                     2
3218 #define mmDCRX_PHY_MACRO_CNTL_RESERVED376                                                              0x2d7e
3219 #define mmDCRX_PHY_MACRO_CNTL_RESERVED376_BASE_IDX                                                     2
3220 #define mmDCRX_PHY_MACRO_CNTL_RESERVED377                                                              0x2d7f
3221 #define mmDCRX_PHY_MACRO_CNTL_RESERVED377_BASE_IDX                                                     2
3222 #define mmDCRX_PHY_MACRO_CNTL_RESERVED378                                                              0x2d80
3223 #define mmDCRX_PHY_MACRO_CNTL_RESERVED378_BASE_IDX                                                     2
3224 #define mmDCRX_PHY_MACRO_CNTL_RESERVED379                                                              0x2d81
3225 #define mmDCRX_PHY_MACRO_CNTL_RESERVED379_BASE_IDX                                                     2
3226 #define mmI2S0_CNTL                                                                                    0x2d82
3227 #define mmI2S0_CNTL_BASE_IDX                                                                           2
3228 #define mmSPDIF0_CNTL                                                                                  0x2d83
3229 #define mmSPDIF0_CNTL_BASE_IDX                                                                         2
3230 #define mmI2S1_CNTL                                                                                    0x2d84
3231 #define mmI2S1_CNTL_BASE_IDX                                                                           2
3232 #define mmSPDIF1_CNTL                                                                                  0x2d85
3233 #define mmSPDIF1_CNTL_BASE_IDX                                                                         2
3234 #define mmI2S0_STATUS                                                                                  0x2d86
3235 #define mmI2S0_STATUS_BASE_IDX                                                                         2
3236 #define mmI2S1_STATUS                                                                                  0x2d87
3237 #define mmI2S1_STATUS_BASE_IDX                                                                         2
3238 #define mmI2S0_CRC_TEST_CNTL                                                                           0x2d8a
3239 #define mmI2S0_CRC_TEST_CNTL_BASE_IDX                                                                  2
3240 #define mmI2S0_CRC_TEST_DATA_01                                                                        0x2d8b
3241 #define mmI2S0_CRC_TEST_DATA_01_BASE_IDX                                                               2
3242 #define mmI2S0_CRC_TEST_DATA_23                                                                        0x2d8c
3243 #define mmI2S0_CRC_TEST_DATA_23_BASE_IDX                                                               2
3244 #define mmI2S1_CRC_TEST_CNTL                                                                           0x2d8d
3245 #define mmI2S1_CRC_TEST_CNTL_BASE_IDX                                                                  2
3246 #define mmI2S1_CRC_TEST_DATA_0                                                                         0x2d8e
3247 #define mmI2S1_CRC_TEST_DATA_0_BASE_IDX                                                                2
3248 #define mmSPDIF0_CRC_TEST_CNTL                                                                         0x2d8f
3249 #define mmSPDIF0_CRC_TEST_CNTL_BASE_IDX                                                                2
3250 #define mmSPDIF0_CRC_TEST_DATA_0                                                                       0x2d90
3251 #define mmSPDIF0_CRC_TEST_DATA_0_BASE_IDX                                                              2
3252 #define mmSPDIF1_CRC_TEST_CNTL                                                                         0x2d91
3253 #define mmSPDIF1_CRC_TEST_CNTL_BASE_IDX                                                                2
3254 #define mmSPDIF1_CRC_TEST_DATA                                                                         0x2d92
3255 #define mmSPDIF1_CRC_TEST_DATA_BASE_IDX                                                                2
3256 #define mmCRC_I2S_CONT_REPEAT_NUM                                                                      0x2d93
3257 #define mmCRC_I2S_CONT_REPEAT_NUM_BASE_IDX                                                             2
3258 #define mmCRC_SPDIF_CONT_REPEAT_NUM                                                                    0x2d94
3259 #define mmCRC_SPDIF_CONT_REPEAT_NUM_BASE_IDX                                                           2
3260 #define mmZCAL_MACRO_CNTL_RESERVED0                                                                    0x2d96
3261 #define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX                                                           2
3262 #define mmZCAL_MACRO_CNTL_RESERVED1                                                                    0x2d97
3263 #define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX                                                           2
3264 #define mmZCAL_MACRO_CNTL_RESERVED2                                                                    0x2d98
3265 #define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX                                                           2
3266 #define mmZCAL_MACRO_CNTL_RESERVED3                                                                    0x2d99
3267 #define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX                                                           2
3268 #define mmZCAL_MACRO_CNTL_RESERVED4                                                                    0x2d9a
3269 #define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX                                                           2
3270 
3271 
3272 // addressBlock: dce_dc_azf0stream0_dispdec
3273 // base address: 0x0
3274 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x0458
3275 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3276 #define mmAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x0459
3277 #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3278 
3279 
3280 // addressBlock: dce_dc_azf0stream1_dispdec
3281 // base address: 0x8
3282 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x045a
3283 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3284 #define mmAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x045b
3285 #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3286 
3287 
3288 // addressBlock: dce_dc_azf0stream2_dispdec
3289 // base address: 0x10
3290 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x045c
3291 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3292 #define mmAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x045d
3293 #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3294 
3295 
3296 // addressBlock: dce_dc_azf0stream3_dispdec
3297 // base address: 0x18
3298 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x045e
3299 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3300 #define mmAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x045f
3301 #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3302 
3303 
3304 // addressBlock: dce_dc_azf0stream4_dispdec
3305 // base address: 0x20
3306 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0460
3307 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3308 #define mmAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0461
3309 #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3310 
3311 
3312 // addressBlock: dce_dc_azf0stream5_dispdec
3313 // base address: 0x28
3314 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0462
3315 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3316 #define mmAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0463
3317 #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3318 
3319 
3320 // addressBlock: dce_dc_azf0stream6_dispdec
3321 // base address: 0x30
3322 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x0464
3323 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3324 #define mmAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x0465
3325 #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3326 
3327 
3328 // addressBlock: dce_dc_azf0stream7_dispdec
3329 // base address: 0x38
3330 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x0466
3331 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3332 #define mmAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x0467
3333 #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3334 
3335 
3336 // addressBlock: dce_dc_azf0endpoint0_dispdec
3337 // base address: 0x0
3338 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0480
3339 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
3340 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0481
3341 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
3342 
3343 
3344 // addressBlock: dce_dc_azf0endpoint1_dispdec
3345 // base address: 0x18
3346 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0486
3347 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
3348 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0487
3349 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
3350 
3351 
3352 // addressBlock: dce_dc_azf0endpoint2_dispdec
3353 // base address: 0x30
3354 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x048c
3355 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
3356 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x048d
3357 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
3358 
3359 
3360 // addressBlock: dce_dc_azf0endpoint3_dispdec
3361 // base address: 0x48
3362 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0492
3363 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
3364 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0493
3365 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
3366 
3367 
3368 // addressBlock: dce_dc_azf0endpoint4_dispdec
3369 // base address: 0x60
3370 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0498
3371 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
3372 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0499
3373 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
3374 
3375 
3376 // addressBlock: dce_dc_azf0endpoint5_dispdec
3377 // base address: 0x78
3378 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x049e
3379 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
3380 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x049f
3381 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
3382 
3383 
3384 // addressBlock: dce_dc_azf0endpoint6_dispdec
3385 // base address: 0x90
3386 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x04a4
3387 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
3388 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x04a5
3389 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
3390 
3391 
3392 // addressBlock: dce_dc_azf0endpoint7_dispdec
3393 // base address: 0xa8
3394 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x04aa
3395 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
3396 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x04ab
3397 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
3398 
3399 
3400 // addressBlock: dce_dc_azf0stream8_dispdec
3401 // base address: 0x320
3402 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0520
3403 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3404 #define mmAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0521
3405 #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3406 
3407 
3408 // addressBlock: dce_dc_azf0stream9_dispdec
3409 // base address: 0x328
3410 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0522
3411 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
3412 #define mmAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0523
3413 #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
3414 
3415 
3416 // addressBlock: dce_dc_azf0stream10_dispdec
3417 // base address: 0x330
3418 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x0524
3419 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
3420 #define mmAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x0525
3421 #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
3422 
3423 
3424 // addressBlock: dce_dc_azf0stream11_dispdec
3425 // base address: 0x338
3426 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x0526
3427 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
3428 #define mmAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x0527
3429 #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
3430 
3431 
3432 // addressBlock: dce_dc_azf0stream12_dispdec
3433 // base address: 0x340
3434 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x0528
3435 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
3436 #define mmAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x0529
3437 #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
3438 
3439 
3440 // addressBlock: dce_dc_azf0stream13_dispdec
3441 // base address: 0x348
3442 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x052a
3443 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
3444 #define mmAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x052b
3445 #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
3446 
3447 
3448 // addressBlock: dce_dc_azf0stream14_dispdec
3449 // base address: 0x350
3450 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x052c
3451 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
3452 #define mmAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x052d
3453 #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
3454 
3455 
3456 // addressBlock: dce_dc_azf0stream15_dispdec
3457 // base address: 0x358
3458 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x052e
3459 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
3460 #define mmAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x052f
3461 #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
3462 
3463 
3464 // addressBlock: dce_dc_azf0inputendpoint0_dispdec
3465 // base address: 0x0
3466 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0534
3467 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
3468 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0535
3469 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
3470 
3471 
3472 // addressBlock: dce_dc_azf0inputendpoint1_dispdec
3473 // base address: 0x10
3474 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0538
3475 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
3476 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0539
3477 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
3478 
3479 
3480 // addressBlock: dce_dc_azf0inputendpoint2_dispdec
3481 // base address: 0x20
3482 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x053c
3483 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
3484 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x053d
3485 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
3486 
3487 
3488 // addressBlock: dce_dc_azf0inputendpoint3_dispdec
3489 // base address: 0x30
3490 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0540
3491 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
3492 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0541
3493 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
3494 
3495 
3496 // addressBlock: dce_dc_azf0inputendpoint4_dispdec
3497 // base address: 0x40
3498 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0544
3499 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
3500 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0545
3501 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
3502 
3503 
3504 // addressBlock: dce_dc_azf0inputendpoint5_dispdec
3505 // base address: 0x50
3506 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0548
3507 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
3508 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0549
3509 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
3510 
3511 
3512 // addressBlock: dce_dc_azf0inputendpoint6_dispdec
3513 // base address: 0x60
3514 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x054c
3515 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
3516 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x054d
3517 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
3518 
3519 
3520 // addressBlock: dce_dc_azf0inputendpoint7_dispdec
3521 // base address: 0x70
3522 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0550
3523 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
3524 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0551
3525 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
3526 
3527 
3528 // addressBlock: dce_dc_dcp0_dispdec
3529 // base address: 0x0
3530 #define mmDCP0_GRPH_ENABLE                                                                             0x055a
3531 #define mmDCP0_GRPH_ENABLE_BASE_IDX                                                                    2
3532 #define mmDCP0_GRPH_CONTROL                                                                            0x055b
3533 #define mmDCP0_GRPH_CONTROL_BASE_IDX                                                                   2
3534 #define mmDCP0_GRPH_LUT_10BIT_BYPASS                                                                   0x055c
3535 #define mmDCP0_GRPH_LUT_10BIT_BYPASS_BASE_IDX                                                          2
3536 #define mmDCP0_GRPH_SWAP_CNTL                                                                          0x055d
3537 #define mmDCP0_GRPH_SWAP_CNTL_BASE_IDX                                                                 2
3538 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS                                                            0x055e
3539 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                                   2
3540 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS                                                          0x055f
3541 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                                 2
3542 #define mmDCP0_GRPH_PITCH                                                                              0x0560
3543 #define mmDCP0_GRPH_PITCH_BASE_IDX                                                                     2
3544 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                                       0x0561
3545 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                              2
3546 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                                     0x0562
3547 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                            2
3548 #define mmDCP0_GRPH_SURFACE_OFFSET_X                                                                   0x0563
3549 #define mmDCP0_GRPH_SURFACE_OFFSET_X_BASE_IDX                                                          2
3550 #define mmDCP0_GRPH_SURFACE_OFFSET_Y                                                                   0x0564
3551 #define mmDCP0_GRPH_SURFACE_OFFSET_Y_BASE_IDX                                                          2
3552 #define mmDCP0_GRPH_X_START                                                                            0x0565
3553 #define mmDCP0_GRPH_X_START_BASE_IDX                                                                   2
3554 #define mmDCP0_GRPH_Y_START                                                                            0x0566
3555 #define mmDCP0_GRPH_Y_START_BASE_IDX                                                                   2
3556 #define mmDCP0_GRPH_X_END                                                                              0x0567
3557 #define mmDCP0_GRPH_X_END_BASE_IDX                                                                     2
3558 #define mmDCP0_GRPH_Y_END                                                                              0x0568
3559 #define mmDCP0_GRPH_Y_END_BASE_IDX                                                                     2
3560 #define mmDCP0_INPUT_GAMMA_CONTROL                                                                     0x0569
3561 #define mmDCP0_INPUT_GAMMA_CONTROL_BASE_IDX                                                            2
3562 #define mmDCP0_GRPH_UPDATE                                                                             0x056a
3563 #define mmDCP0_GRPH_UPDATE_BASE_IDX                                                                    2
3564 #define mmDCP0_GRPH_FLIP_CONTROL                                                                       0x056b
3565 #define mmDCP0_GRPH_FLIP_CONTROL_BASE_IDX                                                              2
3566 #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE                                                              0x056c
3567 #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX                                                     2
3568 #define mmDCP0_GRPH_DFQ_CONTROL                                                                        0x056d
3569 #define mmDCP0_GRPH_DFQ_CONTROL_BASE_IDX                                                               2
3570 #define mmDCP0_GRPH_DFQ_STATUS                                                                         0x056e
3571 #define mmDCP0_GRPH_DFQ_STATUS_BASE_IDX                                                                2
3572 #define mmDCP0_GRPH_INTERRUPT_STATUS                                                                   0x056f
3573 #define mmDCP0_GRPH_INTERRUPT_STATUS_BASE_IDX                                                          2
3574 #define mmDCP0_GRPH_INTERRUPT_CONTROL                                                                  0x0570
3575 #define mmDCP0_GRPH_INTERRUPT_CONTROL_BASE_IDX                                                         2
3576 #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                                         0x0571
3577 #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX                                                2
3578 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS                                                           0x0572
3579 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX                                                  2
3580 #define mmDCP0_GRPH_COMPRESS_PITCH                                                                     0x0573
3581 #define mmDCP0_GRPH_COMPRESS_PITCH_BASE_IDX                                                            2
3582 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                                      0x0574
3583 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX                                             2
3584 #define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                                                     0x0575
3585 #define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX                                            2
3586 #define mmDCP0_PRESCALE_GRPH_CONTROL                                                                   0x0576
3587 #define mmDCP0_PRESCALE_GRPH_CONTROL_BASE_IDX                                                          2
3588 #define mmDCP0_PRESCALE_VALUES_GRPH_R                                                                  0x0577
3589 #define mmDCP0_PRESCALE_VALUES_GRPH_R_BASE_IDX                                                         2
3590 #define mmDCP0_PRESCALE_VALUES_GRPH_G                                                                  0x0578
3591 #define mmDCP0_PRESCALE_VALUES_GRPH_G_BASE_IDX                                                         2
3592 #define mmDCP0_PRESCALE_VALUES_GRPH_B                                                                  0x0579
3593 #define mmDCP0_PRESCALE_VALUES_GRPH_B_BASE_IDX                                                         2
3594 #define mmDCP0_INPUT_CSC_CONTROL                                                                       0x057a
3595 #define mmDCP0_INPUT_CSC_CONTROL_BASE_IDX                                                              2
3596 #define mmDCP0_INPUT_CSC_C11_C12                                                                       0x057b
3597 #define mmDCP0_INPUT_CSC_C11_C12_BASE_IDX                                                              2
3598 #define mmDCP0_INPUT_CSC_C13_C14                                                                       0x057c
3599 #define mmDCP0_INPUT_CSC_C13_C14_BASE_IDX                                                              2
3600 #define mmDCP0_INPUT_CSC_C21_C22                                                                       0x057d
3601 #define mmDCP0_INPUT_CSC_C21_C22_BASE_IDX                                                              2
3602 #define mmDCP0_INPUT_CSC_C23_C24                                                                       0x057e
3603 #define mmDCP0_INPUT_CSC_C23_C24_BASE_IDX                                                              2
3604 #define mmDCP0_INPUT_CSC_C31_C32                                                                       0x057f
3605 #define mmDCP0_INPUT_CSC_C31_C32_BASE_IDX                                                              2
3606 #define mmDCP0_INPUT_CSC_C33_C34                                                                       0x0580
3607 #define mmDCP0_INPUT_CSC_C33_C34_BASE_IDX                                                              2
3608 #define mmDCP0_OUTPUT_CSC_CONTROL                                                                      0x0581
3609 #define mmDCP0_OUTPUT_CSC_CONTROL_BASE_IDX                                                             2
3610 #define mmDCP0_OUTPUT_CSC_C11_C12                                                                      0x0582
3611 #define mmDCP0_OUTPUT_CSC_C11_C12_BASE_IDX                                                             2
3612 #define mmDCP0_OUTPUT_CSC_C13_C14                                                                      0x0583
3613 #define mmDCP0_OUTPUT_CSC_C13_C14_BASE_IDX                                                             2
3614 #define mmDCP0_OUTPUT_CSC_C21_C22                                                                      0x0584
3615 #define mmDCP0_OUTPUT_CSC_C21_C22_BASE_IDX                                                             2
3616 #define mmDCP0_OUTPUT_CSC_C23_C24                                                                      0x0585
3617 #define mmDCP0_OUTPUT_CSC_C23_C24_BASE_IDX                                                             2
3618 #define mmDCP0_OUTPUT_CSC_C31_C32                                                                      0x0586
3619 #define mmDCP0_OUTPUT_CSC_C31_C32_BASE_IDX                                                             2
3620 #define mmDCP0_OUTPUT_CSC_C33_C34                                                                      0x0587
3621 #define mmDCP0_OUTPUT_CSC_C33_C34_BASE_IDX                                                             2
3622 #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12                                                              0x0588
3623 #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX                                                     2
3624 #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14                                                              0x0589
3625 #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX                                                     2
3626 #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22                                                              0x058a
3627 #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX                                                     2
3628 #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24                                                              0x058b
3629 #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX                                                     2
3630 #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32                                                              0x058c
3631 #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX                                                     2
3632 #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34                                                              0x058d
3633 #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX                                                     2
3634 #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12                                                              0x058e
3635 #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX                                                     2
3636 #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14                                                              0x058f
3637 #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX                                                     2
3638 #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22                                                              0x0590
3639 #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX                                                     2
3640 #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24                                                              0x0591
3641 #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX                                                     2
3642 #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32                                                              0x0592
3643 #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX                                                     2
3644 #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34                                                              0x0593
3645 #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX                                                     2
3646 #define mmDCP0_DENORM_CONTROL                                                                          0x0594
3647 #define mmDCP0_DENORM_CONTROL_BASE_IDX                                                                 2
3648 #define mmDCP0_OUT_ROUND_CONTROL                                                                       0x0595
3649 #define mmDCP0_OUT_ROUND_CONTROL_BASE_IDX                                                              2
3650 #define mmDCP0_OUT_CLAMP_CONTROL_R_CR                                                                  0x0596
3651 #define mmDCP0_OUT_CLAMP_CONTROL_R_CR_BASE_IDX                                                         2
3652 #define mmDCP0_OUT_CLAMP_CONTROL_G_Y                                                                   0x0597
3653 #define mmDCP0_OUT_CLAMP_CONTROL_G_Y_BASE_IDX                                                          2
3654 #define mmDCP0_OUT_CLAMP_CONTROL_B_CB                                                                  0x0598
3655 #define mmDCP0_OUT_CLAMP_CONTROL_B_CB_BASE_IDX                                                         2
3656 #define mmDCP0_KEY_CONTROL                                                                             0x0599
3657 #define mmDCP0_KEY_CONTROL_BASE_IDX                                                                    2
3658 #define mmDCP0_KEY_RANGE_ALPHA                                                                         0x059a
3659 #define mmDCP0_KEY_RANGE_ALPHA_BASE_IDX                                                                2
3660 #define mmDCP0_KEY_RANGE_RED                                                                           0x059b
3661 #define mmDCP0_KEY_RANGE_RED_BASE_IDX                                                                  2
3662 #define mmDCP0_KEY_RANGE_GREEN                                                                         0x059c
3663 #define mmDCP0_KEY_RANGE_GREEN_BASE_IDX                                                                2
3664 #define mmDCP0_KEY_RANGE_BLUE                                                                          0x059d
3665 #define mmDCP0_KEY_RANGE_BLUE_BASE_IDX                                                                 2
3666 #define mmDCP0_DEGAMMA_CONTROL                                                                         0x059e
3667 #define mmDCP0_DEGAMMA_CONTROL_BASE_IDX                                                                2
3668 #define mmDCP0_GAMUT_REMAP_CONTROL                                                                     0x059f
3669 #define mmDCP0_GAMUT_REMAP_CONTROL_BASE_IDX                                                            2
3670 #define mmDCP0_GAMUT_REMAP_C11_C12                                                                     0x05a0
3671 #define mmDCP0_GAMUT_REMAP_C11_C12_BASE_IDX                                                            2
3672 #define mmDCP0_GAMUT_REMAP_C13_C14                                                                     0x05a1
3673 #define mmDCP0_GAMUT_REMAP_C13_C14_BASE_IDX                                                            2
3674 #define mmDCP0_GAMUT_REMAP_C21_C22                                                                     0x05a2
3675 #define mmDCP0_GAMUT_REMAP_C21_C22_BASE_IDX                                                            2
3676 #define mmDCP0_GAMUT_REMAP_C23_C24                                                                     0x05a3
3677 #define mmDCP0_GAMUT_REMAP_C23_C24_BASE_IDX                                                            2
3678 #define mmDCP0_GAMUT_REMAP_C31_C32                                                                     0x05a4
3679 #define mmDCP0_GAMUT_REMAP_C31_C32_BASE_IDX                                                            2
3680 #define mmDCP0_GAMUT_REMAP_C33_C34                                                                     0x05a5
3681 #define mmDCP0_GAMUT_REMAP_C33_C34_BASE_IDX                                                            2
3682 #define mmDCP0_DCP_SPATIAL_DITHER_CNTL                                                                 0x05a6
3683 #define mmDCP0_DCP_SPATIAL_DITHER_CNTL_BASE_IDX                                                        2
3684 #define mmDCP0_DCP_RANDOM_SEEDS                                                                        0x05a7
3685 #define mmDCP0_DCP_RANDOM_SEEDS_BASE_IDX                                                               2
3686 #define mmDCP0_DCP_FP_CONVERTED_FIELD                                                                  0x05a8
3687 #define mmDCP0_DCP_FP_CONVERTED_FIELD_BASE_IDX                                                         2
3688 #define mmDCP0_CUR_CONTROL                                                                             0x05a9
3689 #define mmDCP0_CUR_CONTROL_BASE_IDX                                                                    2
3690 #define mmDCP0_CUR_SURFACE_ADDRESS                                                                     0x05aa
3691 #define mmDCP0_CUR_SURFACE_ADDRESS_BASE_IDX                                                            2
3692 #define mmDCP0_CUR_SIZE                                                                                0x05ab
3693 #define mmDCP0_CUR_SIZE_BASE_IDX                                                                       2
3694 #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH                                                                0x05ac
3695 #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX                                                       2
3696 #define mmDCP0_CUR_POSITION                                                                            0x05ad
3697 #define mmDCP0_CUR_POSITION_BASE_IDX                                                                   2
3698 #define mmDCP0_CUR_HOT_SPOT                                                                            0x05ae
3699 #define mmDCP0_CUR_HOT_SPOT_BASE_IDX                                                                   2
3700 #define mmDCP0_CUR_COLOR1                                                                              0x05af
3701 #define mmDCP0_CUR_COLOR1_BASE_IDX                                                                     2
3702 #define mmDCP0_CUR_COLOR2                                                                              0x05b0
3703 #define mmDCP0_CUR_COLOR2_BASE_IDX                                                                     2
3704 #define mmDCP0_CUR_UPDATE                                                                              0x05b1
3705 #define mmDCP0_CUR_UPDATE_BASE_IDX                                                                     2
3706 #define mmDCP0_CUR_REQUEST_FILTER_CNTL                                                                 0x05bb
3707 #define mmDCP0_CUR_REQUEST_FILTER_CNTL_BASE_IDX                                                        2
3708 #define mmDCP0_CUR_STEREO_CONTROL                                                                      0x05bc
3709 #define mmDCP0_CUR_STEREO_CONTROL_BASE_IDX                                                             2
3710 #define mmDCP0_DC_LUT_RW_MODE                                                                          0x05be
3711 #define mmDCP0_DC_LUT_RW_MODE_BASE_IDX                                                                 2
3712 #define mmDCP0_DC_LUT_RW_INDEX                                                                         0x05bf
3713 #define mmDCP0_DC_LUT_RW_INDEX_BASE_IDX                                                                2
3714 #define mmDCP0_DC_LUT_SEQ_COLOR                                                                        0x05c0
3715 #define mmDCP0_DC_LUT_SEQ_COLOR_BASE_IDX                                                               2
3716 #define mmDCP0_DC_LUT_PWL_DATA                                                                         0x05c1
3717 #define mmDCP0_DC_LUT_PWL_DATA_BASE_IDX                                                                2
3718 #define mmDCP0_DC_LUT_30_COLOR                                                                         0x05c2
3719 #define mmDCP0_DC_LUT_30_COLOR_BASE_IDX                                                                2
3720 #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE                                                                0x05c3
3721 #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX                                                       2
3722 #define mmDCP0_DC_LUT_WRITE_EN_MASK                                                                    0x05c4
3723 #define mmDCP0_DC_LUT_WRITE_EN_MASK_BASE_IDX                                                           2
3724 #define mmDCP0_DC_LUT_AUTOFILL                                                                         0x05c5
3725 #define mmDCP0_DC_LUT_AUTOFILL_BASE_IDX                                                                2
3726 #define mmDCP0_DC_LUT_CONTROL                                                                          0x05c6
3727 #define mmDCP0_DC_LUT_CONTROL_BASE_IDX                                                                 2
3728 #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE                                                                0x05c7
3729 #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX                                                       2
3730 #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN                                                               0x05c8
3731 #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX                                                      2
3732 #define mmDCP0_DC_LUT_BLACK_OFFSET_RED                                                                 0x05c9
3733 #define mmDCP0_DC_LUT_BLACK_OFFSET_RED_BASE_IDX                                                        2
3734 #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE                                                                0x05ca
3735 #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX                                                       2
3736 #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN                                                               0x05cb
3737 #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX                                                      2
3738 #define mmDCP0_DC_LUT_WHITE_OFFSET_RED                                                                 0x05cc
3739 #define mmDCP0_DC_LUT_WHITE_OFFSET_RED_BASE_IDX                                                        2
3740 #define mmDCP0_DCP_CRC_CONTROL                                                                         0x05cd
3741 #define mmDCP0_DCP_CRC_CONTROL_BASE_IDX                                                                2
3742 #define mmDCP0_DCP_CRC_MASK                                                                            0x05ce
3743 #define mmDCP0_DCP_CRC_MASK_BASE_IDX                                                                   2
3744 #define mmDCP0_DCP_CRC_CURRENT                                                                         0x05cf
3745 #define mmDCP0_DCP_CRC_CURRENT_BASE_IDX                                                                2
3746 #define mmDCP0_DVMM_PTE_CONTROL                                                                        0x05d0
3747 #define mmDCP0_DVMM_PTE_CONTROL_BASE_IDX                                                               2
3748 #define mmDCP0_DCP_CRC_LAST                                                                            0x05d1
3749 #define mmDCP0_DCP_CRC_LAST_BASE_IDX                                                                   2
3750 #define mmDCP0_DVMM_PTE_ARB_CONTROL                                                                    0x05d2
3751 #define mmDCP0_DVMM_PTE_ARB_CONTROL_BASE_IDX                                                           2
3752 #define mmDCP0_GRPH_FLIP_RATE_CNTL                                                                     0x05d4
3753 #define mmDCP0_GRPH_FLIP_RATE_CNTL_BASE_IDX                                                            2
3754 #define mmDCP0_DCP_GSL_CONTROL                                                                         0x05d5
3755 #define mmDCP0_DCP_GSL_CONTROL_BASE_IDX                                                                2
3756 #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                                           0x05d6
3757 #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX                                                  2
3758 #define mmDCP0_GRPH_STEREOSYNC_FLIP                                                                    0x05dc
3759 #define mmDCP0_GRPH_STEREOSYNC_FLIP_BASE_IDX                                                           2
3760 #define mmDCP0_HW_ROTATION                                                                             0x05de
3761 #define mmDCP0_HW_ROTATION_BASE_IDX                                                                    2
3762 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                                      0x05df
3763 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX                                             2
3764 #define mmDCP0_REGAMMA_CONTROL                                                                         0x05e0
3765 #define mmDCP0_REGAMMA_CONTROL_BASE_IDX                                                                2
3766 #define mmDCP0_REGAMMA_LUT_INDEX                                                                       0x05e1
3767 #define mmDCP0_REGAMMA_LUT_INDEX_BASE_IDX                                                              2
3768 #define mmDCP0_REGAMMA_LUT_DATA                                                                        0x05e2
3769 #define mmDCP0_REGAMMA_LUT_DATA_BASE_IDX                                                               2
3770 #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK                                                               0x05e3
3771 #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX                                                      2
3772 #define mmDCP0_REGAMMA_CNTLA_START_CNTL                                                                0x05e4
3773 #define mmDCP0_REGAMMA_CNTLA_START_CNTL_BASE_IDX                                                       2
3774 #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL                                                                0x05e5
3775 #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX                                                       2
3776 #define mmDCP0_REGAMMA_CNTLA_END_CNTL1                                                                 0x05e6
3777 #define mmDCP0_REGAMMA_CNTLA_END_CNTL1_BASE_IDX                                                        2
3778 #define mmDCP0_REGAMMA_CNTLA_END_CNTL2                                                                 0x05e7
3779 #define mmDCP0_REGAMMA_CNTLA_END_CNTL2_BASE_IDX                                                        2
3780 #define mmDCP0_REGAMMA_CNTLA_REGION_0_1                                                                0x05e8
3781 #define mmDCP0_REGAMMA_CNTLA_REGION_0_1_BASE_IDX                                                       2
3782 #define mmDCP0_REGAMMA_CNTLA_REGION_2_3                                                                0x05e9
3783 #define mmDCP0_REGAMMA_CNTLA_REGION_2_3_BASE_IDX                                                       2
3784 #define mmDCP0_REGAMMA_CNTLA_REGION_4_5                                                                0x05ea
3785 #define mmDCP0_REGAMMA_CNTLA_REGION_4_5_BASE_IDX                                                       2
3786 #define mmDCP0_REGAMMA_CNTLA_REGION_6_7                                                                0x05eb
3787 #define mmDCP0_REGAMMA_CNTLA_REGION_6_7_BASE_IDX                                                       2
3788 #define mmDCP0_REGAMMA_CNTLA_REGION_8_9                                                                0x05ec
3789 #define mmDCP0_REGAMMA_CNTLA_REGION_8_9_BASE_IDX                                                       2
3790 #define mmDCP0_REGAMMA_CNTLA_REGION_10_11                                                              0x05ed
3791 #define mmDCP0_REGAMMA_CNTLA_REGION_10_11_BASE_IDX                                                     2
3792 #define mmDCP0_REGAMMA_CNTLA_REGION_12_13                                                              0x05ee
3793 #define mmDCP0_REGAMMA_CNTLA_REGION_12_13_BASE_IDX                                                     2
3794 #define mmDCP0_REGAMMA_CNTLA_REGION_14_15                                                              0x05ef
3795 #define mmDCP0_REGAMMA_CNTLA_REGION_14_15_BASE_IDX                                                     2
3796 #define mmDCP0_REGAMMA_CNTLB_START_CNTL                                                                0x05f0
3797 #define mmDCP0_REGAMMA_CNTLB_START_CNTL_BASE_IDX                                                       2
3798 #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL                                                                0x05f1
3799 #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX                                                       2
3800 #define mmDCP0_REGAMMA_CNTLB_END_CNTL1                                                                 0x05f2
3801 #define mmDCP0_REGAMMA_CNTLB_END_CNTL1_BASE_IDX                                                        2
3802 #define mmDCP0_REGAMMA_CNTLB_END_CNTL2                                                                 0x05f3
3803 #define mmDCP0_REGAMMA_CNTLB_END_CNTL2_BASE_IDX                                                        2
3804 #define mmDCP0_REGAMMA_CNTLB_REGION_0_1                                                                0x05f4
3805 #define mmDCP0_REGAMMA_CNTLB_REGION_0_1_BASE_IDX                                                       2
3806 #define mmDCP0_REGAMMA_CNTLB_REGION_2_3                                                                0x05f5
3807 #define mmDCP0_REGAMMA_CNTLB_REGION_2_3_BASE_IDX                                                       2
3808 #define mmDCP0_REGAMMA_CNTLB_REGION_4_5                                                                0x05f6
3809 #define mmDCP0_REGAMMA_CNTLB_REGION_4_5_BASE_IDX                                                       2
3810 #define mmDCP0_REGAMMA_CNTLB_REGION_6_7                                                                0x05f7
3811 #define mmDCP0_REGAMMA_CNTLB_REGION_6_7_BASE_IDX                                                       2
3812 #define mmDCP0_REGAMMA_CNTLB_REGION_8_9                                                                0x05f8
3813 #define mmDCP0_REGAMMA_CNTLB_REGION_8_9_BASE_IDX                                                       2
3814 #define mmDCP0_REGAMMA_CNTLB_REGION_10_11                                                              0x05f9
3815 #define mmDCP0_REGAMMA_CNTLB_REGION_10_11_BASE_IDX                                                     2
3816 #define mmDCP0_REGAMMA_CNTLB_REGION_12_13                                                              0x05fa
3817 #define mmDCP0_REGAMMA_CNTLB_REGION_12_13_BASE_IDX                                                     2
3818 #define mmDCP0_REGAMMA_CNTLB_REGION_14_15                                                              0x05fb
3819 #define mmDCP0_REGAMMA_CNTLB_REGION_14_15_BASE_IDX                                                     2
3820 #define mmDCP0_ALPHA_CONTROL                                                                           0x05fc
3821 #define mmDCP0_ALPHA_CONTROL_BASE_IDX                                                                  2
3822 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                                      0x05fd
3823 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX                                             2
3824 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                                                 0x05fe
3825 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
3826 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                                    0x05ff
3827 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX                                           2
3828 #define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT                                                                  0x0600
3829 #define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX                                                         2
3830 #define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY                                                                0x0601
3831 #define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX                                                       2
3832 #define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL                                                            0x0602
3833 #define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX                                                   2
3834 #define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT                                                             0x0603
3835 #define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX                                                    2
3836 
3837 
3838 // addressBlock: dce_dc_lb0_dispdec
3839 // base address: 0x0
3840 #define mmLB0_LB_DATA_FORMAT                                                                           0x061a
3841 #define mmLB0_LB_DATA_FORMAT_BASE_IDX                                                                  2
3842 #define mmLB0_LB_MEMORY_CTRL                                                                           0x061b
3843 #define mmLB0_LB_MEMORY_CTRL_BASE_IDX                                                                  2
3844 #define mmLB0_LB_MEMORY_SIZE_STATUS                                                                    0x061c
3845 #define mmLB0_LB_MEMORY_SIZE_STATUS_BASE_IDX                                                           2
3846 #define mmLB0_LB_DESKTOP_HEIGHT                                                                        0x061d
3847 #define mmLB0_LB_DESKTOP_HEIGHT_BASE_IDX                                                               2
3848 #define mmLB0_LB_VLINE_START_END                                                                       0x061e
3849 #define mmLB0_LB_VLINE_START_END_BASE_IDX                                                              2
3850 #define mmLB0_LB_VLINE2_START_END                                                                      0x061f
3851 #define mmLB0_LB_VLINE2_START_END_BASE_IDX                                                             2
3852 #define mmLB0_LB_V_COUNTER                                                                             0x0620
3853 #define mmLB0_LB_V_COUNTER_BASE_IDX                                                                    2
3854 #define mmLB0_LB_SNAPSHOT_V_COUNTER                                                                    0x0621
3855 #define mmLB0_LB_SNAPSHOT_V_COUNTER_BASE_IDX                                                           2
3856 #define mmLB0_LB_INTERRUPT_MASK                                                                        0x0622
3857 #define mmLB0_LB_INTERRUPT_MASK_BASE_IDX                                                               2
3858 #define mmLB0_LB_VLINE_STATUS                                                                          0x0623
3859 #define mmLB0_LB_VLINE_STATUS_BASE_IDX                                                                 2
3860 #define mmLB0_LB_VLINE2_STATUS                                                                         0x0624
3861 #define mmLB0_LB_VLINE2_STATUS_BASE_IDX                                                                2
3862 #define mmLB0_LB_VBLANK_STATUS                                                                         0x0625
3863 #define mmLB0_LB_VBLANK_STATUS_BASE_IDX                                                                2
3864 #define mmLB0_LB_SYNC_RESET_SEL                                                                        0x0626
3865 #define mmLB0_LB_SYNC_RESET_SEL_BASE_IDX                                                               2
3866 #define mmLB0_LB_BLACK_KEYER_R_CR                                                                      0x0627
3867 #define mmLB0_LB_BLACK_KEYER_R_CR_BASE_IDX                                                             2
3868 #define mmLB0_LB_BLACK_KEYER_G_Y                                                                       0x0628
3869 #define mmLB0_LB_BLACK_KEYER_G_Y_BASE_IDX                                                              2
3870 #define mmLB0_LB_BLACK_KEYER_B_CB                                                                      0x0629
3871 #define mmLB0_LB_BLACK_KEYER_B_CB_BASE_IDX                                                             2
3872 #define mmLB0_LB_KEYER_COLOR_CTRL                                                                      0x062a
3873 #define mmLB0_LB_KEYER_COLOR_CTRL_BASE_IDX                                                             2
3874 #define mmLB0_LB_KEYER_COLOR_R_CR                                                                      0x062b
3875 #define mmLB0_LB_KEYER_COLOR_R_CR_BASE_IDX                                                             2
3876 #define mmLB0_LB_KEYER_COLOR_G_Y                                                                       0x062c
3877 #define mmLB0_LB_KEYER_COLOR_G_Y_BASE_IDX                                                              2
3878 #define mmLB0_LB_KEYER_COLOR_B_CB                                                                      0x062d
3879 #define mmLB0_LB_KEYER_COLOR_B_CB_BASE_IDX                                                             2
3880 #define mmLB0_LB_KEYER_COLOR_REP_R_CR                                                                  0x062e
3881 #define mmLB0_LB_KEYER_COLOR_REP_R_CR_BASE_IDX                                                         2
3882 #define mmLB0_LB_KEYER_COLOR_REP_G_Y                                                                   0x062f
3883 #define mmLB0_LB_KEYER_COLOR_REP_G_Y_BASE_IDX                                                          2
3884 #define mmLB0_LB_KEYER_COLOR_REP_B_CB                                                                  0x0630
3885 #define mmLB0_LB_KEYER_COLOR_REP_B_CB_BASE_IDX                                                         2
3886 #define mmLB0_LB_BUFFER_LEVEL_STATUS                                                                   0x0631
3887 #define mmLB0_LB_BUFFER_LEVEL_STATUS_BASE_IDX                                                          2
3888 #define mmLB0_LB_BUFFER_URGENCY_CTRL                                                                   0x0632
3889 #define mmLB0_LB_BUFFER_URGENCY_CTRL_BASE_IDX                                                          2
3890 #define mmLB0_LB_BUFFER_URGENCY_STATUS                                                                 0x0633
3891 #define mmLB0_LB_BUFFER_URGENCY_STATUS_BASE_IDX                                                        2
3892 #define mmLB0_LB_BUFFER_STATUS                                                                         0x0634
3893 #define mmLB0_LB_BUFFER_STATUS_BASE_IDX                                                                2
3894 #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS                                                             0x0635
3895 #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX                                                    2
3896 #define mmLB0_MVP_AFR_FLIP_MODE                                                                        0x0636
3897 #define mmLB0_MVP_AFR_FLIP_MODE_BASE_IDX                                                               2
3898 #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL                                                                   0x0637
3899 #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX                                                          2
3900 #define mmLB0_MVP_FLIP_LINE_NUM_INSERT                                                                 0x0638
3901 #define mmLB0_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX                                                        2
3902 #define mmLB0_DC_MVP_LB_CONTROL                                                                        0x0639
3903 #define mmLB0_DC_MVP_LB_CONTROL_BASE_IDX                                                               2
3904 
3905 
3906 // addressBlock: dce_dc_dcfe0_dispdec
3907 // base address: 0x0
3908 #define mmDCFE0_DCFE_CLOCK_CONTROL                                                                     0x065a
3909 #define mmDCFE0_DCFE_CLOCK_CONTROL_BASE_IDX                                                            2
3910 #define mmDCFE0_DCFE_SOFT_RESET                                                                        0x065b
3911 #define mmDCFE0_DCFE_SOFT_RESET_BASE_IDX                                                               2
3912 #define mmDCFE0_DCFE_MEM_PWR_CTRL                                                                      0x065d
3913 #define mmDCFE0_DCFE_MEM_PWR_CTRL_BASE_IDX                                                             2
3914 #define mmDCFE0_DCFE_MEM_PWR_CTRL2                                                                     0x065e
3915 #define mmDCFE0_DCFE_MEM_PWR_CTRL2_BASE_IDX                                                            2
3916 #define mmDCFE0_DCFE_MEM_PWR_STATUS                                                                    0x065f
3917 #define mmDCFE0_DCFE_MEM_PWR_STATUS_BASE_IDX                                                           2
3918 #define mmDCFE0_DCFE_MISC                                                                              0x0660
3919 #define mmDCFE0_DCFE_MISC_BASE_IDX                                                                     2
3920 #define mmDCFE0_DCFE_FLUSH                                                                             0x0661
3921 #define mmDCFE0_DCFE_FLUSH_BASE_IDX                                                                    2
3922 
3923 
3924 // addressBlock: dce_dc_dc_perfmon3_dispdec
3925 // base address: 0x1938
3926 #define mmDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x066e
3927 #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
3928 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x066f
3929 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
3930 #define mmDC_PERFMON3_PERFCOUNTER_STATE                                                                0x0670
3931 #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
3932 #define mmDC_PERFMON3_PERFMON_CNTL                                                                     0x0671
3933 #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
3934 #define mmDC_PERFMON3_PERFMON_CNTL2                                                                    0x0672
3935 #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
3936 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x0673
3937 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
3938 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x0674
3939 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
3940 #define mmDC_PERFMON3_PERFMON_HI                                                                       0x0675
3941 #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
3942 #define mmDC_PERFMON3_PERFMON_LOW                                                                      0x0676
3943 #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
3944 
3945 
3946 // addressBlock: dce_dc_dmif_pg0_dispdec
3947 // base address: 0x0
3948 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1                                                       0x067a
3949 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                              2
3950 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2                                                       0x067b
3951 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                              2
3952 #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL                                                          0x067c
3953 #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_BASE_IDX                                                 2
3954 #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL                                                            0x067d
3955 #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_BASE_IDX                                                   2
3956 #define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL                                                       0x067e
3957 #define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX                                              2
3958 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL                                                            0x067f
3959 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_BASE_IDX                                                   2
3960 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2                                                           0x0680
3961 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX                                                  2
3962 #define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL                                                          0x0681
3963 #define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX                                                 2
3964 #define mmDMIF_PG0_DPG_REPEATER_PROGRAM                                                                0x0682
3965 #define mmDMIF_PG0_DPG_REPEATER_PROGRAM_BASE_IDX                                                       2
3966 #define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL                                                               0x0686
3967 #define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_BASE_IDX                                                      2
3968 #define mmDMIF_PG0_DPG_DVMM_STATUS                                                                     0x0687
3969 #define mmDMIF_PG0_DPG_DVMM_STATUS_BASE_IDX                                                            2
3970 
3971 
3972 // addressBlock: dce_dc_scl0_dispdec
3973 // base address: 0x0
3974 #define mmSCL0_SCL_COEF_RAM_SELECT                                                                     0x069a
3975 #define mmSCL0_SCL_COEF_RAM_SELECT_BASE_IDX                                                            2
3976 #define mmSCL0_SCL_COEF_RAM_TAP_DATA                                                                   0x069b
3977 #define mmSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                          2
3978 #define mmSCL0_SCL_MODE                                                                                0x069c
3979 #define mmSCL0_SCL_MODE_BASE_IDX                                                                       2
3980 #define mmSCL0_SCL_TAP_CONTROL                                                                         0x069d
3981 #define mmSCL0_SCL_TAP_CONTROL_BASE_IDX                                                                2
3982 #define mmSCL0_SCL_CONTROL                                                                             0x069e
3983 #define mmSCL0_SCL_CONTROL_BASE_IDX                                                                    2
3984 #define mmSCL0_SCL_BYPASS_CONTROL                                                                      0x069f
3985 #define mmSCL0_SCL_BYPASS_CONTROL_BASE_IDX                                                             2
3986 #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                            0x06a0
3987 #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                   2
3988 #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL                                                              0x06a1
3989 #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX                                                     2
3990 #define mmSCL0_SCL_HORZ_FILTER_CONTROL                                                                 0x06a2
3991 #define mmSCL0_SCL_HORZ_FILTER_CONTROL_BASE_IDX                                                        2
3992 #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                             0x06a3
3993 #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                    2
3994 #define mmSCL0_SCL_HORZ_FILTER_INIT                                                                    0x06a4
3995 #define mmSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                           2
3996 #define mmSCL0_SCL_VERT_FILTER_CONTROL                                                                 0x06a5
3997 #define mmSCL0_SCL_VERT_FILTER_CONTROL_BASE_IDX                                                        2
3998 #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                             0x06a6
3999 #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                    2
4000 #define mmSCL0_SCL_VERT_FILTER_INIT                                                                    0x06a7
4001 #define mmSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                           2
4002 #define mmSCL0_SCL_VERT_FILTER_INIT_BOT                                                                0x06a8
4003 #define mmSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                       2
4004 #define mmSCL0_SCL_ROUND_OFFSET                                                                        0x06a9
4005 #define mmSCL0_SCL_ROUND_OFFSET_BASE_IDX                                                               2
4006 #define mmSCL0_SCL_UPDATE                                                                              0x06aa
4007 #define mmSCL0_SCL_UPDATE_BASE_IDX                                                                     2
4008 #define mmSCL0_SCL_F_SHARP_CONTROL                                                                     0x06ab
4009 #define mmSCL0_SCL_F_SHARP_CONTROL_BASE_IDX                                                            2
4010 #define mmSCL0_SCL_ALU_CONTROL                                                                         0x06ac
4011 #define mmSCL0_SCL_ALU_CONTROL_BASE_IDX                                                                2
4012 #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS                                                            0x06ad
4013 #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                   2
4014 #define mmSCL0_VIEWPORT_START_SECONDARY                                                                0x06ae
4015 #define mmSCL0_VIEWPORT_START_SECONDARY_BASE_IDX                                                       2
4016 #define mmSCL0_VIEWPORT_START                                                                          0x06af
4017 #define mmSCL0_VIEWPORT_START_BASE_IDX                                                                 2
4018 #define mmSCL0_VIEWPORT_SIZE                                                                           0x06b0
4019 #define mmSCL0_VIEWPORT_SIZE_BASE_IDX                                                                  2
4020 #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT                                                                 0x06b1
4021 #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                        2
4022 #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM                                                                 0x06b2
4023 #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                        2
4024 #define mmSCL0_SCL_MODE_CHANGE_DET1                                                                    0x06b3
4025 #define mmSCL0_SCL_MODE_CHANGE_DET1_BASE_IDX                                                           2
4026 #define mmSCL0_SCL_MODE_CHANGE_DET2                                                                    0x06b4
4027 #define mmSCL0_SCL_MODE_CHANGE_DET2_BASE_IDX                                                           2
4028 #define mmSCL0_SCL_MODE_CHANGE_DET3                                                                    0x06b5
4029 #define mmSCL0_SCL_MODE_CHANGE_DET3_BASE_IDX                                                           2
4030 #define mmSCL0_SCL_MODE_CHANGE_MASK                                                                    0x06b6
4031 #define mmSCL0_SCL_MODE_CHANGE_MASK_BASE_IDX                                                           2
4032 
4033 
4034 // addressBlock: dce_dc_blnd0_dispdec
4035 // base address: 0x0
4036 #define mmBLND0_BLND_CONTROL                                                                           0x06c7
4037 #define mmBLND0_BLND_CONTROL_BASE_IDX                                                                  2
4038 #define mmBLND0_BLND_SM_CONTROL2                                                                       0x06c8
4039 #define mmBLND0_BLND_SM_CONTROL2_BASE_IDX                                                              2
4040 #define mmBLND0_BLND_CONTROL2                                                                          0x06c9
4041 #define mmBLND0_BLND_CONTROL2_BASE_IDX                                                                 2
4042 #define mmBLND0_BLND_UPDATE                                                                            0x06ca
4043 #define mmBLND0_BLND_UPDATE_BASE_IDX                                                                   2
4044 #define mmBLND0_BLND_UNDERFLOW_INTERRUPT                                                               0x06cb
4045 #define mmBLND0_BLND_UNDERFLOW_INTERRUPT_BASE_IDX                                                      2
4046 #define mmBLND0_BLND_V_UPDATE_LOCK                                                                     0x06cc
4047 #define mmBLND0_BLND_V_UPDATE_LOCK_BASE_IDX                                                            2
4048 #define mmBLND0_BLND_REG_UPDATE_STATUS                                                                 0x06cd
4049 #define mmBLND0_BLND_REG_UPDATE_STATUS_BASE_IDX                                                        2
4050 
4051 
4052 // addressBlock: dce_dc_crtc0_dispdec
4053 // base address: 0x0
4054 #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM                                                                 0x06d2
4055 #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_BASE_IDX                                                        2
4056 #define mmCRTC0_CRTC_H_TOTAL                                                                           0x06d3
4057 #define mmCRTC0_CRTC_H_TOTAL_BASE_IDX                                                                  2
4058 #define mmCRTC0_CRTC_H_BLANK_START_END                                                                 0x06d4
4059 #define mmCRTC0_CRTC_H_BLANK_START_END_BASE_IDX                                                        2
4060 #define mmCRTC0_CRTC_H_SYNC_A                                                                          0x06d5
4061 #define mmCRTC0_CRTC_H_SYNC_A_BASE_IDX                                                                 2
4062 #define mmCRTC0_CRTC_H_SYNC_A_CNTL                                                                     0x06d6
4063 #define mmCRTC0_CRTC_H_SYNC_A_CNTL_BASE_IDX                                                            2
4064 #define mmCRTC0_CRTC_H_SYNC_B                                                                          0x06d7
4065 #define mmCRTC0_CRTC_H_SYNC_B_BASE_IDX                                                                 2
4066 #define mmCRTC0_CRTC_H_SYNC_B_CNTL                                                                     0x06d8
4067 #define mmCRTC0_CRTC_H_SYNC_B_CNTL_BASE_IDX                                                            2
4068 #define mmCRTC0_CRTC_VBI_END                                                                           0x06d9
4069 #define mmCRTC0_CRTC_VBI_END_BASE_IDX                                                                  2
4070 #define mmCRTC0_CRTC_V_TOTAL                                                                           0x06da
4071 #define mmCRTC0_CRTC_V_TOTAL_BASE_IDX                                                                  2
4072 #define mmCRTC0_CRTC_V_TOTAL_MIN                                                                       0x06db
4073 #define mmCRTC0_CRTC_V_TOTAL_MIN_BASE_IDX                                                              2
4074 #define mmCRTC0_CRTC_V_TOTAL_MAX                                                                       0x06dc
4075 #define mmCRTC0_CRTC_V_TOTAL_MAX_BASE_IDX                                                              2
4076 #define mmCRTC0_CRTC_V_TOTAL_CONTROL                                                                   0x06dd
4077 #define mmCRTC0_CRTC_V_TOTAL_CONTROL_BASE_IDX                                                          2
4078 #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS                                                                0x06de
4079 #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_BASE_IDX                                                       2
4080 #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS                                                              0x06df
4081 #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX                                                     2
4082 #define mmCRTC0_CRTC_V_BLANK_START_END                                                                 0x06e0
4083 #define mmCRTC0_CRTC_V_BLANK_START_END_BASE_IDX                                                        2
4084 #define mmCRTC0_CRTC_V_SYNC_A                                                                          0x06e1
4085 #define mmCRTC0_CRTC_V_SYNC_A_BASE_IDX                                                                 2
4086 #define mmCRTC0_CRTC_V_SYNC_A_CNTL                                                                     0x06e2
4087 #define mmCRTC0_CRTC_V_SYNC_A_CNTL_BASE_IDX                                                            2
4088 #define mmCRTC0_CRTC_V_SYNC_B                                                                          0x06e3
4089 #define mmCRTC0_CRTC_V_SYNC_B_BASE_IDX                                                                 2
4090 #define mmCRTC0_CRTC_V_SYNC_B_CNTL                                                                     0x06e4
4091 #define mmCRTC0_CRTC_V_SYNC_B_CNTL_BASE_IDX                                                            2
4092 #define mmCRTC0_CRTC_DTMTEST_CNTL                                                                      0x06e5
4093 #define mmCRTC0_CRTC_DTMTEST_CNTL_BASE_IDX                                                             2
4094 #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION                                                           0x06e6
4095 #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX                                                  2
4096 #define mmCRTC0_CRTC_TRIGA_CNTL                                                                        0x06e7
4097 #define mmCRTC0_CRTC_TRIGA_CNTL_BASE_IDX                                                               2
4098 #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG                                                                 0x06e8
4099 #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX                                                        2
4100 #define mmCRTC0_CRTC_TRIGB_CNTL                                                                        0x06e9
4101 #define mmCRTC0_CRTC_TRIGB_CNTL_BASE_IDX                                                               2
4102 #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG                                                                 0x06ea
4103 #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX                                                        2
4104 #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL                                                              0x06eb
4105 #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                     2
4106 #define mmCRTC0_CRTC_FLOW_CONTROL                                                                      0x06ec
4107 #define mmCRTC0_CRTC_FLOW_CONTROL_BASE_IDX                                                             2
4108 #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE                                                             0x06ed
4109 #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                    2
4110 #define mmCRTC0_CRTC_AVSYNC_COUNTER                                                                    0x06ee
4111 #define mmCRTC0_CRTC_AVSYNC_COUNTER_BASE_IDX                                                           2
4112 #define mmCRTC0_CRTC_CONTROL                                                                           0x06ef
4113 #define mmCRTC0_CRTC_CONTROL_BASE_IDX                                                                  2
4114 #define mmCRTC0_CRTC_BLANK_CONTROL                                                                     0x06f0
4115 #define mmCRTC0_CRTC_BLANK_CONTROL_BASE_IDX                                                            2
4116 #define mmCRTC0_CRTC_INTERLACE_CONTROL                                                                 0x06f1
4117 #define mmCRTC0_CRTC_INTERLACE_CONTROL_BASE_IDX                                                        2
4118 #define mmCRTC0_CRTC_INTERLACE_STATUS                                                                  0x06f2
4119 #define mmCRTC0_CRTC_INTERLACE_STATUS_BASE_IDX                                                         2
4120 #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL                                                          0x06f3
4121 #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX                                                 2
4122 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0                                                              0x06f4
4123 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_BASE_IDX                                                     2
4124 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1                                                              0x06f5
4125 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_BASE_IDX                                                     2
4126 #define mmCRTC0_CRTC_STATUS                                                                            0x06f6
4127 #define mmCRTC0_CRTC_STATUS_BASE_IDX                                                                   2
4128 #define mmCRTC0_CRTC_STATUS_POSITION                                                                   0x06f7
4129 #define mmCRTC0_CRTC_STATUS_POSITION_BASE_IDX                                                          2
4130 #define mmCRTC0_CRTC_NOM_VERT_POSITION                                                                 0x06f8
4131 #define mmCRTC0_CRTC_NOM_VERT_POSITION_BASE_IDX                                                        2
4132 #define mmCRTC0_CRTC_STATUS_FRAME_COUNT                                                                0x06f9
4133 #define mmCRTC0_CRTC_STATUS_FRAME_COUNT_BASE_IDX                                                       2
4134 #define mmCRTC0_CRTC_STATUS_VF_COUNT                                                                   0x06fa
4135 #define mmCRTC0_CRTC_STATUS_VF_COUNT_BASE_IDX                                                          2
4136 #define mmCRTC0_CRTC_STATUS_HV_COUNT                                                                   0x06fb
4137 #define mmCRTC0_CRTC_STATUS_HV_COUNT_BASE_IDX                                                          2
4138 #define mmCRTC0_CRTC_COUNT_CONTROL                                                                     0x06fc
4139 #define mmCRTC0_CRTC_COUNT_CONTROL_BASE_IDX                                                            2
4140 #define mmCRTC0_CRTC_COUNT_RESET                                                                       0x06fd
4141 #define mmCRTC0_CRTC_COUNT_RESET_BASE_IDX                                                              2
4142 #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                                      0x06fe
4143 #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                             2
4144 #define mmCRTC0_CRTC_VERT_SYNC_CONTROL                                                                 0x06ff
4145 #define mmCRTC0_CRTC_VERT_SYNC_CONTROL_BASE_IDX                                                        2
4146 #define mmCRTC0_CRTC_STEREO_STATUS                                                                     0x0700
4147 #define mmCRTC0_CRTC_STEREO_STATUS_BASE_IDX                                                            2
4148 #define mmCRTC0_CRTC_STEREO_CONTROL                                                                    0x0701
4149 #define mmCRTC0_CRTC_STEREO_CONTROL_BASE_IDX                                                           2
4150 #define mmCRTC0_CRTC_SNAPSHOT_STATUS                                                                   0x0702
4151 #define mmCRTC0_CRTC_SNAPSHOT_STATUS_BASE_IDX                                                          2
4152 #define mmCRTC0_CRTC_SNAPSHOT_CONTROL                                                                  0x0703
4153 #define mmCRTC0_CRTC_SNAPSHOT_CONTROL_BASE_IDX                                                         2
4154 #define mmCRTC0_CRTC_SNAPSHOT_POSITION                                                                 0x0704
4155 #define mmCRTC0_CRTC_SNAPSHOT_POSITION_BASE_IDX                                                        2
4156 #define mmCRTC0_CRTC_SNAPSHOT_FRAME                                                                    0x0705
4157 #define mmCRTC0_CRTC_SNAPSHOT_FRAME_BASE_IDX                                                           2
4158 #define mmCRTC0_CRTC_START_LINE_CONTROL                                                                0x0706
4159 #define mmCRTC0_CRTC_START_LINE_CONTROL_BASE_IDX                                                       2
4160 #define mmCRTC0_CRTC_INTERRUPT_CONTROL                                                                 0x0707
4161 #define mmCRTC0_CRTC_INTERRUPT_CONTROL_BASE_IDX                                                        2
4162 #define mmCRTC0_CRTC_UPDATE_LOCK                                                                       0x0708
4163 #define mmCRTC0_CRTC_UPDATE_LOCK_BASE_IDX                                                              2
4164 #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL                                                             0x0709
4165 #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                    2
4166 #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE                                                        0x070a
4167 #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX                                               2
4168 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL                                                              0x070b
4169 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_BASE_IDX                                                     2
4170 #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS                                                           0x070c
4171 #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX                                                  2
4172 #define mmCRTC0_CRTC_TEST_PATTERN_COLOR                                                                0x070d
4173 #define mmCRTC0_CRTC_TEST_PATTERN_COLOR_BASE_IDX                                                       2
4174 #define mmCRTC0_CRTC_MASTER_UPDATE_LOCK                                                                0x070e
4175 #define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_BASE_IDX                                                       2
4176 #define mmCRTC0_CRTC_MASTER_UPDATE_MODE                                                                0x070f
4177 #define mmCRTC0_CRTC_MASTER_UPDATE_MODE_BASE_IDX                                                       2
4178 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT                                                            0x0710
4179 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX                                                   2
4180 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                                                      0x0711
4181 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX                                             2
4182 #define mmCRTC0_CRTC_MVP_STATUS                                                                        0x0712
4183 #define mmCRTC0_CRTC_MVP_STATUS_BASE_IDX                                                               2
4184 #define mmCRTC0_CRTC_MASTER_EN                                                                         0x0713
4185 #define mmCRTC0_CRTC_MASTER_EN_BASE_IDX                                                                2
4186 #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT                                                              0x0714
4187 #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX                                                     2
4188 #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS                                                               0x0715
4189 #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_BASE_IDX                                                      2
4190 #define mmCRTC0_CRTC_OVERSCAN_COLOR                                                                    0x0717
4191 #define mmCRTC0_CRTC_OVERSCAN_COLOR_BASE_IDX                                                           2
4192 #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT                                                                0x0718
4193 #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX                                                       2
4194 #define mmCRTC0_CRTC_BLANK_DATA_COLOR                                                                  0x0719
4195 #define mmCRTC0_CRTC_BLANK_DATA_COLOR_BASE_IDX                                                         2
4196 #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT                                                              0x071a
4197 #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX                                                     2
4198 #define mmCRTC0_CRTC_BLACK_COLOR                                                                       0x071b
4199 #define mmCRTC0_CRTC_BLACK_COLOR_BASE_IDX                                                              2
4200 #define mmCRTC0_CRTC_BLACK_COLOR_EXT                                                                   0x071c
4201 #define mmCRTC0_CRTC_BLACK_COLOR_EXT_BASE_IDX                                                          2
4202 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION                                                      0x071d
4203 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                             2
4204 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL                                                       0x071e
4205 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                              2
4206 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION                                                      0x071f
4207 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                             2
4208 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL                                                       0x0720
4209 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                              2
4210 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION                                                      0x0721
4211 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                             2
4212 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL                                                       0x0722
4213 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                              2
4214 #define mmCRTC0_CRTC_CRC_CNTL                                                                          0x0723
4215 #define mmCRTC0_CRTC_CRC_CNTL_BASE_IDX                                                                 2
4216 #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL                                                            0x0724
4217 #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                   2
4218 #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL                                                            0x0725
4219 #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
4220 #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL                                                            0x0726
4221 #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                   2
4222 #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL                                                            0x0727
4223 #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
4224 #define mmCRTC0_CRTC_CRC0_DATA_RG                                                                      0x0728
4225 #define mmCRTC0_CRTC_CRC0_DATA_RG_BASE_IDX                                                             2
4226 #define mmCRTC0_CRTC_CRC0_DATA_B                                                                       0x0729
4227 #define mmCRTC0_CRTC_CRC0_DATA_B_BASE_IDX                                                              2
4228 #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL                                                            0x072a
4229 #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                   2
4230 #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL                                                            0x072b
4231 #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
4232 #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL                                                            0x072c
4233 #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                   2
4234 #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL                                                            0x072d
4235 #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
4236 #define mmCRTC0_CRTC_CRC1_DATA_RG                                                                      0x072e
4237 #define mmCRTC0_CRTC_CRC1_DATA_RG_BASE_IDX                                                             2
4238 #define mmCRTC0_CRTC_CRC1_DATA_B                                                                       0x072f
4239 #define mmCRTC0_CRTC_CRC1_DATA_B_BASE_IDX                                                              2
4240 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL                                                           0x0730
4241 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX                                                  2
4242 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START                                                      0x0731
4243 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX                                             2
4244 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END                                                        0x0732
4245 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX                                               2
4246 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                                            0x0733
4247 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX                                   2
4248 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                                 0x0734
4249 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX                                        2
4250 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                                          0x0735
4251 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX                                 2
4252 #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL                                                             0x0736
4253 #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX                                                    2
4254 #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL                                                              0x0737
4255 #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX                                                     2
4256 #define mmCRTC0_CRTC_GSL_VSYNC_GAP                                                                     0x0738
4257 #define mmCRTC0_CRTC_GSL_VSYNC_GAP_BASE_IDX                                                            2
4258 #define mmCRTC0_CRTC_GSL_WINDOW                                                                        0x0739
4259 #define mmCRTC0_CRTC_GSL_WINDOW_BASE_IDX                                                               2
4260 #define mmCRTC0_CRTC_GSL_CONTROL                                                                       0x073a
4261 #define mmCRTC0_CRTC_GSL_CONTROL_BASE_IDX                                                              2
4262 #define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS                                                           0x073d
4263 #define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX                                                  2
4264 #define mmCRTC0_CRTC_DRR_CONTROL                                                                       0x073e
4265 #define mmCRTC0_CRTC_DRR_CONTROL_BASE_IDX                                                              2
4266 
4267 
4268 // addressBlock: dce_dc_fmt0_dispdec
4269 // base address: 0x0
4270 #define mmFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x0742
4271 #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
4272 #define mmFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x0743
4273 #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
4274 #define mmFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x0744
4275 #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
4276 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x0745
4277 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
4278 #define mmFMT0_FMT_CONTROL                                                                             0x0746
4279 #define mmFMT0_FMT_CONTROL_BASE_IDX                                                                    2
4280 #define mmFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x0747
4281 #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
4282 #define mmFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x0748
4283 #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
4284 #define mmFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x0749
4285 #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
4286 #define mmFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x074a
4287 #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
4288 #define mmFMT0_FMT_CLAMP_CNTL                                                                          0x074e
4289 #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
4290 #define mmFMT0_FMT_CRC_CNTL                                                                            0x074f
4291 #define mmFMT0_FMT_CRC_CNTL_BASE_IDX                                                                   2
4292 #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK                                                              0x0750
4293 #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
4294 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK                                                           0x0751
4295 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
4296 #define mmFMT0_FMT_CRC_SIG_RED_GREEN                                                                   0x0752
4297 #define mmFMT0_FMT_CRC_SIG_RED_GREEN_BASE_IDX                                                          2
4298 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL                                                                0x0753
4299 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX                                                       2
4300 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x0754
4301 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
4302 #define mmFMT0_FMT_420_HBLANK_EARLY_START                                                              0x0755
4303 #define mmFMT0_FMT_420_HBLANK_EARLY_START_BASE_IDX                                                     2
4304 
4305 
4306 // addressBlock: dce_dc_dcp1_dispdec
4307 // base address: 0x800
4308 #define mmDCP1_GRPH_ENABLE                                                                             0x075a
4309 #define mmDCP1_GRPH_ENABLE_BASE_IDX                                                                    2
4310 #define mmDCP1_GRPH_CONTROL                                                                            0x075b
4311 #define mmDCP1_GRPH_CONTROL_BASE_IDX                                                                   2
4312 #define mmDCP1_GRPH_LUT_10BIT_BYPASS                                                                   0x075c
4313 #define mmDCP1_GRPH_LUT_10BIT_BYPASS_BASE_IDX                                                          2
4314 #define mmDCP1_GRPH_SWAP_CNTL                                                                          0x075d
4315 #define mmDCP1_GRPH_SWAP_CNTL_BASE_IDX                                                                 2
4316 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS                                                            0x075e
4317 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                                   2
4318 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS                                                          0x075f
4319 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                                 2
4320 #define mmDCP1_GRPH_PITCH                                                                              0x0760
4321 #define mmDCP1_GRPH_PITCH_BASE_IDX                                                                     2
4322 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                                       0x0761
4323 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                              2
4324 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                                     0x0762
4325 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                            2
4326 #define mmDCP1_GRPH_SURFACE_OFFSET_X                                                                   0x0763
4327 #define mmDCP1_GRPH_SURFACE_OFFSET_X_BASE_IDX                                                          2
4328 #define mmDCP1_GRPH_SURFACE_OFFSET_Y                                                                   0x0764
4329 #define mmDCP1_GRPH_SURFACE_OFFSET_Y_BASE_IDX                                                          2
4330 #define mmDCP1_GRPH_X_START                                                                            0x0765
4331 #define mmDCP1_GRPH_X_START_BASE_IDX                                                                   2
4332 #define mmDCP1_GRPH_Y_START                                                                            0x0766
4333 #define mmDCP1_GRPH_Y_START_BASE_IDX                                                                   2
4334 #define mmDCP1_GRPH_X_END                                                                              0x0767
4335 #define mmDCP1_GRPH_X_END_BASE_IDX                                                                     2
4336 #define mmDCP1_GRPH_Y_END                                                                              0x0768
4337 #define mmDCP1_GRPH_Y_END_BASE_IDX                                                                     2
4338 #define mmDCP1_INPUT_GAMMA_CONTROL                                                                     0x0769
4339 #define mmDCP1_INPUT_GAMMA_CONTROL_BASE_IDX                                                            2
4340 #define mmDCP1_GRPH_UPDATE                                                                             0x076a
4341 #define mmDCP1_GRPH_UPDATE_BASE_IDX                                                                    2
4342 #define mmDCP1_GRPH_FLIP_CONTROL                                                                       0x076b
4343 #define mmDCP1_GRPH_FLIP_CONTROL_BASE_IDX                                                              2
4344 #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE                                                              0x076c
4345 #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX                                                     2
4346 #define mmDCP1_GRPH_DFQ_CONTROL                                                                        0x076d
4347 #define mmDCP1_GRPH_DFQ_CONTROL_BASE_IDX                                                               2
4348 #define mmDCP1_GRPH_DFQ_STATUS                                                                         0x076e
4349 #define mmDCP1_GRPH_DFQ_STATUS_BASE_IDX                                                                2
4350 #define mmDCP1_GRPH_INTERRUPT_STATUS                                                                   0x076f
4351 #define mmDCP1_GRPH_INTERRUPT_STATUS_BASE_IDX                                                          2
4352 #define mmDCP1_GRPH_INTERRUPT_CONTROL                                                                  0x0770
4353 #define mmDCP1_GRPH_INTERRUPT_CONTROL_BASE_IDX                                                         2
4354 #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                                         0x0771
4355 #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX                                                2
4356 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS                                                           0x0772
4357 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX                                                  2
4358 #define mmDCP1_GRPH_COMPRESS_PITCH                                                                     0x0773
4359 #define mmDCP1_GRPH_COMPRESS_PITCH_BASE_IDX                                                            2
4360 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                                      0x0774
4361 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX                                             2
4362 #define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                                                     0x0775
4363 #define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX                                            2
4364 #define mmDCP1_PRESCALE_GRPH_CONTROL                                                                   0x0776
4365 #define mmDCP1_PRESCALE_GRPH_CONTROL_BASE_IDX                                                          2
4366 #define mmDCP1_PRESCALE_VALUES_GRPH_R                                                                  0x0777
4367 #define mmDCP1_PRESCALE_VALUES_GRPH_R_BASE_IDX                                                         2
4368 #define mmDCP1_PRESCALE_VALUES_GRPH_G                                                                  0x0778
4369 #define mmDCP1_PRESCALE_VALUES_GRPH_G_BASE_IDX                                                         2
4370 #define mmDCP1_PRESCALE_VALUES_GRPH_B                                                                  0x0779
4371 #define mmDCP1_PRESCALE_VALUES_GRPH_B_BASE_IDX                                                         2
4372 #define mmDCP1_INPUT_CSC_CONTROL                                                                       0x077a
4373 #define mmDCP1_INPUT_CSC_CONTROL_BASE_IDX                                                              2
4374 #define mmDCP1_INPUT_CSC_C11_C12                                                                       0x077b
4375 #define mmDCP1_INPUT_CSC_C11_C12_BASE_IDX                                                              2
4376 #define mmDCP1_INPUT_CSC_C13_C14                                                                       0x077c
4377 #define mmDCP1_INPUT_CSC_C13_C14_BASE_IDX                                                              2
4378 #define mmDCP1_INPUT_CSC_C21_C22                                                                       0x077d
4379 #define mmDCP1_INPUT_CSC_C21_C22_BASE_IDX                                                              2
4380 #define mmDCP1_INPUT_CSC_C23_C24                                                                       0x077e
4381 #define mmDCP1_INPUT_CSC_C23_C24_BASE_IDX                                                              2
4382 #define mmDCP1_INPUT_CSC_C31_C32                                                                       0x077f
4383 #define mmDCP1_INPUT_CSC_C31_C32_BASE_IDX                                                              2
4384 #define mmDCP1_INPUT_CSC_C33_C34                                                                       0x0780
4385 #define mmDCP1_INPUT_CSC_C33_C34_BASE_IDX                                                              2
4386 #define mmDCP1_OUTPUT_CSC_CONTROL                                                                      0x0781
4387 #define mmDCP1_OUTPUT_CSC_CONTROL_BASE_IDX                                                             2
4388 #define mmDCP1_OUTPUT_CSC_C11_C12                                                                      0x0782
4389 #define mmDCP1_OUTPUT_CSC_C11_C12_BASE_IDX                                                             2
4390 #define mmDCP1_OUTPUT_CSC_C13_C14                                                                      0x0783
4391 #define mmDCP1_OUTPUT_CSC_C13_C14_BASE_IDX                                                             2
4392 #define mmDCP1_OUTPUT_CSC_C21_C22                                                                      0x0784
4393 #define mmDCP1_OUTPUT_CSC_C21_C22_BASE_IDX                                                             2
4394 #define mmDCP1_OUTPUT_CSC_C23_C24                                                                      0x0785
4395 #define mmDCP1_OUTPUT_CSC_C23_C24_BASE_IDX                                                             2
4396 #define mmDCP1_OUTPUT_CSC_C31_C32                                                                      0x0786
4397 #define mmDCP1_OUTPUT_CSC_C31_C32_BASE_IDX                                                             2
4398 #define mmDCP1_OUTPUT_CSC_C33_C34                                                                      0x0787
4399 #define mmDCP1_OUTPUT_CSC_C33_C34_BASE_IDX                                                             2
4400 #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12                                                              0x0788
4401 #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX                                                     2
4402 #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14                                                              0x0789
4403 #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX                                                     2
4404 #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22                                                              0x078a
4405 #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX                                                     2
4406 #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24                                                              0x078b
4407 #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX                                                     2
4408 #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32                                                              0x078c
4409 #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX                                                     2
4410 #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34                                                              0x078d
4411 #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX                                                     2
4412 #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12                                                              0x078e
4413 #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX                                                     2
4414 #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14                                                              0x078f
4415 #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX                                                     2
4416 #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22                                                              0x0790
4417 #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX                                                     2
4418 #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24                                                              0x0791
4419 #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX                                                     2
4420 #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32                                                              0x0792
4421 #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX                                                     2
4422 #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34                                                              0x0793
4423 #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX                                                     2
4424 #define mmDCP1_DENORM_CONTROL                                                                          0x0794
4425 #define mmDCP1_DENORM_CONTROL_BASE_IDX                                                                 2
4426 #define mmDCP1_OUT_ROUND_CONTROL                                                                       0x0795
4427 #define mmDCP1_OUT_ROUND_CONTROL_BASE_IDX                                                              2
4428 #define mmDCP1_OUT_CLAMP_CONTROL_R_CR                                                                  0x0796
4429 #define mmDCP1_OUT_CLAMP_CONTROL_R_CR_BASE_IDX                                                         2
4430 #define mmDCP1_OUT_CLAMP_CONTROL_G_Y                                                                   0x0797
4431 #define mmDCP1_OUT_CLAMP_CONTROL_G_Y_BASE_IDX                                                          2
4432 #define mmDCP1_OUT_CLAMP_CONTROL_B_CB                                                                  0x0798
4433 #define mmDCP1_OUT_CLAMP_CONTROL_B_CB_BASE_IDX                                                         2
4434 #define mmDCP1_KEY_CONTROL                                                                             0x0799
4435 #define mmDCP1_KEY_CONTROL_BASE_IDX                                                                    2
4436 #define mmDCP1_KEY_RANGE_ALPHA                                                                         0x079a
4437 #define mmDCP1_KEY_RANGE_ALPHA_BASE_IDX                                                                2
4438 #define mmDCP1_KEY_RANGE_RED                                                                           0x079b
4439 #define mmDCP1_KEY_RANGE_RED_BASE_IDX                                                                  2
4440 #define mmDCP1_KEY_RANGE_GREEN                                                                         0x079c
4441 #define mmDCP1_KEY_RANGE_GREEN_BASE_IDX                                                                2
4442 #define mmDCP1_KEY_RANGE_BLUE                                                                          0x079d
4443 #define mmDCP1_KEY_RANGE_BLUE_BASE_IDX                                                                 2
4444 #define mmDCP1_DEGAMMA_CONTROL                                                                         0x079e
4445 #define mmDCP1_DEGAMMA_CONTROL_BASE_IDX                                                                2
4446 #define mmDCP1_GAMUT_REMAP_CONTROL                                                                     0x079f
4447 #define mmDCP1_GAMUT_REMAP_CONTROL_BASE_IDX                                                            2
4448 #define mmDCP1_GAMUT_REMAP_C11_C12                                                                     0x07a0
4449 #define mmDCP1_GAMUT_REMAP_C11_C12_BASE_IDX                                                            2
4450 #define mmDCP1_GAMUT_REMAP_C13_C14                                                                     0x07a1
4451 #define mmDCP1_GAMUT_REMAP_C13_C14_BASE_IDX                                                            2
4452 #define mmDCP1_GAMUT_REMAP_C21_C22                                                                     0x07a2
4453 #define mmDCP1_GAMUT_REMAP_C21_C22_BASE_IDX                                                            2
4454 #define mmDCP1_GAMUT_REMAP_C23_C24                                                                     0x07a3
4455 #define mmDCP1_GAMUT_REMAP_C23_C24_BASE_IDX                                                            2
4456 #define mmDCP1_GAMUT_REMAP_C31_C32                                                                     0x07a4
4457 #define mmDCP1_GAMUT_REMAP_C31_C32_BASE_IDX                                                            2
4458 #define mmDCP1_GAMUT_REMAP_C33_C34                                                                     0x07a5
4459 #define mmDCP1_GAMUT_REMAP_C33_C34_BASE_IDX                                                            2
4460 #define mmDCP1_DCP_SPATIAL_DITHER_CNTL                                                                 0x07a6
4461 #define mmDCP1_DCP_SPATIAL_DITHER_CNTL_BASE_IDX                                                        2
4462 #define mmDCP1_DCP_RANDOM_SEEDS                                                                        0x07a7
4463 #define mmDCP1_DCP_RANDOM_SEEDS_BASE_IDX                                                               2
4464 #define mmDCP1_DCP_FP_CONVERTED_FIELD                                                                  0x07a8
4465 #define mmDCP1_DCP_FP_CONVERTED_FIELD_BASE_IDX                                                         2
4466 #define mmDCP1_CUR_CONTROL                                                                             0x07a9
4467 #define mmDCP1_CUR_CONTROL_BASE_IDX                                                                    2
4468 #define mmDCP1_CUR_SURFACE_ADDRESS                                                                     0x07aa
4469 #define mmDCP1_CUR_SURFACE_ADDRESS_BASE_IDX                                                            2
4470 #define mmDCP1_CUR_SIZE                                                                                0x07ab
4471 #define mmDCP1_CUR_SIZE_BASE_IDX                                                                       2
4472 #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH                                                                0x07ac
4473 #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX                                                       2
4474 #define mmDCP1_CUR_POSITION                                                                            0x07ad
4475 #define mmDCP1_CUR_POSITION_BASE_IDX                                                                   2
4476 #define mmDCP1_CUR_HOT_SPOT                                                                            0x07ae
4477 #define mmDCP1_CUR_HOT_SPOT_BASE_IDX                                                                   2
4478 #define mmDCP1_CUR_COLOR1                                                                              0x07af
4479 #define mmDCP1_CUR_COLOR1_BASE_IDX                                                                     2
4480 #define mmDCP1_CUR_COLOR2                                                                              0x07b0
4481 #define mmDCP1_CUR_COLOR2_BASE_IDX                                                                     2
4482 #define mmDCP1_CUR_UPDATE                                                                              0x07b1
4483 #define mmDCP1_CUR_UPDATE_BASE_IDX                                                                     2
4484 #define mmDCP1_CUR_REQUEST_FILTER_CNTL                                                                 0x07bb
4485 #define mmDCP1_CUR_REQUEST_FILTER_CNTL_BASE_IDX                                                        2
4486 #define mmDCP1_CUR_STEREO_CONTROL                                                                      0x07bc
4487 #define mmDCP1_CUR_STEREO_CONTROL_BASE_IDX                                                             2
4488 #define mmDCP1_DC_LUT_RW_MODE                                                                          0x07be
4489 #define mmDCP1_DC_LUT_RW_MODE_BASE_IDX                                                                 2
4490 #define mmDCP1_DC_LUT_RW_INDEX                                                                         0x07bf
4491 #define mmDCP1_DC_LUT_RW_INDEX_BASE_IDX                                                                2
4492 #define mmDCP1_DC_LUT_SEQ_COLOR                                                                        0x07c0
4493 #define mmDCP1_DC_LUT_SEQ_COLOR_BASE_IDX                                                               2
4494 #define mmDCP1_DC_LUT_PWL_DATA                                                                         0x07c1
4495 #define mmDCP1_DC_LUT_PWL_DATA_BASE_IDX                                                                2
4496 #define mmDCP1_DC_LUT_30_COLOR                                                                         0x07c2
4497 #define mmDCP1_DC_LUT_30_COLOR_BASE_IDX                                                                2
4498 #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE                                                                0x07c3
4499 #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX                                                       2
4500 #define mmDCP1_DC_LUT_WRITE_EN_MASK                                                                    0x07c4
4501 #define mmDCP1_DC_LUT_WRITE_EN_MASK_BASE_IDX                                                           2
4502 #define mmDCP1_DC_LUT_AUTOFILL                                                                         0x07c5
4503 #define mmDCP1_DC_LUT_AUTOFILL_BASE_IDX                                                                2
4504 #define mmDCP1_DC_LUT_CONTROL                                                                          0x07c6
4505 #define mmDCP1_DC_LUT_CONTROL_BASE_IDX                                                                 2
4506 #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE                                                                0x07c7
4507 #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX                                                       2
4508 #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN                                                               0x07c8
4509 #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX                                                      2
4510 #define mmDCP1_DC_LUT_BLACK_OFFSET_RED                                                                 0x07c9
4511 #define mmDCP1_DC_LUT_BLACK_OFFSET_RED_BASE_IDX                                                        2
4512 #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE                                                                0x07ca
4513 #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX                                                       2
4514 #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN                                                               0x07cb
4515 #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX                                                      2
4516 #define mmDCP1_DC_LUT_WHITE_OFFSET_RED                                                                 0x07cc
4517 #define mmDCP1_DC_LUT_WHITE_OFFSET_RED_BASE_IDX                                                        2
4518 #define mmDCP1_DCP_CRC_CONTROL                                                                         0x07cd
4519 #define mmDCP1_DCP_CRC_CONTROL_BASE_IDX                                                                2
4520 #define mmDCP1_DCP_CRC_MASK                                                                            0x07ce
4521 #define mmDCP1_DCP_CRC_MASK_BASE_IDX                                                                   2
4522 #define mmDCP1_DCP_CRC_CURRENT                                                                         0x07cf
4523 #define mmDCP1_DCP_CRC_CURRENT_BASE_IDX                                                                2
4524 #define mmDCP1_DVMM_PTE_CONTROL                                                                        0x07d0
4525 #define mmDCP1_DVMM_PTE_CONTROL_BASE_IDX                                                               2
4526 #define mmDCP1_DCP_CRC_LAST                                                                            0x07d1
4527 #define mmDCP1_DCP_CRC_LAST_BASE_IDX                                                                   2
4528 #define mmDCP1_DVMM_PTE_ARB_CONTROL                                                                    0x07d2
4529 #define mmDCP1_DVMM_PTE_ARB_CONTROL_BASE_IDX                                                           2
4530 #define mmDCP1_GRPH_FLIP_RATE_CNTL                                                                     0x07d4
4531 #define mmDCP1_GRPH_FLIP_RATE_CNTL_BASE_IDX                                                            2
4532 #define mmDCP1_DCP_GSL_CONTROL                                                                         0x07d5
4533 #define mmDCP1_DCP_GSL_CONTROL_BASE_IDX                                                                2
4534 #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                                           0x07d6
4535 #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX                                                  2
4536 #define mmDCP1_GRPH_STEREOSYNC_FLIP                                                                    0x07dc
4537 #define mmDCP1_GRPH_STEREOSYNC_FLIP_BASE_IDX                                                           2
4538 #define mmDCP1_HW_ROTATION                                                                             0x07de
4539 #define mmDCP1_HW_ROTATION_BASE_IDX                                                                    2
4540 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                                      0x07df
4541 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX                                             2
4542 #define mmDCP1_REGAMMA_CONTROL                                                                         0x07e0
4543 #define mmDCP1_REGAMMA_CONTROL_BASE_IDX                                                                2
4544 #define mmDCP1_REGAMMA_LUT_INDEX                                                                       0x07e1
4545 #define mmDCP1_REGAMMA_LUT_INDEX_BASE_IDX                                                              2
4546 #define mmDCP1_REGAMMA_LUT_DATA                                                                        0x07e2
4547 #define mmDCP1_REGAMMA_LUT_DATA_BASE_IDX                                                               2
4548 #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK                                                               0x07e3
4549 #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX                                                      2
4550 #define mmDCP1_REGAMMA_CNTLA_START_CNTL                                                                0x07e4
4551 #define mmDCP1_REGAMMA_CNTLA_START_CNTL_BASE_IDX                                                       2
4552 #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL                                                                0x07e5
4553 #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX                                                       2
4554 #define mmDCP1_REGAMMA_CNTLA_END_CNTL1                                                                 0x07e6
4555 #define mmDCP1_REGAMMA_CNTLA_END_CNTL1_BASE_IDX                                                        2
4556 #define mmDCP1_REGAMMA_CNTLA_END_CNTL2                                                                 0x07e7
4557 #define mmDCP1_REGAMMA_CNTLA_END_CNTL2_BASE_IDX                                                        2
4558 #define mmDCP1_REGAMMA_CNTLA_REGION_0_1                                                                0x07e8
4559 #define mmDCP1_REGAMMA_CNTLA_REGION_0_1_BASE_IDX                                                       2
4560 #define mmDCP1_REGAMMA_CNTLA_REGION_2_3                                                                0x07e9
4561 #define mmDCP1_REGAMMA_CNTLA_REGION_2_3_BASE_IDX                                                       2
4562 #define mmDCP1_REGAMMA_CNTLA_REGION_4_5                                                                0x07ea
4563 #define mmDCP1_REGAMMA_CNTLA_REGION_4_5_BASE_IDX                                                       2
4564 #define mmDCP1_REGAMMA_CNTLA_REGION_6_7                                                                0x07eb
4565 #define mmDCP1_REGAMMA_CNTLA_REGION_6_7_BASE_IDX                                                       2
4566 #define mmDCP1_REGAMMA_CNTLA_REGION_8_9                                                                0x07ec
4567 #define mmDCP1_REGAMMA_CNTLA_REGION_8_9_BASE_IDX                                                       2
4568 #define mmDCP1_REGAMMA_CNTLA_REGION_10_11                                                              0x07ed
4569 #define mmDCP1_REGAMMA_CNTLA_REGION_10_11_BASE_IDX                                                     2
4570 #define mmDCP1_REGAMMA_CNTLA_REGION_12_13                                                              0x07ee
4571 #define mmDCP1_REGAMMA_CNTLA_REGION_12_13_BASE_IDX                                                     2
4572 #define mmDCP1_REGAMMA_CNTLA_REGION_14_15                                                              0x07ef
4573 #define mmDCP1_REGAMMA_CNTLA_REGION_14_15_BASE_IDX                                                     2
4574 #define mmDCP1_REGAMMA_CNTLB_START_CNTL                                                                0x07f0
4575 #define mmDCP1_REGAMMA_CNTLB_START_CNTL_BASE_IDX                                                       2
4576 #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL                                                                0x07f1
4577 #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX                                                       2
4578 #define mmDCP1_REGAMMA_CNTLB_END_CNTL1                                                                 0x07f2
4579 #define mmDCP1_REGAMMA_CNTLB_END_CNTL1_BASE_IDX                                                        2
4580 #define mmDCP1_REGAMMA_CNTLB_END_CNTL2                                                                 0x07f3
4581 #define mmDCP1_REGAMMA_CNTLB_END_CNTL2_BASE_IDX                                                        2
4582 #define mmDCP1_REGAMMA_CNTLB_REGION_0_1                                                                0x07f4
4583 #define mmDCP1_REGAMMA_CNTLB_REGION_0_1_BASE_IDX                                                       2
4584 #define mmDCP1_REGAMMA_CNTLB_REGION_2_3                                                                0x07f5
4585 #define mmDCP1_REGAMMA_CNTLB_REGION_2_3_BASE_IDX                                                       2
4586 #define mmDCP1_REGAMMA_CNTLB_REGION_4_5                                                                0x07f6
4587 #define mmDCP1_REGAMMA_CNTLB_REGION_4_5_BASE_IDX                                                       2
4588 #define mmDCP1_REGAMMA_CNTLB_REGION_6_7                                                                0x07f7
4589 #define mmDCP1_REGAMMA_CNTLB_REGION_6_7_BASE_IDX                                                       2
4590 #define mmDCP1_REGAMMA_CNTLB_REGION_8_9                                                                0x07f8
4591 #define mmDCP1_REGAMMA_CNTLB_REGION_8_9_BASE_IDX                                                       2
4592 #define mmDCP1_REGAMMA_CNTLB_REGION_10_11                                                              0x07f9
4593 #define mmDCP1_REGAMMA_CNTLB_REGION_10_11_BASE_IDX                                                     2
4594 #define mmDCP1_REGAMMA_CNTLB_REGION_12_13                                                              0x07fa
4595 #define mmDCP1_REGAMMA_CNTLB_REGION_12_13_BASE_IDX                                                     2
4596 #define mmDCP1_REGAMMA_CNTLB_REGION_14_15                                                              0x07fb
4597 #define mmDCP1_REGAMMA_CNTLB_REGION_14_15_BASE_IDX                                                     2
4598 #define mmDCP1_ALPHA_CONTROL                                                                           0x07fc
4599 #define mmDCP1_ALPHA_CONTROL_BASE_IDX                                                                  2
4600 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                                      0x07fd
4601 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX                                             2
4602 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                                                 0x07fe
4603 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
4604 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                                    0x07ff
4605 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX                                           2
4606 #define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT                                                                  0x0800
4607 #define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX                                                         2
4608 #define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY                                                                0x0801
4609 #define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX                                                       2
4610 #define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL                                                            0x0802
4611 #define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX                                                   2
4612 #define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT                                                             0x0803
4613 #define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX                                                    2
4614 
4615 
4616 // addressBlock: dce_dc_lb1_dispdec
4617 // base address: 0x800
4618 #define mmLB1_LB_DATA_FORMAT                                                                           0x081a
4619 #define mmLB1_LB_DATA_FORMAT_BASE_IDX                                                                  2
4620 #define mmLB1_LB_MEMORY_CTRL                                                                           0x081b
4621 #define mmLB1_LB_MEMORY_CTRL_BASE_IDX                                                                  2
4622 #define mmLB1_LB_MEMORY_SIZE_STATUS                                                                    0x081c
4623 #define mmLB1_LB_MEMORY_SIZE_STATUS_BASE_IDX                                                           2
4624 #define mmLB1_LB_DESKTOP_HEIGHT                                                                        0x081d
4625 #define mmLB1_LB_DESKTOP_HEIGHT_BASE_IDX                                                               2
4626 #define mmLB1_LB_VLINE_START_END                                                                       0x081e
4627 #define mmLB1_LB_VLINE_START_END_BASE_IDX                                                              2
4628 #define mmLB1_LB_VLINE2_START_END                                                                      0x081f
4629 #define mmLB1_LB_VLINE2_START_END_BASE_IDX                                                             2
4630 #define mmLB1_LB_V_COUNTER                                                                             0x0820
4631 #define mmLB1_LB_V_COUNTER_BASE_IDX                                                                    2
4632 #define mmLB1_LB_SNAPSHOT_V_COUNTER                                                                    0x0821
4633 #define mmLB1_LB_SNAPSHOT_V_COUNTER_BASE_IDX                                                           2
4634 #define mmLB1_LB_INTERRUPT_MASK                                                                        0x0822
4635 #define mmLB1_LB_INTERRUPT_MASK_BASE_IDX                                                               2
4636 #define mmLB1_LB_VLINE_STATUS                                                                          0x0823
4637 #define mmLB1_LB_VLINE_STATUS_BASE_IDX                                                                 2
4638 #define mmLB1_LB_VLINE2_STATUS                                                                         0x0824
4639 #define mmLB1_LB_VLINE2_STATUS_BASE_IDX                                                                2
4640 #define mmLB1_LB_VBLANK_STATUS                                                                         0x0825
4641 #define mmLB1_LB_VBLANK_STATUS_BASE_IDX                                                                2
4642 #define mmLB1_LB_SYNC_RESET_SEL                                                                        0x0826
4643 #define mmLB1_LB_SYNC_RESET_SEL_BASE_IDX                                                               2
4644 #define mmLB1_LB_BLACK_KEYER_R_CR                                                                      0x0827
4645 #define mmLB1_LB_BLACK_KEYER_R_CR_BASE_IDX                                                             2
4646 #define mmLB1_LB_BLACK_KEYER_G_Y                                                                       0x0828
4647 #define mmLB1_LB_BLACK_KEYER_G_Y_BASE_IDX                                                              2
4648 #define mmLB1_LB_BLACK_KEYER_B_CB                                                                      0x0829
4649 #define mmLB1_LB_BLACK_KEYER_B_CB_BASE_IDX                                                             2
4650 #define mmLB1_LB_KEYER_COLOR_CTRL                                                                      0x082a
4651 #define mmLB1_LB_KEYER_COLOR_CTRL_BASE_IDX                                                             2
4652 #define mmLB1_LB_KEYER_COLOR_R_CR                                                                      0x082b
4653 #define mmLB1_LB_KEYER_COLOR_R_CR_BASE_IDX                                                             2
4654 #define mmLB1_LB_KEYER_COLOR_G_Y                                                                       0x082c
4655 #define mmLB1_LB_KEYER_COLOR_G_Y_BASE_IDX                                                              2
4656 #define mmLB1_LB_KEYER_COLOR_B_CB                                                                      0x082d
4657 #define mmLB1_LB_KEYER_COLOR_B_CB_BASE_IDX                                                             2
4658 #define mmLB1_LB_KEYER_COLOR_REP_R_CR                                                                  0x082e
4659 #define mmLB1_LB_KEYER_COLOR_REP_R_CR_BASE_IDX                                                         2
4660 #define mmLB1_LB_KEYER_COLOR_REP_G_Y                                                                   0x082f
4661 #define mmLB1_LB_KEYER_COLOR_REP_G_Y_BASE_IDX                                                          2
4662 #define mmLB1_LB_KEYER_COLOR_REP_B_CB                                                                  0x0830
4663 #define mmLB1_LB_KEYER_COLOR_REP_B_CB_BASE_IDX                                                         2
4664 #define mmLB1_LB_BUFFER_LEVEL_STATUS                                                                   0x0831
4665 #define mmLB1_LB_BUFFER_LEVEL_STATUS_BASE_IDX                                                          2
4666 #define mmLB1_LB_BUFFER_URGENCY_CTRL                                                                   0x0832
4667 #define mmLB1_LB_BUFFER_URGENCY_CTRL_BASE_IDX                                                          2
4668 #define mmLB1_LB_BUFFER_URGENCY_STATUS                                                                 0x0833
4669 #define mmLB1_LB_BUFFER_URGENCY_STATUS_BASE_IDX                                                        2
4670 #define mmLB1_LB_BUFFER_STATUS                                                                         0x0834
4671 #define mmLB1_LB_BUFFER_STATUS_BASE_IDX                                                                2
4672 #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS                                                             0x0835
4673 #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX                                                    2
4674 #define mmLB1_MVP_AFR_FLIP_MODE                                                                        0x0836
4675 #define mmLB1_MVP_AFR_FLIP_MODE_BASE_IDX                                                               2
4676 #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL                                                                   0x0837
4677 #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX                                                          2
4678 #define mmLB1_MVP_FLIP_LINE_NUM_INSERT                                                                 0x0838
4679 #define mmLB1_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX                                                        2
4680 #define mmLB1_DC_MVP_LB_CONTROL                                                                        0x0839
4681 #define mmLB1_DC_MVP_LB_CONTROL_BASE_IDX                                                               2
4682 
4683 
4684 // addressBlock: dce_dc_dcfe1_dispdec
4685 // base address: 0x800
4686 #define mmDCFE1_DCFE_CLOCK_CONTROL                                                                     0x085a
4687 #define mmDCFE1_DCFE_CLOCK_CONTROL_BASE_IDX                                                            2
4688 #define mmDCFE1_DCFE_SOFT_RESET                                                                        0x085b
4689 #define mmDCFE1_DCFE_SOFT_RESET_BASE_IDX                                                               2
4690 #define mmDCFE1_DCFE_MEM_PWR_CTRL                                                                      0x085d
4691 #define mmDCFE1_DCFE_MEM_PWR_CTRL_BASE_IDX                                                             2
4692 #define mmDCFE1_DCFE_MEM_PWR_CTRL2                                                                     0x085e
4693 #define mmDCFE1_DCFE_MEM_PWR_CTRL2_BASE_IDX                                                            2
4694 #define mmDCFE1_DCFE_MEM_PWR_STATUS                                                                    0x085f
4695 #define mmDCFE1_DCFE_MEM_PWR_STATUS_BASE_IDX                                                           2
4696 #define mmDCFE1_DCFE_MISC                                                                              0x0860
4697 #define mmDCFE1_DCFE_MISC_BASE_IDX                                                                     2
4698 #define mmDCFE1_DCFE_FLUSH                                                                             0x0861
4699 #define mmDCFE1_DCFE_FLUSH_BASE_IDX                                                                    2
4700 
4701 
4702 // addressBlock: dce_dc_dc_perfmon4_dispdec
4703 // base address: 0x2138
4704 #define mmDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x086e
4705 #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
4706 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x086f
4707 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
4708 #define mmDC_PERFMON4_PERFCOUNTER_STATE                                                                0x0870
4709 #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
4710 #define mmDC_PERFMON4_PERFMON_CNTL                                                                     0x0871
4711 #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
4712 #define mmDC_PERFMON4_PERFMON_CNTL2                                                                    0x0872
4713 #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
4714 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0873
4715 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
4716 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0874
4717 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
4718 #define mmDC_PERFMON4_PERFMON_HI                                                                       0x0875
4719 #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
4720 #define mmDC_PERFMON4_PERFMON_LOW                                                                      0x0876
4721 #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
4722 
4723 
4724 // addressBlock: dce_dc_dmif_pg1_dispdec
4725 // base address: 0x800
4726 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1                                                       0x087a
4727 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                              2
4728 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2                                                       0x087b
4729 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                              2
4730 #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL                                                          0x087c
4731 #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_BASE_IDX                                                 2
4732 #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL                                                            0x087d
4733 #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_BASE_IDX                                                   2
4734 #define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL                                                       0x087e
4735 #define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX                                              2
4736 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL                                                            0x087f
4737 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_BASE_IDX                                                   2
4738 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2                                                           0x0880
4739 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX                                                  2
4740 #define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL                                                          0x0881
4741 #define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX                                                 2
4742 #define mmDMIF_PG1_DPG_REPEATER_PROGRAM                                                                0x0882
4743 #define mmDMIF_PG1_DPG_REPEATER_PROGRAM_BASE_IDX                                                       2
4744 #define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL                                                               0x0886
4745 #define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_BASE_IDX                                                      2
4746 #define mmDMIF_PG1_DPG_DVMM_STATUS                                                                     0x0887
4747 #define mmDMIF_PG1_DPG_DVMM_STATUS_BASE_IDX                                                            2
4748 
4749 
4750 // addressBlock: dce_dc_scl1_dispdec
4751 // base address: 0x800
4752 #define mmSCL1_SCL_COEF_RAM_SELECT                                                                     0x089a
4753 #define mmSCL1_SCL_COEF_RAM_SELECT_BASE_IDX                                                            2
4754 #define mmSCL1_SCL_COEF_RAM_TAP_DATA                                                                   0x089b
4755 #define mmSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                          2
4756 #define mmSCL1_SCL_MODE                                                                                0x089c
4757 #define mmSCL1_SCL_MODE_BASE_IDX                                                                       2
4758 #define mmSCL1_SCL_TAP_CONTROL                                                                         0x089d
4759 #define mmSCL1_SCL_TAP_CONTROL_BASE_IDX                                                                2
4760 #define mmSCL1_SCL_CONTROL                                                                             0x089e
4761 #define mmSCL1_SCL_CONTROL_BASE_IDX                                                                    2
4762 #define mmSCL1_SCL_BYPASS_CONTROL                                                                      0x089f
4763 #define mmSCL1_SCL_BYPASS_CONTROL_BASE_IDX                                                             2
4764 #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                            0x08a0
4765 #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                   2
4766 #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL                                                              0x08a1
4767 #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX                                                     2
4768 #define mmSCL1_SCL_HORZ_FILTER_CONTROL                                                                 0x08a2
4769 #define mmSCL1_SCL_HORZ_FILTER_CONTROL_BASE_IDX                                                        2
4770 #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                             0x08a3
4771 #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                    2
4772 #define mmSCL1_SCL_HORZ_FILTER_INIT                                                                    0x08a4
4773 #define mmSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                           2
4774 #define mmSCL1_SCL_VERT_FILTER_CONTROL                                                                 0x08a5
4775 #define mmSCL1_SCL_VERT_FILTER_CONTROL_BASE_IDX                                                        2
4776 #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                             0x08a6
4777 #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                    2
4778 #define mmSCL1_SCL_VERT_FILTER_INIT                                                                    0x08a7
4779 #define mmSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                           2
4780 #define mmSCL1_SCL_VERT_FILTER_INIT_BOT                                                                0x08a8
4781 #define mmSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                       2
4782 #define mmSCL1_SCL_ROUND_OFFSET                                                                        0x08a9
4783 #define mmSCL1_SCL_ROUND_OFFSET_BASE_IDX                                                               2
4784 #define mmSCL1_SCL_UPDATE                                                                              0x08aa
4785 #define mmSCL1_SCL_UPDATE_BASE_IDX                                                                     2
4786 #define mmSCL1_SCL_F_SHARP_CONTROL                                                                     0x08ab
4787 #define mmSCL1_SCL_F_SHARP_CONTROL_BASE_IDX                                                            2
4788 #define mmSCL1_SCL_ALU_CONTROL                                                                         0x08ac
4789 #define mmSCL1_SCL_ALU_CONTROL_BASE_IDX                                                                2
4790 #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS                                                            0x08ad
4791 #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                   2
4792 #define mmSCL1_VIEWPORT_START_SECONDARY                                                                0x08ae
4793 #define mmSCL1_VIEWPORT_START_SECONDARY_BASE_IDX                                                       2
4794 #define mmSCL1_VIEWPORT_START                                                                          0x08af
4795 #define mmSCL1_VIEWPORT_START_BASE_IDX                                                                 2
4796 #define mmSCL1_VIEWPORT_SIZE                                                                           0x08b0
4797 #define mmSCL1_VIEWPORT_SIZE_BASE_IDX                                                                  2
4798 #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT                                                                 0x08b1
4799 #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                        2
4800 #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM                                                                 0x08b2
4801 #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                        2
4802 #define mmSCL1_SCL_MODE_CHANGE_DET1                                                                    0x08b3
4803 #define mmSCL1_SCL_MODE_CHANGE_DET1_BASE_IDX                                                           2
4804 #define mmSCL1_SCL_MODE_CHANGE_DET2                                                                    0x08b4
4805 #define mmSCL1_SCL_MODE_CHANGE_DET2_BASE_IDX                                                           2
4806 #define mmSCL1_SCL_MODE_CHANGE_DET3                                                                    0x08b5
4807 #define mmSCL1_SCL_MODE_CHANGE_DET3_BASE_IDX                                                           2
4808 #define mmSCL1_SCL_MODE_CHANGE_MASK                                                                    0x08b6
4809 #define mmSCL1_SCL_MODE_CHANGE_MASK_BASE_IDX                                                           2
4810 
4811 
4812 // addressBlock: dce_dc_blnd1_dispdec
4813 // base address: 0x800
4814 #define mmBLND1_BLND_CONTROL                                                                           0x08c7
4815 #define mmBLND1_BLND_CONTROL_BASE_IDX                                                                  2
4816 #define mmBLND1_BLND_SM_CONTROL2                                                                       0x08c8
4817 #define mmBLND1_BLND_SM_CONTROL2_BASE_IDX                                                              2
4818 #define mmBLND1_BLND_CONTROL2                                                                          0x08c9
4819 #define mmBLND1_BLND_CONTROL2_BASE_IDX                                                                 2
4820 #define mmBLND1_BLND_UPDATE                                                                            0x08ca
4821 #define mmBLND1_BLND_UPDATE_BASE_IDX                                                                   2
4822 #define mmBLND1_BLND_UNDERFLOW_INTERRUPT                                                               0x08cb
4823 #define mmBLND1_BLND_UNDERFLOW_INTERRUPT_BASE_IDX                                                      2
4824 #define mmBLND1_BLND_V_UPDATE_LOCK                                                                     0x08cc
4825 #define mmBLND1_BLND_V_UPDATE_LOCK_BASE_IDX                                                            2
4826 #define mmBLND1_BLND_REG_UPDATE_STATUS                                                                 0x08cd
4827 #define mmBLND1_BLND_REG_UPDATE_STATUS_BASE_IDX                                                        2
4828 
4829 
4830 // addressBlock: dce_dc_crtc1_dispdec
4831 // base address: 0x800
4832 #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM                                                                 0x08d2
4833 #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_BASE_IDX                                                        2
4834 #define mmCRTC1_CRTC_H_TOTAL                                                                           0x08d3
4835 #define mmCRTC1_CRTC_H_TOTAL_BASE_IDX                                                                  2
4836 #define mmCRTC1_CRTC_H_BLANK_START_END                                                                 0x08d4
4837 #define mmCRTC1_CRTC_H_BLANK_START_END_BASE_IDX                                                        2
4838 #define mmCRTC1_CRTC_H_SYNC_A                                                                          0x08d5
4839 #define mmCRTC1_CRTC_H_SYNC_A_BASE_IDX                                                                 2
4840 #define mmCRTC1_CRTC_H_SYNC_A_CNTL                                                                     0x08d6
4841 #define mmCRTC1_CRTC_H_SYNC_A_CNTL_BASE_IDX                                                            2
4842 #define mmCRTC1_CRTC_H_SYNC_B                                                                          0x08d7
4843 #define mmCRTC1_CRTC_H_SYNC_B_BASE_IDX                                                                 2
4844 #define mmCRTC1_CRTC_H_SYNC_B_CNTL                                                                     0x08d8
4845 #define mmCRTC1_CRTC_H_SYNC_B_CNTL_BASE_IDX                                                            2
4846 #define mmCRTC1_CRTC_VBI_END                                                                           0x08d9
4847 #define mmCRTC1_CRTC_VBI_END_BASE_IDX                                                                  2
4848 #define mmCRTC1_CRTC_V_TOTAL                                                                           0x08da
4849 #define mmCRTC1_CRTC_V_TOTAL_BASE_IDX                                                                  2
4850 #define mmCRTC1_CRTC_V_TOTAL_MIN                                                                       0x08db
4851 #define mmCRTC1_CRTC_V_TOTAL_MIN_BASE_IDX                                                              2
4852 #define mmCRTC1_CRTC_V_TOTAL_MAX                                                                       0x08dc
4853 #define mmCRTC1_CRTC_V_TOTAL_MAX_BASE_IDX                                                              2
4854 #define mmCRTC1_CRTC_V_TOTAL_CONTROL                                                                   0x08dd
4855 #define mmCRTC1_CRTC_V_TOTAL_CONTROL_BASE_IDX                                                          2
4856 #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS                                                                0x08de
4857 #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_BASE_IDX                                                       2
4858 #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS                                                              0x08df
4859 #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX                                                     2
4860 #define mmCRTC1_CRTC_V_BLANK_START_END                                                                 0x08e0
4861 #define mmCRTC1_CRTC_V_BLANK_START_END_BASE_IDX                                                        2
4862 #define mmCRTC1_CRTC_V_SYNC_A                                                                          0x08e1
4863 #define mmCRTC1_CRTC_V_SYNC_A_BASE_IDX                                                                 2
4864 #define mmCRTC1_CRTC_V_SYNC_A_CNTL                                                                     0x08e2
4865 #define mmCRTC1_CRTC_V_SYNC_A_CNTL_BASE_IDX                                                            2
4866 #define mmCRTC1_CRTC_V_SYNC_B                                                                          0x08e3
4867 #define mmCRTC1_CRTC_V_SYNC_B_BASE_IDX                                                                 2
4868 #define mmCRTC1_CRTC_V_SYNC_B_CNTL                                                                     0x08e4
4869 #define mmCRTC1_CRTC_V_SYNC_B_CNTL_BASE_IDX                                                            2
4870 #define mmCRTC1_CRTC_DTMTEST_CNTL                                                                      0x08e5
4871 #define mmCRTC1_CRTC_DTMTEST_CNTL_BASE_IDX                                                             2
4872 #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION                                                           0x08e6
4873 #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX                                                  2
4874 #define mmCRTC1_CRTC_TRIGA_CNTL                                                                        0x08e7
4875 #define mmCRTC1_CRTC_TRIGA_CNTL_BASE_IDX                                                               2
4876 #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG                                                                 0x08e8
4877 #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX                                                        2
4878 #define mmCRTC1_CRTC_TRIGB_CNTL                                                                        0x08e9
4879 #define mmCRTC1_CRTC_TRIGB_CNTL_BASE_IDX                                                               2
4880 #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG                                                                 0x08ea
4881 #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX                                                        2
4882 #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL                                                              0x08eb
4883 #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                     2
4884 #define mmCRTC1_CRTC_FLOW_CONTROL                                                                      0x08ec
4885 #define mmCRTC1_CRTC_FLOW_CONTROL_BASE_IDX                                                             2
4886 #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE                                                             0x08ed
4887 #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                    2
4888 #define mmCRTC1_CRTC_AVSYNC_COUNTER                                                                    0x08ee
4889 #define mmCRTC1_CRTC_AVSYNC_COUNTER_BASE_IDX                                                           2
4890 #define mmCRTC1_CRTC_CONTROL                                                                           0x08ef
4891 #define mmCRTC1_CRTC_CONTROL_BASE_IDX                                                                  2
4892 #define mmCRTC1_CRTC_BLANK_CONTROL                                                                     0x08f0
4893 #define mmCRTC1_CRTC_BLANK_CONTROL_BASE_IDX                                                            2
4894 #define mmCRTC1_CRTC_INTERLACE_CONTROL                                                                 0x08f1
4895 #define mmCRTC1_CRTC_INTERLACE_CONTROL_BASE_IDX                                                        2
4896 #define mmCRTC1_CRTC_INTERLACE_STATUS                                                                  0x08f2
4897 #define mmCRTC1_CRTC_INTERLACE_STATUS_BASE_IDX                                                         2
4898 #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL                                                          0x08f3
4899 #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX                                                 2
4900 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0                                                              0x08f4
4901 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_BASE_IDX                                                     2
4902 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1                                                              0x08f5
4903 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_BASE_IDX                                                     2
4904 #define mmCRTC1_CRTC_STATUS                                                                            0x08f6
4905 #define mmCRTC1_CRTC_STATUS_BASE_IDX                                                                   2
4906 #define mmCRTC1_CRTC_STATUS_POSITION                                                                   0x08f7
4907 #define mmCRTC1_CRTC_STATUS_POSITION_BASE_IDX                                                          2
4908 #define mmCRTC1_CRTC_NOM_VERT_POSITION                                                                 0x08f8
4909 #define mmCRTC1_CRTC_NOM_VERT_POSITION_BASE_IDX                                                        2
4910 #define mmCRTC1_CRTC_STATUS_FRAME_COUNT                                                                0x08f9
4911 #define mmCRTC1_CRTC_STATUS_FRAME_COUNT_BASE_IDX                                                       2
4912 #define mmCRTC1_CRTC_STATUS_VF_COUNT                                                                   0x08fa
4913 #define mmCRTC1_CRTC_STATUS_VF_COUNT_BASE_IDX                                                          2
4914 #define mmCRTC1_CRTC_STATUS_HV_COUNT                                                                   0x08fb
4915 #define mmCRTC1_CRTC_STATUS_HV_COUNT_BASE_IDX                                                          2
4916 #define mmCRTC1_CRTC_COUNT_CONTROL                                                                     0x08fc
4917 #define mmCRTC1_CRTC_COUNT_CONTROL_BASE_IDX                                                            2
4918 #define mmCRTC1_CRTC_COUNT_RESET                                                                       0x08fd
4919 #define mmCRTC1_CRTC_COUNT_RESET_BASE_IDX                                                              2
4920 #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                                      0x08fe
4921 #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                             2
4922 #define mmCRTC1_CRTC_VERT_SYNC_CONTROL                                                                 0x08ff
4923 #define mmCRTC1_CRTC_VERT_SYNC_CONTROL_BASE_IDX                                                        2
4924 #define mmCRTC1_CRTC_STEREO_STATUS                                                                     0x0900
4925 #define mmCRTC1_CRTC_STEREO_STATUS_BASE_IDX                                                            2
4926 #define mmCRTC1_CRTC_STEREO_CONTROL                                                                    0x0901
4927 #define mmCRTC1_CRTC_STEREO_CONTROL_BASE_IDX                                                           2
4928 #define mmCRTC1_CRTC_SNAPSHOT_STATUS                                                                   0x0902
4929 #define mmCRTC1_CRTC_SNAPSHOT_STATUS_BASE_IDX                                                          2
4930 #define mmCRTC1_CRTC_SNAPSHOT_CONTROL                                                                  0x0903
4931 #define mmCRTC1_CRTC_SNAPSHOT_CONTROL_BASE_IDX                                                         2
4932 #define mmCRTC1_CRTC_SNAPSHOT_POSITION                                                                 0x0904
4933 #define mmCRTC1_CRTC_SNAPSHOT_POSITION_BASE_IDX                                                        2
4934 #define mmCRTC1_CRTC_SNAPSHOT_FRAME                                                                    0x0905
4935 #define mmCRTC1_CRTC_SNAPSHOT_FRAME_BASE_IDX                                                           2
4936 #define mmCRTC1_CRTC_START_LINE_CONTROL                                                                0x0906
4937 #define mmCRTC1_CRTC_START_LINE_CONTROL_BASE_IDX                                                       2
4938 #define mmCRTC1_CRTC_INTERRUPT_CONTROL                                                                 0x0907
4939 #define mmCRTC1_CRTC_INTERRUPT_CONTROL_BASE_IDX                                                        2
4940 #define mmCRTC1_CRTC_UPDATE_LOCK                                                                       0x0908
4941 #define mmCRTC1_CRTC_UPDATE_LOCK_BASE_IDX                                                              2
4942 #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL                                                             0x0909
4943 #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                    2
4944 #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE                                                        0x090a
4945 #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX                                               2
4946 #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL                                                              0x090b
4947 #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_BASE_IDX                                                     2
4948 #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS                                                           0x090c
4949 #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX                                                  2
4950 #define mmCRTC1_CRTC_TEST_PATTERN_COLOR                                                                0x090d
4951 #define mmCRTC1_CRTC_TEST_PATTERN_COLOR_BASE_IDX                                                       2
4952 #define mmCRTC1_CRTC_MASTER_UPDATE_LOCK                                                                0x090e
4953 #define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_BASE_IDX                                                       2
4954 #define mmCRTC1_CRTC_MASTER_UPDATE_MODE                                                                0x090f
4955 #define mmCRTC1_CRTC_MASTER_UPDATE_MODE_BASE_IDX                                                       2
4956 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT                                                            0x0910
4957 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX                                                   2
4958 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                                                      0x0911
4959 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX                                             2
4960 #define mmCRTC1_CRTC_MVP_STATUS                                                                        0x0912
4961 #define mmCRTC1_CRTC_MVP_STATUS_BASE_IDX                                                               2
4962 #define mmCRTC1_CRTC_MASTER_EN                                                                         0x0913
4963 #define mmCRTC1_CRTC_MASTER_EN_BASE_IDX                                                                2
4964 #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT                                                              0x0914
4965 #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX                                                     2
4966 #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS                                                               0x0915
4967 #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_BASE_IDX                                                      2
4968 #define mmCRTC1_CRTC_OVERSCAN_COLOR                                                                    0x0917
4969 #define mmCRTC1_CRTC_OVERSCAN_COLOR_BASE_IDX                                                           2
4970 #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT                                                                0x0918
4971 #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX                                                       2
4972 #define mmCRTC1_CRTC_BLANK_DATA_COLOR                                                                  0x0919
4973 #define mmCRTC1_CRTC_BLANK_DATA_COLOR_BASE_IDX                                                         2
4974 #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT                                                              0x091a
4975 #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX                                                     2
4976 #define mmCRTC1_CRTC_BLACK_COLOR                                                                       0x091b
4977 #define mmCRTC1_CRTC_BLACK_COLOR_BASE_IDX                                                              2
4978 #define mmCRTC1_CRTC_BLACK_COLOR_EXT                                                                   0x091c
4979 #define mmCRTC1_CRTC_BLACK_COLOR_EXT_BASE_IDX                                                          2
4980 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION                                                      0x091d
4981 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                             2
4982 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL                                                       0x091e
4983 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                              2
4984 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION                                                      0x091f
4985 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                             2
4986 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL                                                       0x0920
4987 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                              2
4988 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION                                                      0x0921
4989 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                             2
4990 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL                                                       0x0922
4991 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                              2
4992 #define mmCRTC1_CRTC_CRC_CNTL                                                                          0x0923
4993 #define mmCRTC1_CRTC_CRC_CNTL_BASE_IDX                                                                 2
4994 #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL                                                            0x0924
4995 #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                   2
4996 #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL                                                            0x0925
4997 #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
4998 #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL                                                            0x0926
4999 #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                   2
5000 #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL                                                            0x0927
5001 #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
5002 #define mmCRTC1_CRTC_CRC0_DATA_RG                                                                      0x0928
5003 #define mmCRTC1_CRTC_CRC0_DATA_RG_BASE_IDX                                                             2
5004 #define mmCRTC1_CRTC_CRC0_DATA_B                                                                       0x0929
5005 #define mmCRTC1_CRTC_CRC0_DATA_B_BASE_IDX                                                              2
5006 #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL                                                            0x092a
5007 #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                   2
5008 #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL                                                            0x092b
5009 #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
5010 #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL                                                            0x092c
5011 #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                   2
5012 #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL                                                            0x092d
5013 #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
5014 #define mmCRTC1_CRTC_CRC1_DATA_RG                                                                      0x092e
5015 #define mmCRTC1_CRTC_CRC1_DATA_RG_BASE_IDX                                                             2
5016 #define mmCRTC1_CRTC_CRC1_DATA_B                                                                       0x092f
5017 #define mmCRTC1_CRTC_CRC1_DATA_B_BASE_IDX                                                              2
5018 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL                                                           0x0930
5019 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX                                                  2
5020 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START                                                      0x0931
5021 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX                                             2
5022 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END                                                        0x0932
5023 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX                                               2
5024 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                                            0x0933
5025 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX                                   2
5026 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                                 0x0934
5027 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX                                        2
5028 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                                          0x0935
5029 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX                                 2
5030 #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL                                                             0x0936
5031 #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX                                                    2
5032 #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL                                                              0x0937
5033 #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX                                                     2
5034 #define mmCRTC1_CRTC_GSL_VSYNC_GAP                                                                     0x0938
5035 #define mmCRTC1_CRTC_GSL_VSYNC_GAP_BASE_IDX                                                            2
5036 #define mmCRTC1_CRTC_GSL_WINDOW                                                                        0x0939
5037 #define mmCRTC1_CRTC_GSL_WINDOW_BASE_IDX                                                               2
5038 #define mmCRTC1_CRTC_GSL_CONTROL                                                                       0x093a
5039 #define mmCRTC1_CRTC_GSL_CONTROL_BASE_IDX                                                              2
5040 #define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS                                                           0x093d
5041 #define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX                                                  2
5042 #define mmCRTC1_CRTC_DRR_CONTROL                                                                       0x093e
5043 #define mmCRTC1_CRTC_DRR_CONTROL_BASE_IDX                                                              2
5044 
5045 
5046 // addressBlock: dce_dc_fmt1_dispdec
5047 // base address: 0x800
5048 #define mmFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x0942
5049 #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
5050 #define mmFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x0943
5051 #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
5052 #define mmFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x0944
5053 #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
5054 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x0945
5055 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
5056 #define mmFMT1_FMT_CONTROL                                                                             0x0946
5057 #define mmFMT1_FMT_CONTROL_BASE_IDX                                                                    2
5058 #define mmFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x0947
5059 #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
5060 #define mmFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x0948
5061 #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
5062 #define mmFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x0949
5063 #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
5064 #define mmFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x094a
5065 #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
5066 #define mmFMT1_FMT_CLAMP_CNTL                                                                          0x094e
5067 #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
5068 #define mmFMT1_FMT_CRC_CNTL                                                                            0x094f
5069 #define mmFMT1_FMT_CRC_CNTL_BASE_IDX                                                                   2
5070 #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK                                                              0x0950
5071 #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
5072 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK                                                           0x0951
5073 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
5074 #define mmFMT1_FMT_CRC_SIG_RED_GREEN                                                                   0x0952
5075 #define mmFMT1_FMT_CRC_SIG_RED_GREEN_BASE_IDX                                                          2
5076 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL                                                                0x0953
5077 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX                                                       2
5078 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x0954
5079 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
5080 #define mmFMT1_FMT_420_HBLANK_EARLY_START                                                              0x0955
5081 #define mmFMT1_FMT_420_HBLANK_EARLY_START_BASE_IDX                                                     2
5082 
5083 
5084 // addressBlock: dce_dc_dcp2_dispdec
5085 // base address: 0x1000
5086 #define mmDCP2_GRPH_ENABLE                                                                             0x095a
5087 #define mmDCP2_GRPH_ENABLE_BASE_IDX                                                                    2
5088 #define mmDCP2_GRPH_CONTROL                                                                            0x095b
5089 #define mmDCP2_GRPH_CONTROL_BASE_IDX                                                                   2
5090 #define mmDCP2_GRPH_LUT_10BIT_BYPASS                                                                   0x095c
5091 #define mmDCP2_GRPH_LUT_10BIT_BYPASS_BASE_IDX                                                          2
5092 #define mmDCP2_GRPH_SWAP_CNTL                                                                          0x095d
5093 #define mmDCP2_GRPH_SWAP_CNTL_BASE_IDX                                                                 2
5094 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS                                                            0x095e
5095 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                                   2
5096 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS                                                          0x095f
5097 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                                 2
5098 #define mmDCP2_GRPH_PITCH                                                                              0x0960
5099 #define mmDCP2_GRPH_PITCH_BASE_IDX                                                                     2
5100 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                                       0x0961
5101 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                              2
5102 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                                     0x0962
5103 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                            2
5104 #define mmDCP2_GRPH_SURFACE_OFFSET_X                                                                   0x0963
5105 #define mmDCP2_GRPH_SURFACE_OFFSET_X_BASE_IDX                                                          2
5106 #define mmDCP2_GRPH_SURFACE_OFFSET_Y                                                                   0x0964
5107 #define mmDCP2_GRPH_SURFACE_OFFSET_Y_BASE_IDX                                                          2
5108 #define mmDCP2_GRPH_X_START                                                                            0x0965
5109 #define mmDCP2_GRPH_X_START_BASE_IDX                                                                   2
5110 #define mmDCP2_GRPH_Y_START                                                                            0x0966
5111 #define mmDCP2_GRPH_Y_START_BASE_IDX                                                                   2
5112 #define mmDCP2_GRPH_X_END                                                                              0x0967
5113 #define mmDCP2_GRPH_X_END_BASE_IDX                                                                     2
5114 #define mmDCP2_GRPH_Y_END                                                                              0x0968
5115 #define mmDCP2_GRPH_Y_END_BASE_IDX                                                                     2
5116 #define mmDCP2_INPUT_GAMMA_CONTROL                                                                     0x0969
5117 #define mmDCP2_INPUT_GAMMA_CONTROL_BASE_IDX                                                            2
5118 #define mmDCP2_GRPH_UPDATE                                                                             0x096a
5119 #define mmDCP2_GRPH_UPDATE_BASE_IDX                                                                    2
5120 #define mmDCP2_GRPH_FLIP_CONTROL                                                                       0x096b
5121 #define mmDCP2_GRPH_FLIP_CONTROL_BASE_IDX                                                              2
5122 #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE                                                              0x096c
5123 #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX                                                     2
5124 #define mmDCP2_GRPH_DFQ_CONTROL                                                                        0x096d
5125 #define mmDCP2_GRPH_DFQ_CONTROL_BASE_IDX                                                               2
5126 #define mmDCP2_GRPH_DFQ_STATUS                                                                         0x096e
5127 #define mmDCP2_GRPH_DFQ_STATUS_BASE_IDX                                                                2
5128 #define mmDCP2_GRPH_INTERRUPT_STATUS                                                                   0x096f
5129 #define mmDCP2_GRPH_INTERRUPT_STATUS_BASE_IDX                                                          2
5130 #define mmDCP2_GRPH_INTERRUPT_CONTROL                                                                  0x0970
5131 #define mmDCP2_GRPH_INTERRUPT_CONTROL_BASE_IDX                                                         2
5132 #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                                         0x0971
5133 #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX                                                2
5134 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS                                                           0x0972
5135 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX                                                  2
5136 #define mmDCP2_GRPH_COMPRESS_PITCH                                                                     0x0973
5137 #define mmDCP2_GRPH_COMPRESS_PITCH_BASE_IDX                                                            2
5138 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                                      0x0974
5139 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX                                             2
5140 #define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                                                     0x0975
5141 #define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX                                            2
5142 #define mmDCP2_PRESCALE_GRPH_CONTROL                                                                   0x0976
5143 #define mmDCP2_PRESCALE_GRPH_CONTROL_BASE_IDX                                                          2
5144 #define mmDCP2_PRESCALE_VALUES_GRPH_R                                                                  0x0977
5145 #define mmDCP2_PRESCALE_VALUES_GRPH_R_BASE_IDX                                                         2
5146 #define mmDCP2_PRESCALE_VALUES_GRPH_G                                                                  0x0978
5147 #define mmDCP2_PRESCALE_VALUES_GRPH_G_BASE_IDX                                                         2
5148 #define mmDCP2_PRESCALE_VALUES_GRPH_B                                                                  0x0979
5149 #define mmDCP2_PRESCALE_VALUES_GRPH_B_BASE_IDX                                                         2
5150 #define mmDCP2_INPUT_CSC_CONTROL                                                                       0x097a
5151 #define mmDCP2_INPUT_CSC_CONTROL_BASE_IDX                                                              2
5152 #define mmDCP2_INPUT_CSC_C11_C12                                                                       0x097b
5153 #define mmDCP2_INPUT_CSC_C11_C12_BASE_IDX                                                              2
5154 #define mmDCP2_INPUT_CSC_C13_C14                                                                       0x097c
5155 #define mmDCP2_INPUT_CSC_C13_C14_BASE_IDX                                                              2
5156 #define mmDCP2_INPUT_CSC_C21_C22                                                                       0x097d
5157 #define mmDCP2_INPUT_CSC_C21_C22_BASE_IDX                                                              2
5158 #define mmDCP2_INPUT_CSC_C23_C24                                                                       0x097e
5159 #define mmDCP2_INPUT_CSC_C23_C24_BASE_IDX                                                              2
5160 #define mmDCP2_INPUT_CSC_C31_C32                                                                       0x097f
5161 #define mmDCP2_INPUT_CSC_C31_C32_BASE_IDX                                                              2
5162 #define mmDCP2_INPUT_CSC_C33_C34                                                                       0x0980
5163 #define mmDCP2_INPUT_CSC_C33_C34_BASE_IDX                                                              2
5164 #define mmDCP2_OUTPUT_CSC_CONTROL                                                                      0x0981
5165 #define mmDCP2_OUTPUT_CSC_CONTROL_BASE_IDX                                                             2
5166 #define mmDCP2_OUTPUT_CSC_C11_C12                                                                      0x0982
5167 #define mmDCP2_OUTPUT_CSC_C11_C12_BASE_IDX                                                             2
5168 #define mmDCP2_OUTPUT_CSC_C13_C14                                                                      0x0983
5169 #define mmDCP2_OUTPUT_CSC_C13_C14_BASE_IDX                                                             2
5170 #define mmDCP2_OUTPUT_CSC_C21_C22                                                                      0x0984
5171 #define mmDCP2_OUTPUT_CSC_C21_C22_BASE_IDX                                                             2
5172 #define mmDCP2_OUTPUT_CSC_C23_C24                                                                      0x0985
5173 #define mmDCP2_OUTPUT_CSC_C23_C24_BASE_IDX                                                             2
5174 #define mmDCP2_OUTPUT_CSC_C31_C32                                                                      0x0986
5175 #define mmDCP2_OUTPUT_CSC_C31_C32_BASE_IDX                                                             2
5176 #define mmDCP2_OUTPUT_CSC_C33_C34                                                                      0x0987
5177 #define mmDCP2_OUTPUT_CSC_C33_C34_BASE_IDX                                                             2
5178 #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12                                                              0x0988
5179 #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX                                                     2
5180 #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14                                                              0x0989
5181 #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX                                                     2
5182 #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22                                                              0x098a
5183 #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX                                                     2
5184 #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24                                                              0x098b
5185 #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX                                                     2
5186 #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32                                                              0x098c
5187 #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX                                                     2
5188 #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34                                                              0x098d
5189 #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX                                                     2
5190 #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12                                                              0x098e
5191 #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX                                                     2
5192 #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14                                                              0x098f
5193 #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX                                                     2
5194 #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22                                                              0x0990
5195 #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX                                                     2
5196 #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24                                                              0x0991
5197 #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX                                                     2
5198 #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32                                                              0x0992
5199 #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX                                                     2
5200 #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34                                                              0x0993
5201 #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX                                                     2
5202 #define mmDCP2_DENORM_CONTROL                                                                          0x0994
5203 #define mmDCP2_DENORM_CONTROL_BASE_IDX                                                                 2
5204 #define mmDCP2_OUT_ROUND_CONTROL                                                                       0x0995
5205 #define mmDCP2_OUT_ROUND_CONTROL_BASE_IDX                                                              2
5206 #define mmDCP2_OUT_CLAMP_CONTROL_R_CR                                                                  0x0996
5207 #define mmDCP2_OUT_CLAMP_CONTROL_R_CR_BASE_IDX                                                         2
5208 #define mmDCP2_OUT_CLAMP_CONTROL_G_Y                                                                   0x0997
5209 #define mmDCP2_OUT_CLAMP_CONTROL_G_Y_BASE_IDX                                                          2
5210 #define mmDCP2_OUT_CLAMP_CONTROL_B_CB                                                                  0x0998
5211 #define mmDCP2_OUT_CLAMP_CONTROL_B_CB_BASE_IDX                                                         2
5212 #define mmDCP2_KEY_CONTROL                                                                             0x0999
5213 #define mmDCP2_KEY_CONTROL_BASE_IDX                                                                    2
5214 #define mmDCP2_KEY_RANGE_ALPHA                                                                         0x099a
5215 #define mmDCP2_KEY_RANGE_ALPHA_BASE_IDX                                                                2
5216 #define mmDCP2_KEY_RANGE_RED                                                                           0x099b
5217 #define mmDCP2_KEY_RANGE_RED_BASE_IDX                                                                  2
5218 #define mmDCP2_KEY_RANGE_GREEN                                                                         0x099c
5219 #define mmDCP2_KEY_RANGE_GREEN_BASE_IDX                                                                2
5220 #define mmDCP2_KEY_RANGE_BLUE                                                                          0x099d
5221 #define mmDCP2_KEY_RANGE_BLUE_BASE_IDX                                                                 2
5222 #define mmDCP2_DEGAMMA_CONTROL                                                                         0x099e
5223 #define mmDCP2_DEGAMMA_CONTROL_BASE_IDX                                                                2
5224 #define mmDCP2_GAMUT_REMAP_CONTROL                                                                     0x099f
5225 #define mmDCP2_GAMUT_REMAP_CONTROL_BASE_IDX                                                            2
5226 #define mmDCP2_GAMUT_REMAP_C11_C12                                                                     0x09a0
5227 #define mmDCP2_GAMUT_REMAP_C11_C12_BASE_IDX                                                            2
5228 #define mmDCP2_GAMUT_REMAP_C13_C14                                                                     0x09a1
5229 #define mmDCP2_GAMUT_REMAP_C13_C14_BASE_IDX                                                            2
5230 #define mmDCP2_GAMUT_REMAP_C21_C22                                                                     0x09a2
5231 #define mmDCP2_GAMUT_REMAP_C21_C22_BASE_IDX                                                            2
5232 #define mmDCP2_GAMUT_REMAP_C23_C24                                                                     0x09a3
5233 #define mmDCP2_GAMUT_REMAP_C23_C24_BASE_IDX                                                            2
5234 #define mmDCP2_GAMUT_REMAP_C31_C32                                                                     0x09a4
5235 #define mmDCP2_GAMUT_REMAP_C31_C32_BASE_IDX                                                            2
5236 #define mmDCP2_GAMUT_REMAP_C33_C34                                                                     0x09a5
5237 #define mmDCP2_GAMUT_REMAP_C33_C34_BASE_IDX                                                            2
5238 #define mmDCP2_DCP_SPATIAL_DITHER_CNTL                                                                 0x09a6
5239 #define mmDCP2_DCP_SPATIAL_DITHER_CNTL_BASE_IDX                                                        2
5240 #define mmDCP2_DCP_RANDOM_SEEDS                                                                        0x09a7
5241 #define mmDCP2_DCP_RANDOM_SEEDS_BASE_IDX                                                               2
5242 #define mmDCP2_DCP_FP_CONVERTED_FIELD                                                                  0x09a8
5243 #define mmDCP2_DCP_FP_CONVERTED_FIELD_BASE_IDX                                                         2
5244 #define mmDCP2_CUR_CONTROL                                                                             0x09a9
5245 #define mmDCP2_CUR_CONTROL_BASE_IDX                                                                    2
5246 #define mmDCP2_CUR_SURFACE_ADDRESS                                                                     0x09aa
5247 #define mmDCP2_CUR_SURFACE_ADDRESS_BASE_IDX                                                            2
5248 #define mmDCP2_CUR_SIZE                                                                                0x09ab
5249 #define mmDCP2_CUR_SIZE_BASE_IDX                                                                       2
5250 #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH                                                                0x09ac
5251 #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX                                                       2
5252 #define mmDCP2_CUR_POSITION                                                                            0x09ad
5253 #define mmDCP2_CUR_POSITION_BASE_IDX                                                                   2
5254 #define mmDCP2_CUR_HOT_SPOT                                                                            0x09ae
5255 #define mmDCP2_CUR_HOT_SPOT_BASE_IDX                                                                   2
5256 #define mmDCP2_CUR_COLOR1                                                                              0x09af
5257 #define mmDCP2_CUR_COLOR1_BASE_IDX                                                                     2
5258 #define mmDCP2_CUR_COLOR2                                                                              0x09b0
5259 #define mmDCP2_CUR_COLOR2_BASE_IDX                                                                     2
5260 #define mmDCP2_CUR_UPDATE                                                                              0x09b1
5261 #define mmDCP2_CUR_UPDATE_BASE_IDX                                                                     2
5262 #define mmDCP2_CUR_REQUEST_FILTER_CNTL                                                                 0x09bb
5263 #define mmDCP2_CUR_REQUEST_FILTER_CNTL_BASE_IDX                                                        2
5264 #define mmDCP2_CUR_STEREO_CONTROL                                                                      0x09bc
5265 #define mmDCP2_CUR_STEREO_CONTROL_BASE_IDX                                                             2
5266 #define mmDCP2_DC_LUT_RW_MODE                                                                          0x09be
5267 #define mmDCP2_DC_LUT_RW_MODE_BASE_IDX                                                                 2
5268 #define mmDCP2_DC_LUT_RW_INDEX                                                                         0x09bf
5269 #define mmDCP2_DC_LUT_RW_INDEX_BASE_IDX                                                                2
5270 #define mmDCP2_DC_LUT_SEQ_COLOR                                                                        0x09c0
5271 #define mmDCP2_DC_LUT_SEQ_COLOR_BASE_IDX                                                               2
5272 #define mmDCP2_DC_LUT_PWL_DATA                                                                         0x09c1
5273 #define mmDCP2_DC_LUT_PWL_DATA_BASE_IDX                                                                2
5274 #define mmDCP2_DC_LUT_30_COLOR                                                                         0x09c2
5275 #define mmDCP2_DC_LUT_30_COLOR_BASE_IDX                                                                2
5276 #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE                                                                0x09c3
5277 #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX                                                       2
5278 #define mmDCP2_DC_LUT_WRITE_EN_MASK                                                                    0x09c4
5279 #define mmDCP2_DC_LUT_WRITE_EN_MASK_BASE_IDX                                                           2
5280 #define mmDCP2_DC_LUT_AUTOFILL                                                                         0x09c5
5281 #define mmDCP2_DC_LUT_AUTOFILL_BASE_IDX                                                                2
5282 #define mmDCP2_DC_LUT_CONTROL                                                                          0x09c6
5283 #define mmDCP2_DC_LUT_CONTROL_BASE_IDX                                                                 2
5284 #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE                                                                0x09c7
5285 #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX                                                       2
5286 #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN                                                               0x09c8
5287 #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX                                                      2
5288 #define mmDCP2_DC_LUT_BLACK_OFFSET_RED                                                                 0x09c9
5289 #define mmDCP2_DC_LUT_BLACK_OFFSET_RED_BASE_IDX                                                        2
5290 #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE                                                                0x09ca
5291 #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX                                                       2
5292 #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN                                                               0x09cb
5293 #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX                                                      2
5294 #define mmDCP2_DC_LUT_WHITE_OFFSET_RED                                                                 0x09cc
5295 #define mmDCP2_DC_LUT_WHITE_OFFSET_RED_BASE_IDX                                                        2
5296 #define mmDCP2_DCP_CRC_CONTROL                                                                         0x09cd
5297 #define mmDCP2_DCP_CRC_CONTROL_BASE_IDX                                                                2
5298 #define mmDCP2_DCP_CRC_MASK                                                                            0x09ce
5299 #define mmDCP2_DCP_CRC_MASK_BASE_IDX                                                                   2
5300 #define mmDCP2_DCP_CRC_CURRENT                                                                         0x09cf
5301 #define mmDCP2_DCP_CRC_CURRENT_BASE_IDX                                                                2
5302 #define mmDCP2_DVMM_PTE_CONTROL                                                                        0x09d0
5303 #define mmDCP2_DVMM_PTE_CONTROL_BASE_IDX                                                               2
5304 #define mmDCP2_DCP_CRC_LAST                                                                            0x09d1
5305 #define mmDCP2_DCP_CRC_LAST_BASE_IDX                                                                   2
5306 #define mmDCP2_DVMM_PTE_ARB_CONTROL                                                                    0x09d2
5307 #define mmDCP2_DVMM_PTE_ARB_CONTROL_BASE_IDX                                                           2
5308 #define mmDCP2_GRPH_FLIP_RATE_CNTL                                                                     0x09d4
5309 #define mmDCP2_GRPH_FLIP_RATE_CNTL_BASE_IDX                                                            2
5310 #define mmDCP2_DCP_GSL_CONTROL                                                                         0x09d5
5311 #define mmDCP2_DCP_GSL_CONTROL_BASE_IDX                                                                2
5312 #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                                           0x09d6
5313 #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX                                                  2
5314 #define mmDCP2_GRPH_STEREOSYNC_FLIP                                                                    0x09dc
5315 #define mmDCP2_GRPH_STEREOSYNC_FLIP_BASE_IDX                                                           2
5316 #define mmDCP2_HW_ROTATION                                                                             0x09de
5317 #define mmDCP2_HW_ROTATION_BASE_IDX                                                                    2
5318 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                                      0x09df
5319 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX                                             2
5320 #define mmDCP2_REGAMMA_CONTROL                                                                         0x09e0
5321 #define mmDCP2_REGAMMA_CONTROL_BASE_IDX                                                                2
5322 #define mmDCP2_REGAMMA_LUT_INDEX                                                                       0x09e1
5323 #define mmDCP2_REGAMMA_LUT_INDEX_BASE_IDX                                                              2
5324 #define mmDCP2_REGAMMA_LUT_DATA                                                                        0x09e2
5325 #define mmDCP2_REGAMMA_LUT_DATA_BASE_IDX                                                               2
5326 #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK                                                               0x09e3
5327 #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX                                                      2
5328 #define mmDCP2_REGAMMA_CNTLA_START_CNTL                                                                0x09e4
5329 #define mmDCP2_REGAMMA_CNTLA_START_CNTL_BASE_IDX                                                       2
5330 #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL                                                                0x09e5
5331 #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX                                                       2
5332 #define mmDCP2_REGAMMA_CNTLA_END_CNTL1                                                                 0x09e6
5333 #define mmDCP2_REGAMMA_CNTLA_END_CNTL1_BASE_IDX                                                        2
5334 #define mmDCP2_REGAMMA_CNTLA_END_CNTL2                                                                 0x09e7
5335 #define mmDCP2_REGAMMA_CNTLA_END_CNTL2_BASE_IDX                                                        2
5336 #define mmDCP2_REGAMMA_CNTLA_REGION_0_1                                                                0x09e8
5337 #define mmDCP2_REGAMMA_CNTLA_REGION_0_1_BASE_IDX                                                       2
5338 #define mmDCP2_REGAMMA_CNTLA_REGION_2_3                                                                0x09e9
5339 #define mmDCP2_REGAMMA_CNTLA_REGION_2_3_BASE_IDX                                                       2
5340 #define mmDCP2_REGAMMA_CNTLA_REGION_4_5                                                                0x09ea
5341 #define mmDCP2_REGAMMA_CNTLA_REGION_4_5_BASE_IDX                                                       2
5342 #define mmDCP2_REGAMMA_CNTLA_REGION_6_7                                                                0x09eb
5343 #define mmDCP2_REGAMMA_CNTLA_REGION_6_7_BASE_IDX                                                       2
5344 #define mmDCP2_REGAMMA_CNTLA_REGION_8_9                                                                0x09ec
5345 #define mmDCP2_REGAMMA_CNTLA_REGION_8_9_BASE_IDX                                                       2
5346 #define mmDCP2_REGAMMA_CNTLA_REGION_10_11                                                              0x09ed
5347 #define mmDCP2_REGAMMA_CNTLA_REGION_10_11_BASE_IDX                                                     2
5348 #define mmDCP2_REGAMMA_CNTLA_REGION_12_13                                                              0x09ee
5349 #define mmDCP2_REGAMMA_CNTLA_REGION_12_13_BASE_IDX                                                     2
5350 #define mmDCP2_REGAMMA_CNTLA_REGION_14_15                                                              0x09ef
5351 #define mmDCP2_REGAMMA_CNTLA_REGION_14_15_BASE_IDX                                                     2
5352 #define mmDCP2_REGAMMA_CNTLB_START_CNTL                                                                0x09f0
5353 #define mmDCP2_REGAMMA_CNTLB_START_CNTL_BASE_IDX                                                       2
5354 #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL                                                                0x09f1
5355 #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX                                                       2
5356 #define mmDCP2_REGAMMA_CNTLB_END_CNTL1                                                                 0x09f2
5357 #define mmDCP2_REGAMMA_CNTLB_END_CNTL1_BASE_IDX                                                        2
5358 #define mmDCP2_REGAMMA_CNTLB_END_CNTL2                                                                 0x09f3
5359 #define mmDCP2_REGAMMA_CNTLB_END_CNTL2_BASE_IDX                                                        2
5360 #define mmDCP2_REGAMMA_CNTLB_REGION_0_1                                                                0x09f4
5361 #define mmDCP2_REGAMMA_CNTLB_REGION_0_1_BASE_IDX                                                       2
5362 #define mmDCP2_REGAMMA_CNTLB_REGION_2_3                                                                0x09f5
5363 #define mmDCP2_REGAMMA_CNTLB_REGION_2_3_BASE_IDX                                                       2
5364 #define mmDCP2_REGAMMA_CNTLB_REGION_4_5                                                                0x09f6
5365 #define mmDCP2_REGAMMA_CNTLB_REGION_4_5_BASE_IDX                                                       2
5366 #define mmDCP2_REGAMMA_CNTLB_REGION_6_7                                                                0x09f7
5367 #define mmDCP2_REGAMMA_CNTLB_REGION_6_7_BASE_IDX                                                       2
5368 #define mmDCP2_REGAMMA_CNTLB_REGION_8_9                                                                0x09f8
5369 #define mmDCP2_REGAMMA_CNTLB_REGION_8_9_BASE_IDX                                                       2
5370 #define mmDCP2_REGAMMA_CNTLB_REGION_10_11                                                              0x09f9
5371 #define mmDCP2_REGAMMA_CNTLB_REGION_10_11_BASE_IDX                                                     2
5372 #define mmDCP2_REGAMMA_CNTLB_REGION_12_13                                                              0x09fa
5373 #define mmDCP2_REGAMMA_CNTLB_REGION_12_13_BASE_IDX                                                     2
5374 #define mmDCP2_REGAMMA_CNTLB_REGION_14_15                                                              0x09fb
5375 #define mmDCP2_REGAMMA_CNTLB_REGION_14_15_BASE_IDX                                                     2
5376 #define mmDCP2_ALPHA_CONTROL                                                                           0x09fc
5377 #define mmDCP2_ALPHA_CONTROL_BASE_IDX                                                                  2
5378 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                                      0x09fd
5379 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX                                             2
5380 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                                                 0x09fe
5381 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
5382 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                                    0x09ff
5383 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX                                           2
5384 #define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT                                                                  0x0a00
5385 #define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX                                                         2
5386 #define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY                                                                0x0a01
5387 #define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX                                                       2
5388 #define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL                                                            0x0a02
5389 #define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX                                                   2
5390 #define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT                                                             0x0a03
5391 #define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX                                                    2
5392 
5393 
5394 // addressBlock: dce_dc_lb2_dispdec
5395 // base address: 0x1000
5396 #define mmLB2_LB_DATA_FORMAT                                                                           0x0a1a
5397 #define mmLB2_LB_DATA_FORMAT_BASE_IDX                                                                  2
5398 #define mmLB2_LB_MEMORY_CTRL                                                                           0x0a1b
5399 #define mmLB2_LB_MEMORY_CTRL_BASE_IDX                                                                  2
5400 #define mmLB2_LB_MEMORY_SIZE_STATUS                                                                    0x0a1c
5401 #define mmLB2_LB_MEMORY_SIZE_STATUS_BASE_IDX                                                           2
5402 #define mmLB2_LB_DESKTOP_HEIGHT                                                                        0x0a1d
5403 #define mmLB2_LB_DESKTOP_HEIGHT_BASE_IDX                                                               2
5404 #define mmLB2_LB_VLINE_START_END                                                                       0x0a1e
5405 #define mmLB2_LB_VLINE_START_END_BASE_IDX                                                              2
5406 #define mmLB2_LB_VLINE2_START_END                                                                      0x0a1f
5407 #define mmLB2_LB_VLINE2_START_END_BASE_IDX                                                             2
5408 #define mmLB2_LB_V_COUNTER                                                                             0x0a20
5409 #define mmLB2_LB_V_COUNTER_BASE_IDX                                                                    2
5410 #define mmLB2_LB_SNAPSHOT_V_COUNTER                                                                    0x0a21
5411 #define mmLB2_LB_SNAPSHOT_V_COUNTER_BASE_IDX                                                           2
5412 #define mmLB2_LB_INTERRUPT_MASK                                                                        0x0a22
5413 #define mmLB2_LB_INTERRUPT_MASK_BASE_IDX                                                               2
5414 #define mmLB2_LB_VLINE_STATUS                                                                          0x0a23
5415 #define mmLB2_LB_VLINE_STATUS_BASE_IDX                                                                 2
5416 #define mmLB2_LB_VLINE2_STATUS                                                                         0x0a24
5417 #define mmLB2_LB_VLINE2_STATUS_BASE_IDX                                                                2
5418 #define mmLB2_LB_VBLANK_STATUS                                                                         0x0a25
5419 #define mmLB2_LB_VBLANK_STATUS_BASE_IDX                                                                2
5420 #define mmLB2_LB_SYNC_RESET_SEL                                                                        0x0a26
5421 #define mmLB2_LB_SYNC_RESET_SEL_BASE_IDX                                                               2
5422 #define mmLB2_LB_BLACK_KEYER_R_CR                                                                      0x0a27
5423 #define mmLB2_LB_BLACK_KEYER_R_CR_BASE_IDX                                                             2
5424 #define mmLB2_LB_BLACK_KEYER_G_Y                                                                       0x0a28
5425 #define mmLB2_LB_BLACK_KEYER_G_Y_BASE_IDX                                                              2
5426 #define mmLB2_LB_BLACK_KEYER_B_CB                                                                      0x0a29
5427 #define mmLB2_LB_BLACK_KEYER_B_CB_BASE_IDX                                                             2
5428 #define mmLB2_LB_KEYER_COLOR_CTRL                                                                      0x0a2a
5429 #define mmLB2_LB_KEYER_COLOR_CTRL_BASE_IDX                                                             2
5430 #define mmLB2_LB_KEYER_COLOR_R_CR                                                                      0x0a2b
5431 #define mmLB2_LB_KEYER_COLOR_R_CR_BASE_IDX                                                             2
5432 #define mmLB2_LB_KEYER_COLOR_G_Y                                                                       0x0a2c
5433 #define mmLB2_LB_KEYER_COLOR_G_Y_BASE_IDX                                                              2
5434 #define mmLB2_LB_KEYER_COLOR_B_CB                                                                      0x0a2d
5435 #define mmLB2_LB_KEYER_COLOR_B_CB_BASE_IDX                                                             2
5436 #define mmLB2_LB_KEYER_COLOR_REP_R_CR                                                                  0x0a2e
5437 #define mmLB2_LB_KEYER_COLOR_REP_R_CR_BASE_IDX                                                         2
5438 #define mmLB2_LB_KEYER_COLOR_REP_G_Y                                                                   0x0a2f
5439 #define mmLB2_LB_KEYER_COLOR_REP_G_Y_BASE_IDX                                                          2
5440 #define mmLB2_LB_KEYER_COLOR_REP_B_CB                                                                  0x0a30
5441 #define mmLB2_LB_KEYER_COLOR_REP_B_CB_BASE_IDX                                                         2
5442 #define mmLB2_LB_BUFFER_LEVEL_STATUS                                                                   0x0a31
5443 #define mmLB2_LB_BUFFER_LEVEL_STATUS_BASE_IDX                                                          2
5444 #define mmLB2_LB_BUFFER_URGENCY_CTRL                                                                   0x0a32
5445 #define mmLB2_LB_BUFFER_URGENCY_CTRL_BASE_IDX                                                          2
5446 #define mmLB2_LB_BUFFER_URGENCY_STATUS                                                                 0x0a33
5447 #define mmLB2_LB_BUFFER_URGENCY_STATUS_BASE_IDX                                                        2
5448 #define mmLB2_LB_BUFFER_STATUS                                                                         0x0a34
5449 #define mmLB2_LB_BUFFER_STATUS_BASE_IDX                                                                2
5450 #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS                                                             0x0a35
5451 #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX                                                    2
5452 #define mmLB2_MVP_AFR_FLIP_MODE                                                                        0x0a36
5453 #define mmLB2_MVP_AFR_FLIP_MODE_BASE_IDX                                                               2
5454 #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL                                                                   0x0a37
5455 #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX                                                          2
5456 #define mmLB2_MVP_FLIP_LINE_NUM_INSERT                                                                 0x0a38
5457 #define mmLB2_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX                                                        2
5458 #define mmLB2_DC_MVP_LB_CONTROL                                                                        0x0a39
5459 #define mmLB2_DC_MVP_LB_CONTROL_BASE_IDX                                                               2
5460 
5461 
5462 // addressBlock: dce_dc_dcfe2_dispdec
5463 // base address: 0x1000
5464 #define mmDCFE2_DCFE_CLOCK_CONTROL                                                                     0x0a5a
5465 #define mmDCFE2_DCFE_CLOCK_CONTROL_BASE_IDX                                                            2
5466 #define mmDCFE2_DCFE_SOFT_RESET                                                                        0x0a5b
5467 #define mmDCFE2_DCFE_SOFT_RESET_BASE_IDX                                                               2
5468 #define mmDCFE2_DCFE_MEM_PWR_CTRL                                                                      0x0a5d
5469 #define mmDCFE2_DCFE_MEM_PWR_CTRL_BASE_IDX                                                             2
5470 #define mmDCFE2_DCFE_MEM_PWR_CTRL2                                                                     0x0a5e
5471 #define mmDCFE2_DCFE_MEM_PWR_CTRL2_BASE_IDX                                                            2
5472 #define mmDCFE2_DCFE_MEM_PWR_STATUS                                                                    0x0a5f
5473 #define mmDCFE2_DCFE_MEM_PWR_STATUS_BASE_IDX                                                           2
5474 #define mmDCFE2_DCFE_MISC                                                                              0x0a60
5475 #define mmDCFE2_DCFE_MISC_BASE_IDX                                                                     2
5476 #define mmDCFE2_DCFE_FLUSH                                                                             0x0a61
5477 #define mmDCFE2_DCFE_FLUSH_BASE_IDX                                                                    2
5478 
5479 
5480 // addressBlock: dce_dc_dc_perfmon5_dispdec
5481 // base address: 0x2938
5482 #define mmDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x0a6e
5483 #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
5484 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x0a6f
5485 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
5486 #define mmDC_PERFMON5_PERFCOUNTER_STATE                                                                0x0a70
5487 #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
5488 #define mmDC_PERFMON5_PERFMON_CNTL                                                                     0x0a71
5489 #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
5490 #define mmDC_PERFMON5_PERFMON_CNTL2                                                                    0x0a72
5491 #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
5492 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x0a73
5493 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
5494 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0a74
5495 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
5496 #define mmDC_PERFMON5_PERFMON_HI                                                                       0x0a75
5497 #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
5498 #define mmDC_PERFMON5_PERFMON_LOW                                                                      0x0a76
5499 #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
5500 
5501 
5502 // addressBlock: dce_dc_dmif_pg2_dispdec
5503 // base address: 0x1000
5504 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1                                                       0x0a7a
5505 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                              2
5506 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2                                                       0x0a7b
5507 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                              2
5508 #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL                                                          0x0a7c
5509 #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_BASE_IDX                                                 2
5510 #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL                                                            0x0a7d
5511 #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_BASE_IDX                                                   2
5512 #define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL                                                       0x0a7e
5513 #define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX                                              2
5514 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL                                                            0x0a7f
5515 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_BASE_IDX                                                   2
5516 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2                                                           0x0a80
5517 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX                                                  2
5518 #define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL                                                          0x0a81
5519 #define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX                                                 2
5520 #define mmDMIF_PG2_DPG_REPEATER_PROGRAM                                                                0x0a82
5521 #define mmDMIF_PG2_DPG_REPEATER_PROGRAM_BASE_IDX                                                       2
5522 #define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL                                                               0x0a86
5523 #define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_BASE_IDX                                                      2
5524 #define mmDMIF_PG2_DPG_DVMM_STATUS                                                                     0x0a87
5525 #define mmDMIF_PG2_DPG_DVMM_STATUS_BASE_IDX                                                            2
5526 
5527 
5528 // addressBlock: dce_dc_scl2_dispdec
5529 // base address: 0x1000
5530 #define mmSCL2_SCL_COEF_RAM_SELECT                                                                     0x0a9a
5531 #define mmSCL2_SCL_COEF_RAM_SELECT_BASE_IDX                                                            2
5532 #define mmSCL2_SCL_COEF_RAM_TAP_DATA                                                                   0x0a9b
5533 #define mmSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                          2
5534 #define mmSCL2_SCL_MODE                                                                                0x0a9c
5535 #define mmSCL2_SCL_MODE_BASE_IDX                                                                       2
5536 #define mmSCL2_SCL_TAP_CONTROL                                                                         0x0a9d
5537 #define mmSCL2_SCL_TAP_CONTROL_BASE_IDX                                                                2
5538 #define mmSCL2_SCL_CONTROL                                                                             0x0a9e
5539 #define mmSCL2_SCL_CONTROL_BASE_IDX                                                                    2
5540 #define mmSCL2_SCL_BYPASS_CONTROL                                                                      0x0a9f
5541 #define mmSCL2_SCL_BYPASS_CONTROL_BASE_IDX                                                             2
5542 #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                            0x0aa0
5543 #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                   2
5544 #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL                                                              0x0aa1
5545 #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX                                                     2
5546 #define mmSCL2_SCL_HORZ_FILTER_CONTROL                                                                 0x0aa2
5547 #define mmSCL2_SCL_HORZ_FILTER_CONTROL_BASE_IDX                                                        2
5548 #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                             0x0aa3
5549 #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                    2
5550 #define mmSCL2_SCL_HORZ_FILTER_INIT                                                                    0x0aa4
5551 #define mmSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                           2
5552 #define mmSCL2_SCL_VERT_FILTER_CONTROL                                                                 0x0aa5
5553 #define mmSCL2_SCL_VERT_FILTER_CONTROL_BASE_IDX                                                        2
5554 #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                             0x0aa6
5555 #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                    2
5556 #define mmSCL2_SCL_VERT_FILTER_INIT                                                                    0x0aa7
5557 #define mmSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                           2
5558 #define mmSCL2_SCL_VERT_FILTER_INIT_BOT                                                                0x0aa8
5559 #define mmSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                       2
5560 #define mmSCL2_SCL_ROUND_OFFSET                                                                        0x0aa9
5561 #define mmSCL2_SCL_ROUND_OFFSET_BASE_IDX                                                               2
5562 #define mmSCL2_SCL_UPDATE                                                                              0x0aaa
5563 #define mmSCL2_SCL_UPDATE_BASE_IDX                                                                     2
5564 #define mmSCL2_SCL_F_SHARP_CONTROL                                                                     0x0aab
5565 #define mmSCL2_SCL_F_SHARP_CONTROL_BASE_IDX                                                            2
5566 #define mmSCL2_SCL_ALU_CONTROL                                                                         0x0aac
5567 #define mmSCL2_SCL_ALU_CONTROL_BASE_IDX                                                                2
5568 #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS                                                            0x0aad
5569 #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                   2
5570 #define mmSCL2_VIEWPORT_START_SECONDARY                                                                0x0aae
5571 #define mmSCL2_VIEWPORT_START_SECONDARY_BASE_IDX                                                       2
5572 #define mmSCL2_VIEWPORT_START                                                                          0x0aaf
5573 #define mmSCL2_VIEWPORT_START_BASE_IDX                                                                 2
5574 #define mmSCL2_VIEWPORT_SIZE                                                                           0x0ab0
5575 #define mmSCL2_VIEWPORT_SIZE_BASE_IDX                                                                  2
5576 #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT                                                                 0x0ab1
5577 #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                        2
5578 #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM                                                                 0x0ab2
5579 #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                        2
5580 #define mmSCL2_SCL_MODE_CHANGE_DET1                                                                    0x0ab3
5581 #define mmSCL2_SCL_MODE_CHANGE_DET1_BASE_IDX                                                           2
5582 #define mmSCL2_SCL_MODE_CHANGE_DET2                                                                    0x0ab4
5583 #define mmSCL2_SCL_MODE_CHANGE_DET2_BASE_IDX                                                           2
5584 #define mmSCL2_SCL_MODE_CHANGE_DET3                                                                    0x0ab5
5585 #define mmSCL2_SCL_MODE_CHANGE_DET3_BASE_IDX                                                           2
5586 #define mmSCL2_SCL_MODE_CHANGE_MASK                                                                    0x0ab6
5587 #define mmSCL2_SCL_MODE_CHANGE_MASK_BASE_IDX                                                           2
5588 
5589 
5590 // addressBlock: dce_dc_blnd2_dispdec
5591 // base address: 0x1000
5592 #define mmBLND2_BLND_CONTROL                                                                           0x0ac7
5593 #define mmBLND2_BLND_CONTROL_BASE_IDX                                                                  2
5594 #define mmBLND2_BLND_SM_CONTROL2                                                                       0x0ac8
5595 #define mmBLND2_BLND_SM_CONTROL2_BASE_IDX                                                              2
5596 #define mmBLND2_BLND_CONTROL2                                                                          0x0ac9
5597 #define mmBLND2_BLND_CONTROL2_BASE_IDX                                                                 2
5598 #define mmBLND2_BLND_UPDATE                                                                            0x0aca
5599 #define mmBLND2_BLND_UPDATE_BASE_IDX                                                                   2
5600 #define mmBLND2_BLND_UNDERFLOW_INTERRUPT                                                               0x0acb
5601 #define mmBLND2_BLND_UNDERFLOW_INTERRUPT_BASE_IDX                                                      2
5602 #define mmBLND2_BLND_V_UPDATE_LOCK                                                                     0x0acc
5603 #define mmBLND2_BLND_V_UPDATE_LOCK_BASE_IDX                                                            2
5604 #define mmBLND2_BLND_REG_UPDATE_STATUS                                                                 0x0acd
5605 #define mmBLND2_BLND_REG_UPDATE_STATUS_BASE_IDX                                                        2
5606 
5607 
5608 // addressBlock: dce_dc_crtc2_dispdec
5609 // base address: 0x1000
5610 #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM                                                                 0x0ad2
5611 #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_BASE_IDX                                                        2
5612 #define mmCRTC2_CRTC_H_TOTAL                                                                           0x0ad3
5613 #define mmCRTC2_CRTC_H_TOTAL_BASE_IDX                                                                  2
5614 #define mmCRTC2_CRTC_H_BLANK_START_END                                                                 0x0ad4
5615 #define mmCRTC2_CRTC_H_BLANK_START_END_BASE_IDX                                                        2
5616 #define mmCRTC2_CRTC_H_SYNC_A                                                                          0x0ad5
5617 #define mmCRTC2_CRTC_H_SYNC_A_BASE_IDX                                                                 2
5618 #define mmCRTC2_CRTC_H_SYNC_A_CNTL                                                                     0x0ad6
5619 #define mmCRTC2_CRTC_H_SYNC_A_CNTL_BASE_IDX                                                            2
5620 #define mmCRTC2_CRTC_H_SYNC_B                                                                          0x0ad7
5621 #define mmCRTC2_CRTC_H_SYNC_B_BASE_IDX                                                                 2
5622 #define mmCRTC2_CRTC_H_SYNC_B_CNTL                                                                     0x0ad8
5623 #define mmCRTC2_CRTC_H_SYNC_B_CNTL_BASE_IDX                                                            2
5624 #define mmCRTC2_CRTC_VBI_END                                                                           0x0ad9
5625 #define mmCRTC2_CRTC_VBI_END_BASE_IDX                                                                  2
5626 #define mmCRTC2_CRTC_V_TOTAL                                                                           0x0ada
5627 #define mmCRTC2_CRTC_V_TOTAL_BASE_IDX                                                                  2
5628 #define mmCRTC2_CRTC_V_TOTAL_MIN                                                                       0x0adb
5629 #define mmCRTC2_CRTC_V_TOTAL_MIN_BASE_IDX                                                              2
5630 #define mmCRTC2_CRTC_V_TOTAL_MAX                                                                       0x0adc
5631 #define mmCRTC2_CRTC_V_TOTAL_MAX_BASE_IDX                                                              2
5632 #define mmCRTC2_CRTC_V_TOTAL_CONTROL                                                                   0x0add
5633 #define mmCRTC2_CRTC_V_TOTAL_CONTROL_BASE_IDX                                                          2
5634 #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS                                                                0x0ade
5635 #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_BASE_IDX                                                       2
5636 #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS                                                              0x0adf
5637 #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX                                                     2
5638 #define mmCRTC2_CRTC_V_BLANK_START_END                                                                 0x0ae0
5639 #define mmCRTC2_CRTC_V_BLANK_START_END_BASE_IDX                                                        2
5640 #define mmCRTC2_CRTC_V_SYNC_A                                                                          0x0ae1
5641 #define mmCRTC2_CRTC_V_SYNC_A_BASE_IDX                                                                 2
5642 #define mmCRTC2_CRTC_V_SYNC_A_CNTL                                                                     0x0ae2
5643 #define mmCRTC2_CRTC_V_SYNC_A_CNTL_BASE_IDX                                                            2
5644 #define mmCRTC2_CRTC_V_SYNC_B                                                                          0x0ae3
5645 #define mmCRTC2_CRTC_V_SYNC_B_BASE_IDX                                                                 2
5646 #define mmCRTC2_CRTC_V_SYNC_B_CNTL                                                                     0x0ae4
5647 #define mmCRTC2_CRTC_V_SYNC_B_CNTL_BASE_IDX                                                            2
5648 #define mmCRTC2_CRTC_DTMTEST_CNTL                                                                      0x0ae5
5649 #define mmCRTC2_CRTC_DTMTEST_CNTL_BASE_IDX                                                             2
5650 #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION                                                           0x0ae6
5651 #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX                                                  2
5652 #define mmCRTC2_CRTC_TRIGA_CNTL                                                                        0x0ae7
5653 #define mmCRTC2_CRTC_TRIGA_CNTL_BASE_IDX                                                               2
5654 #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG                                                                 0x0ae8
5655 #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX                                                        2
5656 #define mmCRTC2_CRTC_TRIGB_CNTL                                                                        0x0ae9
5657 #define mmCRTC2_CRTC_TRIGB_CNTL_BASE_IDX                                                               2
5658 #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG                                                                 0x0aea
5659 #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX                                                        2
5660 #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL                                                              0x0aeb
5661 #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                     2
5662 #define mmCRTC2_CRTC_FLOW_CONTROL                                                                      0x0aec
5663 #define mmCRTC2_CRTC_FLOW_CONTROL_BASE_IDX                                                             2
5664 #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE                                                             0x0aed
5665 #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                    2
5666 #define mmCRTC2_CRTC_AVSYNC_COUNTER                                                                    0x0aee
5667 #define mmCRTC2_CRTC_AVSYNC_COUNTER_BASE_IDX                                                           2
5668 #define mmCRTC2_CRTC_CONTROL                                                                           0x0aef
5669 #define mmCRTC2_CRTC_CONTROL_BASE_IDX                                                                  2
5670 #define mmCRTC2_CRTC_BLANK_CONTROL                                                                     0x0af0
5671 #define mmCRTC2_CRTC_BLANK_CONTROL_BASE_IDX                                                            2
5672 #define mmCRTC2_CRTC_INTERLACE_CONTROL                                                                 0x0af1
5673 #define mmCRTC2_CRTC_INTERLACE_CONTROL_BASE_IDX                                                        2
5674 #define mmCRTC2_CRTC_INTERLACE_STATUS                                                                  0x0af2
5675 #define mmCRTC2_CRTC_INTERLACE_STATUS_BASE_IDX                                                         2
5676 #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL                                                          0x0af3
5677 #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX                                                 2
5678 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0                                                              0x0af4
5679 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_BASE_IDX                                                     2
5680 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1                                                              0x0af5
5681 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_BASE_IDX                                                     2
5682 #define mmCRTC2_CRTC_STATUS                                                                            0x0af6
5683 #define mmCRTC2_CRTC_STATUS_BASE_IDX                                                                   2
5684 #define mmCRTC2_CRTC_STATUS_POSITION                                                                   0x0af7
5685 #define mmCRTC2_CRTC_STATUS_POSITION_BASE_IDX                                                          2
5686 #define mmCRTC2_CRTC_NOM_VERT_POSITION                                                                 0x0af8
5687 #define mmCRTC2_CRTC_NOM_VERT_POSITION_BASE_IDX                                                        2
5688 #define mmCRTC2_CRTC_STATUS_FRAME_COUNT                                                                0x0af9
5689 #define mmCRTC2_CRTC_STATUS_FRAME_COUNT_BASE_IDX                                                       2
5690 #define mmCRTC2_CRTC_STATUS_VF_COUNT                                                                   0x0afa
5691 #define mmCRTC2_CRTC_STATUS_VF_COUNT_BASE_IDX                                                          2
5692 #define mmCRTC2_CRTC_STATUS_HV_COUNT                                                                   0x0afb
5693 #define mmCRTC2_CRTC_STATUS_HV_COUNT_BASE_IDX                                                          2
5694 #define mmCRTC2_CRTC_COUNT_CONTROL                                                                     0x0afc
5695 #define mmCRTC2_CRTC_COUNT_CONTROL_BASE_IDX                                                            2
5696 #define mmCRTC2_CRTC_COUNT_RESET                                                                       0x0afd
5697 #define mmCRTC2_CRTC_COUNT_RESET_BASE_IDX                                                              2
5698 #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                                      0x0afe
5699 #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                             2
5700 #define mmCRTC2_CRTC_VERT_SYNC_CONTROL                                                                 0x0aff
5701 #define mmCRTC2_CRTC_VERT_SYNC_CONTROL_BASE_IDX                                                        2
5702 #define mmCRTC2_CRTC_STEREO_STATUS                                                                     0x0b00
5703 #define mmCRTC2_CRTC_STEREO_STATUS_BASE_IDX                                                            2
5704 #define mmCRTC2_CRTC_STEREO_CONTROL                                                                    0x0b01
5705 #define mmCRTC2_CRTC_STEREO_CONTROL_BASE_IDX                                                           2
5706 #define mmCRTC2_CRTC_SNAPSHOT_STATUS                                                                   0x0b02
5707 #define mmCRTC2_CRTC_SNAPSHOT_STATUS_BASE_IDX                                                          2
5708 #define mmCRTC2_CRTC_SNAPSHOT_CONTROL                                                                  0x0b03
5709 #define mmCRTC2_CRTC_SNAPSHOT_CONTROL_BASE_IDX                                                         2
5710 #define mmCRTC2_CRTC_SNAPSHOT_POSITION                                                                 0x0b04
5711 #define mmCRTC2_CRTC_SNAPSHOT_POSITION_BASE_IDX                                                        2
5712 #define mmCRTC2_CRTC_SNAPSHOT_FRAME                                                                    0x0b05
5713 #define mmCRTC2_CRTC_SNAPSHOT_FRAME_BASE_IDX                                                           2
5714 #define mmCRTC2_CRTC_START_LINE_CONTROL                                                                0x0b06
5715 #define mmCRTC2_CRTC_START_LINE_CONTROL_BASE_IDX                                                       2
5716 #define mmCRTC2_CRTC_INTERRUPT_CONTROL                                                                 0x0b07
5717 #define mmCRTC2_CRTC_INTERRUPT_CONTROL_BASE_IDX                                                        2
5718 #define mmCRTC2_CRTC_UPDATE_LOCK                                                                       0x0b08
5719 #define mmCRTC2_CRTC_UPDATE_LOCK_BASE_IDX                                                              2
5720 #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL                                                             0x0b09
5721 #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                    2
5722 #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE                                                        0x0b0a
5723 #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX                                               2
5724 #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL                                                              0x0b0b
5725 #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_BASE_IDX                                                     2
5726 #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS                                                           0x0b0c
5727 #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX                                                  2
5728 #define mmCRTC2_CRTC_TEST_PATTERN_COLOR                                                                0x0b0d
5729 #define mmCRTC2_CRTC_TEST_PATTERN_COLOR_BASE_IDX                                                       2
5730 #define mmCRTC2_CRTC_MASTER_UPDATE_LOCK                                                                0x0b0e
5731 #define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_BASE_IDX                                                       2
5732 #define mmCRTC2_CRTC_MASTER_UPDATE_MODE                                                                0x0b0f
5733 #define mmCRTC2_CRTC_MASTER_UPDATE_MODE_BASE_IDX                                                       2
5734 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT                                                            0x0b10
5735 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX                                                   2
5736 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                                                      0x0b11
5737 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX                                             2
5738 #define mmCRTC2_CRTC_MVP_STATUS                                                                        0x0b12
5739 #define mmCRTC2_CRTC_MVP_STATUS_BASE_IDX                                                               2
5740 #define mmCRTC2_CRTC_MASTER_EN                                                                         0x0b13
5741 #define mmCRTC2_CRTC_MASTER_EN_BASE_IDX                                                                2
5742 #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT                                                              0x0b14
5743 #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX                                                     2
5744 #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS                                                               0x0b15
5745 #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_BASE_IDX                                                      2
5746 #define mmCRTC2_CRTC_OVERSCAN_COLOR                                                                    0x0b17
5747 #define mmCRTC2_CRTC_OVERSCAN_COLOR_BASE_IDX                                                           2
5748 #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT                                                                0x0b18
5749 #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX                                                       2
5750 #define mmCRTC2_CRTC_BLANK_DATA_COLOR                                                                  0x0b19
5751 #define mmCRTC2_CRTC_BLANK_DATA_COLOR_BASE_IDX                                                         2
5752 #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT                                                              0x0b1a
5753 #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX                                                     2
5754 #define mmCRTC2_CRTC_BLACK_COLOR                                                                       0x0b1b
5755 #define mmCRTC2_CRTC_BLACK_COLOR_BASE_IDX                                                              2
5756 #define mmCRTC2_CRTC_BLACK_COLOR_EXT                                                                   0x0b1c
5757 #define mmCRTC2_CRTC_BLACK_COLOR_EXT_BASE_IDX                                                          2
5758 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION                                                      0x0b1d
5759 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                             2
5760 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL                                                       0x0b1e
5761 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                              2
5762 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION                                                      0x0b1f
5763 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                             2
5764 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL                                                       0x0b20
5765 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                              2
5766 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION                                                      0x0b21
5767 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                             2
5768 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL                                                       0x0b22
5769 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                              2
5770 #define mmCRTC2_CRTC_CRC_CNTL                                                                          0x0b23
5771 #define mmCRTC2_CRTC_CRC_CNTL_BASE_IDX                                                                 2
5772 #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL                                                            0x0b24
5773 #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                   2
5774 #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL                                                            0x0b25
5775 #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
5776 #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL                                                            0x0b26
5777 #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                   2
5778 #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL                                                            0x0b27
5779 #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
5780 #define mmCRTC2_CRTC_CRC0_DATA_RG                                                                      0x0b28
5781 #define mmCRTC2_CRTC_CRC0_DATA_RG_BASE_IDX                                                             2
5782 #define mmCRTC2_CRTC_CRC0_DATA_B                                                                       0x0b29
5783 #define mmCRTC2_CRTC_CRC0_DATA_B_BASE_IDX                                                              2
5784 #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL                                                            0x0b2a
5785 #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                   2
5786 #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL                                                            0x0b2b
5787 #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
5788 #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL                                                            0x0b2c
5789 #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                   2
5790 #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL                                                            0x0b2d
5791 #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
5792 #define mmCRTC2_CRTC_CRC1_DATA_RG                                                                      0x0b2e
5793 #define mmCRTC2_CRTC_CRC1_DATA_RG_BASE_IDX                                                             2
5794 #define mmCRTC2_CRTC_CRC1_DATA_B                                                                       0x0b2f
5795 #define mmCRTC2_CRTC_CRC1_DATA_B_BASE_IDX                                                              2
5796 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL                                                           0x0b30
5797 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX                                                  2
5798 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START                                                      0x0b31
5799 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX                                             2
5800 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END                                                        0x0b32
5801 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX                                               2
5802 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                                            0x0b33
5803 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX                                   2
5804 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                                 0x0b34
5805 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX                                        2
5806 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                                          0x0b35
5807 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX                                 2
5808 #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL                                                             0x0b36
5809 #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX                                                    2
5810 #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL                                                              0x0b37
5811 #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX                                                     2
5812 #define mmCRTC2_CRTC_GSL_VSYNC_GAP                                                                     0x0b38
5813 #define mmCRTC2_CRTC_GSL_VSYNC_GAP_BASE_IDX                                                            2
5814 #define mmCRTC2_CRTC_GSL_WINDOW                                                                        0x0b39
5815 #define mmCRTC2_CRTC_GSL_WINDOW_BASE_IDX                                                               2
5816 #define mmCRTC2_CRTC_GSL_CONTROL                                                                       0x0b3a
5817 #define mmCRTC2_CRTC_GSL_CONTROL_BASE_IDX                                                              2
5818 #define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS                                                           0x0b3d
5819 #define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX                                                  2
5820 #define mmCRTC2_CRTC_DRR_CONTROL                                                                       0x0b3e
5821 #define mmCRTC2_CRTC_DRR_CONTROL_BASE_IDX                                                              2
5822 
5823 
5824 // addressBlock: dce_dc_fmt2_dispdec
5825 // base address: 0x1000
5826 #define mmFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x0b42
5827 #define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
5828 #define mmFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x0b43
5829 #define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
5830 #define mmFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x0b44
5831 #define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
5832 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x0b45
5833 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
5834 #define mmFMT2_FMT_CONTROL                                                                             0x0b46
5835 #define mmFMT2_FMT_CONTROL_BASE_IDX                                                                    2
5836 #define mmFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x0b47
5837 #define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
5838 #define mmFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x0b48
5839 #define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
5840 #define mmFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x0b49
5841 #define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
5842 #define mmFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x0b4a
5843 #define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
5844 #define mmFMT2_FMT_CLAMP_CNTL                                                                          0x0b4e
5845 #define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
5846 #define mmFMT2_FMT_CRC_CNTL                                                                            0x0b4f
5847 #define mmFMT2_FMT_CRC_CNTL_BASE_IDX                                                                   2
5848 #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK                                                              0x0b50
5849 #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
5850 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK                                                           0x0b51
5851 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
5852 #define mmFMT2_FMT_CRC_SIG_RED_GREEN                                                                   0x0b52
5853 #define mmFMT2_FMT_CRC_SIG_RED_GREEN_BASE_IDX                                                          2
5854 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL                                                                0x0b53
5855 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX                                                       2
5856 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x0b54
5857 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
5858 #define mmFMT2_FMT_420_HBLANK_EARLY_START                                                              0x0b55
5859 #define mmFMT2_FMT_420_HBLANK_EARLY_START_BASE_IDX                                                     2
5860 
5861 
5862 // addressBlock: dce_dc_dcp3_dispdec
5863 // base address: 0x1800
5864 #define mmDCP3_GRPH_ENABLE                                                                             0x0b5a
5865 #define mmDCP3_GRPH_ENABLE_BASE_IDX                                                                    2
5866 #define mmDCP3_GRPH_CONTROL                                                                            0x0b5b
5867 #define mmDCP3_GRPH_CONTROL_BASE_IDX                                                                   2
5868 #define mmDCP3_GRPH_LUT_10BIT_BYPASS                                                                   0x0b5c
5869 #define mmDCP3_GRPH_LUT_10BIT_BYPASS_BASE_IDX                                                          2
5870 #define mmDCP3_GRPH_SWAP_CNTL                                                                          0x0b5d
5871 #define mmDCP3_GRPH_SWAP_CNTL_BASE_IDX                                                                 2
5872 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS                                                            0x0b5e
5873 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                                   2
5874 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS                                                          0x0b5f
5875 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                                 2
5876 #define mmDCP3_GRPH_PITCH                                                                              0x0b60
5877 #define mmDCP3_GRPH_PITCH_BASE_IDX                                                                     2
5878 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                                       0x0b61
5879 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                              2
5880 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                                     0x0b62
5881 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                            2
5882 #define mmDCP3_GRPH_SURFACE_OFFSET_X                                                                   0x0b63
5883 #define mmDCP3_GRPH_SURFACE_OFFSET_X_BASE_IDX                                                          2
5884 #define mmDCP3_GRPH_SURFACE_OFFSET_Y                                                                   0x0b64
5885 #define mmDCP3_GRPH_SURFACE_OFFSET_Y_BASE_IDX                                                          2
5886 #define mmDCP3_GRPH_X_START                                                                            0x0b65
5887 #define mmDCP3_GRPH_X_START_BASE_IDX                                                                   2
5888 #define mmDCP3_GRPH_Y_START                                                                            0x0b66
5889 #define mmDCP3_GRPH_Y_START_BASE_IDX                                                                   2
5890 #define mmDCP3_GRPH_X_END                                                                              0x0b67
5891 #define mmDCP3_GRPH_X_END_BASE_IDX                                                                     2
5892 #define mmDCP3_GRPH_Y_END                                                                              0x0b68
5893 #define mmDCP3_GRPH_Y_END_BASE_IDX                                                                     2
5894 #define mmDCP3_INPUT_GAMMA_CONTROL                                                                     0x0b69
5895 #define mmDCP3_INPUT_GAMMA_CONTROL_BASE_IDX                                                            2
5896 #define mmDCP3_GRPH_UPDATE                                                                             0x0b6a
5897 #define mmDCP3_GRPH_UPDATE_BASE_IDX                                                                    2
5898 #define mmDCP3_GRPH_FLIP_CONTROL                                                                       0x0b6b
5899 #define mmDCP3_GRPH_FLIP_CONTROL_BASE_IDX                                                              2
5900 #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE                                                              0x0b6c
5901 #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX                                                     2
5902 #define mmDCP3_GRPH_DFQ_CONTROL                                                                        0x0b6d
5903 #define mmDCP3_GRPH_DFQ_CONTROL_BASE_IDX                                                               2
5904 #define mmDCP3_GRPH_DFQ_STATUS                                                                         0x0b6e
5905 #define mmDCP3_GRPH_DFQ_STATUS_BASE_IDX                                                                2
5906 #define mmDCP3_GRPH_INTERRUPT_STATUS                                                                   0x0b6f
5907 #define mmDCP3_GRPH_INTERRUPT_STATUS_BASE_IDX                                                          2
5908 #define mmDCP3_GRPH_INTERRUPT_CONTROL                                                                  0x0b70
5909 #define mmDCP3_GRPH_INTERRUPT_CONTROL_BASE_IDX                                                         2
5910 #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                                         0x0b71
5911 #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX                                                2
5912 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS                                                           0x0b72
5913 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX                                                  2
5914 #define mmDCP3_GRPH_COMPRESS_PITCH                                                                     0x0b73
5915 #define mmDCP3_GRPH_COMPRESS_PITCH_BASE_IDX                                                            2
5916 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                                      0x0b74
5917 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX                                             2
5918 #define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                                                     0x0b75
5919 #define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX                                            2
5920 #define mmDCP3_PRESCALE_GRPH_CONTROL                                                                   0x0b76
5921 #define mmDCP3_PRESCALE_GRPH_CONTROL_BASE_IDX                                                          2
5922 #define mmDCP3_PRESCALE_VALUES_GRPH_R                                                                  0x0b77
5923 #define mmDCP3_PRESCALE_VALUES_GRPH_R_BASE_IDX                                                         2
5924 #define mmDCP3_PRESCALE_VALUES_GRPH_G                                                                  0x0b78
5925 #define mmDCP3_PRESCALE_VALUES_GRPH_G_BASE_IDX                                                         2
5926 #define mmDCP3_PRESCALE_VALUES_GRPH_B                                                                  0x0b79
5927 #define mmDCP3_PRESCALE_VALUES_GRPH_B_BASE_IDX                                                         2
5928 #define mmDCP3_INPUT_CSC_CONTROL                                                                       0x0b7a
5929 #define mmDCP3_INPUT_CSC_CONTROL_BASE_IDX                                                              2
5930 #define mmDCP3_INPUT_CSC_C11_C12                                                                       0x0b7b
5931 #define mmDCP3_INPUT_CSC_C11_C12_BASE_IDX                                                              2
5932 #define mmDCP3_INPUT_CSC_C13_C14                                                                       0x0b7c
5933 #define mmDCP3_INPUT_CSC_C13_C14_BASE_IDX                                                              2
5934 #define mmDCP3_INPUT_CSC_C21_C22                                                                       0x0b7d
5935 #define mmDCP3_INPUT_CSC_C21_C22_BASE_IDX                                                              2
5936 #define mmDCP3_INPUT_CSC_C23_C24                                                                       0x0b7e
5937 #define mmDCP3_INPUT_CSC_C23_C24_BASE_IDX                                                              2
5938 #define mmDCP3_INPUT_CSC_C31_C32                                                                       0x0b7f
5939 #define mmDCP3_INPUT_CSC_C31_C32_BASE_IDX                                                              2
5940 #define mmDCP3_INPUT_CSC_C33_C34                                                                       0x0b80
5941 #define mmDCP3_INPUT_CSC_C33_C34_BASE_IDX                                                              2
5942 #define mmDCP3_OUTPUT_CSC_CONTROL                                                                      0x0b81
5943 #define mmDCP3_OUTPUT_CSC_CONTROL_BASE_IDX                                                             2
5944 #define mmDCP3_OUTPUT_CSC_C11_C12                                                                      0x0b82
5945 #define mmDCP3_OUTPUT_CSC_C11_C12_BASE_IDX                                                             2
5946 #define mmDCP3_OUTPUT_CSC_C13_C14                                                                      0x0b83
5947 #define mmDCP3_OUTPUT_CSC_C13_C14_BASE_IDX                                                             2
5948 #define mmDCP3_OUTPUT_CSC_C21_C22                                                                      0x0b84
5949 #define mmDCP3_OUTPUT_CSC_C21_C22_BASE_IDX                                                             2
5950 #define mmDCP3_OUTPUT_CSC_C23_C24                                                                      0x0b85
5951 #define mmDCP3_OUTPUT_CSC_C23_C24_BASE_IDX                                                             2
5952 #define mmDCP3_OUTPUT_CSC_C31_C32                                                                      0x0b86
5953 #define mmDCP3_OUTPUT_CSC_C31_C32_BASE_IDX                                                             2
5954 #define mmDCP3_OUTPUT_CSC_C33_C34                                                                      0x0b87
5955 #define mmDCP3_OUTPUT_CSC_C33_C34_BASE_IDX                                                             2
5956 #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12                                                              0x0b88
5957 #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX                                                     2
5958 #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14                                                              0x0b89
5959 #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX                                                     2
5960 #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22                                                              0x0b8a
5961 #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX                                                     2
5962 #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24                                                              0x0b8b
5963 #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX                                                     2
5964 #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32                                                              0x0b8c
5965 #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX                                                     2
5966 #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34                                                              0x0b8d
5967 #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX                                                     2
5968 #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12                                                              0x0b8e
5969 #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX                                                     2
5970 #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14                                                              0x0b8f
5971 #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX                                                     2
5972 #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22                                                              0x0b90
5973 #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX                                                     2
5974 #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24                                                              0x0b91
5975 #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX                                                     2
5976 #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32                                                              0x0b92
5977 #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX                                                     2
5978 #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34                                                              0x0b93
5979 #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX                                                     2
5980 #define mmDCP3_DENORM_CONTROL                                                                          0x0b94
5981 #define mmDCP3_DENORM_CONTROL_BASE_IDX                                                                 2
5982 #define mmDCP3_OUT_ROUND_CONTROL                                                                       0x0b95
5983 #define mmDCP3_OUT_ROUND_CONTROL_BASE_IDX                                                              2
5984 #define mmDCP3_OUT_CLAMP_CONTROL_R_CR                                                                  0x0b96
5985 #define mmDCP3_OUT_CLAMP_CONTROL_R_CR_BASE_IDX                                                         2
5986 #define mmDCP3_OUT_CLAMP_CONTROL_G_Y                                                                   0x0b97
5987 #define mmDCP3_OUT_CLAMP_CONTROL_G_Y_BASE_IDX                                                          2
5988 #define mmDCP3_OUT_CLAMP_CONTROL_B_CB                                                                  0x0b98
5989 #define mmDCP3_OUT_CLAMP_CONTROL_B_CB_BASE_IDX                                                         2
5990 #define mmDCP3_KEY_CONTROL                                                                             0x0b99
5991 #define mmDCP3_KEY_CONTROL_BASE_IDX                                                                    2
5992 #define mmDCP3_KEY_RANGE_ALPHA                                                                         0x0b9a
5993 #define mmDCP3_KEY_RANGE_ALPHA_BASE_IDX                                                                2
5994 #define mmDCP3_KEY_RANGE_RED                                                                           0x0b9b
5995 #define mmDCP3_KEY_RANGE_RED_BASE_IDX                                                                  2
5996 #define mmDCP3_KEY_RANGE_GREEN                                                                         0x0b9c
5997 #define mmDCP3_KEY_RANGE_GREEN_BASE_IDX                                                                2
5998 #define mmDCP3_KEY_RANGE_BLUE                                                                          0x0b9d
5999 #define mmDCP3_KEY_RANGE_BLUE_BASE_IDX                                                                 2
6000 #define mmDCP3_DEGAMMA_CONTROL                                                                         0x0b9e
6001 #define mmDCP3_DEGAMMA_CONTROL_BASE_IDX                                                                2
6002 #define mmDCP3_GAMUT_REMAP_CONTROL                                                                     0x0b9f
6003 #define mmDCP3_GAMUT_REMAP_CONTROL_BASE_IDX                                                            2
6004 #define mmDCP3_GAMUT_REMAP_C11_C12                                                                     0x0ba0
6005 #define mmDCP3_GAMUT_REMAP_C11_C12_BASE_IDX                                                            2
6006 #define mmDCP3_GAMUT_REMAP_C13_C14                                                                     0x0ba1
6007 #define mmDCP3_GAMUT_REMAP_C13_C14_BASE_IDX                                                            2
6008 #define mmDCP3_GAMUT_REMAP_C21_C22                                                                     0x0ba2
6009 #define mmDCP3_GAMUT_REMAP_C21_C22_BASE_IDX                                                            2
6010 #define mmDCP3_GAMUT_REMAP_C23_C24                                                                     0x0ba3
6011 #define mmDCP3_GAMUT_REMAP_C23_C24_BASE_IDX                                                            2
6012 #define mmDCP3_GAMUT_REMAP_C31_C32                                                                     0x0ba4
6013 #define mmDCP3_GAMUT_REMAP_C31_C32_BASE_IDX                                                            2
6014 #define mmDCP3_GAMUT_REMAP_C33_C34                                                                     0x0ba5
6015 #define mmDCP3_GAMUT_REMAP_C33_C34_BASE_IDX                                                            2
6016 #define mmDCP3_DCP_SPATIAL_DITHER_CNTL                                                                 0x0ba6
6017 #define mmDCP3_DCP_SPATIAL_DITHER_CNTL_BASE_IDX                                                        2
6018 #define mmDCP3_DCP_RANDOM_SEEDS                                                                        0x0ba7
6019 #define mmDCP3_DCP_RANDOM_SEEDS_BASE_IDX                                                               2
6020 #define mmDCP3_DCP_FP_CONVERTED_FIELD                                                                  0x0ba8
6021 #define mmDCP3_DCP_FP_CONVERTED_FIELD_BASE_IDX                                                         2
6022 #define mmDCP3_CUR_CONTROL                                                                             0x0ba9
6023 #define mmDCP3_CUR_CONTROL_BASE_IDX                                                                    2
6024 #define mmDCP3_CUR_SURFACE_ADDRESS                                                                     0x0baa
6025 #define mmDCP3_CUR_SURFACE_ADDRESS_BASE_IDX                                                            2
6026 #define mmDCP3_CUR_SIZE                                                                                0x0bab
6027 #define mmDCP3_CUR_SIZE_BASE_IDX                                                                       2
6028 #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH                                                                0x0bac
6029 #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX                                                       2
6030 #define mmDCP3_CUR_POSITION                                                                            0x0bad
6031 #define mmDCP3_CUR_POSITION_BASE_IDX                                                                   2
6032 #define mmDCP3_CUR_HOT_SPOT                                                                            0x0bae
6033 #define mmDCP3_CUR_HOT_SPOT_BASE_IDX                                                                   2
6034 #define mmDCP3_CUR_COLOR1                                                                              0x0baf
6035 #define mmDCP3_CUR_COLOR1_BASE_IDX                                                                     2
6036 #define mmDCP3_CUR_COLOR2                                                                              0x0bb0
6037 #define mmDCP3_CUR_COLOR2_BASE_IDX                                                                     2
6038 #define mmDCP3_CUR_UPDATE                                                                              0x0bb1
6039 #define mmDCP3_CUR_UPDATE_BASE_IDX                                                                     2
6040 #define mmDCP3_CUR_REQUEST_FILTER_CNTL                                                                 0x0bbb
6041 #define mmDCP3_CUR_REQUEST_FILTER_CNTL_BASE_IDX                                                        2
6042 #define mmDCP3_CUR_STEREO_CONTROL                                                                      0x0bbc
6043 #define mmDCP3_CUR_STEREO_CONTROL_BASE_IDX                                                             2
6044 #define mmDCP3_DC_LUT_RW_MODE                                                                          0x0bbe
6045 #define mmDCP3_DC_LUT_RW_MODE_BASE_IDX                                                                 2
6046 #define mmDCP3_DC_LUT_RW_INDEX                                                                         0x0bbf
6047 #define mmDCP3_DC_LUT_RW_INDEX_BASE_IDX                                                                2
6048 #define mmDCP3_DC_LUT_SEQ_COLOR                                                                        0x0bc0
6049 #define mmDCP3_DC_LUT_SEQ_COLOR_BASE_IDX                                                               2
6050 #define mmDCP3_DC_LUT_PWL_DATA                                                                         0x0bc1
6051 #define mmDCP3_DC_LUT_PWL_DATA_BASE_IDX                                                                2
6052 #define mmDCP3_DC_LUT_30_COLOR                                                                         0x0bc2
6053 #define mmDCP3_DC_LUT_30_COLOR_BASE_IDX                                                                2
6054 #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE                                                                0x0bc3
6055 #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX                                                       2
6056 #define mmDCP3_DC_LUT_WRITE_EN_MASK                                                                    0x0bc4
6057 #define mmDCP3_DC_LUT_WRITE_EN_MASK_BASE_IDX                                                           2
6058 #define mmDCP3_DC_LUT_AUTOFILL                                                                         0x0bc5
6059 #define mmDCP3_DC_LUT_AUTOFILL_BASE_IDX                                                                2
6060 #define mmDCP3_DC_LUT_CONTROL                                                                          0x0bc6
6061 #define mmDCP3_DC_LUT_CONTROL_BASE_IDX                                                                 2
6062 #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE                                                                0x0bc7
6063 #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX                                                       2
6064 #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN                                                               0x0bc8
6065 #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX                                                      2
6066 #define mmDCP3_DC_LUT_BLACK_OFFSET_RED                                                                 0x0bc9
6067 #define mmDCP3_DC_LUT_BLACK_OFFSET_RED_BASE_IDX                                                        2
6068 #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE                                                                0x0bca
6069 #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX                                                       2
6070 #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN                                                               0x0bcb
6071 #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX                                                      2
6072 #define mmDCP3_DC_LUT_WHITE_OFFSET_RED                                                                 0x0bcc
6073 #define mmDCP3_DC_LUT_WHITE_OFFSET_RED_BASE_IDX                                                        2
6074 #define mmDCP3_DCP_CRC_CONTROL                                                                         0x0bcd
6075 #define mmDCP3_DCP_CRC_CONTROL_BASE_IDX                                                                2
6076 #define mmDCP3_DCP_CRC_MASK                                                                            0x0bce
6077 #define mmDCP3_DCP_CRC_MASK_BASE_IDX                                                                   2
6078 #define mmDCP3_DCP_CRC_CURRENT                                                                         0x0bcf
6079 #define mmDCP3_DCP_CRC_CURRENT_BASE_IDX                                                                2
6080 #define mmDCP3_DVMM_PTE_CONTROL                                                                        0x0bd0
6081 #define mmDCP3_DVMM_PTE_CONTROL_BASE_IDX                                                               2
6082 #define mmDCP3_DCP_CRC_LAST                                                                            0x0bd1
6083 #define mmDCP3_DCP_CRC_LAST_BASE_IDX                                                                   2
6084 #define mmDCP3_DVMM_PTE_ARB_CONTROL                                                                    0x0bd2
6085 #define mmDCP3_DVMM_PTE_ARB_CONTROL_BASE_IDX                                                           2
6086 #define mmDCP3_GRPH_FLIP_RATE_CNTL                                                                     0x0bd4
6087 #define mmDCP3_GRPH_FLIP_RATE_CNTL_BASE_IDX                                                            2
6088 #define mmDCP3_DCP_GSL_CONTROL                                                                         0x0bd5
6089 #define mmDCP3_DCP_GSL_CONTROL_BASE_IDX                                                                2
6090 #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                                           0x0bd6
6091 #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX                                                  2
6092 #define mmDCP3_GRPH_STEREOSYNC_FLIP                                                                    0x0bdc
6093 #define mmDCP3_GRPH_STEREOSYNC_FLIP_BASE_IDX                                                           2
6094 #define mmDCP3_HW_ROTATION                                                                             0x0bde
6095 #define mmDCP3_HW_ROTATION_BASE_IDX                                                                    2
6096 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                                      0x0bdf
6097 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX                                             2
6098 #define mmDCP3_REGAMMA_CONTROL                                                                         0x0be0
6099 #define mmDCP3_REGAMMA_CONTROL_BASE_IDX                                                                2
6100 #define mmDCP3_REGAMMA_LUT_INDEX                                                                       0x0be1
6101 #define mmDCP3_REGAMMA_LUT_INDEX_BASE_IDX                                                              2
6102 #define mmDCP3_REGAMMA_LUT_DATA                                                                        0x0be2
6103 #define mmDCP3_REGAMMA_LUT_DATA_BASE_IDX                                                               2
6104 #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK                                                               0x0be3
6105 #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX                                                      2
6106 #define mmDCP3_REGAMMA_CNTLA_START_CNTL                                                                0x0be4
6107 #define mmDCP3_REGAMMA_CNTLA_START_CNTL_BASE_IDX                                                       2
6108 #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL                                                                0x0be5
6109 #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX                                                       2
6110 #define mmDCP3_REGAMMA_CNTLA_END_CNTL1                                                                 0x0be6
6111 #define mmDCP3_REGAMMA_CNTLA_END_CNTL1_BASE_IDX                                                        2
6112 #define mmDCP3_REGAMMA_CNTLA_END_CNTL2                                                                 0x0be7
6113 #define mmDCP3_REGAMMA_CNTLA_END_CNTL2_BASE_IDX                                                        2
6114 #define mmDCP3_REGAMMA_CNTLA_REGION_0_1                                                                0x0be8
6115 #define mmDCP3_REGAMMA_CNTLA_REGION_0_1_BASE_IDX                                                       2
6116 #define mmDCP3_REGAMMA_CNTLA_REGION_2_3                                                                0x0be9
6117 #define mmDCP3_REGAMMA_CNTLA_REGION_2_3_BASE_IDX                                                       2
6118 #define mmDCP3_REGAMMA_CNTLA_REGION_4_5                                                                0x0bea
6119 #define mmDCP3_REGAMMA_CNTLA_REGION_4_5_BASE_IDX                                                       2
6120 #define mmDCP3_REGAMMA_CNTLA_REGION_6_7                                                                0x0beb
6121 #define mmDCP3_REGAMMA_CNTLA_REGION_6_7_BASE_IDX                                                       2
6122 #define mmDCP3_REGAMMA_CNTLA_REGION_8_9                                                                0x0bec
6123 #define mmDCP3_REGAMMA_CNTLA_REGION_8_9_BASE_IDX                                                       2
6124 #define mmDCP3_REGAMMA_CNTLA_REGION_10_11                                                              0x0bed
6125 #define mmDCP3_REGAMMA_CNTLA_REGION_10_11_BASE_IDX                                                     2
6126 #define mmDCP3_REGAMMA_CNTLA_REGION_12_13                                                              0x0bee
6127 #define mmDCP3_REGAMMA_CNTLA_REGION_12_13_BASE_IDX                                                     2
6128 #define mmDCP3_REGAMMA_CNTLA_REGION_14_15                                                              0x0bef
6129 #define mmDCP3_REGAMMA_CNTLA_REGION_14_15_BASE_IDX                                                     2
6130 #define mmDCP3_REGAMMA_CNTLB_START_CNTL                                                                0x0bf0
6131 #define mmDCP3_REGAMMA_CNTLB_START_CNTL_BASE_IDX                                                       2
6132 #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL                                                                0x0bf1
6133 #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX                                                       2
6134 #define mmDCP3_REGAMMA_CNTLB_END_CNTL1                                                                 0x0bf2
6135 #define mmDCP3_REGAMMA_CNTLB_END_CNTL1_BASE_IDX                                                        2
6136 #define mmDCP3_REGAMMA_CNTLB_END_CNTL2                                                                 0x0bf3
6137 #define mmDCP3_REGAMMA_CNTLB_END_CNTL2_BASE_IDX                                                        2
6138 #define mmDCP3_REGAMMA_CNTLB_REGION_0_1                                                                0x0bf4
6139 #define mmDCP3_REGAMMA_CNTLB_REGION_0_1_BASE_IDX                                                       2
6140 #define mmDCP3_REGAMMA_CNTLB_REGION_2_3                                                                0x0bf5
6141 #define mmDCP3_REGAMMA_CNTLB_REGION_2_3_BASE_IDX                                                       2
6142 #define mmDCP3_REGAMMA_CNTLB_REGION_4_5                                                                0x0bf6
6143 #define mmDCP3_REGAMMA_CNTLB_REGION_4_5_BASE_IDX                                                       2
6144 #define mmDCP3_REGAMMA_CNTLB_REGION_6_7                                                                0x0bf7
6145 #define mmDCP3_REGAMMA_CNTLB_REGION_6_7_BASE_IDX                                                       2
6146 #define mmDCP3_REGAMMA_CNTLB_REGION_8_9                                                                0x0bf8
6147 #define mmDCP3_REGAMMA_CNTLB_REGION_8_9_BASE_IDX                                                       2
6148 #define mmDCP3_REGAMMA_CNTLB_REGION_10_11                                                              0x0bf9
6149 #define mmDCP3_REGAMMA_CNTLB_REGION_10_11_BASE_IDX                                                     2
6150 #define mmDCP3_REGAMMA_CNTLB_REGION_12_13                                                              0x0bfa
6151 #define mmDCP3_REGAMMA_CNTLB_REGION_12_13_BASE_IDX                                                     2
6152 #define mmDCP3_REGAMMA_CNTLB_REGION_14_15                                                              0x0bfb
6153 #define mmDCP3_REGAMMA_CNTLB_REGION_14_15_BASE_IDX                                                     2
6154 #define mmDCP3_ALPHA_CONTROL                                                                           0x0bfc
6155 #define mmDCP3_ALPHA_CONTROL_BASE_IDX                                                                  2
6156 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                                      0x0bfd
6157 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX                                             2
6158 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                                                 0x0bfe
6159 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
6160 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                                    0x0bff
6161 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX                                           2
6162 #define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT                                                                  0x0c00
6163 #define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX                                                         2
6164 #define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY                                                                0x0c01
6165 #define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX                                                       2
6166 #define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL                                                            0x0c02
6167 #define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX                                                   2
6168 #define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT                                                             0x0c03
6169 #define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX                                                    2
6170 
6171 
6172 // addressBlock: dce_dc_lb3_dispdec
6173 // base address: 0x1800
6174 #define mmLB3_LB_DATA_FORMAT                                                                           0x0c1a
6175 #define mmLB3_LB_DATA_FORMAT_BASE_IDX                                                                  2
6176 #define mmLB3_LB_MEMORY_CTRL                                                                           0x0c1b
6177 #define mmLB3_LB_MEMORY_CTRL_BASE_IDX                                                                  2
6178 #define mmLB3_LB_MEMORY_SIZE_STATUS                                                                    0x0c1c
6179 #define mmLB3_LB_MEMORY_SIZE_STATUS_BASE_IDX                                                           2
6180 #define mmLB3_LB_DESKTOP_HEIGHT                                                                        0x0c1d
6181 #define mmLB3_LB_DESKTOP_HEIGHT_BASE_IDX                                                               2
6182 #define mmLB3_LB_VLINE_START_END                                                                       0x0c1e
6183 #define mmLB3_LB_VLINE_START_END_BASE_IDX                                                              2
6184 #define mmLB3_LB_VLINE2_START_END                                                                      0x0c1f
6185 #define mmLB3_LB_VLINE2_START_END_BASE_IDX                                                             2
6186 #define mmLB3_LB_V_COUNTER                                                                             0x0c20
6187 #define mmLB3_LB_V_COUNTER_BASE_IDX                                                                    2
6188 #define mmLB3_LB_SNAPSHOT_V_COUNTER                                                                    0x0c21
6189 #define mmLB3_LB_SNAPSHOT_V_COUNTER_BASE_IDX                                                           2
6190 #define mmLB3_LB_INTERRUPT_MASK                                                                        0x0c22
6191 #define mmLB3_LB_INTERRUPT_MASK_BASE_IDX                                                               2
6192 #define mmLB3_LB_VLINE_STATUS                                                                          0x0c23
6193 #define mmLB3_LB_VLINE_STATUS_BASE_IDX                                                                 2
6194 #define mmLB3_LB_VLINE2_STATUS                                                                         0x0c24
6195 #define mmLB3_LB_VLINE2_STATUS_BASE_IDX                                                                2
6196 #define mmLB3_LB_VBLANK_STATUS                                                                         0x0c25
6197 #define mmLB3_LB_VBLANK_STATUS_BASE_IDX                                                                2
6198 #define mmLB3_LB_SYNC_RESET_SEL                                                                        0x0c26
6199 #define mmLB3_LB_SYNC_RESET_SEL_BASE_IDX                                                               2
6200 #define mmLB3_LB_BLACK_KEYER_R_CR                                                                      0x0c27
6201 #define mmLB3_LB_BLACK_KEYER_R_CR_BASE_IDX                                                             2
6202 #define mmLB3_LB_BLACK_KEYER_G_Y                                                                       0x0c28
6203 #define mmLB3_LB_BLACK_KEYER_G_Y_BASE_IDX                                                              2
6204 #define mmLB3_LB_BLACK_KEYER_B_CB                                                                      0x0c29
6205 #define mmLB3_LB_BLACK_KEYER_B_CB_BASE_IDX                                                             2
6206 #define mmLB3_LB_KEYER_COLOR_CTRL                                                                      0x0c2a
6207 #define mmLB3_LB_KEYER_COLOR_CTRL_BASE_IDX                                                             2
6208 #define mmLB3_LB_KEYER_COLOR_R_CR                                                                      0x0c2b
6209 #define mmLB3_LB_KEYER_COLOR_R_CR_BASE_IDX                                                             2
6210 #define mmLB3_LB_KEYER_COLOR_G_Y                                                                       0x0c2c
6211 #define mmLB3_LB_KEYER_COLOR_G_Y_BASE_IDX                                                              2
6212 #define mmLB3_LB_KEYER_COLOR_B_CB                                                                      0x0c2d
6213 #define mmLB3_LB_KEYER_COLOR_B_CB_BASE_IDX                                                             2
6214 #define mmLB3_LB_KEYER_COLOR_REP_R_CR                                                                  0x0c2e
6215 #define mmLB3_LB_KEYER_COLOR_REP_R_CR_BASE_IDX                                                         2
6216 #define mmLB3_LB_KEYER_COLOR_REP_G_Y                                                                   0x0c2f
6217 #define mmLB3_LB_KEYER_COLOR_REP_G_Y_BASE_IDX                                                          2
6218 #define mmLB3_LB_KEYER_COLOR_REP_B_CB                                                                  0x0c30
6219 #define mmLB3_LB_KEYER_COLOR_REP_B_CB_BASE_IDX                                                         2
6220 #define mmLB3_LB_BUFFER_LEVEL_STATUS                                                                   0x0c31
6221 #define mmLB3_LB_BUFFER_LEVEL_STATUS_BASE_IDX                                                          2
6222 #define mmLB3_LB_BUFFER_URGENCY_CTRL                                                                   0x0c32
6223 #define mmLB3_LB_BUFFER_URGENCY_CTRL_BASE_IDX                                                          2
6224 #define mmLB3_LB_BUFFER_URGENCY_STATUS                                                                 0x0c33
6225 #define mmLB3_LB_BUFFER_URGENCY_STATUS_BASE_IDX                                                        2
6226 #define mmLB3_LB_BUFFER_STATUS                                                                         0x0c34
6227 #define mmLB3_LB_BUFFER_STATUS_BASE_IDX                                                                2
6228 #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS                                                             0x0c35
6229 #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX                                                    2
6230 #define mmLB3_MVP_AFR_FLIP_MODE                                                                        0x0c36
6231 #define mmLB3_MVP_AFR_FLIP_MODE_BASE_IDX                                                               2
6232 #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL                                                                   0x0c37
6233 #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX                                                          2
6234 #define mmLB3_MVP_FLIP_LINE_NUM_INSERT                                                                 0x0c38
6235 #define mmLB3_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX                                                        2
6236 #define mmLB3_DC_MVP_LB_CONTROL                                                                        0x0c39
6237 #define mmLB3_DC_MVP_LB_CONTROL_BASE_IDX                                                               2
6238 
6239 
6240 // addressBlock: dce_dc_dcfe3_dispdec
6241 // base address: 0x1800
6242 #define mmDCFE3_DCFE_CLOCK_CONTROL                                                                     0x0c5a
6243 #define mmDCFE3_DCFE_CLOCK_CONTROL_BASE_IDX                                                            2
6244 #define mmDCFE3_DCFE_SOFT_RESET                                                                        0x0c5b
6245 #define mmDCFE3_DCFE_SOFT_RESET_BASE_IDX                                                               2
6246 #define mmDCFE3_DCFE_MEM_PWR_CTRL                                                                      0x0c5d
6247 #define mmDCFE3_DCFE_MEM_PWR_CTRL_BASE_IDX                                                             2
6248 #define mmDCFE3_DCFE_MEM_PWR_CTRL2                                                                     0x0c5e
6249 #define mmDCFE3_DCFE_MEM_PWR_CTRL2_BASE_IDX                                                            2
6250 #define mmDCFE3_DCFE_MEM_PWR_STATUS                                                                    0x0c5f
6251 #define mmDCFE3_DCFE_MEM_PWR_STATUS_BASE_IDX                                                           2
6252 #define mmDCFE3_DCFE_MISC                                                                              0x0c60
6253 #define mmDCFE3_DCFE_MISC_BASE_IDX                                                                     2
6254 #define mmDCFE3_DCFE_FLUSH                                                                             0x0c61
6255 #define mmDCFE3_DCFE_FLUSH_BASE_IDX                                                                    2
6256 
6257 
6258 // addressBlock: dce_dc_dc_perfmon6_dispdec
6259 // base address: 0x3138
6260 #define mmDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x0c6e
6261 #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
6262 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x0c6f
6263 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
6264 #define mmDC_PERFMON6_PERFCOUNTER_STATE                                                                0x0c70
6265 #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
6266 #define mmDC_PERFMON6_PERFMON_CNTL                                                                     0x0c71
6267 #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
6268 #define mmDC_PERFMON6_PERFMON_CNTL2                                                                    0x0c72
6269 #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
6270 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x0c73
6271 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
6272 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x0c74
6273 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
6274 #define mmDC_PERFMON6_PERFMON_HI                                                                       0x0c75
6275 #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
6276 #define mmDC_PERFMON6_PERFMON_LOW                                                                      0x0c76
6277 #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
6278 
6279 
6280 // addressBlock: dce_dc_dmif_pg3_dispdec
6281 // base address: 0x1800
6282 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1                                                       0x0c7a
6283 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                              2
6284 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2                                                       0x0c7b
6285 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                              2
6286 #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL                                                          0x0c7c
6287 #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_BASE_IDX                                                 2
6288 #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL                                                            0x0c7d
6289 #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_BASE_IDX                                                   2
6290 #define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL                                                       0x0c7e
6291 #define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX                                              2
6292 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL                                                            0x0c7f
6293 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_BASE_IDX                                                   2
6294 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2                                                           0x0c80
6295 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX                                                  2
6296 #define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL                                                          0x0c81
6297 #define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX                                                 2
6298 #define mmDMIF_PG3_DPG_REPEATER_PROGRAM                                                                0x0c82
6299 #define mmDMIF_PG3_DPG_REPEATER_PROGRAM_BASE_IDX                                                       2
6300 #define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL                                                               0x0c86
6301 #define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_BASE_IDX                                                      2
6302 #define mmDMIF_PG3_DPG_DVMM_STATUS                                                                     0x0c87
6303 #define mmDMIF_PG3_DPG_DVMM_STATUS_BASE_IDX                                                            2
6304 
6305 
6306 // addressBlock: dce_dc_scl3_dispdec
6307 // base address: 0x1800
6308 #define mmSCL3_SCL_COEF_RAM_SELECT                                                                     0x0c9a
6309 #define mmSCL3_SCL_COEF_RAM_SELECT_BASE_IDX                                                            2
6310 #define mmSCL3_SCL_COEF_RAM_TAP_DATA                                                                   0x0c9b
6311 #define mmSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                          2
6312 #define mmSCL3_SCL_MODE                                                                                0x0c9c
6313 #define mmSCL3_SCL_MODE_BASE_IDX                                                                       2
6314 #define mmSCL3_SCL_TAP_CONTROL                                                                         0x0c9d
6315 #define mmSCL3_SCL_TAP_CONTROL_BASE_IDX                                                                2
6316 #define mmSCL3_SCL_CONTROL                                                                             0x0c9e
6317 #define mmSCL3_SCL_CONTROL_BASE_IDX                                                                    2
6318 #define mmSCL3_SCL_BYPASS_CONTROL                                                                      0x0c9f
6319 #define mmSCL3_SCL_BYPASS_CONTROL_BASE_IDX                                                             2
6320 #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                            0x0ca0
6321 #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                   2
6322 #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL                                                              0x0ca1
6323 #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX                                                     2
6324 #define mmSCL3_SCL_HORZ_FILTER_CONTROL                                                                 0x0ca2
6325 #define mmSCL3_SCL_HORZ_FILTER_CONTROL_BASE_IDX                                                        2
6326 #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                             0x0ca3
6327 #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                    2
6328 #define mmSCL3_SCL_HORZ_FILTER_INIT                                                                    0x0ca4
6329 #define mmSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                           2
6330 #define mmSCL3_SCL_VERT_FILTER_CONTROL                                                                 0x0ca5
6331 #define mmSCL3_SCL_VERT_FILTER_CONTROL_BASE_IDX                                                        2
6332 #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                             0x0ca6
6333 #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                    2
6334 #define mmSCL3_SCL_VERT_FILTER_INIT                                                                    0x0ca7
6335 #define mmSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                           2
6336 #define mmSCL3_SCL_VERT_FILTER_INIT_BOT                                                                0x0ca8
6337 #define mmSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                       2
6338 #define mmSCL3_SCL_ROUND_OFFSET                                                                        0x0ca9
6339 #define mmSCL3_SCL_ROUND_OFFSET_BASE_IDX                                                               2
6340 #define mmSCL3_SCL_UPDATE                                                                              0x0caa
6341 #define mmSCL3_SCL_UPDATE_BASE_IDX                                                                     2
6342 #define mmSCL3_SCL_F_SHARP_CONTROL                                                                     0x0cab
6343 #define mmSCL3_SCL_F_SHARP_CONTROL_BASE_IDX                                                            2
6344 #define mmSCL3_SCL_ALU_CONTROL                                                                         0x0cac
6345 #define mmSCL3_SCL_ALU_CONTROL_BASE_IDX                                                                2
6346 #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS                                                            0x0cad
6347 #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                   2
6348 #define mmSCL3_VIEWPORT_START_SECONDARY                                                                0x0cae
6349 #define mmSCL3_VIEWPORT_START_SECONDARY_BASE_IDX                                                       2
6350 #define mmSCL3_VIEWPORT_START                                                                          0x0caf
6351 #define mmSCL3_VIEWPORT_START_BASE_IDX                                                                 2
6352 #define mmSCL3_VIEWPORT_SIZE                                                                           0x0cb0
6353 #define mmSCL3_VIEWPORT_SIZE_BASE_IDX                                                                  2
6354 #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT                                                                 0x0cb1
6355 #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                        2
6356 #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM                                                                 0x0cb2
6357 #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                        2
6358 #define mmSCL3_SCL_MODE_CHANGE_DET1                                                                    0x0cb3
6359 #define mmSCL3_SCL_MODE_CHANGE_DET1_BASE_IDX                                                           2
6360 #define mmSCL3_SCL_MODE_CHANGE_DET2                                                                    0x0cb4
6361 #define mmSCL3_SCL_MODE_CHANGE_DET2_BASE_IDX                                                           2
6362 #define mmSCL3_SCL_MODE_CHANGE_DET3                                                                    0x0cb5
6363 #define mmSCL3_SCL_MODE_CHANGE_DET3_BASE_IDX                                                           2
6364 #define mmSCL3_SCL_MODE_CHANGE_MASK                                                                    0x0cb6
6365 #define mmSCL3_SCL_MODE_CHANGE_MASK_BASE_IDX                                                           2
6366 
6367 
6368 // addressBlock: dce_dc_blnd3_dispdec
6369 // base address: 0x1800
6370 #define mmBLND3_BLND_CONTROL                                                                           0x0cc7
6371 #define mmBLND3_BLND_CONTROL_BASE_IDX                                                                  2
6372 #define mmBLND3_BLND_SM_CONTROL2                                                                       0x0cc8
6373 #define mmBLND3_BLND_SM_CONTROL2_BASE_IDX                                                              2
6374 #define mmBLND3_BLND_CONTROL2                                                                          0x0cc9
6375 #define mmBLND3_BLND_CONTROL2_BASE_IDX                                                                 2
6376 #define mmBLND3_BLND_UPDATE                                                                            0x0cca
6377 #define mmBLND3_BLND_UPDATE_BASE_IDX                                                                   2
6378 #define mmBLND3_BLND_UNDERFLOW_INTERRUPT                                                               0x0ccb
6379 #define mmBLND3_BLND_UNDERFLOW_INTERRUPT_BASE_IDX                                                      2
6380 #define mmBLND3_BLND_V_UPDATE_LOCK                                                                     0x0ccc
6381 #define mmBLND3_BLND_V_UPDATE_LOCK_BASE_IDX                                                            2
6382 #define mmBLND3_BLND_REG_UPDATE_STATUS                                                                 0x0ccd
6383 #define mmBLND3_BLND_REG_UPDATE_STATUS_BASE_IDX                                                        2
6384 
6385 
6386 // addressBlock: dce_dc_crtc3_dispdec
6387 // base address: 0x1800
6388 #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM                                                                 0x0cd2
6389 #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_BASE_IDX                                                        2
6390 #define mmCRTC3_CRTC_H_TOTAL                                                                           0x0cd3
6391 #define mmCRTC3_CRTC_H_TOTAL_BASE_IDX                                                                  2
6392 #define mmCRTC3_CRTC_H_BLANK_START_END                                                                 0x0cd4
6393 #define mmCRTC3_CRTC_H_BLANK_START_END_BASE_IDX                                                        2
6394 #define mmCRTC3_CRTC_H_SYNC_A                                                                          0x0cd5
6395 #define mmCRTC3_CRTC_H_SYNC_A_BASE_IDX                                                                 2
6396 #define mmCRTC3_CRTC_H_SYNC_A_CNTL                                                                     0x0cd6
6397 #define mmCRTC3_CRTC_H_SYNC_A_CNTL_BASE_IDX                                                            2
6398 #define mmCRTC3_CRTC_H_SYNC_B                                                                          0x0cd7
6399 #define mmCRTC3_CRTC_H_SYNC_B_BASE_IDX                                                                 2
6400 #define mmCRTC3_CRTC_H_SYNC_B_CNTL                                                                     0x0cd8
6401 #define mmCRTC3_CRTC_H_SYNC_B_CNTL_BASE_IDX                                                            2
6402 #define mmCRTC3_CRTC_VBI_END                                                                           0x0cd9
6403 #define mmCRTC3_CRTC_VBI_END_BASE_IDX                                                                  2
6404 #define mmCRTC3_CRTC_V_TOTAL                                                                           0x0cda
6405 #define mmCRTC3_CRTC_V_TOTAL_BASE_IDX                                                                  2
6406 #define mmCRTC3_CRTC_V_TOTAL_MIN                                                                       0x0cdb
6407 #define mmCRTC3_CRTC_V_TOTAL_MIN_BASE_IDX                                                              2
6408 #define mmCRTC3_CRTC_V_TOTAL_MAX                                                                       0x0cdc
6409 #define mmCRTC3_CRTC_V_TOTAL_MAX_BASE_IDX                                                              2
6410 #define mmCRTC3_CRTC_V_TOTAL_CONTROL                                                                   0x0cdd
6411 #define mmCRTC3_CRTC_V_TOTAL_CONTROL_BASE_IDX                                                          2
6412 #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS                                                                0x0cde
6413 #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_BASE_IDX                                                       2
6414 #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS                                                              0x0cdf
6415 #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX                                                     2
6416 #define mmCRTC3_CRTC_V_BLANK_START_END                                                                 0x0ce0
6417 #define mmCRTC3_CRTC_V_BLANK_START_END_BASE_IDX                                                        2
6418 #define mmCRTC3_CRTC_V_SYNC_A                                                                          0x0ce1
6419 #define mmCRTC3_CRTC_V_SYNC_A_BASE_IDX                                                                 2
6420 #define mmCRTC3_CRTC_V_SYNC_A_CNTL                                                                     0x0ce2
6421 #define mmCRTC3_CRTC_V_SYNC_A_CNTL_BASE_IDX                                                            2
6422 #define mmCRTC3_CRTC_V_SYNC_B                                                                          0x0ce3
6423 #define mmCRTC3_CRTC_V_SYNC_B_BASE_IDX                                                                 2
6424 #define mmCRTC3_CRTC_V_SYNC_B_CNTL                                                                     0x0ce4
6425 #define mmCRTC3_CRTC_V_SYNC_B_CNTL_BASE_IDX                                                            2
6426 #define mmCRTC3_CRTC_DTMTEST_CNTL                                                                      0x0ce5
6427 #define mmCRTC3_CRTC_DTMTEST_CNTL_BASE_IDX                                                             2
6428 #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION                                                           0x0ce6
6429 #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX                                                  2
6430 #define mmCRTC3_CRTC_TRIGA_CNTL                                                                        0x0ce7
6431 #define mmCRTC3_CRTC_TRIGA_CNTL_BASE_IDX                                                               2
6432 #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG                                                                 0x0ce8
6433 #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX                                                        2
6434 #define mmCRTC3_CRTC_TRIGB_CNTL                                                                        0x0ce9
6435 #define mmCRTC3_CRTC_TRIGB_CNTL_BASE_IDX                                                               2
6436 #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG                                                                 0x0cea
6437 #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX                                                        2
6438 #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL                                                              0x0ceb
6439 #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                     2
6440 #define mmCRTC3_CRTC_FLOW_CONTROL                                                                      0x0cec
6441 #define mmCRTC3_CRTC_FLOW_CONTROL_BASE_IDX                                                             2
6442 #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE                                                             0x0ced
6443 #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                    2
6444 #define mmCRTC3_CRTC_AVSYNC_COUNTER                                                                    0x0cee
6445 #define mmCRTC3_CRTC_AVSYNC_COUNTER_BASE_IDX                                                           2
6446 #define mmCRTC3_CRTC_CONTROL                                                                           0x0cef
6447 #define mmCRTC3_CRTC_CONTROL_BASE_IDX                                                                  2
6448 #define mmCRTC3_CRTC_BLANK_CONTROL                                                                     0x0cf0
6449 #define mmCRTC3_CRTC_BLANK_CONTROL_BASE_IDX                                                            2
6450 #define mmCRTC3_CRTC_INTERLACE_CONTROL                                                                 0x0cf1
6451 #define mmCRTC3_CRTC_INTERLACE_CONTROL_BASE_IDX                                                        2
6452 #define mmCRTC3_CRTC_INTERLACE_STATUS                                                                  0x0cf2
6453 #define mmCRTC3_CRTC_INTERLACE_STATUS_BASE_IDX                                                         2
6454 #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL                                                          0x0cf3
6455 #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX                                                 2
6456 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0                                                              0x0cf4
6457 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_BASE_IDX                                                     2
6458 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1                                                              0x0cf5
6459 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_BASE_IDX                                                     2
6460 #define mmCRTC3_CRTC_STATUS                                                                            0x0cf6
6461 #define mmCRTC3_CRTC_STATUS_BASE_IDX                                                                   2
6462 #define mmCRTC3_CRTC_STATUS_POSITION                                                                   0x0cf7
6463 #define mmCRTC3_CRTC_STATUS_POSITION_BASE_IDX                                                          2
6464 #define mmCRTC3_CRTC_NOM_VERT_POSITION                                                                 0x0cf8
6465 #define mmCRTC3_CRTC_NOM_VERT_POSITION_BASE_IDX                                                        2
6466 #define mmCRTC3_CRTC_STATUS_FRAME_COUNT                                                                0x0cf9
6467 #define mmCRTC3_CRTC_STATUS_FRAME_COUNT_BASE_IDX                                                       2
6468 #define mmCRTC3_CRTC_STATUS_VF_COUNT                                                                   0x0cfa
6469 #define mmCRTC3_CRTC_STATUS_VF_COUNT_BASE_IDX                                                          2
6470 #define mmCRTC3_CRTC_STATUS_HV_COUNT                                                                   0x0cfb
6471 #define mmCRTC3_CRTC_STATUS_HV_COUNT_BASE_IDX                                                          2
6472 #define mmCRTC3_CRTC_COUNT_CONTROL                                                                     0x0cfc
6473 #define mmCRTC3_CRTC_COUNT_CONTROL_BASE_IDX                                                            2
6474 #define mmCRTC3_CRTC_COUNT_RESET                                                                       0x0cfd
6475 #define mmCRTC3_CRTC_COUNT_RESET_BASE_IDX                                                              2
6476 #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                                      0x0cfe
6477 #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                             2
6478 #define mmCRTC3_CRTC_VERT_SYNC_CONTROL                                                                 0x0cff
6479 #define mmCRTC3_CRTC_VERT_SYNC_CONTROL_BASE_IDX                                                        2
6480 #define mmCRTC3_CRTC_STEREO_STATUS                                                                     0x0d00
6481 #define mmCRTC3_CRTC_STEREO_STATUS_BASE_IDX                                                            2
6482 #define mmCRTC3_CRTC_STEREO_CONTROL                                                                    0x0d01
6483 #define mmCRTC3_CRTC_STEREO_CONTROL_BASE_IDX                                                           2
6484 #define mmCRTC3_CRTC_SNAPSHOT_STATUS                                                                   0x0d02
6485 #define mmCRTC3_CRTC_SNAPSHOT_STATUS_BASE_IDX                                                          2
6486 #define mmCRTC3_CRTC_SNAPSHOT_CONTROL                                                                  0x0d03
6487 #define mmCRTC3_CRTC_SNAPSHOT_CONTROL_BASE_IDX                                                         2
6488 #define mmCRTC3_CRTC_SNAPSHOT_POSITION                                                                 0x0d04
6489 #define mmCRTC3_CRTC_SNAPSHOT_POSITION_BASE_IDX                                                        2
6490 #define mmCRTC3_CRTC_SNAPSHOT_FRAME                                                                    0x0d05
6491 #define mmCRTC3_CRTC_SNAPSHOT_FRAME_BASE_IDX                                                           2
6492 #define mmCRTC3_CRTC_START_LINE_CONTROL                                                                0x0d06
6493 #define mmCRTC3_CRTC_START_LINE_CONTROL_BASE_IDX                                                       2
6494 #define mmCRTC3_CRTC_INTERRUPT_CONTROL                                                                 0x0d07
6495 #define mmCRTC3_CRTC_INTERRUPT_CONTROL_BASE_IDX                                                        2
6496 #define mmCRTC3_CRTC_UPDATE_LOCK                                                                       0x0d08
6497 #define mmCRTC3_CRTC_UPDATE_LOCK_BASE_IDX                                                              2
6498 #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL                                                             0x0d09
6499 #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                    2
6500 #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE                                                        0x0d0a
6501 #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX                                               2
6502 #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL                                                              0x0d0b
6503 #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_BASE_IDX                                                     2
6504 #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS                                                           0x0d0c
6505 #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX                                                  2
6506 #define mmCRTC3_CRTC_TEST_PATTERN_COLOR                                                                0x0d0d
6507 #define mmCRTC3_CRTC_TEST_PATTERN_COLOR_BASE_IDX                                                       2
6508 #define mmCRTC3_CRTC_MASTER_UPDATE_LOCK                                                                0x0d0e
6509 #define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_BASE_IDX                                                       2
6510 #define mmCRTC3_CRTC_MASTER_UPDATE_MODE                                                                0x0d0f
6511 #define mmCRTC3_CRTC_MASTER_UPDATE_MODE_BASE_IDX                                                       2
6512 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT                                                            0x0d10
6513 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX                                                   2
6514 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                                                      0x0d11
6515 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX                                             2
6516 #define mmCRTC3_CRTC_MVP_STATUS                                                                        0x0d12
6517 #define mmCRTC3_CRTC_MVP_STATUS_BASE_IDX                                                               2
6518 #define mmCRTC3_CRTC_MASTER_EN                                                                         0x0d13
6519 #define mmCRTC3_CRTC_MASTER_EN_BASE_IDX                                                                2
6520 #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT                                                              0x0d14
6521 #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX                                                     2
6522 #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS                                                               0x0d15
6523 #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_BASE_IDX                                                      2
6524 #define mmCRTC3_CRTC_OVERSCAN_COLOR                                                                    0x0d17
6525 #define mmCRTC3_CRTC_OVERSCAN_COLOR_BASE_IDX                                                           2
6526 #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT                                                                0x0d18
6527 #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX                                                       2
6528 #define mmCRTC3_CRTC_BLANK_DATA_COLOR                                                                  0x0d19
6529 #define mmCRTC3_CRTC_BLANK_DATA_COLOR_BASE_IDX                                                         2
6530 #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT                                                              0x0d1a
6531 #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX                                                     2
6532 #define mmCRTC3_CRTC_BLACK_COLOR                                                                       0x0d1b
6533 #define mmCRTC3_CRTC_BLACK_COLOR_BASE_IDX                                                              2
6534 #define mmCRTC3_CRTC_BLACK_COLOR_EXT                                                                   0x0d1c
6535 #define mmCRTC3_CRTC_BLACK_COLOR_EXT_BASE_IDX                                                          2
6536 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION                                                      0x0d1d
6537 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                             2
6538 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL                                                       0x0d1e
6539 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                              2
6540 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION                                                      0x0d1f
6541 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                             2
6542 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL                                                       0x0d20
6543 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                              2
6544 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION                                                      0x0d21
6545 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                             2
6546 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL                                                       0x0d22
6547 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                              2
6548 #define mmCRTC3_CRTC_CRC_CNTL                                                                          0x0d23
6549 #define mmCRTC3_CRTC_CRC_CNTL_BASE_IDX                                                                 2
6550 #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL                                                            0x0d24
6551 #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                   2
6552 #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL                                                            0x0d25
6553 #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
6554 #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL                                                            0x0d26
6555 #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                   2
6556 #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL                                                            0x0d27
6557 #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
6558 #define mmCRTC3_CRTC_CRC0_DATA_RG                                                                      0x0d28
6559 #define mmCRTC3_CRTC_CRC0_DATA_RG_BASE_IDX                                                             2
6560 #define mmCRTC3_CRTC_CRC0_DATA_B                                                                       0x0d29
6561 #define mmCRTC3_CRTC_CRC0_DATA_B_BASE_IDX                                                              2
6562 #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL                                                            0x0d2a
6563 #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                   2
6564 #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL                                                            0x0d2b
6565 #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
6566 #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL                                                            0x0d2c
6567 #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                   2
6568 #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL                                                            0x0d2d
6569 #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
6570 #define mmCRTC3_CRTC_CRC1_DATA_RG                                                                      0x0d2e
6571 #define mmCRTC3_CRTC_CRC1_DATA_RG_BASE_IDX                                                             2
6572 #define mmCRTC3_CRTC_CRC1_DATA_B                                                                       0x0d2f
6573 #define mmCRTC3_CRTC_CRC1_DATA_B_BASE_IDX                                                              2
6574 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL                                                           0x0d30
6575 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX                                                  2
6576 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START                                                      0x0d31
6577 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX                                             2
6578 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END                                                        0x0d32
6579 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX                                               2
6580 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                                            0x0d33
6581 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX                                   2
6582 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                                 0x0d34
6583 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX                                        2
6584 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                                          0x0d35
6585 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX                                 2
6586 #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL                                                             0x0d36
6587 #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX                                                    2
6588 #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL                                                              0x0d37
6589 #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX                                                     2
6590 #define mmCRTC3_CRTC_GSL_VSYNC_GAP                                                                     0x0d38
6591 #define mmCRTC3_CRTC_GSL_VSYNC_GAP_BASE_IDX                                                            2
6592 #define mmCRTC3_CRTC_GSL_WINDOW                                                                        0x0d39
6593 #define mmCRTC3_CRTC_GSL_WINDOW_BASE_IDX                                                               2
6594 #define mmCRTC3_CRTC_GSL_CONTROL                                                                       0x0d3a
6595 #define mmCRTC3_CRTC_GSL_CONTROL_BASE_IDX                                                              2
6596 #define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS                                                           0x0d3d
6597 #define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX                                                  2
6598 #define mmCRTC3_CRTC_DRR_CONTROL                                                                       0x0d3e
6599 #define mmCRTC3_CRTC_DRR_CONTROL_BASE_IDX                                                              2
6600 
6601 
6602 // addressBlock: dce_dc_fmt3_dispdec
6603 // base address: 0x1800
6604 #define mmFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x0d42
6605 #define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
6606 #define mmFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x0d43
6607 #define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
6608 #define mmFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x0d44
6609 #define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
6610 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x0d45
6611 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
6612 #define mmFMT3_FMT_CONTROL                                                                             0x0d46
6613 #define mmFMT3_FMT_CONTROL_BASE_IDX                                                                    2
6614 #define mmFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x0d47
6615 #define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
6616 #define mmFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x0d48
6617 #define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
6618 #define mmFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x0d49
6619 #define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
6620 #define mmFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x0d4a
6621 #define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
6622 #define mmFMT3_FMT_CLAMP_CNTL                                                                          0x0d4e
6623 #define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
6624 #define mmFMT3_FMT_CRC_CNTL                                                                            0x0d4f
6625 #define mmFMT3_FMT_CRC_CNTL_BASE_IDX                                                                   2
6626 #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK                                                              0x0d50
6627 #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
6628 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK                                                           0x0d51
6629 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
6630 #define mmFMT3_FMT_CRC_SIG_RED_GREEN                                                                   0x0d52
6631 #define mmFMT3_FMT_CRC_SIG_RED_GREEN_BASE_IDX                                                          2
6632 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL                                                                0x0d53
6633 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX                                                       2
6634 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x0d54
6635 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
6636 #define mmFMT3_FMT_420_HBLANK_EARLY_START                                                              0x0d55
6637 #define mmFMT3_FMT_420_HBLANK_EARLY_START_BASE_IDX                                                     2
6638 
6639 
6640 // addressBlock: dce_dc_dcp4_dispdec
6641 // base address: 0x2000
6642 #define mmDCP4_GRPH_ENABLE                                                                             0x0d5a
6643 #define mmDCP4_GRPH_ENABLE_BASE_IDX                                                                    2
6644 #define mmDCP4_GRPH_CONTROL                                                                            0x0d5b
6645 #define mmDCP4_GRPH_CONTROL_BASE_IDX                                                                   2
6646 #define mmDCP4_GRPH_LUT_10BIT_BYPASS                                                                   0x0d5c
6647 #define mmDCP4_GRPH_LUT_10BIT_BYPASS_BASE_IDX                                                          2
6648 #define mmDCP4_GRPH_SWAP_CNTL                                                                          0x0d5d
6649 #define mmDCP4_GRPH_SWAP_CNTL_BASE_IDX                                                                 2
6650 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS                                                            0x0d5e
6651 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                                   2
6652 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS                                                          0x0d5f
6653 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                                 2
6654 #define mmDCP4_GRPH_PITCH                                                                              0x0d60
6655 #define mmDCP4_GRPH_PITCH_BASE_IDX                                                                     2
6656 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                                       0x0d61
6657 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                              2
6658 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                                     0x0d62
6659 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                            2
6660 #define mmDCP4_GRPH_SURFACE_OFFSET_X                                                                   0x0d63
6661 #define mmDCP4_GRPH_SURFACE_OFFSET_X_BASE_IDX                                                          2
6662 #define mmDCP4_GRPH_SURFACE_OFFSET_Y                                                                   0x0d64
6663 #define mmDCP4_GRPH_SURFACE_OFFSET_Y_BASE_IDX                                                          2
6664 #define mmDCP4_GRPH_X_START                                                                            0x0d65
6665 #define mmDCP4_GRPH_X_START_BASE_IDX                                                                   2
6666 #define mmDCP4_GRPH_Y_START                                                                            0x0d66
6667 #define mmDCP4_GRPH_Y_START_BASE_IDX                                                                   2
6668 #define mmDCP4_GRPH_X_END                                                                              0x0d67
6669 #define mmDCP4_GRPH_X_END_BASE_IDX                                                                     2
6670 #define mmDCP4_GRPH_Y_END                                                                              0x0d68
6671 #define mmDCP4_GRPH_Y_END_BASE_IDX                                                                     2
6672 #define mmDCP4_INPUT_GAMMA_CONTROL                                                                     0x0d69
6673 #define mmDCP4_INPUT_GAMMA_CONTROL_BASE_IDX                                                            2
6674 #define mmDCP4_GRPH_UPDATE                                                                             0x0d6a
6675 #define mmDCP4_GRPH_UPDATE_BASE_IDX                                                                    2
6676 #define mmDCP4_GRPH_FLIP_CONTROL                                                                       0x0d6b
6677 #define mmDCP4_GRPH_FLIP_CONTROL_BASE_IDX                                                              2
6678 #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE                                                              0x0d6c
6679 #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX                                                     2
6680 #define mmDCP4_GRPH_DFQ_CONTROL                                                                        0x0d6d
6681 #define mmDCP4_GRPH_DFQ_CONTROL_BASE_IDX                                                               2
6682 #define mmDCP4_GRPH_DFQ_STATUS                                                                         0x0d6e
6683 #define mmDCP4_GRPH_DFQ_STATUS_BASE_IDX                                                                2
6684 #define mmDCP4_GRPH_INTERRUPT_STATUS                                                                   0x0d6f
6685 #define mmDCP4_GRPH_INTERRUPT_STATUS_BASE_IDX                                                          2
6686 #define mmDCP4_GRPH_INTERRUPT_CONTROL                                                                  0x0d70
6687 #define mmDCP4_GRPH_INTERRUPT_CONTROL_BASE_IDX                                                         2
6688 #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                                         0x0d71
6689 #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX                                                2
6690 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS                                                           0x0d72
6691 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX                                                  2
6692 #define mmDCP4_GRPH_COMPRESS_PITCH                                                                     0x0d73
6693 #define mmDCP4_GRPH_COMPRESS_PITCH_BASE_IDX                                                            2
6694 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                                      0x0d74
6695 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX                                             2
6696 #define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                                                     0x0d75
6697 #define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX                                            2
6698 #define mmDCP4_PRESCALE_GRPH_CONTROL                                                                   0x0d76
6699 #define mmDCP4_PRESCALE_GRPH_CONTROL_BASE_IDX                                                          2
6700 #define mmDCP4_PRESCALE_VALUES_GRPH_R                                                                  0x0d77
6701 #define mmDCP4_PRESCALE_VALUES_GRPH_R_BASE_IDX                                                         2
6702 #define mmDCP4_PRESCALE_VALUES_GRPH_G                                                                  0x0d78
6703 #define mmDCP4_PRESCALE_VALUES_GRPH_G_BASE_IDX                                                         2
6704 #define mmDCP4_PRESCALE_VALUES_GRPH_B                                                                  0x0d79
6705 #define mmDCP4_PRESCALE_VALUES_GRPH_B_BASE_IDX                                                         2
6706 #define mmDCP4_INPUT_CSC_CONTROL                                                                       0x0d7a
6707 #define mmDCP4_INPUT_CSC_CONTROL_BASE_IDX                                                              2
6708 #define mmDCP4_INPUT_CSC_C11_C12                                                                       0x0d7b
6709 #define mmDCP4_INPUT_CSC_C11_C12_BASE_IDX                                                              2
6710 #define mmDCP4_INPUT_CSC_C13_C14                                                                       0x0d7c
6711 #define mmDCP4_INPUT_CSC_C13_C14_BASE_IDX                                                              2
6712 #define mmDCP4_INPUT_CSC_C21_C22                                                                       0x0d7d
6713 #define mmDCP4_INPUT_CSC_C21_C22_BASE_IDX                                                              2
6714 #define mmDCP4_INPUT_CSC_C23_C24                                                                       0x0d7e
6715 #define mmDCP4_INPUT_CSC_C23_C24_BASE_IDX                                                              2
6716 #define mmDCP4_INPUT_CSC_C31_C32                                                                       0x0d7f
6717 #define mmDCP4_INPUT_CSC_C31_C32_BASE_IDX                                                              2
6718 #define mmDCP4_INPUT_CSC_C33_C34                                                                       0x0d80
6719 #define mmDCP4_INPUT_CSC_C33_C34_BASE_IDX                                                              2
6720 #define mmDCP4_OUTPUT_CSC_CONTROL                                                                      0x0d81
6721 #define mmDCP4_OUTPUT_CSC_CONTROL_BASE_IDX                                                             2
6722 #define mmDCP4_OUTPUT_CSC_C11_C12                                                                      0x0d82
6723 #define mmDCP4_OUTPUT_CSC_C11_C12_BASE_IDX                                                             2
6724 #define mmDCP4_OUTPUT_CSC_C13_C14                                                                      0x0d83
6725 #define mmDCP4_OUTPUT_CSC_C13_C14_BASE_IDX                                                             2
6726 #define mmDCP4_OUTPUT_CSC_C21_C22                                                                      0x0d84
6727 #define mmDCP4_OUTPUT_CSC_C21_C22_BASE_IDX                                                             2
6728 #define mmDCP4_OUTPUT_CSC_C23_C24                                                                      0x0d85
6729 #define mmDCP4_OUTPUT_CSC_C23_C24_BASE_IDX                                                             2
6730 #define mmDCP4_OUTPUT_CSC_C31_C32                                                                      0x0d86
6731 #define mmDCP4_OUTPUT_CSC_C31_C32_BASE_IDX                                                             2
6732 #define mmDCP4_OUTPUT_CSC_C33_C34                                                                      0x0d87
6733 #define mmDCP4_OUTPUT_CSC_C33_C34_BASE_IDX                                                             2
6734 #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12                                                              0x0d88
6735 #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX                                                     2
6736 #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14                                                              0x0d89
6737 #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX                                                     2
6738 #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22                                                              0x0d8a
6739 #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX                                                     2
6740 #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24                                                              0x0d8b
6741 #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX                                                     2
6742 #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32                                                              0x0d8c
6743 #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX                                                     2
6744 #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34                                                              0x0d8d
6745 #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX                                                     2
6746 #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12                                                              0x0d8e
6747 #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX                                                     2
6748 #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14                                                              0x0d8f
6749 #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX                                                     2
6750 #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22                                                              0x0d90
6751 #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX                                                     2
6752 #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24                                                              0x0d91
6753 #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX                                                     2
6754 #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32                                                              0x0d92
6755 #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX                                                     2
6756 #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34                                                              0x0d93
6757 #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX                                                     2
6758 #define mmDCP4_DENORM_CONTROL                                                                          0x0d94
6759 #define mmDCP4_DENORM_CONTROL_BASE_IDX                                                                 2
6760 #define mmDCP4_OUT_ROUND_CONTROL                                                                       0x0d95
6761 #define mmDCP4_OUT_ROUND_CONTROL_BASE_IDX                                                              2
6762 #define mmDCP4_OUT_CLAMP_CONTROL_R_CR                                                                  0x0d96
6763 #define mmDCP4_OUT_CLAMP_CONTROL_R_CR_BASE_IDX                                                         2
6764 #define mmDCP4_OUT_CLAMP_CONTROL_G_Y                                                                   0x0d97
6765 #define mmDCP4_OUT_CLAMP_CONTROL_G_Y_BASE_IDX                                                          2
6766 #define mmDCP4_OUT_CLAMP_CONTROL_B_CB                                                                  0x0d98
6767 #define mmDCP4_OUT_CLAMP_CONTROL_B_CB_BASE_IDX                                                         2
6768 #define mmDCP4_KEY_CONTROL                                                                             0x0d99
6769 #define mmDCP4_KEY_CONTROL_BASE_IDX                                                                    2
6770 #define mmDCP4_KEY_RANGE_ALPHA                                                                         0x0d9a
6771 #define mmDCP4_KEY_RANGE_ALPHA_BASE_IDX                                                                2
6772 #define mmDCP4_KEY_RANGE_RED                                                                           0x0d9b
6773 #define mmDCP4_KEY_RANGE_RED_BASE_IDX                                                                  2
6774 #define mmDCP4_KEY_RANGE_GREEN                                                                         0x0d9c
6775 #define mmDCP4_KEY_RANGE_GREEN_BASE_IDX                                                                2
6776 #define mmDCP4_KEY_RANGE_BLUE                                                                          0x0d9d
6777 #define mmDCP4_KEY_RANGE_BLUE_BASE_IDX                                                                 2
6778 #define mmDCP4_DEGAMMA_CONTROL                                                                         0x0d9e
6779 #define mmDCP4_DEGAMMA_CONTROL_BASE_IDX                                                                2
6780 #define mmDCP4_GAMUT_REMAP_CONTROL                                                                     0x0d9f
6781 #define mmDCP4_GAMUT_REMAP_CONTROL_BASE_IDX                                                            2
6782 #define mmDCP4_GAMUT_REMAP_C11_C12                                                                     0x0da0
6783 #define mmDCP4_GAMUT_REMAP_C11_C12_BASE_IDX                                                            2
6784 #define mmDCP4_GAMUT_REMAP_C13_C14                                                                     0x0da1
6785 #define mmDCP4_GAMUT_REMAP_C13_C14_BASE_IDX                                                            2
6786 #define mmDCP4_GAMUT_REMAP_C21_C22                                                                     0x0da2
6787 #define mmDCP4_GAMUT_REMAP_C21_C22_BASE_IDX                                                            2
6788 #define mmDCP4_GAMUT_REMAP_C23_C24                                                                     0x0da3
6789 #define mmDCP4_GAMUT_REMAP_C23_C24_BASE_IDX                                                            2
6790 #define mmDCP4_GAMUT_REMAP_C31_C32                                                                     0x0da4
6791 #define mmDCP4_GAMUT_REMAP_C31_C32_BASE_IDX                                                            2
6792 #define mmDCP4_GAMUT_REMAP_C33_C34                                                                     0x0da5
6793 #define mmDCP4_GAMUT_REMAP_C33_C34_BASE_IDX                                                            2
6794 #define mmDCP4_DCP_SPATIAL_DITHER_CNTL                                                                 0x0da6
6795 #define mmDCP4_DCP_SPATIAL_DITHER_CNTL_BASE_IDX                                                        2
6796 #define mmDCP4_DCP_RANDOM_SEEDS                                                                        0x0da7
6797 #define mmDCP4_DCP_RANDOM_SEEDS_BASE_IDX                                                               2
6798 #define mmDCP4_DCP_FP_CONVERTED_FIELD                                                                  0x0da8
6799 #define mmDCP4_DCP_FP_CONVERTED_FIELD_BASE_IDX                                                         2
6800 #define mmDCP4_CUR_CONTROL                                                                             0x0da9
6801 #define mmDCP4_CUR_CONTROL_BASE_IDX                                                                    2
6802 #define mmDCP4_CUR_SURFACE_ADDRESS                                                                     0x0daa
6803 #define mmDCP4_CUR_SURFACE_ADDRESS_BASE_IDX                                                            2
6804 #define mmDCP4_CUR_SIZE                                                                                0x0dab
6805 #define mmDCP4_CUR_SIZE_BASE_IDX                                                                       2
6806 #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH                                                                0x0dac
6807 #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX                                                       2
6808 #define mmDCP4_CUR_POSITION                                                                            0x0dad
6809 #define mmDCP4_CUR_POSITION_BASE_IDX                                                                   2
6810 #define mmDCP4_CUR_HOT_SPOT                                                                            0x0dae
6811 #define mmDCP4_CUR_HOT_SPOT_BASE_IDX                                                                   2
6812 #define mmDCP4_CUR_COLOR1                                                                              0x0daf
6813 #define mmDCP4_CUR_COLOR1_BASE_IDX                                                                     2
6814 #define mmDCP4_CUR_COLOR2                                                                              0x0db0
6815 #define mmDCP4_CUR_COLOR2_BASE_IDX                                                                     2
6816 #define mmDCP4_CUR_UPDATE                                                                              0x0db1
6817 #define mmDCP4_CUR_UPDATE_BASE_IDX                                                                     2
6818 #define mmDCP4_CUR_REQUEST_FILTER_CNTL                                                                 0x0dbb
6819 #define mmDCP4_CUR_REQUEST_FILTER_CNTL_BASE_IDX                                                        2
6820 #define mmDCP4_CUR_STEREO_CONTROL                                                                      0x0dbc
6821 #define mmDCP4_CUR_STEREO_CONTROL_BASE_IDX                                                             2
6822 #define mmDCP4_DC_LUT_RW_MODE                                                                          0x0dbe
6823 #define mmDCP4_DC_LUT_RW_MODE_BASE_IDX                                                                 2
6824 #define mmDCP4_DC_LUT_RW_INDEX                                                                         0x0dbf
6825 #define mmDCP4_DC_LUT_RW_INDEX_BASE_IDX                                                                2
6826 #define mmDCP4_DC_LUT_SEQ_COLOR                                                                        0x0dc0
6827 #define mmDCP4_DC_LUT_SEQ_COLOR_BASE_IDX                                                               2
6828 #define mmDCP4_DC_LUT_PWL_DATA                                                                         0x0dc1
6829 #define mmDCP4_DC_LUT_PWL_DATA_BASE_IDX                                                                2
6830 #define mmDCP4_DC_LUT_30_COLOR                                                                         0x0dc2
6831 #define mmDCP4_DC_LUT_30_COLOR_BASE_IDX                                                                2
6832 #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE                                                                0x0dc3
6833 #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX                                                       2
6834 #define mmDCP4_DC_LUT_WRITE_EN_MASK                                                                    0x0dc4
6835 #define mmDCP4_DC_LUT_WRITE_EN_MASK_BASE_IDX                                                           2
6836 #define mmDCP4_DC_LUT_AUTOFILL                                                                         0x0dc5
6837 #define mmDCP4_DC_LUT_AUTOFILL_BASE_IDX                                                                2
6838 #define mmDCP4_DC_LUT_CONTROL                                                                          0x0dc6
6839 #define mmDCP4_DC_LUT_CONTROL_BASE_IDX                                                                 2
6840 #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE                                                                0x0dc7
6841 #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX                                                       2
6842 #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN                                                               0x0dc8
6843 #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX                                                      2
6844 #define mmDCP4_DC_LUT_BLACK_OFFSET_RED                                                                 0x0dc9
6845 #define mmDCP4_DC_LUT_BLACK_OFFSET_RED_BASE_IDX                                                        2
6846 #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE                                                                0x0dca
6847 #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX                                                       2
6848 #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN                                                               0x0dcb
6849 #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX                                                      2
6850 #define mmDCP4_DC_LUT_WHITE_OFFSET_RED                                                                 0x0dcc
6851 #define mmDCP4_DC_LUT_WHITE_OFFSET_RED_BASE_IDX                                                        2
6852 #define mmDCP4_DCP_CRC_CONTROL                                                                         0x0dcd
6853 #define mmDCP4_DCP_CRC_CONTROL_BASE_IDX                                                                2
6854 #define mmDCP4_DCP_CRC_MASK                                                                            0x0dce
6855 #define mmDCP4_DCP_CRC_MASK_BASE_IDX                                                                   2
6856 #define mmDCP4_DCP_CRC_CURRENT                                                                         0x0dcf
6857 #define mmDCP4_DCP_CRC_CURRENT_BASE_IDX                                                                2
6858 #define mmDCP4_DVMM_PTE_CONTROL                                                                        0x0dd0
6859 #define mmDCP4_DVMM_PTE_CONTROL_BASE_IDX                                                               2
6860 #define mmDCP4_DCP_CRC_LAST                                                                            0x0dd1
6861 #define mmDCP4_DCP_CRC_LAST_BASE_IDX                                                                   2
6862 #define mmDCP4_DVMM_PTE_ARB_CONTROL                                                                    0x0dd2
6863 #define mmDCP4_DVMM_PTE_ARB_CONTROL_BASE_IDX                                                           2
6864 #define mmDCP4_GRPH_FLIP_RATE_CNTL                                                                     0x0dd4
6865 #define mmDCP4_GRPH_FLIP_RATE_CNTL_BASE_IDX                                                            2
6866 #define mmDCP4_DCP_GSL_CONTROL                                                                         0x0dd5
6867 #define mmDCP4_DCP_GSL_CONTROL_BASE_IDX                                                                2
6868 #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                                           0x0dd6
6869 #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX                                                  2
6870 #define mmDCP4_GRPH_STEREOSYNC_FLIP                                                                    0x0ddc
6871 #define mmDCP4_GRPH_STEREOSYNC_FLIP_BASE_IDX                                                           2
6872 #define mmDCP4_HW_ROTATION                                                                             0x0dde
6873 #define mmDCP4_HW_ROTATION_BASE_IDX                                                                    2
6874 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                                      0x0ddf
6875 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX                                             2
6876 #define mmDCP4_REGAMMA_CONTROL                                                                         0x0de0
6877 #define mmDCP4_REGAMMA_CONTROL_BASE_IDX                                                                2
6878 #define mmDCP4_REGAMMA_LUT_INDEX                                                                       0x0de1
6879 #define mmDCP4_REGAMMA_LUT_INDEX_BASE_IDX                                                              2
6880 #define mmDCP4_REGAMMA_LUT_DATA                                                                        0x0de2
6881 #define mmDCP4_REGAMMA_LUT_DATA_BASE_IDX                                                               2
6882 #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK                                                               0x0de3
6883 #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX                                                      2
6884 #define mmDCP4_REGAMMA_CNTLA_START_CNTL                                                                0x0de4
6885 #define mmDCP4_REGAMMA_CNTLA_START_CNTL_BASE_IDX                                                       2
6886 #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL                                                                0x0de5
6887 #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX                                                       2
6888 #define mmDCP4_REGAMMA_CNTLA_END_CNTL1                                                                 0x0de6
6889 #define mmDCP4_REGAMMA_CNTLA_END_CNTL1_BASE_IDX                                                        2
6890 #define mmDCP4_REGAMMA_CNTLA_END_CNTL2                                                                 0x0de7
6891 #define mmDCP4_REGAMMA_CNTLA_END_CNTL2_BASE_IDX                                                        2
6892 #define mmDCP4_REGAMMA_CNTLA_REGION_0_1                                                                0x0de8
6893 #define mmDCP4_REGAMMA_CNTLA_REGION_0_1_BASE_IDX                                                       2
6894 #define mmDCP4_REGAMMA_CNTLA_REGION_2_3                                                                0x0de9
6895 #define mmDCP4_REGAMMA_CNTLA_REGION_2_3_BASE_IDX                                                       2
6896 #define mmDCP4_REGAMMA_CNTLA_REGION_4_5                                                                0x0dea
6897 #define mmDCP4_REGAMMA_CNTLA_REGION_4_5_BASE_IDX                                                       2
6898 #define mmDCP4_REGAMMA_CNTLA_REGION_6_7                                                                0x0deb
6899 #define mmDCP4_REGAMMA_CNTLA_REGION_6_7_BASE_IDX                                                       2
6900 #define mmDCP4_REGAMMA_CNTLA_REGION_8_9                                                                0x0dec
6901 #define mmDCP4_REGAMMA_CNTLA_REGION_8_9_BASE_IDX                                                       2
6902 #define mmDCP4_REGAMMA_CNTLA_REGION_10_11                                                              0x0ded
6903 #define mmDCP4_REGAMMA_CNTLA_REGION_10_11_BASE_IDX                                                     2
6904 #define mmDCP4_REGAMMA_CNTLA_REGION_12_13                                                              0x0dee
6905 #define mmDCP4_REGAMMA_CNTLA_REGION_12_13_BASE_IDX                                                     2
6906 #define mmDCP4_REGAMMA_CNTLA_REGION_14_15                                                              0x0def
6907 #define mmDCP4_REGAMMA_CNTLA_REGION_14_15_BASE_IDX                                                     2
6908 #define mmDCP4_REGAMMA_CNTLB_START_CNTL                                                                0x0df0
6909 #define mmDCP4_REGAMMA_CNTLB_START_CNTL_BASE_IDX                                                       2
6910 #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL                                                                0x0df1
6911 #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX                                                       2
6912 #define mmDCP4_REGAMMA_CNTLB_END_CNTL1                                                                 0x0df2
6913 #define mmDCP4_REGAMMA_CNTLB_END_CNTL1_BASE_IDX                                                        2
6914 #define mmDCP4_REGAMMA_CNTLB_END_CNTL2                                                                 0x0df3
6915 #define mmDCP4_REGAMMA_CNTLB_END_CNTL2_BASE_IDX                                                        2
6916 #define mmDCP4_REGAMMA_CNTLB_REGION_0_1                                                                0x0df4
6917 #define mmDCP4_REGAMMA_CNTLB_REGION_0_1_BASE_IDX                                                       2
6918 #define mmDCP4_REGAMMA_CNTLB_REGION_2_3                                                                0x0df5
6919 #define mmDCP4_REGAMMA_CNTLB_REGION_2_3_BASE_IDX                                                       2
6920 #define mmDCP4_REGAMMA_CNTLB_REGION_4_5                                                                0x0df6
6921 #define mmDCP4_REGAMMA_CNTLB_REGION_4_5_BASE_IDX                                                       2
6922 #define mmDCP4_REGAMMA_CNTLB_REGION_6_7                                                                0x0df7
6923 #define mmDCP4_REGAMMA_CNTLB_REGION_6_7_BASE_IDX                                                       2
6924 #define mmDCP4_REGAMMA_CNTLB_REGION_8_9                                                                0x0df8
6925 #define mmDCP4_REGAMMA_CNTLB_REGION_8_9_BASE_IDX                                                       2
6926 #define mmDCP4_REGAMMA_CNTLB_REGION_10_11                                                              0x0df9
6927 #define mmDCP4_REGAMMA_CNTLB_REGION_10_11_BASE_IDX                                                     2
6928 #define mmDCP4_REGAMMA_CNTLB_REGION_12_13                                                              0x0dfa
6929 #define mmDCP4_REGAMMA_CNTLB_REGION_12_13_BASE_IDX                                                     2
6930 #define mmDCP4_REGAMMA_CNTLB_REGION_14_15                                                              0x0dfb
6931 #define mmDCP4_REGAMMA_CNTLB_REGION_14_15_BASE_IDX                                                     2
6932 #define mmDCP4_ALPHA_CONTROL                                                                           0x0dfc
6933 #define mmDCP4_ALPHA_CONTROL_BASE_IDX                                                                  2
6934 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                                      0x0dfd
6935 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX                                             2
6936 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                                                 0x0dfe
6937 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
6938 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                                    0x0dff
6939 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX                                           2
6940 #define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT                                                                  0x0e00
6941 #define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX                                                         2
6942 #define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY                                                                0x0e01
6943 #define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX                                                       2
6944 #define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL                                                            0x0e02
6945 #define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX                                                   2
6946 #define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT                                                             0x0e03
6947 #define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX                                                    2
6948 
6949 
6950 // addressBlock: dce_dc_lb4_dispdec
6951 // base address: 0x2000
6952 #define mmLB4_LB_DATA_FORMAT                                                                           0x0e1a
6953 #define mmLB4_LB_DATA_FORMAT_BASE_IDX                                                                  2
6954 #define mmLB4_LB_MEMORY_CTRL                                                                           0x0e1b
6955 #define mmLB4_LB_MEMORY_CTRL_BASE_IDX                                                                  2
6956 #define mmLB4_LB_MEMORY_SIZE_STATUS                                                                    0x0e1c
6957 #define mmLB4_LB_MEMORY_SIZE_STATUS_BASE_IDX                                                           2
6958 #define mmLB4_LB_DESKTOP_HEIGHT                                                                        0x0e1d
6959 #define mmLB4_LB_DESKTOP_HEIGHT_BASE_IDX                                                               2
6960 #define mmLB4_LB_VLINE_START_END                                                                       0x0e1e
6961 #define mmLB4_LB_VLINE_START_END_BASE_IDX                                                              2
6962 #define mmLB4_LB_VLINE2_START_END                                                                      0x0e1f
6963 #define mmLB4_LB_VLINE2_START_END_BASE_IDX                                                             2
6964 #define mmLB4_LB_V_COUNTER                                                                             0x0e20
6965 #define mmLB4_LB_V_COUNTER_BASE_IDX                                                                    2
6966 #define mmLB4_LB_SNAPSHOT_V_COUNTER                                                                    0x0e21
6967 #define mmLB4_LB_SNAPSHOT_V_COUNTER_BASE_IDX                                                           2
6968 #define mmLB4_LB_INTERRUPT_MASK                                                                        0x0e22
6969 #define mmLB4_LB_INTERRUPT_MASK_BASE_IDX                                                               2
6970 #define mmLB4_LB_VLINE_STATUS                                                                          0x0e23
6971 #define mmLB4_LB_VLINE_STATUS_BASE_IDX                                                                 2
6972 #define mmLB4_LB_VLINE2_STATUS                                                                         0x0e24
6973 #define mmLB4_LB_VLINE2_STATUS_BASE_IDX                                                                2
6974 #define mmLB4_LB_VBLANK_STATUS                                                                         0x0e25
6975 #define mmLB4_LB_VBLANK_STATUS_BASE_IDX                                                                2
6976 #define mmLB4_LB_SYNC_RESET_SEL                                                                        0x0e26
6977 #define mmLB4_LB_SYNC_RESET_SEL_BASE_IDX                                                               2
6978 #define mmLB4_LB_BLACK_KEYER_R_CR                                                                      0x0e27
6979 #define mmLB4_LB_BLACK_KEYER_R_CR_BASE_IDX                                                             2
6980 #define mmLB4_LB_BLACK_KEYER_G_Y                                                                       0x0e28
6981 #define mmLB4_LB_BLACK_KEYER_G_Y_BASE_IDX                                                              2
6982 #define mmLB4_LB_BLACK_KEYER_B_CB                                                                      0x0e29
6983 #define mmLB4_LB_BLACK_KEYER_B_CB_BASE_IDX                                                             2
6984 #define mmLB4_LB_KEYER_COLOR_CTRL                                                                      0x0e2a
6985 #define mmLB4_LB_KEYER_COLOR_CTRL_BASE_IDX                                                             2
6986 #define mmLB4_LB_KEYER_COLOR_R_CR                                                                      0x0e2b
6987 #define mmLB4_LB_KEYER_COLOR_R_CR_BASE_IDX                                                             2
6988 #define mmLB4_LB_KEYER_COLOR_G_Y                                                                       0x0e2c
6989 #define mmLB4_LB_KEYER_COLOR_G_Y_BASE_IDX                                                              2
6990 #define mmLB4_LB_KEYER_COLOR_B_CB                                                                      0x0e2d
6991 #define mmLB4_LB_KEYER_COLOR_B_CB_BASE_IDX                                                             2
6992 #define mmLB4_LB_KEYER_COLOR_REP_R_CR                                                                  0x0e2e
6993 #define mmLB4_LB_KEYER_COLOR_REP_R_CR_BASE_IDX                                                         2
6994 #define mmLB4_LB_KEYER_COLOR_REP_G_Y                                                                   0x0e2f
6995 #define mmLB4_LB_KEYER_COLOR_REP_G_Y_BASE_IDX                                                          2
6996 #define mmLB4_LB_KEYER_COLOR_REP_B_CB                                                                  0x0e30
6997 #define mmLB4_LB_KEYER_COLOR_REP_B_CB_BASE_IDX                                                         2
6998 #define mmLB4_LB_BUFFER_LEVEL_STATUS                                                                   0x0e31
6999 #define mmLB4_LB_BUFFER_LEVEL_STATUS_BASE_IDX                                                          2
7000 #define mmLB4_LB_BUFFER_URGENCY_CTRL                                                                   0x0e32
7001 #define mmLB4_LB_BUFFER_URGENCY_CTRL_BASE_IDX                                                          2
7002 #define mmLB4_LB_BUFFER_URGENCY_STATUS                                                                 0x0e33
7003 #define mmLB4_LB_BUFFER_URGENCY_STATUS_BASE_IDX                                                        2
7004 #define mmLB4_LB_BUFFER_STATUS                                                                         0x0e34
7005 #define mmLB4_LB_BUFFER_STATUS_BASE_IDX                                                                2
7006 #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS                                                             0x0e35
7007 #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX                                                    2
7008 #define mmLB4_MVP_AFR_FLIP_MODE                                                                        0x0e36
7009 #define mmLB4_MVP_AFR_FLIP_MODE_BASE_IDX                                                               2
7010 #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL                                                                   0x0e37
7011 #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX                                                          2
7012 #define mmLB4_MVP_FLIP_LINE_NUM_INSERT                                                                 0x0e38
7013 #define mmLB4_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX                                                        2
7014 #define mmLB4_DC_MVP_LB_CONTROL                                                                        0x0e39
7015 #define mmLB4_DC_MVP_LB_CONTROL_BASE_IDX                                                               2
7016 
7017 
7018 // addressBlock: dce_dc_dcfe4_dispdec
7019 // base address: 0x2000
7020 #define mmDCFE4_DCFE_CLOCK_CONTROL                                                                     0x0e5a
7021 #define mmDCFE4_DCFE_CLOCK_CONTROL_BASE_IDX                                                            2
7022 #define mmDCFE4_DCFE_SOFT_RESET                                                                        0x0e5b
7023 #define mmDCFE4_DCFE_SOFT_RESET_BASE_IDX                                                               2
7024 #define mmDCFE4_DCFE_MEM_PWR_CTRL                                                                      0x0e5d
7025 #define mmDCFE4_DCFE_MEM_PWR_CTRL_BASE_IDX                                                             2
7026 #define mmDCFE4_DCFE_MEM_PWR_CTRL2                                                                     0x0e5e
7027 #define mmDCFE4_DCFE_MEM_PWR_CTRL2_BASE_IDX                                                            2
7028 #define mmDCFE4_DCFE_MEM_PWR_STATUS                                                                    0x0e5f
7029 #define mmDCFE4_DCFE_MEM_PWR_STATUS_BASE_IDX                                                           2
7030 #define mmDCFE4_DCFE_MISC                                                                              0x0e60
7031 #define mmDCFE4_DCFE_MISC_BASE_IDX                                                                     2
7032 #define mmDCFE4_DCFE_FLUSH                                                                             0x0e61
7033 #define mmDCFE4_DCFE_FLUSH_BASE_IDX                                                                    2
7034 
7035 
7036 // addressBlock: dce_dc_dc_perfmon7_dispdec
7037 // base address: 0x3938
7038 #define mmDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x0e6e
7039 #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
7040 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x0e6f
7041 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
7042 #define mmDC_PERFMON7_PERFCOUNTER_STATE                                                                0x0e70
7043 #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
7044 #define mmDC_PERFMON7_PERFMON_CNTL                                                                     0x0e71
7045 #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
7046 #define mmDC_PERFMON7_PERFMON_CNTL2                                                                    0x0e72
7047 #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
7048 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x0e73
7049 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
7050 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x0e74
7051 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
7052 #define mmDC_PERFMON7_PERFMON_HI                                                                       0x0e75
7053 #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
7054 #define mmDC_PERFMON7_PERFMON_LOW                                                                      0x0e76
7055 #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
7056 
7057 
7058 // addressBlock: dce_dc_dmif_pg4_dispdec
7059 // base address: 0x2000
7060 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1                                                       0x0e7a
7061 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                              2
7062 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2                                                       0x0e7b
7063 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                              2
7064 #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL                                                          0x0e7c
7065 #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_BASE_IDX                                                 2
7066 #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL                                                            0x0e7d
7067 #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_BASE_IDX                                                   2
7068 #define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL                                                       0x0e7e
7069 #define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX                                              2
7070 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL                                                            0x0e7f
7071 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_BASE_IDX                                                   2
7072 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2                                                           0x0e80
7073 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX                                                  2
7074 #define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL                                                          0x0e81
7075 #define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX                                                 2
7076 #define mmDMIF_PG4_DPG_REPEATER_PROGRAM                                                                0x0e82
7077 #define mmDMIF_PG4_DPG_REPEATER_PROGRAM_BASE_IDX                                                       2
7078 #define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL                                                               0x0e86
7079 #define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_BASE_IDX                                                      2
7080 #define mmDMIF_PG4_DPG_DVMM_STATUS                                                                     0x0e87
7081 #define mmDMIF_PG4_DPG_DVMM_STATUS_BASE_IDX                                                            2
7082 
7083 
7084 // addressBlock: dce_dc_scl4_dispdec
7085 // base address: 0x2000
7086 #define mmSCL4_SCL_COEF_RAM_SELECT                                                                     0x0e9a
7087 #define mmSCL4_SCL_COEF_RAM_SELECT_BASE_IDX                                                            2
7088 #define mmSCL4_SCL_COEF_RAM_TAP_DATA                                                                   0x0e9b
7089 #define mmSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                          2
7090 #define mmSCL4_SCL_MODE                                                                                0x0e9c
7091 #define mmSCL4_SCL_MODE_BASE_IDX                                                                       2
7092 #define mmSCL4_SCL_TAP_CONTROL                                                                         0x0e9d
7093 #define mmSCL4_SCL_TAP_CONTROL_BASE_IDX                                                                2
7094 #define mmSCL4_SCL_CONTROL                                                                             0x0e9e
7095 #define mmSCL4_SCL_CONTROL_BASE_IDX                                                                    2
7096 #define mmSCL4_SCL_BYPASS_CONTROL                                                                      0x0e9f
7097 #define mmSCL4_SCL_BYPASS_CONTROL_BASE_IDX                                                             2
7098 #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL                                                            0x0ea0
7099 #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                   2
7100 #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL                                                              0x0ea1
7101 #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX                                                     2
7102 #define mmSCL4_SCL_HORZ_FILTER_CONTROL                                                                 0x0ea2
7103 #define mmSCL4_SCL_HORZ_FILTER_CONTROL_BASE_IDX                                                        2
7104 #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO                                                             0x0ea3
7105 #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                    2
7106 #define mmSCL4_SCL_HORZ_FILTER_INIT                                                                    0x0ea4
7107 #define mmSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX                                                           2
7108 #define mmSCL4_SCL_VERT_FILTER_CONTROL                                                                 0x0ea5
7109 #define mmSCL4_SCL_VERT_FILTER_CONTROL_BASE_IDX                                                        2
7110 #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO                                                             0x0ea6
7111 #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                    2
7112 #define mmSCL4_SCL_VERT_FILTER_INIT                                                                    0x0ea7
7113 #define mmSCL4_SCL_VERT_FILTER_INIT_BASE_IDX                                                           2
7114 #define mmSCL4_SCL_VERT_FILTER_INIT_BOT                                                                0x0ea8
7115 #define mmSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                       2
7116 #define mmSCL4_SCL_ROUND_OFFSET                                                                        0x0ea9
7117 #define mmSCL4_SCL_ROUND_OFFSET_BASE_IDX                                                               2
7118 #define mmSCL4_SCL_UPDATE                                                                              0x0eaa
7119 #define mmSCL4_SCL_UPDATE_BASE_IDX                                                                     2
7120 #define mmSCL4_SCL_F_SHARP_CONTROL                                                                     0x0eab
7121 #define mmSCL4_SCL_F_SHARP_CONTROL_BASE_IDX                                                            2
7122 #define mmSCL4_SCL_ALU_CONTROL                                                                         0x0eac
7123 #define mmSCL4_SCL_ALU_CONTROL_BASE_IDX                                                                2
7124 #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS                                                            0x0ead
7125 #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                   2
7126 #define mmSCL4_VIEWPORT_START_SECONDARY                                                                0x0eae
7127 #define mmSCL4_VIEWPORT_START_SECONDARY_BASE_IDX                                                       2
7128 #define mmSCL4_VIEWPORT_START                                                                          0x0eaf
7129 #define mmSCL4_VIEWPORT_START_BASE_IDX                                                                 2
7130 #define mmSCL4_VIEWPORT_SIZE                                                                           0x0eb0
7131 #define mmSCL4_VIEWPORT_SIZE_BASE_IDX                                                                  2
7132 #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT                                                                 0x0eb1
7133 #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                        2
7134 #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM                                                                 0x0eb2
7135 #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                        2
7136 #define mmSCL4_SCL_MODE_CHANGE_DET1                                                                    0x0eb3
7137 #define mmSCL4_SCL_MODE_CHANGE_DET1_BASE_IDX                                                           2
7138 #define mmSCL4_SCL_MODE_CHANGE_DET2                                                                    0x0eb4
7139 #define mmSCL4_SCL_MODE_CHANGE_DET2_BASE_IDX                                                           2
7140 #define mmSCL4_SCL_MODE_CHANGE_DET3                                                                    0x0eb5
7141 #define mmSCL4_SCL_MODE_CHANGE_DET3_BASE_IDX                                                           2
7142 #define mmSCL4_SCL_MODE_CHANGE_MASK                                                                    0x0eb6
7143 #define mmSCL4_SCL_MODE_CHANGE_MASK_BASE_IDX                                                           2
7144 
7145 
7146 // addressBlock: dce_dc_blnd4_dispdec
7147 // base address: 0x2000
7148 #define mmBLND4_BLND_CONTROL                                                                           0x0ec7
7149 #define mmBLND4_BLND_CONTROL_BASE_IDX                                                                  2
7150 #define mmBLND4_BLND_SM_CONTROL2                                                                       0x0ec8
7151 #define mmBLND4_BLND_SM_CONTROL2_BASE_IDX                                                              2
7152 #define mmBLND4_BLND_CONTROL2                                                                          0x0ec9
7153 #define mmBLND4_BLND_CONTROL2_BASE_IDX                                                                 2
7154 #define mmBLND4_BLND_UPDATE                                                                            0x0eca
7155 #define mmBLND4_BLND_UPDATE_BASE_IDX                                                                   2
7156 #define mmBLND4_BLND_UNDERFLOW_INTERRUPT                                                               0x0ecb
7157 #define mmBLND4_BLND_UNDERFLOW_INTERRUPT_BASE_IDX                                                      2
7158 #define mmBLND4_BLND_V_UPDATE_LOCK                                                                     0x0ecc
7159 #define mmBLND4_BLND_V_UPDATE_LOCK_BASE_IDX                                                            2
7160 #define mmBLND4_BLND_REG_UPDATE_STATUS                                                                 0x0ecd
7161 #define mmBLND4_BLND_REG_UPDATE_STATUS_BASE_IDX                                                        2
7162 
7163 
7164 // addressBlock: dce_dc_crtc4_dispdec
7165 // base address: 0x2000
7166 #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM                                                                 0x0ed2
7167 #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_BASE_IDX                                                        2
7168 #define mmCRTC4_CRTC_H_TOTAL                                                                           0x0ed3
7169 #define mmCRTC4_CRTC_H_TOTAL_BASE_IDX                                                                  2
7170 #define mmCRTC4_CRTC_H_BLANK_START_END                                                                 0x0ed4
7171 #define mmCRTC4_CRTC_H_BLANK_START_END_BASE_IDX                                                        2
7172 #define mmCRTC4_CRTC_H_SYNC_A                                                                          0x0ed5
7173 #define mmCRTC4_CRTC_H_SYNC_A_BASE_IDX                                                                 2
7174 #define mmCRTC4_CRTC_H_SYNC_A_CNTL                                                                     0x0ed6
7175 #define mmCRTC4_CRTC_H_SYNC_A_CNTL_BASE_IDX                                                            2
7176 #define mmCRTC4_CRTC_H_SYNC_B                                                                          0x0ed7
7177 #define mmCRTC4_CRTC_H_SYNC_B_BASE_IDX                                                                 2
7178 #define mmCRTC4_CRTC_H_SYNC_B_CNTL                                                                     0x0ed8
7179 #define mmCRTC4_CRTC_H_SYNC_B_CNTL_BASE_IDX                                                            2
7180 #define mmCRTC4_CRTC_VBI_END                                                                           0x0ed9
7181 #define mmCRTC4_CRTC_VBI_END_BASE_IDX                                                                  2
7182 #define mmCRTC4_CRTC_V_TOTAL                                                                           0x0eda
7183 #define mmCRTC4_CRTC_V_TOTAL_BASE_IDX                                                                  2
7184 #define mmCRTC4_CRTC_V_TOTAL_MIN                                                                       0x0edb
7185 #define mmCRTC4_CRTC_V_TOTAL_MIN_BASE_IDX                                                              2
7186 #define mmCRTC4_CRTC_V_TOTAL_MAX                                                                       0x0edc
7187 #define mmCRTC4_CRTC_V_TOTAL_MAX_BASE_IDX                                                              2
7188 #define mmCRTC4_CRTC_V_TOTAL_CONTROL                                                                   0x0edd
7189 #define mmCRTC4_CRTC_V_TOTAL_CONTROL_BASE_IDX                                                          2
7190 #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS                                                                0x0ede
7191 #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_BASE_IDX                                                       2
7192 #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS                                                              0x0edf
7193 #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX                                                     2
7194 #define mmCRTC4_CRTC_V_BLANK_START_END                                                                 0x0ee0
7195 #define mmCRTC4_CRTC_V_BLANK_START_END_BASE_IDX                                                        2
7196 #define mmCRTC4_CRTC_V_SYNC_A                                                                          0x0ee1
7197 #define mmCRTC4_CRTC_V_SYNC_A_BASE_IDX                                                                 2
7198 #define mmCRTC4_CRTC_V_SYNC_A_CNTL                                                                     0x0ee2
7199 #define mmCRTC4_CRTC_V_SYNC_A_CNTL_BASE_IDX                                                            2
7200 #define mmCRTC4_CRTC_V_SYNC_B                                                                          0x0ee3
7201 #define mmCRTC4_CRTC_V_SYNC_B_BASE_IDX                                                                 2
7202 #define mmCRTC4_CRTC_V_SYNC_B_CNTL                                                                     0x0ee4
7203 #define mmCRTC4_CRTC_V_SYNC_B_CNTL_BASE_IDX                                                            2
7204 #define mmCRTC4_CRTC_DTMTEST_CNTL                                                                      0x0ee5
7205 #define mmCRTC4_CRTC_DTMTEST_CNTL_BASE_IDX                                                             2
7206 #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION                                                           0x0ee6
7207 #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX                                                  2
7208 #define mmCRTC4_CRTC_TRIGA_CNTL                                                                        0x0ee7
7209 #define mmCRTC4_CRTC_TRIGA_CNTL_BASE_IDX                                                               2
7210 #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG                                                                 0x0ee8
7211 #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX                                                        2
7212 #define mmCRTC4_CRTC_TRIGB_CNTL                                                                        0x0ee9
7213 #define mmCRTC4_CRTC_TRIGB_CNTL_BASE_IDX                                                               2
7214 #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG                                                                 0x0eea
7215 #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX                                                        2
7216 #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL                                                              0x0eeb
7217 #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                     2
7218 #define mmCRTC4_CRTC_FLOW_CONTROL                                                                      0x0eec
7219 #define mmCRTC4_CRTC_FLOW_CONTROL_BASE_IDX                                                             2
7220 #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE                                                             0x0eed
7221 #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                    2
7222 #define mmCRTC4_CRTC_AVSYNC_COUNTER                                                                    0x0eee
7223 #define mmCRTC4_CRTC_AVSYNC_COUNTER_BASE_IDX                                                           2
7224 #define mmCRTC4_CRTC_CONTROL                                                                           0x0eef
7225 #define mmCRTC4_CRTC_CONTROL_BASE_IDX                                                                  2
7226 #define mmCRTC4_CRTC_BLANK_CONTROL                                                                     0x0ef0
7227 #define mmCRTC4_CRTC_BLANK_CONTROL_BASE_IDX                                                            2
7228 #define mmCRTC4_CRTC_INTERLACE_CONTROL                                                                 0x0ef1
7229 #define mmCRTC4_CRTC_INTERLACE_CONTROL_BASE_IDX                                                        2
7230 #define mmCRTC4_CRTC_INTERLACE_STATUS                                                                  0x0ef2
7231 #define mmCRTC4_CRTC_INTERLACE_STATUS_BASE_IDX                                                         2
7232 #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL                                                          0x0ef3
7233 #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX                                                 2
7234 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0                                                              0x0ef4
7235 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_BASE_IDX                                                     2
7236 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1                                                              0x0ef5
7237 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_BASE_IDX                                                     2
7238 #define mmCRTC4_CRTC_STATUS                                                                            0x0ef6
7239 #define mmCRTC4_CRTC_STATUS_BASE_IDX                                                                   2
7240 #define mmCRTC4_CRTC_STATUS_POSITION                                                                   0x0ef7
7241 #define mmCRTC4_CRTC_STATUS_POSITION_BASE_IDX                                                          2
7242 #define mmCRTC4_CRTC_NOM_VERT_POSITION                                                                 0x0ef8
7243 #define mmCRTC4_CRTC_NOM_VERT_POSITION_BASE_IDX                                                        2
7244 #define mmCRTC4_CRTC_STATUS_FRAME_COUNT                                                                0x0ef9
7245 #define mmCRTC4_CRTC_STATUS_FRAME_COUNT_BASE_IDX                                                       2
7246 #define mmCRTC4_CRTC_STATUS_VF_COUNT                                                                   0x0efa
7247 #define mmCRTC4_CRTC_STATUS_VF_COUNT_BASE_IDX                                                          2
7248 #define mmCRTC4_CRTC_STATUS_HV_COUNT                                                                   0x0efb
7249 #define mmCRTC4_CRTC_STATUS_HV_COUNT_BASE_IDX                                                          2
7250 #define mmCRTC4_CRTC_COUNT_CONTROL                                                                     0x0efc
7251 #define mmCRTC4_CRTC_COUNT_CONTROL_BASE_IDX                                                            2
7252 #define mmCRTC4_CRTC_COUNT_RESET                                                                       0x0efd
7253 #define mmCRTC4_CRTC_COUNT_RESET_BASE_IDX                                                              2
7254 #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                                      0x0efe
7255 #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                             2
7256 #define mmCRTC4_CRTC_VERT_SYNC_CONTROL                                                                 0x0eff
7257 #define mmCRTC4_CRTC_VERT_SYNC_CONTROL_BASE_IDX                                                        2
7258 #define mmCRTC4_CRTC_STEREO_STATUS                                                                     0x0f00
7259 #define mmCRTC4_CRTC_STEREO_STATUS_BASE_IDX                                                            2
7260 #define mmCRTC4_CRTC_STEREO_CONTROL                                                                    0x0f01
7261 #define mmCRTC4_CRTC_STEREO_CONTROL_BASE_IDX                                                           2
7262 #define mmCRTC4_CRTC_SNAPSHOT_STATUS                                                                   0x0f02
7263 #define mmCRTC4_CRTC_SNAPSHOT_STATUS_BASE_IDX                                                          2
7264 #define mmCRTC4_CRTC_SNAPSHOT_CONTROL                                                                  0x0f03
7265 #define mmCRTC4_CRTC_SNAPSHOT_CONTROL_BASE_IDX                                                         2
7266 #define mmCRTC4_CRTC_SNAPSHOT_POSITION                                                                 0x0f04
7267 #define mmCRTC4_CRTC_SNAPSHOT_POSITION_BASE_IDX                                                        2
7268 #define mmCRTC4_CRTC_SNAPSHOT_FRAME                                                                    0x0f05
7269 #define mmCRTC4_CRTC_SNAPSHOT_FRAME_BASE_IDX                                                           2
7270 #define mmCRTC4_CRTC_START_LINE_CONTROL                                                                0x0f06
7271 #define mmCRTC4_CRTC_START_LINE_CONTROL_BASE_IDX                                                       2
7272 #define mmCRTC4_CRTC_INTERRUPT_CONTROL                                                                 0x0f07
7273 #define mmCRTC4_CRTC_INTERRUPT_CONTROL_BASE_IDX                                                        2
7274 #define mmCRTC4_CRTC_UPDATE_LOCK                                                                       0x0f08
7275 #define mmCRTC4_CRTC_UPDATE_LOCK_BASE_IDX                                                              2
7276 #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL                                                             0x0f09
7277 #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                    2
7278 #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE                                                        0x0f0a
7279 #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX                                               2
7280 #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL                                                              0x0f0b
7281 #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_BASE_IDX                                                     2
7282 #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS                                                           0x0f0c
7283 #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX                                                  2
7284 #define mmCRTC4_CRTC_TEST_PATTERN_COLOR                                                                0x0f0d
7285 #define mmCRTC4_CRTC_TEST_PATTERN_COLOR_BASE_IDX                                                       2
7286 #define mmCRTC4_CRTC_MASTER_UPDATE_LOCK                                                                0x0f0e
7287 #define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_BASE_IDX                                                       2
7288 #define mmCRTC4_CRTC_MASTER_UPDATE_MODE                                                                0x0f0f
7289 #define mmCRTC4_CRTC_MASTER_UPDATE_MODE_BASE_IDX                                                       2
7290 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT                                                            0x0f10
7291 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX                                                   2
7292 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                                                      0x0f11
7293 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX                                             2
7294 #define mmCRTC4_CRTC_MVP_STATUS                                                                        0x0f12
7295 #define mmCRTC4_CRTC_MVP_STATUS_BASE_IDX                                                               2
7296 #define mmCRTC4_CRTC_MASTER_EN                                                                         0x0f13
7297 #define mmCRTC4_CRTC_MASTER_EN_BASE_IDX                                                                2
7298 #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT                                                              0x0f14
7299 #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX                                                     2
7300 #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS                                                               0x0f15
7301 #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_BASE_IDX                                                      2
7302 #define mmCRTC4_CRTC_OVERSCAN_COLOR                                                                    0x0f17
7303 #define mmCRTC4_CRTC_OVERSCAN_COLOR_BASE_IDX                                                           2
7304 #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT                                                                0x0f18
7305 #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX                                                       2
7306 #define mmCRTC4_CRTC_BLANK_DATA_COLOR                                                                  0x0f19
7307 #define mmCRTC4_CRTC_BLANK_DATA_COLOR_BASE_IDX                                                         2
7308 #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT                                                              0x0f1a
7309 #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX                                                     2
7310 #define mmCRTC4_CRTC_BLACK_COLOR                                                                       0x0f1b
7311 #define mmCRTC4_CRTC_BLACK_COLOR_BASE_IDX                                                              2
7312 #define mmCRTC4_CRTC_BLACK_COLOR_EXT                                                                   0x0f1c
7313 #define mmCRTC4_CRTC_BLACK_COLOR_EXT_BASE_IDX                                                          2
7314 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION                                                      0x0f1d
7315 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                             2
7316 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL                                                       0x0f1e
7317 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                              2
7318 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION                                                      0x0f1f
7319 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                             2
7320 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL                                                       0x0f20
7321 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                              2
7322 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION                                                      0x0f21
7323 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                             2
7324 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL                                                       0x0f22
7325 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                              2
7326 #define mmCRTC4_CRTC_CRC_CNTL                                                                          0x0f23
7327 #define mmCRTC4_CRTC_CRC_CNTL_BASE_IDX                                                                 2
7328 #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL                                                            0x0f24
7329 #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                   2
7330 #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL                                                            0x0f25
7331 #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
7332 #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL                                                            0x0f26
7333 #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                   2
7334 #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL                                                            0x0f27
7335 #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
7336 #define mmCRTC4_CRTC_CRC0_DATA_RG                                                                      0x0f28
7337 #define mmCRTC4_CRTC_CRC0_DATA_RG_BASE_IDX                                                             2
7338 #define mmCRTC4_CRTC_CRC0_DATA_B                                                                       0x0f29
7339 #define mmCRTC4_CRTC_CRC0_DATA_B_BASE_IDX                                                              2
7340 #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL                                                            0x0f2a
7341 #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                   2
7342 #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL                                                            0x0f2b
7343 #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
7344 #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL                                                            0x0f2c
7345 #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                   2
7346 #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL                                                            0x0f2d
7347 #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
7348 #define mmCRTC4_CRTC_CRC1_DATA_RG                                                                      0x0f2e
7349 #define mmCRTC4_CRTC_CRC1_DATA_RG_BASE_IDX                                                             2
7350 #define mmCRTC4_CRTC_CRC1_DATA_B                                                                       0x0f2f
7351 #define mmCRTC4_CRTC_CRC1_DATA_B_BASE_IDX                                                              2
7352 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL                                                           0x0f30
7353 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX                                                  2
7354 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START                                                      0x0f31
7355 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX                                             2
7356 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END                                                        0x0f32
7357 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX                                               2
7358 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                                            0x0f33
7359 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX                                   2
7360 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                                 0x0f34
7361 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX                                        2
7362 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                                          0x0f35
7363 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX                                 2
7364 #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL                                                             0x0f36
7365 #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX                                                    2
7366 #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL                                                              0x0f37
7367 #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX                                                     2
7368 #define mmCRTC4_CRTC_GSL_VSYNC_GAP                                                                     0x0f38
7369 #define mmCRTC4_CRTC_GSL_VSYNC_GAP_BASE_IDX                                                            2
7370 #define mmCRTC4_CRTC_GSL_WINDOW                                                                        0x0f39
7371 #define mmCRTC4_CRTC_GSL_WINDOW_BASE_IDX                                                               2
7372 #define mmCRTC4_CRTC_GSL_CONTROL                                                                       0x0f3a
7373 #define mmCRTC4_CRTC_GSL_CONTROL_BASE_IDX                                                              2
7374 #define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS                                                           0x0f3d
7375 #define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX                                                  2
7376 #define mmCRTC4_CRTC_DRR_CONTROL                                                                       0x0f3e
7377 #define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX                                                              2
7378 
7379 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x395d
7380 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2
7381 
7382 // addressBlock: dce_dc_fmt4_dispdec
7383 // base address: 0x2000
7384 #define mmFMT4_FMT_CLAMP_COMPONENT_R                                                                   0x0f42
7385 #define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
7386 #define mmFMT4_FMT_CLAMP_COMPONENT_G                                                                   0x0f43
7387 #define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
7388 #define mmFMT4_FMT_CLAMP_COMPONENT_B                                                                   0x0f44
7389 #define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
7390 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                                                    0x0f45
7391 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
7392 #define mmFMT4_FMT_CONTROL                                                                             0x0f46
7393 #define mmFMT4_FMT_CONTROL_BASE_IDX                                                                    2
7394 #define mmFMT4_FMT_BIT_DEPTH_CONTROL                                                                   0x0f47
7395 #define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
7396 #define mmFMT4_FMT_DITHER_RAND_R_SEED                                                                  0x0f48
7397 #define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
7398 #define mmFMT4_FMT_DITHER_RAND_G_SEED                                                                  0x0f49
7399 #define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
7400 #define mmFMT4_FMT_DITHER_RAND_B_SEED                                                                  0x0f4a
7401 #define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
7402 #define mmFMT4_FMT_CLAMP_CNTL                                                                          0x0f4e
7403 #define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
7404 #define mmFMT4_FMT_CRC_CNTL                                                                            0x0f4f
7405 #define mmFMT4_FMT_CRC_CNTL_BASE_IDX                                                                   2
7406 #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK                                                              0x0f50
7407 #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
7408 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK                                                           0x0f51
7409 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
7410 #define mmFMT4_FMT_CRC_SIG_RED_GREEN                                                                   0x0f52
7411 #define mmFMT4_FMT_CRC_SIG_RED_GREEN_BASE_IDX                                                          2
7412 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL                                                                0x0f53
7413 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX                                                       2
7414 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x0f54
7415 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
7416 #define mmFMT4_FMT_420_HBLANK_EARLY_START                                                              0x0f55
7417 #define mmFMT4_FMT_420_HBLANK_EARLY_START_BASE_IDX                                                     2
7418 
7419 
7420 // addressBlock: dce_dc_dcp5_dispdec
7421 // base address: 0x2800
7422 #define mmDCP5_GRPH_ENABLE                                                                             0x0f5a
7423 #define mmDCP5_GRPH_ENABLE_BASE_IDX                                                                    2
7424 #define mmDCP5_GRPH_CONTROL                                                                            0x0f5b
7425 #define mmDCP5_GRPH_CONTROL_BASE_IDX                                                                   2
7426 #define mmDCP5_GRPH_LUT_10BIT_BYPASS                                                                   0x0f5c
7427 #define mmDCP5_GRPH_LUT_10BIT_BYPASS_BASE_IDX                                                          2
7428 #define mmDCP5_GRPH_SWAP_CNTL                                                                          0x0f5d
7429 #define mmDCP5_GRPH_SWAP_CNTL_BASE_IDX                                                                 2
7430 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS                                                            0x0f5e
7431 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                                   2
7432 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS                                                          0x0f5f
7433 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                                 2
7434 #define mmDCP5_GRPH_PITCH                                                                              0x0f60
7435 #define mmDCP5_GRPH_PITCH_BASE_IDX                                                                     2
7436 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                                                       0x0f61
7437 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                              2
7438 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH                                                     0x0f62
7439 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                            2
7440 #define mmDCP5_GRPH_SURFACE_OFFSET_X                                                                   0x0f63
7441 #define mmDCP5_GRPH_SURFACE_OFFSET_X_BASE_IDX                                                          2
7442 #define mmDCP5_GRPH_SURFACE_OFFSET_Y                                                                   0x0f64
7443 #define mmDCP5_GRPH_SURFACE_OFFSET_Y_BASE_IDX                                                          2
7444 #define mmDCP5_GRPH_X_START                                                                            0x0f65
7445 #define mmDCP5_GRPH_X_START_BASE_IDX                                                                   2
7446 #define mmDCP5_GRPH_Y_START                                                                            0x0f66
7447 #define mmDCP5_GRPH_Y_START_BASE_IDX                                                                   2
7448 #define mmDCP5_GRPH_X_END                                                                              0x0f67
7449 #define mmDCP5_GRPH_X_END_BASE_IDX                                                                     2
7450 #define mmDCP5_GRPH_Y_END                                                                              0x0f68
7451 #define mmDCP5_GRPH_Y_END_BASE_IDX                                                                     2
7452 #define mmDCP5_INPUT_GAMMA_CONTROL                                                                     0x0f69
7453 #define mmDCP5_INPUT_GAMMA_CONTROL_BASE_IDX                                                            2
7454 #define mmDCP5_GRPH_UPDATE                                                                             0x0f6a
7455 #define mmDCP5_GRPH_UPDATE_BASE_IDX                                                                    2
7456 #define mmDCP5_GRPH_FLIP_CONTROL                                                                       0x0f6b
7457 #define mmDCP5_GRPH_FLIP_CONTROL_BASE_IDX                                                              2
7458 #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE                                                              0x0f6c
7459 #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX                                                     2
7460 #define mmDCP5_GRPH_DFQ_CONTROL                                                                        0x0f6d
7461 #define mmDCP5_GRPH_DFQ_CONTROL_BASE_IDX                                                               2
7462 #define mmDCP5_GRPH_DFQ_STATUS                                                                         0x0f6e
7463 #define mmDCP5_GRPH_DFQ_STATUS_BASE_IDX                                                                2
7464 #define mmDCP5_GRPH_INTERRUPT_STATUS                                                                   0x0f6f
7465 #define mmDCP5_GRPH_INTERRUPT_STATUS_BASE_IDX                                                          2
7466 #define mmDCP5_GRPH_INTERRUPT_CONTROL                                                                  0x0f70
7467 #define mmDCP5_GRPH_INTERRUPT_CONTROL_BASE_IDX                                                         2
7468 #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE                                                         0x0f71
7469 #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX                                                2
7470 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS                                                           0x0f72
7471 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX                                                  2
7472 #define mmDCP5_GRPH_COMPRESS_PITCH                                                                     0x0f73
7473 #define mmDCP5_GRPH_COMPRESS_PITCH_BASE_IDX                                                            2
7474 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH                                                      0x0f74
7475 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX                                             2
7476 #define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT                                                     0x0f75
7477 #define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX                                            2
7478 #define mmDCP5_PRESCALE_GRPH_CONTROL                                                                   0x0f76
7479 #define mmDCP5_PRESCALE_GRPH_CONTROL_BASE_IDX                                                          2
7480 #define mmDCP5_PRESCALE_VALUES_GRPH_R                                                                  0x0f77
7481 #define mmDCP5_PRESCALE_VALUES_GRPH_R_BASE_IDX                                                         2
7482 #define mmDCP5_PRESCALE_VALUES_GRPH_G                                                                  0x0f78
7483 #define mmDCP5_PRESCALE_VALUES_GRPH_G_BASE_IDX                                                         2
7484 #define mmDCP5_PRESCALE_VALUES_GRPH_B                                                                  0x0f79
7485 #define mmDCP5_PRESCALE_VALUES_GRPH_B_BASE_IDX                                                         2
7486 #define mmDCP5_INPUT_CSC_CONTROL                                                                       0x0f7a
7487 #define mmDCP5_INPUT_CSC_CONTROL_BASE_IDX                                                              2
7488 #define mmDCP5_INPUT_CSC_C11_C12                                                                       0x0f7b
7489 #define mmDCP5_INPUT_CSC_C11_C12_BASE_IDX                                                              2
7490 #define mmDCP5_INPUT_CSC_C13_C14                                                                       0x0f7c
7491 #define mmDCP5_INPUT_CSC_C13_C14_BASE_IDX                                                              2
7492 #define mmDCP5_INPUT_CSC_C21_C22                                                                       0x0f7d
7493 #define mmDCP5_INPUT_CSC_C21_C22_BASE_IDX                                                              2
7494 #define mmDCP5_INPUT_CSC_C23_C24                                                                       0x0f7e
7495 #define mmDCP5_INPUT_CSC_C23_C24_BASE_IDX                                                              2
7496 #define mmDCP5_INPUT_CSC_C31_C32                                                                       0x0f7f
7497 #define mmDCP5_INPUT_CSC_C31_C32_BASE_IDX                                                              2
7498 #define mmDCP5_INPUT_CSC_C33_C34                                                                       0x0f80
7499 #define mmDCP5_INPUT_CSC_C33_C34_BASE_IDX                                                              2
7500 #define mmDCP5_OUTPUT_CSC_CONTROL                                                                      0x0f81
7501 #define mmDCP5_OUTPUT_CSC_CONTROL_BASE_IDX                                                             2
7502 #define mmDCP5_OUTPUT_CSC_C11_C12                                                                      0x0f82
7503 #define mmDCP5_OUTPUT_CSC_C11_C12_BASE_IDX                                                             2
7504 #define mmDCP5_OUTPUT_CSC_C13_C14                                                                      0x0f83
7505 #define mmDCP5_OUTPUT_CSC_C13_C14_BASE_IDX                                                             2
7506 #define mmDCP5_OUTPUT_CSC_C21_C22                                                                      0x0f84
7507 #define mmDCP5_OUTPUT_CSC_C21_C22_BASE_IDX                                                             2
7508 #define mmDCP5_OUTPUT_CSC_C23_C24                                                                      0x0f85
7509 #define mmDCP5_OUTPUT_CSC_C23_C24_BASE_IDX                                                             2
7510 #define mmDCP5_OUTPUT_CSC_C31_C32                                                                      0x0f86
7511 #define mmDCP5_OUTPUT_CSC_C31_C32_BASE_IDX                                                             2
7512 #define mmDCP5_OUTPUT_CSC_C33_C34                                                                      0x0f87
7513 #define mmDCP5_OUTPUT_CSC_C33_C34_BASE_IDX                                                             2
7514 #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12                                                              0x0f88
7515 #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX                                                     2
7516 #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14                                                              0x0f89
7517 #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX                                                     2
7518 #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22                                                              0x0f8a
7519 #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX                                                     2
7520 #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24                                                              0x0f8b
7521 #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX                                                     2
7522 #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32                                                              0x0f8c
7523 #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX                                                     2
7524 #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34                                                              0x0f8d
7525 #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX                                                     2
7526 #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12                                                              0x0f8e
7527 #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX                                                     2
7528 #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14                                                              0x0f8f
7529 #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX                                                     2
7530 #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22                                                              0x0f90
7531 #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX                                                     2
7532 #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24                                                              0x0f91
7533 #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX                                                     2
7534 #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32                                                              0x0f92
7535 #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX                                                     2
7536 #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34                                                              0x0f93
7537 #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX                                                     2
7538 #define mmDCP5_DENORM_CONTROL                                                                          0x0f94
7539 #define mmDCP5_DENORM_CONTROL_BASE_IDX                                                                 2
7540 #define mmDCP5_OUT_ROUND_CONTROL                                                                       0x0f95
7541 #define mmDCP5_OUT_ROUND_CONTROL_BASE_IDX                                                              2
7542 #define mmDCP5_OUT_CLAMP_CONTROL_R_CR                                                                  0x0f96
7543 #define mmDCP5_OUT_CLAMP_CONTROL_R_CR_BASE_IDX                                                         2
7544 #define mmDCP5_OUT_CLAMP_CONTROL_G_Y                                                                   0x0f97
7545 #define mmDCP5_OUT_CLAMP_CONTROL_G_Y_BASE_IDX                                                          2
7546 #define mmDCP5_OUT_CLAMP_CONTROL_B_CB                                                                  0x0f98
7547 #define mmDCP5_OUT_CLAMP_CONTROL_B_CB_BASE_IDX                                                         2
7548 #define mmDCP5_KEY_CONTROL                                                                             0x0f99
7549 #define mmDCP5_KEY_CONTROL_BASE_IDX                                                                    2
7550 #define mmDCP5_KEY_RANGE_ALPHA                                                                         0x0f9a
7551 #define mmDCP5_KEY_RANGE_ALPHA_BASE_IDX                                                                2
7552 #define mmDCP5_KEY_RANGE_RED                                                                           0x0f9b
7553 #define mmDCP5_KEY_RANGE_RED_BASE_IDX                                                                  2
7554 #define mmDCP5_KEY_RANGE_GREEN                                                                         0x0f9c
7555 #define mmDCP5_KEY_RANGE_GREEN_BASE_IDX                                                                2
7556 #define mmDCP5_KEY_RANGE_BLUE                                                                          0x0f9d
7557 #define mmDCP5_KEY_RANGE_BLUE_BASE_IDX                                                                 2
7558 #define mmDCP5_DEGAMMA_CONTROL                                                                         0x0f9e
7559 #define mmDCP5_DEGAMMA_CONTROL_BASE_IDX                                                                2
7560 #define mmDCP5_GAMUT_REMAP_CONTROL                                                                     0x0f9f
7561 #define mmDCP5_GAMUT_REMAP_CONTROL_BASE_IDX                                                            2
7562 #define mmDCP5_GAMUT_REMAP_C11_C12                                                                     0x0fa0
7563 #define mmDCP5_GAMUT_REMAP_C11_C12_BASE_IDX                                                            2
7564 #define mmDCP5_GAMUT_REMAP_C13_C14                                                                     0x0fa1
7565 #define mmDCP5_GAMUT_REMAP_C13_C14_BASE_IDX                                                            2
7566 #define mmDCP5_GAMUT_REMAP_C21_C22                                                                     0x0fa2
7567 #define mmDCP5_GAMUT_REMAP_C21_C22_BASE_IDX                                                            2
7568 #define mmDCP5_GAMUT_REMAP_C23_C24                                                                     0x0fa3
7569 #define mmDCP5_GAMUT_REMAP_C23_C24_BASE_IDX                                                            2
7570 #define mmDCP5_GAMUT_REMAP_C31_C32                                                                     0x0fa4
7571 #define mmDCP5_GAMUT_REMAP_C31_C32_BASE_IDX                                                            2
7572 #define mmDCP5_GAMUT_REMAP_C33_C34                                                                     0x0fa5
7573 #define mmDCP5_GAMUT_REMAP_C33_C34_BASE_IDX                                                            2
7574 #define mmDCP5_DCP_SPATIAL_DITHER_CNTL                                                                 0x0fa6
7575 #define mmDCP5_DCP_SPATIAL_DITHER_CNTL_BASE_IDX                                                        2
7576 #define mmDCP5_DCP_RANDOM_SEEDS                                                                        0x0fa7
7577 #define mmDCP5_DCP_RANDOM_SEEDS_BASE_IDX                                                               2
7578 #define mmDCP5_DCP_FP_CONVERTED_FIELD                                                                  0x0fa8
7579 #define mmDCP5_DCP_FP_CONVERTED_FIELD_BASE_IDX                                                         2
7580 #define mmDCP5_CUR_CONTROL                                                                             0x0fa9
7581 #define mmDCP5_CUR_CONTROL_BASE_IDX                                                                    2
7582 #define mmDCP5_CUR_SURFACE_ADDRESS                                                                     0x0faa
7583 #define mmDCP5_CUR_SURFACE_ADDRESS_BASE_IDX                                                            2
7584 #define mmDCP5_CUR_SIZE                                                                                0x0fab
7585 #define mmDCP5_CUR_SIZE_BASE_IDX                                                                       2
7586 #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH                                                                0x0fac
7587 #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX                                                       2
7588 #define mmDCP5_CUR_POSITION                                                                            0x0fad
7589 #define mmDCP5_CUR_POSITION_BASE_IDX                                                                   2
7590 #define mmDCP5_CUR_HOT_SPOT                                                                            0x0fae
7591 #define mmDCP5_CUR_HOT_SPOT_BASE_IDX                                                                   2
7592 #define mmDCP5_CUR_COLOR1                                                                              0x0faf
7593 #define mmDCP5_CUR_COLOR1_BASE_IDX                                                                     2
7594 #define mmDCP5_CUR_COLOR2                                                                              0x0fb0
7595 #define mmDCP5_CUR_COLOR2_BASE_IDX                                                                     2
7596 #define mmDCP5_CUR_UPDATE                                                                              0x0fb1
7597 #define mmDCP5_CUR_UPDATE_BASE_IDX                                                                     2
7598 #define mmDCP5_CUR_REQUEST_FILTER_CNTL                                                                 0x0fbb
7599 #define mmDCP5_CUR_REQUEST_FILTER_CNTL_BASE_IDX                                                        2
7600 #define mmDCP5_CUR_STEREO_CONTROL                                                                      0x0fbc
7601 #define mmDCP5_CUR_STEREO_CONTROL_BASE_IDX                                                             2
7602 #define mmDCP5_DC_LUT_RW_MODE                                                                          0x0fbe
7603 #define mmDCP5_DC_LUT_RW_MODE_BASE_IDX                                                                 2
7604 #define mmDCP5_DC_LUT_RW_INDEX                                                                         0x0fbf
7605 #define mmDCP5_DC_LUT_RW_INDEX_BASE_IDX                                                                2
7606 #define mmDCP5_DC_LUT_SEQ_COLOR                                                                        0x0fc0
7607 #define mmDCP5_DC_LUT_SEQ_COLOR_BASE_IDX                                                               2
7608 #define mmDCP5_DC_LUT_PWL_DATA                                                                         0x0fc1
7609 #define mmDCP5_DC_LUT_PWL_DATA_BASE_IDX                                                                2
7610 #define mmDCP5_DC_LUT_30_COLOR                                                                         0x0fc2
7611 #define mmDCP5_DC_LUT_30_COLOR_BASE_IDX                                                                2
7612 #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE                                                                0x0fc3
7613 #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX                                                       2
7614 #define mmDCP5_DC_LUT_WRITE_EN_MASK                                                                    0x0fc4
7615 #define mmDCP5_DC_LUT_WRITE_EN_MASK_BASE_IDX                                                           2
7616 #define mmDCP5_DC_LUT_AUTOFILL                                                                         0x0fc5
7617 #define mmDCP5_DC_LUT_AUTOFILL_BASE_IDX                                                                2
7618 #define mmDCP5_DC_LUT_CONTROL                                                                          0x0fc6
7619 #define mmDCP5_DC_LUT_CONTROL_BASE_IDX                                                                 2
7620 #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE                                                                0x0fc7
7621 #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX                                                       2
7622 #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN                                                               0x0fc8
7623 #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX                                                      2
7624 #define mmDCP5_DC_LUT_BLACK_OFFSET_RED                                                                 0x0fc9
7625 #define mmDCP5_DC_LUT_BLACK_OFFSET_RED_BASE_IDX                                                        2
7626 #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE                                                                0x0fca
7627 #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX                                                       2
7628 #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN                                                               0x0fcb
7629 #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX                                                      2
7630 #define mmDCP5_DC_LUT_WHITE_OFFSET_RED                                                                 0x0fcc
7631 #define mmDCP5_DC_LUT_WHITE_OFFSET_RED_BASE_IDX                                                        2
7632 #define mmDCP5_DCP_CRC_CONTROL                                                                         0x0fcd
7633 #define mmDCP5_DCP_CRC_CONTROL_BASE_IDX                                                                2
7634 #define mmDCP5_DCP_CRC_MASK                                                                            0x0fce
7635 #define mmDCP5_DCP_CRC_MASK_BASE_IDX                                                                   2
7636 #define mmDCP5_DCP_CRC_CURRENT                                                                         0x0fcf
7637 #define mmDCP5_DCP_CRC_CURRENT_BASE_IDX                                                                2
7638 #define mmDCP5_DVMM_PTE_CONTROL                                                                        0x0fd0
7639 #define mmDCP5_DVMM_PTE_CONTROL_BASE_IDX                                                               2
7640 #define mmDCP5_DCP_CRC_LAST                                                                            0x0fd1
7641 #define mmDCP5_DCP_CRC_LAST_BASE_IDX                                                                   2
7642 #define mmDCP5_DVMM_PTE_ARB_CONTROL                                                                    0x0fd2
7643 #define mmDCP5_DVMM_PTE_ARB_CONTROL_BASE_IDX                                                           2
7644 #define mmDCP5_GRPH_FLIP_RATE_CNTL                                                                     0x0fd4
7645 #define mmDCP5_GRPH_FLIP_RATE_CNTL_BASE_IDX                                                            2
7646 #define mmDCP5_DCP_GSL_CONTROL                                                                         0x0fd5
7647 #define mmDCP5_DCP_GSL_CONTROL_BASE_IDX                                                                2
7648 #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK                                                           0x0fd6
7649 #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX                                                  2
7650 #define mmDCP5_GRPH_STEREOSYNC_FLIP                                                                    0x0fdc
7651 #define mmDCP5_GRPH_STEREOSYNC_FLIP_BASE_IDX                                                           2
7652 #define mmDCP5_HW_ROTATION                                                                             0x0fde
7653 #define mmDCP5_HW_ROTATION_BASE_IDX                                                                    2
7654 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL                                                      0x0fdf
7655 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX                                             2
7656 #define mmDCP5_REGAMMA_CONTROL                                                                         0x0fe0
7657 #define mmDCP5_REGAMMA_CONTROL_BASE_IDX                                                                2
7658 #define mmDCP5_REGAMMA_LUT_INDEX                                                                       0x0fe1
7659 #define mmDCP5_REGAMMA_LUT_INDEX_BASE_IDX                                                              2
7660 #define mmDCP5_REGAMMA_LUT_DATA                                                                        0x0fe2
7661 #define mmDCP5_REGAMMA_LUT_DATA_BASE_IDX                                                               2
7662 #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK                                                               0x0fe3
7663 #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX                                                      2
7664 #define mmDCP5_REGAMMA_CNTLA_START_CNTL                                                                0x0fe4
7665 #define mmDCP5_REGAMMA_CNTLA_START_CNTL_BASE_IDX                                                       2
7666 #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL                                                                0x0fe5
7667 #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX                                                       2
7668 #define mmDCP5_REGAMMA_CNTLA_END_CNTL1                                                                 0x0fe6
7669 #define mmDCP5_REGAMMA_CNTLA_END_CNTL1_BASE_IDX                                                        2
7670 #define mmDCP5_REGAMMA_CNTLA_END_CNTL2                                                                 0x0fe7
7671 #define mmDCP5_REGAMMA_CNTLA_END_CNTL2_BASE_IDX                                                        2
7672 #define mmDCP5_REGAMMA_CNTLA_REGION_0_1                                                                0x0fe8
7673 #define mmDCP5_REGAMMA_CNTLA_REGION_0_1_BASE_IDX                                                       2
7674 #define mmDCP5_REGAMMA_CNTLA_REGION_2_3                                                                0x0fe9
7675 #define mmDCP5_REGAMMA_CNTLA_REGION_2_3_BASE_IDX                                                       2
7676 #define mmDCP5_REGAMMA_CNTLA_REGION_4_5                                                                0x0fea
7677 #define mmDCP5_REGAMMA_CNTLA_REGION_4_5_BASE_IDX                                                       2
7678 #define mmDCP5_REGAMMA_CNTLA_REGION_6_7                                                                0x0feb
7679 #define mmDCP5_REGAMMA_CNTLA_REGION_6_7_BASE_IDX                                                       2
7680 #define mmDCP5_REGAMMA_CNTLA_REGION_8_9                                                                0x0fec
7681 #define mmDCP5_REGAMMA_CNTLA_REGION_8_9_BASE_IDX                                                       2
7682 #define mmDCP5_REGAMMA_CNTLA_REGION_10_11                                                              0x0fed
7683 #define mmDCP5_REGAMMA_CNTLA_REGION_10_11_BASE_IDX                                                     2
7684 #define mmDCP5_REGAMMA_CNTLA_REGION_12_13                                                              0x0fee
7685 #define mmDCP5_REGAMMA_CNTLA_REGION_12_13_BASE_IDX                                                     2
7686 #define mmDCP5_REGAMMA_CNTLA_REGION_14_15                                                              0x0fef
7687 #define mmDCP5_REGAMMA_CNTLA_REGION_14_15_BASE_IDX                                                     2
7688 #define mmDCP5_REGAMMA_CNTLB_START_CNTL                                                                0x0ff0
7689 #define mmDCP5_REGAMMA_CNTLB_START_CNTL_BASE_IDX                                                       2
7690 #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL                                                                0x0ff1
7691 #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX                                                       2
7692 #define mmDCP5_REGAMMA_CNTLB_END_CNTL1                                                                 0x0ff2
7693 #define mmDCP5_REGAMMA_CNTLB_END_CNTL1_BASE_IDX                                                        2
7694 #define mmDCP5_REGAMMA_CNTLB_END_CNTL2                                                                 0x0ff3
7695 #define mmDCP5_REGAMMA_CNTLB_END_CNTL2_BASE_IDX                                                        2
7696 #define mmDCP5_REGAMMA_CNTLB_REGION_0_1                                                                0x0ff4
7697 #define mmDCP5_REGAMMA_CNTLB_REGION_0_1_BASE_IDX                                                       2
7698 #define mmDCP5_REGAMMA_CNTLB_REGION_2_3                                                                0x0ff5
7699 #define mmDCP5_REGAMMA_CNTLB_REGION_2_3_BASE_IDX                                                       2
7700 #define mmDCP5_REGAMMA_CNTLB_REGION_4_5                                                                0x0ff6
7701 #define mmDCP5_REGAMMA_CNTLB_REGION_4_5_BASE_IDX                                                       2
7702 #define mmDCP5_REGAMMA_CNTLB_REGION_6_7                                                                0x0ff7
7703 #define mmDCP5_REGAMMA_CNTLB_REGION_6_7_BASE_IDX                                                       2
7704 #define mmDCP5_REGAMMA_CNTLB_REGION_8_9                                                                0x0ff8
7705 #define mmDCP5_REGAMMA_CNTLB_REGION_8_9_BASE_IDX                                                       2
7706 #define mmDCP5_REGAMMA_CNTLB_REGION_10_11                                                              0x0ff9
7707 #define mmDCP5_REGAMMA_CNTLB_REGION_10_11_BASE_IDX                                                     2
7708 #define mmDCP5_REGAMMA_CNTLB_REGION_12_13                                                              0x0ffa
7709 #define mmDCP5_REGAMMA_CNTLB_REGION_12_13_BASE_IDX                                                     2
7710 #define mmDCP5_REGAMMA_CNTLB_REGION_14_15                                                              0x0ffb
7711 #define mmDCP5_REGAMMA_CNTLB_REGION_14_15_BASE_IDX                                                     2
7712 #define mmDCP5_ALPHA_CONTROL                                                                           0x0ffc
7713 #define mmDCP5_ALPHA_CONTROL_BASE_IDX                                                                  2
7714 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS                                                      0x0ffd
7715 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX                                             2
7716 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH                                                 0x0ffe
7717 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
7718 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS                                                    0x0fff
7719 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX                                           2
7720 #define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT                                                                  0x1000
7721 #define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX                                                         2
7722 #define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY                                                                0x1001
7723 #define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX                                                       2
7724 #define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL                                                            0x1002
7725 #define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX                                                   2
7726 #define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT                                                             0x1003
7727 #define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX                                                    2
7728 
7729 
7730 // addressBlock: dce_dc_lb5_dispdec
7731 // base address: 0x2800
7732 #define mmLB5_LB_DATA_FORMAT                                                                           0x101a
7733 #define mmLB5_LB_DATA_FORMAT_BASE_IDX                                                                  2
7734 #define mmLB5_LB_MEMORY_CTRL                                                                           0x101b
7735 #define mmLB5_LB_MEMORY_CTRL_BASE_IDX                                                                  2
7736 #define mmLB5_LB_MEMORY_SIZE_STATUS                                                                    0x101c
7737 #define mmLB5_LB_MEMORY_SIZE_STATUS_BASE_IDX                                                           2
7738 #define mmLB5_LB_DESKTOP_HEIGHT                                                                        0x101d
7739 #define mmLB5_LB_DESKTOP_HEIGHT_BASE_IDX                                                               2
7740 #define mmLB5_LB_VLINE_START_END                                                                       0x101e
7741 #define mmLB5_LB_VLINE_START_END_BASE_IDX                                                              2
7742 #define mmLB5_LB_VLINE2_START_END                                                                      0x101f
7743 #define mmLB5_LB_VLINE2_START_END_BASE_IDX                                                             2
7744 #define mmLB5_LB_V_COUNTER                                                                             0x1020
7745 #define mmLB5_LB_V_COUNTER_BASE_IDX                                                                    2
7746 #define mmLB5_LB_SNAPSHOT_V_COUNTER                                                                    0x1021
7747 #define mmLB5_LB_SNAPSHOT_V_COUNTER_BASE_IDX                                                           2
7748 #define mmLB5_LB_INTERRUPT_MASK                                                                        0x1022
7749 #define mmLB5_LB_INTERRUPT_MASK_BASE_IDX                                                               2
7750 #define mmLB5_LB_VLINE_STATUS                                                                          0x1023
7751 #define mmLB5_LB_VLINE_STATUS_BASE_IDX                                                                 2
7752 #define mmLB5_LB_VLINE2_STATUS                                                                         0x1024
7753 #define mmLB5_LB_VLINE2_STATUS_BASE_IDX                                                                2
7754 #define mmLB5_LB_VBLANK_STATUS                                                                         0x1025
7755 #define mmLB5_LB_VBLANK_STATUS_BASE_IDX                                                                2
7756 #define mmLB5_LB_SYNC_RESET_SEL                                                                        0x1026
7757 #define mmLB5_LB_SYNC_RESET_SEL_BASE_IDX                                                               2
7758 #define mmLB5_LB_BLACK_KEYER_R_CR                                                                      0x1027
7759 #define mmLB5_LB_BLACK_KEYER_R_CR_BASE_IDX                                                             2
7760 #define mmLB5_LB_BLACK_KEYER_G_Y                                                                       0x1028
7761 #define mmLB5_LB_BLACK_KEYER_G_Y_BASE_IDX                                                              2
7762 #define mmLB5_LB_BLACK_KEYER_B_CB                                                                      0x1029
7763 #define mmLB5_LB_BLACK_KEYER_B_CB_BASE_IDX                                                             2
7764 #define mmLB5_LB_KEYER_COLOR_CTRL                                                                      0x102a
7765 #define mmLB5_LB_KEYER_COLOR_CTRL_BASE_IDX                                                             2
7766 #define mmLB5_LB_KEYER_COLOR_R_CR                                                                      0x102b
7767 #define mmLB5_LB_KEYER_COLOR_R_CR_BASE_IDX                                                             2
7768 #define mmLB5_LB_KEYER_COLOR_G_Y                                                                       0x102c
7769 #define mmLB5_LB_KEYER_COLOR_G_Y_BASE_IDX                                                              2
7770 #define mmLB5_LB_KEYER_COLOR_B_CB                                                                      0x102d
7771 #define mmLB5_LB_KEYER_COLOR_B_CB_BASE_IDX                                                             2
7772 #define mmLB5_LB_KEYER_COLOR_REP_R_CR                                                                  0x102e
7773 #define mmLB5_LB_KEYER_COLOR_REP_R_CR_BASE_IDX                                                         2
7774 #define mmLB5_LB_KEYER_COLOR_REP_G_Y                                                                   0x102f
7775 #define mmLB5_LB_KEYER_COLOR_REP_G_Y_BASE_IDX                                                          2
7776 #define mmLB5_LB_KEYER_COLOR_REP_B_CB                                                                  0x1030
7777 #define mmLB5_LB_KEYER_COLOR_REP_B_CB_BASE_IDX                                                         2
7778 #define mmLB5_LB_BUFFER_LEVEL_STATUS                                                                   0x1031
7779 #define mmLB5_LB_BUFFER_LEVEL_STATUS_BASE_IDX                                                          2
7780 #define mmLB5_LB_BUFFER_URGENCY_CTRL                                                                   0x1032
7781 #define mmLB5_LB_BUFFER_URGENCY_CTRL_BASE_IDX                                                          2
7782 #define mmLB5_LB_BUFFER_URGENCY_STATUS                                                                 0x1033
7783 #define mmLB5_LB_BUFFER_URGENCY_STATUS_BASE_IDX                                                        2
7784 #define mmLB5_LB_BUFFER_STATUS                                                                         0x1034
7785 #define mmLB5_LB_BUFFER_STATUS_BASE_IDX                                                                2
7786 #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS                                                             0x1035
7787 #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX                                                    2
7788 #define mmLB5_MVP_AFR_FLIP_MODE                                                                        0x1036
7789 #define mmLB5_MVP_AFR_FLIP_MODE_BASE_IDX                                                               2
7790 #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL                                                                   0x1037
7791 #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX                                                          2
7792 #define mmLB5_MVP_FLIP_LINE_NUM_INSERT                                                                 0x1038
7793 #define mmLB5_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX                                                        2
7794 #define mmLB5_DC_MVP_LB_CONTROL                                                                        0x1039
7795 #define mmLB5_DC_MVP_LB_CONTROL_BASE_IDX                                                               2
7796 
7797 
7798 // addressBlock: dce_dc_dcfe5_dispdec
7799 // base address: 0x2800
7800 #define mmDCFE5_DCFE_CLOCK_CONTROL                                                                     0x105a
7801 #define mmDCFE5_DCFE_CLOCK_CONTROL_BASE_IDX                                                            2
7802 #define mmDCFE5_DCFE_SOFT_RESET                                                                        0x105b
7803 #define mmDCFE5_DCFE_SOFT_RESET_BASE_IDX                                                               2
7804 #define mmDCFE5_DCFE_MEM_PWR_CTRL                                                                      0x105d
7805 #define mmDCFE5_DCFE_MEM_PWR_CTRL_BASE_IDX                                                             2
7806 #define mmDCFE5_DCFE_MEM_PWR_CTRL2                                                                     0x105e
7807 #define mmDCFE5_DCFE_MEM_PWR_CTRL2_BASE_IDX                                                            2
7808 #define mmDCFE5_DCFE_MEM_PWR_STATUS                                                                    0x105f
7809 #define mmDCFE5_DCFE_MEM_PWR_STATUS_BASE_IDX                                                           2
7810 #define mmDCFE5_DCFE_MISC                                                                              0x1060
7811 #define mmDCFE5_DCFE_MISC_BASE_IDX                                                                     2
7812 #define mmDCFE5_DCFE_FLUSH                                                                             0x1061
7813 #define mmDCFE5_DCFE_FLUSH_BASE_IDX                                                                    2
7814 
7815 
7816 // addressBlock: dce_dc_dc_perfmon8_dispdec
7817 // base address: 0x4138
7818 #define mmDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x106e
7819 #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
7820 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x106f
7821 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
7822 #define mmDC_PERFMON8_PERFCOUNTER_STATE                                                                0x1070
7823 #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
7824 #define mmDC_PERFMON8_PERFMON_CNTL                                                                     0x1071
7825 #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
7826 #define mmDC_PERFMON8_PERFMON_CNTL2                                                                    0x1072
7827 #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
7828 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x1073
7829 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
7830 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x1074
7831 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
7832 #define mmDC_PERFMON8_PERFMON_HI                                                                       0x1075
7833 #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
7834 #define mmDC_PERFMON8_PERFMON_LOW                                                                      0x1076
7835 #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
7836 
7837 
7838 // addressBlock: dce_dc_dmif_pg5_dispdec
7839 // base address: 0x2800
7840 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1                                                       0x107a
7841 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                              2
7842 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2                                                       0x107b
7843 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                              2
7844 #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL                                                          0x107c
7845 #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_BASE_IDX                                                 2
7846 #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL                                                            0x107d
7847 #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_BASE_IDX                                                   2
7848 #define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL                                                       0x107e
7849 #define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX                                              2
7850 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL                                                            0x107f
7851 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_BASE_IDX                                                   2
7852 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2                                                           0x1080
7853 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX                                                  2
7854 #define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL                                                          0x1081
7855 #define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX                                                 2
7856 #define mmDMIF_PG5_DPG_REPEATER_PROGRAM                                                                0x1082
7857 #define mmDMIF_PG5_DPG_REPEATER_PROGRAM_BASE_IDX                                                       2
7858 #define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL                                                               0x1086
7859 #define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_BASE_IDX                                                      2
7860 #define mmDMIF_PG5_DPG_DVMM_STATUS                                                                     0x1087
7861 #define mmDMIF_PG5_DPG_DVMM_STATUS_BASE_IDX                                                            2
7862 
7863 
7864 // addressBlock: dce_dc_scl5_dispdec
7865 // base address: 0x2800
7866 #define mmSCL5_SCL_COEF_RAM_SELECT                                                                     0x109a
7867 #define mmSCL5_SCL_COEF_RAM_SELECT_BASE_IDX                                                            2
7868 #define mmSCL5_SCL_COEF_RAM_TAP_DATA                                                                   0x109b
7869 #define mmSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                          2
7870 #define mmSCL5_SCL_MODE                                                                                0x109c
7871 #define mmSCL5_SCL_MODE_BASE_IDX                                                                       2
7872 #define mmSCL5_SCL_TAP_CONTROL                                                                         0x109d
7873 #define mmSCL5_SCL_TAP_CONTROL_BASE_IDX                                                                2
7874 #define mmSCL5_SCL_CONTROL                                                                             0x109e
7875 #define mmSCL5_SCL_CONTROL_BASE_IDX                                                                    2
7876 #define mmSCL5_SCL_BYPASS_CONTROL                                                                      0x109f
7877 #define mmSCL5_SCL_BYPASS_CONTROL_BASE_IDX                                                             2
7878 #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL                                                            0x10a0
7879 #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                   2
7880 #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL                                                              0x10a1
7881 #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX                                                     2
7882 #define mmSCL5_SCL_HORZ_FILTER_CONTROL                                                                 0x10a2
7883 #define mmSCL5_SCL_HORZ_FILTER_CONTROL_BASE_IDX                                                        2
7884 #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO                                                             0x10a3
7885 #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                    2
7886 #define mmSCL5_SCL_HORZ_FILTER_INIT                                                                    0x10a4
7887 #define mmSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX                                                           2
7888 #define mmSCL5_SCL_VERT_FILTER_CONTROL                                                                 0x10a5
7889 #define mmSCL5_SCL_VERT_FILTER_CONTROL_BASE_IDX                                                        2
7890 #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO                                                             0x10a6
7891 #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                    2
7892 #define mmSCL5_SCL_VERT_FILTER_INIT                                                                    0x10a7
7893 #define mmSCL5_SCL_VERT_FILTER_INIT_BASE_IDX                                                           2
7894 #define mmSCL5_SCL_VERT_FILTER_INIT_BOT                                                                0x10a8
7895 #define mmSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                       2
7896 #define mmSCL5_SCL_ROUND_OFFSET                                                                        0x10a9
7897 #define mmSCL5_SCL_ROUND_OFFSET_BASE_IDX                                                               2
7898 #define mmSCL5_SCL_UPDATE                                                                              0x10aa
7899 #define mmSCL5_SCL_UPDATE_BASE_IDX                                                                     2
7900 #define mmSCL5_SCL_F_SHARP_CONTROL                                                                     0x10ab
7901 #define mmSCL5_SCL_F_SHARP_CONTROL_BASE_IDX                                                            2
7902 #define mmSCL5_SCL_ALU_CONTROL                                                                         0x10ac
7903 #define mmSCL5_SCL_ALU_CONTROL_BASE_IDX                                                                2
7904 #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS                                                            0x10ad
7905 #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                   2
7906 #define mmSCL5_VIEWPORT_START_SECONDARY                                                                0x10ae
7907 #define mmSCL5_VIEWPORT_START_SECONDARY_BASE_IDX                                                       2
7908 #define mmSCL5_VIEWPORT_START                                                                          0x10af
7909 #define mmSCL5_VIEWPORT_START_BASE_IDX                                                                 2
7910 #define mmSCL5_VIEWPORT_SIZE                                                                           0x10b0
7911 #define mmSCL5_VIEWPORT_SIZE_BASE_IDX                                                                  2
7912 #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT                                                                 0x10b1
7913 #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                        2
7914 #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM                                                                 0x10b2
7915 #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                        2
7916 #define mmSCL5_SCL_MODE_CHANGE_DET1                                                                    0x10b3
7917 #define mmSCL5_SCL_MODE_CHANGE_DET1_BASE_IDX                                                           2
7918 #define mmSCL5_SCL_MODE_CHANGE_DET2                                                                    0x10b4
7919 #define mmSCL5_SCL_MODE_CHANGE_DET2_BASE_IDX                                                           2
7920 #define mmSCL5_SCL_MODE_CHANGE_DET3                                                                    0x10b5
7921 #define mmSCL5_SCL_MODE_CHANGE_DET3_BASE_IDX                                                           2
7922 #define mmSCL5_SCL_MODE_CHANGE_MASK                                                                    0x10b6
7923 #define mmSCL5_SCL_MODE_CHANGE_MASK_BASE_IDX                                                           2
7924 
7925 
7926 // addressBlock: dce_dc_blnd5_dispdec
7927 // base address: 0x2800
7928 #define mmBLND5_BLND_CONTROL                                                                           0x10c7
7929 #define mmBLND5_BLND_CONTROL_BASE_IDX                                                                  2
7930 #define mmBLND5_BLND_SM_CONTROL2                                                                       0x10c8
7931 #define mmBLND5_BLND_SM_CONTROL2_BASE_IDX                                                              2
7932 #define mmBLND5_BLND_CONTROL2                                                                          0x10c9
7933 #define mmBLND5_BLND_CONTROL2_BASE_IDX                                                                 2
7934 #define mmBLND5_BLND_UPDATE                                                                            0x10ca
7935 #define mmBLND5_BLND_UPDATE_BASE_IDX                                                                   2
7936 #define mmBLND5_BLND_UNDERFLOW_INTERRUPT                                                               0x10cb
7937 #define mmBLND5_BLND_UNDERFLOW_INTERRUPT_BASE_IDX                                                      2
7938 #define mmBLND5_BLND_V_UPDATE_LOCK                                                                     0x10cc
7939 #define mmBLND5_BLND_V_UPDATE_LOCK_BASE_IDX                                                            2
7940 #define mmBLND5_BLND_REG_UPDATE_STATUS                                                                 0x10cd
7941 #define mmBLND5_BLND_REG_UPDATE_STATUS_BASE_IDX                                                        2
7942 
7943 
7944 // addressBlock: dce_dc_crtc5_dispdec
7945 // base address: 0x2800
7946 #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM                                                                 0x10d2
7947 #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_BASE_IDX                                                        2
7948 #define mmCRTC5_CRTC_H_TOTAL                                                                           0x10d3
7949 #define mmCRTC5_CRTC_H_TOTAL_BASE_IDX                                                                  2
7950 #define mmCRTC5_CRTC_H_BLANK_START_END                                                                 0x10d4
7951 #define mmCRTC5_CRTC_H_BLANK_START_END_BASE_IDX                                                        2
7952 #define mmCRTC5_CRTC_H_SYNC_A                                                                          0x10d5
7953 #define mmCRTC5_CRTC_H_SYNC_A_BASE_IDX                                                                 2
7954 #define mmCRTC5_CRTC_H_SYNC_A_CNTL                                                                     0x10d6
7955 #define mmCRTC5_CRTC_H_SYNC_A_CNTL_BASE_IDX                                                            2
7956 #define mmCRTC5_CRTC_H_SYNC_B                                                                          0x10d7
7957 #define mmCRTC5_CRTC_H_SYNC_B_BASE_IDX                                                                 2
7958 #define mmCRTC5_CRTC_H_SYNC_B_CNTL                                                                     0x10d8
7959 #define mmCRTC5_CRTC_H_SYNC_B_CNTL_BASE_IDX                                                            2
7960 #define mmCRTC5_CRTC_VBI_END                                                                           0x10d9
7961 #define mmCRTC5_CRTC_VBI_END_BASE_IDX                                                                  2
7962 #define mmCRTC5_CRTC_V_TOTAL                                                                           0x10da
7963 #define mmCRTC5_CRTC_V_TOTAL_BASE_IDX                                                                  2
7964 #define mmCRTC5_CRTC_V_TOTAL_MIN                                                                       0x10db
7965 #define mmCRTC5_CRTC_V_TOTAL_MIN_BASE_IDX                                                              2
7966 #define mmCRTC5_CRTC_V_TOTAL_MAX                                                                       0x10dc
7967 #define mmCRTC5_CRTC_V_TOTAL_MAX_BASE_IDX                                                              2
7968 #define mmCRTC5_CRTC_V_TOTAL_CONTROL                                                                   0x10dd
7969 #define mmCRTC5_CRTC_V_TOTAL_CONTROL_BASE_IDX                                                          2
7970 #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS                                                                0x10de
7971 #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_BASE_IDX                                                       2
7972 #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS                                                              0x10df
7973 #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX                                                     2
7974 #define mmCRTC5_CRTC_V_BLANK_START_END                                                                 0x10e0
7975 #define mmCRTC5_CRTC_V_BLANK_START_END_BASE_IDX                                                        2
7976 #define mmCRTC5_CRTC_V_SYNC_A                                                                          0x10e1
7977 #define mmCRTC5_CRTC_V_SYNC_A_BASE_IDX                                                                 2
7978 #define mmCRTC5_CRTC_V_SYNC_A_CNTL                                                                     0x10e2
7979 #define mmCRTC5_CRTC_V_SYNC_A_CNTL_BASE_IDX                                                            2
7980 #define mmCRTC5_CRTC_V_SYNC_B                                                                          0x10e3
7981 #define mmCRTC5_CRTC_V_SYNC_B_BASE_IDX                                                                 2
7982 #define mmCRTC5_CRTC_V_SYNC_B_CNTL                                                                     0x10e4
7983 #define mmCRTC5_CRTC_V_SYNC_B_CNTL_BASE_IDX                                                            2
7984 #define mmCRTC5_CRTC_DTMTEST_CNTL                                                                      0x10e5
7985 #define mmCRTC5_CRTC_DTMTEST_CNTL_BASE_IDX                                                             2
7986 #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION                                                           0x10e6
7987 #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX                                                  2
7988 #define mmCRTC5_CRTC_TRIGA_CNTL                                                                        0x10e7
7989 #define mmCRTC5_CRTC_TRIGA_CNTL_BASE_IDX                                                               2
7990 #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG                                                                 0x10e8
7991 #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX                                                        2
7992 #define mmCRTC5_CRTC_TRIGB_CNTL                                                                        0x10e9
7993 #define mmCRTC5_CRTC_TRIGB_CNTL_BASE_IDX                                                               2
7994 #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG                                                                 0x10ea
7995 #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX                                                        2
7996 #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL                                                              0x10eb
7997 #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                     2
7998 #define mmCRTC5_CRTC_FLOW_CONTROL                                                                      0x10ec
7999 #define mmCRTC5_CRTC_FLOW_CONTROL_BASE_IDX                                                             2
8000 #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE                                                             0x10ed
8001 #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                    2
8002 #define mmCRTC5_CRTC_AVSYNC_COUNTER                                                                    0x10ee
8003 #define mmCRTC5_CRTC_AVSYNC_COUNTER_BASE_IDX                                                           2
8004 #define mmCRTC5_CRTC_CONTROL                                                                           0x10ef
8005 #define mmCRTC5_CRTC_CONTROL_BASE_IDX                                                                  2
8006 #define mmCRTC5_CRTC_BLANK_CONTROL                                                                     0x10f0
8007 #define mmCRTC5_CRTC_BLANK_CONTROL_BASE_IDX                                                            2
8008 #define mmCRTC5_CRTC_INTERLACE_CONTROL                                                                 0x10f1
8009 #define mmCRTC5_CRTC_INTERLACE_CONTROL_BASE_IDX                                                        2
8010 #define mmCRTC5_CRTC_INTERLACE_STATUS                                                                  0x10f2
8011 #define mmCRTC5_CRTC_INTERLACE_STATUS_BASE_IDX                                                         2
8012 #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL                                                          0x10f3
8013 #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX                                                 2
8014 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0                                                              0x10f4
8015 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_BASE_IDX                                                     2
8016 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1                                                              0x10f5
8017 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_BASE_IDX                                                     2
8018 #define mmCRTC5_CRTC_STATUS                                                                            0x10f6
8019 #define mmCRTC5_CRTC_STATUS_BASE_IDX                                                                   2
8020 #define mmCRTC5_CRTC_STATUS_POSITION                                                                   0x10f7
8021 #define mmCRTC5_CRTC_STATUS_POSITION_BASE_IDX                                                          2
8022 #define mmCRTC5_CRTC_NOM_VERT_POSITION                                                                 0x10f8
8023 #define mmCRTC5_CRTC_NOM_VERT_POSITION_BASE_IDX                                                        2
8024 #define mmCRTC5_CRTC_STATUS_FRAME_COUNT                                                                0x10f9
8025 #define mmCRTC5_CRTC_STATUS_FRAME_COUNT_BASE_IDX                                                       2
8026 #define mmCRTC5_CRTC_STATUS_VF_COUNT                                                                   0x10fa
8027 #define mmCRTC5_CRTC_STATUS_VF_COUNT_BASE_IDX                                                          2
8028 #define mmCRTC5_CRTC_STATUS_HV_COUNT                                                                   0x10fb
8029 #define mmCRTC5_CRTC_STATUS_HV_COUNT_BASE_IDX                                                          2
8030 #define mmCRTC5_CRTC_COUNT_CONTROL                                                                     0x10fc
8031 #define mmCRTC5_CRTC_COUNT_CONTROL_BASE_IDX                                                            2
8032 #define mmCRTC5_CRTC_COUNT_RESET                                                                       0x10fd
8033 #define mmCRTC5_CRTC_COUNT_RESET_BASE_IDX                                                              2
8034 #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE                                                      0x10fe
8035 #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                             2
8036 #define mmCRTC5_CRTC_VERT_SYNC_CONTROL                                                                 0x10ff
8037 #define mmCRTC5_CRTC_VERT_SYNC_CONTROL_BASE_IDX                                                        2
8038 #define mmCRTC5_CRTC_STEREO_STATUS                                                                     0x1100
8039 #define mmCRTC5_CRTC_STEREO_STATUS_BASE_IDX                                                            2
8040 #define mmCRTC5_CRTC_STEREO_CONTROL                                                                    0x1101
8041 #define mmCRTC5_CRTC_STEREO_CONTROL_BASE_IDX                                                           2
8042 #define mmCRTC5_CRTC_SNAPSHOT_STATUS                                                                   0x1102
8043 #define mmCRTC5_CRTC_SNAPSHOT_STATUS_BASE_IDX                                                          2
8044 #define mmCRTC5_CRTC_SNAPSHOT_CONTROL                                                                  0x1103
8045 #define mmCRTC5_CRTC_SNAPSHOT_CONTROL_BASE_IDX                                                         2
8046 #define mmCRTC5_CRTC_SNAPSHOT_POSITION                                                                 0x1104
8047 #define mmCRTC5_CRTC_SNAPSHOT_POSITION_BASE_IDX                                                        2
8048 #define mmCRTC5_CRTC_SNAPSHOT_FRAME                                                                    0x1105
8049 #define mmCRTC5_CRTC_SNAPSHOT_FRAME_BASE_IDX                                                           2
8050 #define mmCRTC5_CRTC_START_LINE_CONTROL                                                                0x1106
8051 #define mmCRTC5_CRTC_START_LINE_CONTROL_BASE_IDX                                                       2
8052 #define mmCRTC5_CRTC_INTERRUPT_CONTROL                                                                 0x1107
8053 #define mmCRTC5_CRTC_INTERRUPT_CONTROL_BASE_IDX                                                        2
8054 #define mmCRTC5_CRTC_UPDATE_LOCK                                                                       0x1108
8055 #define mmCRTC5_CRTC_UPDATE_LOCK_BASE_IDX                                                              2
8056 #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL                                                             0x1109
8057 #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                    2
8058 #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE                                                        0x110a
8059 #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX                                               2
8060 #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL                                                              0x110b
8061 #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_BASE_IDX                                                     2
8062 #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS                                                           0x110c
8063 #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX                                                  2
8064 #define mmCRTC5_CRTC_TEST_PATTERN_COLOR                                                                0x110d
8065 #define mmCRTC5_CRTC_TEST_PATTERN_COLOR_BASE_IDX                                                       2
8066 #define mmCRTC5_CRTC_MASTER_UPDATE_LOCK                                                                0x110e
8067 #define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_BASE_IDX                                                       2
8068 #define mmCRTC5_CRTC_MASTER_UPDATE_MODE                                                                0x110f
8069 #define mmCRTC5_CRTC_MASTER_UPDATE_MODE_BASE_IDX                                                       2
8070 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT                                                            0x1110
8071 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX                                                   2
8072 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER                                                      0x1111
8073 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX                                             2
8074 #define mmCRTC5_CRTC_MVP_STATUS                                                                        0x1112
8075 #define mmCRTC5_CRTC_MVP_STATUS_BASE_IDX                                                               2
8076 #define mmCRTC5_CRTC_MASTER_EN                                                                         0x1113
8077 #define mmCRTC5_CRTC_MASTER_EN_BASE_IDX                                                                2
8078 #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT                                                              0x1114
8079 #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX                                                     2
8080 #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS                                                               0x1115
8081 #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_BASE_IDX                                                      2
8082 #define mmCRTC5_CRTC_OVERSCAN_COLOR                                                                    0x1117
8083 #define mmCRTC5_CRTC_OVERSCAN_COLOR_BASE_IDX                                                           2
8084 #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT                                                                0x1118
8085 #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX                                                       2
8086 #define mmCRTC5_CRTC_BLANK_DATA_COLOR                                                                  0x1119
8087 #define mmCRTC5_CRTC_BLANK_DATA_COLOR_BASE_IDX                                                         2
8088 #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT                                                              0x111a
8089 #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX                                                     2
8090 #define mmCRTC5_CRTC_BLACK_COLOR                                                                       0x111b
8091 #define mmCRTC5_CRTC_BLACK_COLOR_BASE_IDX                                                              2
8092 #define mmCRTC5_CRTC_BLACK_COLOR_EXT                                                                   0x111c
8093 #define mmCRTC5_CRTC_BLACK_COLOR_EXT_BASE_IDX                                                          2
8094 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION                                                      0x111d
8095 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                             2
8096 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL                                                       0x111e
8097 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                              2
8098 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION                                                      0x111f
8099 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                             2
8100 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL                                                       0x1120
8101 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                              2
8102 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION                                                      0x1121
8103 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                             2
8104 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL                                                       0x1122
8105 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                              2
8106 #define mmCRTC5_CRTC_CRC_CNTL                                                                          0x1123
8107 #define mmCRTC5_CRTC_CRC_CNTL_BASE_IDX                                                                 2
8108 #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL                                                            0x1124
8109 #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                   2
8110 #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL                                                            0x1125
8111 #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
8112 #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL                                                            0x1126
8113 #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                   2
8114 #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL                                                            0x1127
8115 #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
8116 #define mmCRTC5_CRTC_CRC0_DATA_RG                                                                      0x1128
8117 #define mmCRTC5_CRTC_CRC0_DATA_RG_BASE_IDX                                                             2
8118 #define mmCRTC5_CRTC_CRC0_DATA_B                                                                       0x1129
8119 #define mmCRTC5_CRTC_CRC0_DATA_B_BASE_IDX                                                              2
8120 #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL                                                            0x112a
8121 #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                   2
8122 #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL                                                            0x112b
8123 #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                   2
8124 #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL                                                            0x112c
8125 #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                   2
8126 #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL                                                            0x112d
8127 #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                   2
8128 #define mmCRTC5_CRTC_CRC1_DATA_RG                                                                      0x112e
8129 #define mmCRTC5_CRTC_CRC1_DATA_RG_BASE_IDX                                                             2
8130 #define mmCRTC5_CRTC_CRC1_DATA_B                                                                       0x112f
8131 #define mmCRTC5_CRTC_CRC1_DATA_B_BASE_IDX                                                              2
8132 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL                                                           0x1130
8133 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX                                                  2
8134 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START                                                      0x1131
8135 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX                                             2
8136 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END                                                        0x1132
8137 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX                                               2
8138 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                                            0x1133
8139 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX                                   2
8140 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                                 0x1134
8141 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX                                        2
8142 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                                          0x1135
8143 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX                                 2
8144 #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL                                                             0x1136
8145 #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX                                                    2
8146 #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL                                                              0x1137
8147 #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX                                                     2
8148 #define mmCRTC5_CRTC_GSL_VSYNC_GAP                                                                     0x1138
8149 #define mmCRTC5_CRTC_GSL_VSYNC_GAP_BASE_IDX                                                            2
8150 #define mmCRTC5_CRTC_GSL_WINDOW                                                                        0x1139
8151 #define mmCRTC5_CRTC_GSL_WINDOW_BASE_IDX                                                               2
8152 #define mmCRTC5_CRTC_GSL_CONTROL                                                                       0x113a
8153 #define mmCRTC5_CRTC_GSL_CONTROL_BASE_IDX                                                              2
8154 #define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS                                                           0x113d
8155 #define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX                                                  2
8156 #define mmCRTC5_CRTC_DRR_CONTROL                                                                       0x113e
8157 #define mmCRTC5_CRTC_DRR_CONTROL_BASE_IDX                                                              2
8158 
8159 
8160 // addressBlock: dce_dc_fmt5_dispdec
8161 // base address: 0x2800
8162 #define mmFMT5_FMT_CLAMP_COMPONENT_R                                                                   0x1142
8163 #define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
8164 #define mmFMT5_FMT_CLAMP_COMPONENT_G                                                                   0x1143
8165 #define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
8166 #define mmFMT5_FMT_CLAMP_COMPONENT_B                                                                   0x1144
8167 #define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
8168 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL                                                                    0x1145
8169 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
8170 #define mmFMT5_FMT_CONTROL                                                                             0x1146
8171 #define mmFMT5_FMT_CONTROL_BASE_IDX                                                                    2
8172 #define mmFMT5_FMT_BIT_DEPTH_CONTROL                                                                   0x1147
8173 #define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
8174 #define mmFMT5_FMT_DITHER_RAND_R_SEED                                                                  0x1148
8175 #define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
8176 #define mmFMT5_FMT_DITHER_RAND_G_SEED                                                                  0x1149
8177 #define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
8178 #define mmFMT5_FMT_DITHER_RAND_B_SEED                                                                  0x114a
8179 #define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
8180 #define mmFMT5_FMT_CLAMP_CNTL                                                                          0x114e
8181 #define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
8182 #define mmFMT5_FMT_CRC_CNTL                                                                            0x114f
8183 #define mmFMT5_FMT_CRC_CNTL_BASE_IDX                                                                   2
8184 #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK                                                              0x1150
8185 #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
8186 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1151
8187 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
8188 #define mmFMT5_FMT_CRC_SIG_RED_GREEN                                                                   0x1152
8189 #define mmFMT5_FMT_CRC_SIG_RED_GREEN_BASE_IDX                                                          2
8190 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL                                                                0x1153
8191 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX                                                       2
8192 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1154
8193 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
8194 #define mmFMT5_FMT_420_HBLANK_EARLY_START                                                              0x1155
8195 #define mmFMT5_FMT_420_HBLANK_EARLY_START_BASE_IDX                                                     2
8196 
8197 
8198 // addressBlock: dce_dc_unp0_dispdec
8199 // base address: 0x0
8200 #define mmUNP0_UNP_GRPH_ENABLE                                                                         0x115a
8201 #define mmUNP0_UNP_GRPH_ENABLE_BASE_IDX                                                                2
8202 #define mmUNP0_UNP_GRPH_CONTROL                                                                        0x115b
8203 #define mmUNP0_UNP_GRPH_CONTROL_BASE_IDX                                                               2
8204 #define mmUNP0_UNP_GRPH_CONTROL_C                                                                      0x115c
8205 #define mmUNP0_UNP_GRPH_CONTROL_C_BASE_IDX                                                             2
8206 #define mmUNP0_UNP_GRPH_CONTROL_EXP                                                                    0x115d
8207 #define mmUNP0_UNP_GRPH_CONTROL_EXP_BASE_IDX                                                           2
8208 #define mmUNP0_UNP_GRPH_SWAP_CNTL                                                                      0x115e
8209 #define mmUNP0_UNP_GRPH_SWAP_CNTL_BASE_IDX                                                             2
8210 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                                                      0x115f
8211 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX                                             2
8212 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                                                      0x1160
8213 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                             2
8214 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                                                 0x1161
8215 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX                                        2
8216 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                                                 0x1162
8217 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                        2
8218 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                                               0x1163
8219 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX                                      2
8220 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                                               0x1164
8221 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX                                      2
8222 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                                          0x1165
8223 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX                                 2
8224 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                                          0x1166
8225 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
8226 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                                                    0x1167
8227 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX                                           2
8228 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                                                    0x1168
8229 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
8230 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                                               0x1169
8231 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX                                      2
8232 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                                               0x116a
8233 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
8234 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                                             0x116b
8235 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX                                    2
8236 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                                             0x116c
8237 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX                                    2
8238 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                                        0x116d
8239 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX                               2
8240 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                                        0x116e
8241 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
8242 #define mmUNP0_UNP_GRPH_PITCH_L                                                                        0x116f
8243 #define mmUNP0_UNP_GRPH_PITCH_L_BASE_IDX                                                               2
8244 #define mmUNP0_UNP_GRPH_PITCH_C                                                                        0x1170
8245 #define mmUNP0_UNP_GRPH_PITCH_C_BASE_IDX                                                               2
8246 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L                                                             0x1171
8247 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX                                                    2
8248 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C                                                             0x1172
8249 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX                                                    2
8250 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L                                                             0x1173
8251 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX                                                    2
8252 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C                                                             0x1174
8253 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX                                                    2
8254 #define mmUNP0_UNP_GRPH_X_START_L                                                                      0x1175
8255 #define mmUNP0_UNP_GRPH_X_START_L_BASE_IDX                                                             2
8256 #define mmUNP0_UNP_GRPH_X_START_C                                                                      0x1176
8257 #define mmUNP0_UNP_GRPH_X_START_C_BASE_IDX                                                             2
8258 #define mmUNP0_UNP_GRPH_Y_START_L                                                                      0x1177
8259 #define mmUNP0_UNP_GRPH_Y_START_L_BASE_IDX                                                             2
8260 #define mmUNP0_UNP_GRPH_Y_START_C                                                                      0x1178
8261 #define mmUNP0_UNP_GRPH_Y_START_C_BASE_IDX                                                             2
8262 #define mmUNP0_UNP_GRPH_X_END_L                                                                        0x1179
8263 #define mmUNP0_UNP_GRPH_X_END_L_BASE_IDX                                                               2
8264 #define mmUNP0_UNP_GRPH_X_END_C                                                                        0x117a
8265 #define mmUNP0_UNP_GRPH_X_END_C_BASE_IDX                                                               2
8266 #define mmUNP0_UNP_GRPH_Y_END_L                                                                        0x117b
8267 #define mmUNP0_UNP_GRPH_Y_END_L_BASE_IDX                                                               2
8268 #define mmUNP0_UNP_GRPH_Y_END_C                                                                        0x117c
8269 #define mmUNP0_UNP_GRPH_Y_END_C_BASE_IDX                                                               2
8270 #define mmUNP0_UNP_GRPH_UPDATE                                                                         0x117d
8271 #define mmUNP0_UNP_GRPH_UPDATE_BASE_IDX                                                                2
8272 #define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT                                                      0x117e
8273 #define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX                                             2
8274 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L                                                        0x117f
8275 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX                                               2
8276 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C                                                        0x1180
8277 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX                                               2
8278 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                                                   0x1181
8279 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX                                          2
8280 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                                                   0x1182
8281 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX                                          2
8282 #define mmUNP0_UNP_DVMM_PTE_CONTROL                                                                    0x1183
8283 #define mmUNP0_UNP_DVMM_PTE_CONTROL_BASE_IDX                                                           2
8284 #define mmUNP0_UNP_DVMM_PTE_CONTROL_C                                                                  0x1184
8285 #define mmUNP0_UNP_DVMM_PTE_CONTROL_C_BASE_IDX                                                         2
8286 #define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL                                                                0x1185
8287 #define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX                                                       2
8288 #define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C                                                              0x1186
8289 #define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX                                                     2
8290 #define mmUNP0_UNP_GRPH_INTERRUPT_STATUS                                                               0x1187
8291 #define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX                                                      2
8292 #define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL                                                              0x1188
8293 #define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX                                                     2
8294 #define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP                                                                0x1189
8295 #define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX                                                       2
8296 #define mmUNP0_UNP_FLIP_CONTROL                                                                        0x118a
8297 #define mmUNP0_UNP_FLIP_CONTROL_BASE_IDX                                                               2
8298 #define mmUNP0_UNP_CRC_CONTROL                                                                         0x118b
8299 #define mmUNP0_UNP_CRC_CONTROL_BASE_IDX                                                                2
8300 #define mmUNP0_UNP_CRC_MASK                                                                            0x118c
8301 #define mmUNP0_UNP_CRC_MASK_BASE_IDX                                                                   2
8302 #define mmUNP0_UNP_CRC_CURRENT                                                                         0x118d
8303 #define mmUNP0_UNP_CRC_CURRENT_BASE_IDX                                                                2
8304 #define mmUNP0_UNP_CRC_LAST                                                                            0x118e
8305 #define mmUNP0_UNP_CRC_LAST_BASE_IDX                                                                   2
8306 #define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK                                                           0x118f
8307 #define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX                                                  2
8308 #define mmUNP0_UNP_HW_ROTATION                                                                         0x1190
8309 #define mmUNP0_UNP_HW_ROTATION_BASE_IDX                                                                2
8310 
8311 
8312 // addressBlock: dce_dc_lbv0_dispdec
8313 // base address: 0x0
8314 #define mmLBV0_LBV_DATA_FORMAT                                                                         0x1196
8315 #define mmLBV0_LBV_DATA_FORMAT_BASE_IDX                                                                2
8316 #define mmLBV0_LBV_MEMORY_CTRL                                                                         0x1197
8317 #define mmLBV0_LBV_MEMORY_CTRL_BASE_IDX                                                                2
8318 #define mmLBV0_LBV_MEMORY_SIZE_STATUS                                                                  0x1198
8319 #define mmLBV0_LBV_MEMORY_SIZE_STATUS_BASE_IDX                                                         2
8320 #define mmLBV0_LBV_DESKTOP_HEIGHT                                                                      0x1199
8321 #define mmLBV0_LBV_DESKTOP_HEIGHT_BASE_IDX                                                             2
8322 #define mmLBV0_LBV_VLINE_START_END                                                                     0x119a
8323 #define mmLBV0_LBV_VLINE_START_END_BASE_IDX                                                            2
8324 #define mmLBV0_LBV_VLINE2_START_END                                                                    0x119b
8325 #define mmLBV0_LBV_VLINE2_START_END_BASE_IDX                                                           2
8326 #define mmLBV0_LBV_V_COUNTER                                                                           0x119c
8327 #define mmLBV0_LBV_V_COUNTER_BASE_IDX                                                                  2
8328 #define mmLBV0_LBV_SNAPSHOT_V_COUNTER                                                                  0x119d
8329 #define mmLBV0_LBV_SNAPSHOT_V_COUNTER_BASE_IDX                                                         2
8330 #define mmLBV0_LBV_V_COUNTER_CHROMA                                                                    0x119e
8331 #define mmLBV0_LBV_V_COUNTER_CHROMA_BASE_IDX                                                           2
8332 #define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA                                                           0x119f
8333 #define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX                                                  2
8334 #define mmLBV0_LBV_INTERRUPT_MASK                                                                      0x11a0
8335 #define mmLBV0_LBV_INTERRUPT_MASK_BASE_IDX                                                             2
8336 #define mmLBV0_LBV_VLINE_STATUS                                                                        0x11a1
8337 #define mmLBV0_LBV_VLINE_STATUS_BASE_IDX                                                               2
8338 #define mmLBV0_LBV_VLINE2_STATUS                                                                       0x11a2
8339 #define mmLBV0_LBV_VLINE2_STATUS_BASE_IDX                                                              2
8340 #define mmLBV0_LBV_VBLANK_STATUS                                                                       0x11a3
8341 #define mmLBV0_LBV_VBLANK_STATUS_BASE_IDX                                                              2
8342 #define mmLBV0_LBV_SYNC_RESET_SEL                                                                      0x11a4
8343 #define mmLBV0_LBV_SYNC_RESET_SEL_BASE_IDX                                                             2
8344 #define mmLBV0_LBV_BLACK_KEYER_R_CR                                                                    0x11a5
8345 #define mmLBV0_LBV_BLACK_KEYER_R_CR_BASE_IDX                                                           2
8346 #define mmLBV0_LBV_BLACK_KEYER_G_Y                                                                     0x11a6
8347 #define mmLBV0_LBV_BLACK_KEYER_G_Y_BASE_IDX                                                            2
8348 #define mmLBV0_LBV_BLACK_KEYER_B_CB                                                                    0x11a7
8349 #define mmLBV0_LBV_BLACK_KEYER_B_CB_BASE_IDX                                                           2
8350 #define mmLBV0_LBV_KEYER_COLOR_CTRL                                                                    0x11a8
8351 #define mmLBV0_LBV_KEYER_COLOR_CTRL_BASE_IDX                                                           2
8352 #define mmLBV0_LBV_KEYER_COLOR_R_CR                                                                    0x11a9
8353 #define mmLBV0_LBV_KEYER_COLOR_R_CR_BASE_IDX                                                           2
8354 #define mmLBV0_LBV_KEYER_COLOR_G_Y                                                                     0x11aa
8355 #define mmLBV0_LBV_KEYER_COLOR_G_Y_BASE_IDX                                                            2
8356 #define mmLBV0_LBV_KEYER_COLOR_B_CB                                                                    0x11ab
8357 #define mmLBV0_LBV_KEYER_COLOR_B_CB_BASE_IDX                                                           2
8358 #define mmLBV0_LBV_KEYER_COLOR_REP_R_CR                                                                0x11ac
8359 #define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX                                                       2
8360 #define mmLBV0_LBV_KEYER_COLOR_REP_G_Y                                                                 0x11ad
8361 #define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX                                                        2
8362 #define mmLBV0_LBV_KEYER_COLOR_REP_B_CB                                                                0x11ae
8363 #define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX                                                       2
8364 #define mmLBV0_LBV_BUFFER_LEVEL_STATUS                                                                 0x11af
8365 #define mmLBV0_LBV_BUFFER_LEVEL_STATUS_BASE_IDX                                                        2
8366 #define mmLBV0_LBV_BUFFER_URGENCY_CTRL                                                                 0x11b0
8367 #define mmLBV0_LBV_BUFFER_URGENCY_CTRL_BASE_IDX                                                        2
8368 #define mmLBV0_LBV_BUFFER_URGENCY_STATUS                                                               0x11b1
8369 #define mmLBV0_LBV_BUFFER_URGENCY_STATUS_BASE_IDX                                                      2
8370 #define mmLBV0_LBV_BUFFER_STATUS                                                                       0x11b2
8371 #define mmLBV0_LBV_BUFFER_STATUS_BASE_IDX                                                              2
8372 #define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS                                                           0x11b3
8373 #define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX                                                  2
8374 
8375 
8376 // addressBlock: dce_dc_sclv0_dispdec
8377 // base address: 0x0
8378 #define mmSCLV0_SCLV_COEF_RAM_SELECT                                                                   0x11ca
8379 #define mmSCLV0_SCLV_COEF_RAM_SELECT_BASE_IDX                                                          2
8380 #define mmSCLV0_SCLV_COEF_RAM_TAP_DATA                                                                 0x11cb
8381 #define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_BASE_IDX                                                        2
8382 #define mmSCLV0_SCLV_MODE                                                                              0x11cc
8383 #define mmSCLV0_SCLV_MODE_BASE_IDX                                                                     2
8384 #define mmSCLV0_SCLV_TAP_CONTROL                                                                       0x11cd
8385 #define mmSCLV0_SCLV_TAP_CONTROL_BASE_IDX                                                              2
8386 #define mmSCLV0_SCLV_CONTROL                                                                           0x11ce
8387 #define mmSCLV0_SCLV_CONTROL_BASE_IDX                                                                  2
8388 #define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL                                                          0x11cf
8389 #define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                 2
8390 #define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL                                                            0x11d0
8391 #define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX                                                   2
8392 #define mmSCLV0_SCLV_HORZ_FILTER_CONTROL                                                               0x11d1
8393 #define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_BASE_IDX                                                      2
8394 #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO                                                           0x11d2
8395 #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                  2
8396 #define mmSCLV0_SCLV_HORZ_FILTER_INIT                                                                  0x11d3
8397 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BASE_IDX                                                         2
8398 #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C                                                         0x11d4
8399 #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                2
8400 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_C                                                                0x11d5
8401 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_BASE_IDX                                                       2
8402 #define mmSCLV0_SCLV_VERT_FILTER_CONTROL                                                               0x11d6
8403 #define mmSCLV0_SCLV_VERT_FILTER_CONTROL_BASE_IDX                                                      2
8404 #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO                                                           0x11d7
8405 #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                  2
8406 #define mmSCLV0_SCLV_VERT_FILTER_INIT                                                                  0x11d8
8407 #define mmSCLV0_SCLV_VERT_FILTER_INIT_BASE_IDX                                                         2
8408 #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT                                                              0x11d9
8409 #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX                                                     2
8410 #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C                                                         0x11da
8411 #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                2
8412 #define mmSCLV0_SCLV_VERT_FILTER_INIT_C                                                                0x11db
8413 #define mmSCLV0_SCLV_VERT_FILTER_INIT_C_BASE_IDX                                                       2
8414 #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C                                                            0x11dc
8415 #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                   2
8416 #define mmSCLV0_SCLV_ROUND_OFFSET                                                                      0x11dd
8417 #define mmSCLV0_SCLV_ROUND_OFFSET_BASE_IDX                                                             2
8418 #define mmSCLV0_SCLV_UPDATE                                                                            0x11de
8419 #define mmSCLV0_SCLV_UPDATE_BASE_IDX                                                                   2
8420 #define mmSCLV0_SCLV_ALU_CONTROL                                                                       0x11df
8421 #define mmSCLV0_SCLV_ALU_CONTROL_BASE_IDX                                                              2
8422 #define mmSCLV0_SCLV_VIEWPORT_START                                                                    0x11e0
8423 #define mmSCLV0_SCLV_VIEWPORT_START_BASE_IDX                                                           2
8424 #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY                                                          0x11e1
8425 #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX                                                 2
8426 #define mmSCLV0_SCLV_VIEWPORT_SIZE                                                                     0x11e2
8427 #define mmSCLV0_SCLV_VIEWPORT_SIZE_BASE_IDX                                                            2
8428 #define mmSCLV0_SCLV_VIEWPORT_START_C                                                                  0x11e3
8429 #define mmSCLV0_SCLV_VIEWPORT_START_C_BASE_IDX                                                         2
8430 #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C                                                        0x11e4
8431 #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX                                               2
8432 #define mmSCLV0_SCLV_VIEWPORT_SIZE_C                                                                   0x11e5
8433 #define mmSCLV0_SCLV_VIEWPORT_SIZE_C_BASE_IDX                                                          2
8434 #define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT                                                           0x11e6
8435 #define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
8436 #define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM                                                           0x11e7
8437 #define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
8438 #define mmSCLV0_SCLV_MODE_CHANGE_DET1                                                                  0x11e8
8439 #define mmSCLV0_SCLV_MODE_CHANGE_DET1_BASE_IDX                                                         2
8440 #define mmSCLV0_SCLV_MODE_CHANGE_DET2                                                                  0x11e9
8441 #define mmSCLV0_SCLV_MODE_CHANGE_DET2_BASE_IDX                                                         2
8442 #define mmSCLV0_SCLV_MODE_CHANGE_DET3                                                                  0x11ea
8443 #define mmSCLV0_SCLV_MODE_CHANGE_DET3_BASE_IDX                                                         2
8444 #define mmSCLV0_SCLV_MODE_CHANGE_MASK                                                                  0x11eb
8445 #define mmSCLV0_SCLV_MODE_CHANGE_MASK_BASE_IDX                                                         2
8446 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT                                                              0x11ec
8447 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX                                                     2
8448 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C                                                            0x11ed
8449 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX                                                   2
8450 
8451 
8452 // addressBlock: dce_dc_col_man0_dispdec
8453 // base address: 0x0
8454 #define mmCOL_MAN0_COL_MAN_UPDATE                                                                      0x11fe
8455 #define mmCOL_MAN0_COL_MAN_UPDATE_BASE_IDX                                                             2
8456 #define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL                                                           0x11ff
8457 #define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX                                                  2
8458 #define mmCOL_MAN0_INPUT_CSC_C11_C12_A                                                                 0x1200
8459 #define mmCOL_MAN0_INPUT_CSC_C11_C12_A_BASE_IDX                                                        2
8460 #define mmCOL_MAN0_INPUT_CSC_C13_C14_A                                                                 0x1201
8461 #define mmCOL_MAN0_INPUT_CSC_C13_C14_A_BASE_IDX                                                        2
8462 #define mmCOL_MAN0_INPUT_CSC_C21_C22_A                                                                 0x1202
8463 #define mmCOL_MAN0_INPUT_CSC_C21_C22_A_BASE_IDX                                                        2
8464 #define mmCOL_MAN0_INPUT_CSC_C23_C24_A                                                                 0x1203
8465 #define mmCOL_MAN0_INPUT_CSC_C23_C24_A_BASE_IDX                                                        2
8466 #define mmCOL_MAN0_INPUT_CSC_C31_C32_A                                                                 0x1204
8467 #define mmCOL_MAN0_INPUT_CSC_C31_C32_A_BASE_IDX                                                        2
8468 #define mmCOL_MAN0_INPUT_CSC_C33_C34_A                                                                 0x1205
8469 #define mmCOL_MAN0_INPUT_CSC_C33_C34_A_BASE_IDX                                                        2
8470 #define mmCOL_MAN0_INPUT_CSC_C11_C12_B                                                                 0x1206
8471 #define mmCOL_MAN0_INPUT_CSC_C11_C12_B_BASE_IDX                                                        2
8472 #define mmCOL_MAN0_INPUT_CSC_C13_C14_B                                                                 0x1207
8473 #define mmCOL_MAN0_INPUT_CSC_C13_C14_B_BASE_IDX                                                        2
8474 #define mmCOL_MAN0_INPUT_CSC_C21_C22_B                                                                 0x1208
8475 #define mmCOL_MAN0_INPUT_CSC_C21_C22_B_BASE_IDX                                                        2
8476 #define mmCOL_MAN0_INPUT_CSC_C23_C24_B                                                                 0x1209
8477 #define mmCOL_MAN0_INPUT_CSC_C23_C24_B_BASE_IDX                                                        2
8478 #define mmCOL_MAN0_INPUT_CSC_C31_C32_B                                                                 0x120a
8479 #define mmCOL_MAN0_INPUT_CSC_C31_C32_B_BASE_IDX                                                        2
8480 #define mmCOL_MAN0_INPUT_CSC_C33_C34_B                                                                 0x120b
8481 #define mmCOL_MAN0_INPUT_CSC_C33_C34_B_BASE_IDX                                                        2
8482 #define mmCOL_MAN0_PRESCALE_CONTROL                                                                    0x120c
8483 #define mmCOL_MAN0_PRESCALE_CONTROL_BASE_IDX                                                           2
8484 #define mmCOL_MAN0_PRESCALE_VALUES_R                                                                   0x120d
8485 #define mmCOL_MAN0_PRESCALE_VALUES_R_BASE_IDX                                                          2
8486 #define mmCOL_MAN0_PRESCALE_VALUES_G                                                                   0x120e
8487 #define mmCOL_MAN0_PRESCALE_VALUES_G_BASE_IDX                                                          2
8488 #define mmCOL_MAN0_PRESCALE_VALUES_B                                                                   0x120f
8489 #define mmCOL_MAN0_PRESCALE_VALUES_B_BASE_IDX                                                          2
8490 #define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL                                                          0x1210
8491 #define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX                                                 2
8492 #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A                                                                0x1211
8493 #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_BASE_IDX                                                       2
8494 #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A                                                                0x1212
8495 #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_BASE_IDX                                                       2
8496 #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A                                                                0x1213
8497 #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_BASE_IDX                                                       2
8498 #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A                                                                0x1214
8499 #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_BASE_IDX                                                       2
8500 #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A                                                                0x1215
8501 #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_BASE_IDX                                                       2
8502 #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A                                                                0x1216
8503 #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_BASE_IDX                                                       2
8504 #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B                                                                0x1217
8505 #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_BASE_IDX                                                       2
8506 #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B                                                                0x1218
8507 #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_BASE_IDX                                                       2
8508 #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B                                                                0x1219
8509 #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_BASE_IDX                                                       2
8510 #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B                                                                0x121a
8511 #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_BASE_IDX                                                       2
8512 #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B                                                                0x121b
8513 #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_BASE_IDX                                                       2
8514 #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B                                                                0x121c
8515 #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_BASE_IDX                                                       2
8516 #define mmCOL_MAN0_DENORM_CLAMP_CONTROL                                                                0x121d
8517 #define mmCOL_MAN0_DENORM_CLAMP_CONTROL_BASE_IDX                                                       2
8518 #define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR                                                             0x121e
8519 #define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_BASE_IDX                                                    2
8520 #define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y                                                              0x121f
8521 #define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_BASE_IDX                                                     2
8522 #define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB                                                             0x1220
8523 #define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_BASE_IDX                                                    2
8524 #define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD                                                          0x1221
8525 #define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX                                                 2
8526 #define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL                                                             0x1222
8527 #define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_BASE_IDX                                                    2
8528 #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX                                                           0x1223
8529 #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX                                                  2
8530 #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA                                                            0x1224
8531 #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX                                                   2
8532 #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK                                                   0x1225
8533 #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX                                          2
8534 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL                                                    0x1226
8535 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX                                           2
8536 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL                                                    0x1227
8537 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX                                           2
8538 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1                                                     0x1228
8539 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX                                            2
8540 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2                                                     0x1229
8541 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX                                            2
8542 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1                                                    0x122a
8543 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX                                           2
8544 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3                                                    0x122b
8545 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX                                           2
8546 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5                                                    0x122c
8547 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX                                           2
8548 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7                                                    0x122d
8549 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX                                           2
8550 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9                                                    0x122e
8551 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX                                           2
8552 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11                                                  0x122f
8553 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX                                         2
8554 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13                                                  0x1230
8555 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX                                         2
8556 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15                                                  0x1231
8557 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX                                         2
8558 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL                                                    0x1232
8559 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX                                           2
8560 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL                                                    0x1233
8561 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX                                           2
8562 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1                                                     0x1234
8563 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX                                            2
8564 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2                                                     0x1235
8565 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX                                            2
8566 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1                                                    0x1236
8567 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX                                           2
8568 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3                                                    0x1237
8569 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX                                           2
8570 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5                                                    0x1238
8571 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX                                           2
8572 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7                                                    0x1239
8573 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX                                           2
8574 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9                                                    0x123a
8575 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX                                           2
8576 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11                                                  0x123b
8577 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX                                         2
8578 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13                                                  0x123c
8579 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX                                         2
8580 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15                                                  0x123d
8581 #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX                                         2
8582 #define mmCOL_MAN0_PACK_FIFO_ERROR                                                                     0x123e
8583 #define mmCOL_MAN0_PACK_FIFO_ERROR_BASE_IDX                                                            2
8584 #define mmCOL_MAN0_OUTPUT_FIFO_ERROR                                                                   0x123f
8585 #define mmCOL_MAN0_OUTPUT_FIFO_ERROR_BASE_IDX                                                          2
8586 #define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL                                                            0x1240
8587 #define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX                                                   2
8588 #define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX                                                            0x1241
8589 #define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX                                                   2
8590 #define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR                                                           0x1242
8591 #define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX                                                  2
8592 #define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA                                                            0x1243
8593 #define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX                                                   2
8594 #define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR                                                            0x1244
8595 #define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX                                                   2
8596 #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1                                                        0x1245
8597 #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX                                               2
8598 #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2                                                        0x1246
8599 #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX                                               2
8600 #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B                                                            0x1247
8601 #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX                                                   2
8602 #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G                                                            0x1248
8603 #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX                                                   2
8604 #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R                                                            0x1249
8605 #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX                                                   2
8606 #define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL                                                             0x124a
8607 #define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_BASE_IDX                                                    2
8608 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL                                                         0x124b
8609 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX                                                2
8610 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12                                                         0x124c
8611 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX                                                2
8612 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14                                                         0x124d
8613 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX                                                2
8614 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22                                                         0x124e
8615 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX                                                2
8616 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24                                                         0x124f
8617 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX                                                2
8618 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32                                                         0x1250
8619 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX                                                2
8620 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34                                                         0x1251
8621 #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX                                                2
8622 
8623 
8624 // addressBlock: dce_dc_dcfev0_dispdec
8625 // base address: 0x0
8626 #define mmDCFEV0_DCFEV_CLOCK_CONTROL                                                                   0x127e
8627 #define mmDCFEV0_DCFEV_CLOCK_CONTROL_BASE_IDX                                                          2
8628 #define mmDCFEV0_DCFEV_SOFT_RESET                                                                      0x127f
8629 #define mmDCFEV0_DCFEV_SOFT_RESET_BASE_IDX                                                             2
8630 #define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL                                                             0x1280
8631 #define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX                                                    2
8632 #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL                                                              0x1282
8633 #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX                                                     2
8634 #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS                                                            0x1283
8635 #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX                                                   2
8636 #define mmDCFEV0_DCFEV_MEM_PWR_CTRL                                                                    0x1284
8637 #define mmDCFEV0_DCFEV_MEM_PWR_CTRL_BASE_IDX                                                           2
8638 #define mmDCFEV0_DCFEV_MEM_PWR_CTRL2                                                                   0x1285
8639 #define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_BASE_IDX                                                          2
8640 #define mmDCFEV0_DCFEV_MEM_PWR_STATUS                                                                  0x1286
8641 #define mmDCFEV0_DCFEV_MEM_PWR_STATUS_BASE_IDX                                                         2
8642 #define mmDCFEV0_DCFEV_L_FLUSH                                                                         0x1287
8643 #define mmDCFEV0_DCFEV_L_FLUSH_BASE_IDX                                                                2
8644 #define mmDCFEV0_DCFEV_C_FLUSH                                                                         0x1288
8645 #define mmDCFEV0_DCFEV_C_FLUSH_BASE_IDX                                                                2
8646 #define mmDCFEV0_DCFEV_MISC                                                                            0x128a
8647 #define mmDCFEV0_DCFEV_MISC_BASE_IDX                                                                   2
8648 
8649 
8650 // addressBlock: dce_dc_dc_perfmon11_dispdec
8651 // base address: 0x49c8
8652 #define mmDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x1292
8653 #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
8654 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x1293
8655 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
8656 #define mmDC_PERFMON11_PERFCOUNTER_STATE                                                               0x1294
8657 #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
8658 #define mmDC_PERFMON11_PERFMON_CNTL                                                                    0x1295
8659 #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
8660 #define mmDC_PERFMON11_PERFMON_CNTL2                                                                   0x1296
8661 #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
8662 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x1297
8663 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
8664 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x1298
8665 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
8666 #define mmDC_PERFMON11_PERFMON_HI                                                                      0x1299
8667 #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
8668 #define mmDC_PERFMON11_PERFMON_LOW                                                                     0x129a
8669 #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
8670 
8671 
8672 // addressBlock: dce_dc_dmifv_pg0_dispdec
8673 // base address: 0x0
8674 #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1                                                    0x129e
8675 #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                           2
8676 #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2                                                    0x129f
8677 #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                           2
8678 #define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL                                                       0x12a0
8679 #define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX                                              2
8680 #define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL                                                         0x12a1
8681 #define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX                                                2
8682 #define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL                                                             0x12a2
8683 #define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_BASE_IDX                                                    2
8684 #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL                                                         0x12a3
8685 #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX                                                2
8686 #define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL                                                0x12a4
8687 #define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX                                       2
8688 #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH                                                0x12a5
8689 #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX                                       2
8690 #define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM                                                             0x12a6
8691 #define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_BASE_IDX                                                    2
8692 #define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL                                                            0x12aa
8693 #define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX                                                   2
8694 #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1                                                    0x12ab
8695 #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                           2
8696 #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2                                                    0x12ac
8697 #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                           2
8698 #define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL                                                       0x12ad
8699 #define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX                                              2
8700 #define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL                                                         0x12ae
8701 #define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX                                                2
8702 #define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL                                                             0x12af
8703 #define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_BASE_IDX                                                    2
8704 #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL                                                         0x12b0
8705 #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX                                                2
8706 #define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL                                                0x12b1
8707 #define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX                                       2
8708 #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH                                                0x12b2
8709 #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX                                       2
8710 #define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM                                                             0x12b3
8711 #define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_BASE_IDX                                                    2
8712 #define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL                                                            0x12b7
8713 #define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX                                                   2
8714 
8715 
8716 // addressBlock: dce_dc_blndv0_dispdec
8717 // base address: 0x0
8718 #define mmBLNDV0_BLNDV_CONTROL                                                                         0x12db
8719 #define mmBLNDV0_BLNDV_CONTROL_BASE_IDX                                                                2
8720 #define mmBLNDV0_BLNDV_SM_CONTROL2                                                                     0x12dc
8721 #define mmBLNDV0_BLNDV_SM_CONTROL2_BASE_IDX                                                            2
8722 #define mmBLNDV0_BLNDV_CONTROL2                                                                        0x12dd
8723 #define mmBLNDV0_BLNDV_CONTROL2_BASE_IDX                                                               2
8724 #define mmBLNDV0_BLNDV_UPDATE                                                                          0x12de
8725 #define mmBLNDV0_BLNDV_UPDATE_BASE_IDX                                                                 2
8726 #define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT                                                             0x12df
8727 #define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX                                                    2
8728 #define mmBLNDV0_BLNDV_V_UPDATE_LOCK                                                                   0x12e0
8729 #define mmBLNDV0_BLNDV_V_UPDATE_LOCK_BASE_IDX                                                          2
8730 #define mmBLNDV0_BLNDV_REG_UPDATE_STATUS                                                               0x12e1
8731 #define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_BASE_IDX                                                      2
8732 
8733 
8734 // addressBlock: dce_dc_crtcv0_dispdec
8735 // base address: 0x0
8736 #define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM                                                               0x12e6
8737 #define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX                                                      2
8738 #define mmCRTCV0_CRTCV_H_TOTAL                                                                         0x12e7
8739 #define mmCRTCV0_CRTCV_H_TOTAL_BASE_IDX                                                                2
8740 #define mmCRTCV0_CRTCV_H_BLANK_START_END                                                               0x12e8
8741 #define mmCRTCV0_CRTCV_H_BLANK_START_END_BASE_IDX                                                      2
8742 #define mmCRTCV0_CRTCV_H_SYNC_A                                                                        0x12e9
8743 #define mmCRTCV0_CRTCV_H_SYNC_A_BASE_IDX                                                               2
8744 #define mmCRTCV0_CRTCV_H_SYNC_A_CNTL                                                                   0x12ea
8745 #define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_BASE_IDX                                                          2
8746 #define mmCRTCV0_CRTCV_H_SYNC_B                                                                        0x12eb
8747 #define mmCRTCV0_CRTCV_H_SYNC_B_BASE_IDX                                                               2
8748 #define mmCRTCV0_CRTCV_H_SYNC_B_CNTL                                                                   0x12ec
8749 #define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_BASE_IDX                                                          2
8750 #define mmCRTCV0_CRTCV_VBI_END                                                                         0x12ed
8751 #define mmCRTCV0_CRTCV_VBI_END_BASE_IDX                                                                2
8752 #define mmCRTCV0_CRTCV_V_TOTAL                                                                         0x12ee
8753 #define mmCRTCV0_CRTCV_V_TOTAL_BASE_IDX                                                                2
8754 #define mmCRTCV0_CRTCV_V_TOTAL_MIN                                                                     0x12ef
8755 #define mmCRTCV0_CRTCV_V_TOTAL_MIN_BASE_IDX                                                            2
8756 #define mmCRTCV0_CRTCV_V_TOTAL_MAX                                                                     0x12f0
8757 #define mmCRTCV0_CRTCV_V_TOTAL_MAX_BASE_IDX                                                            2
8758 #define mmCRTCV0_CRTCV_V_TOTAL_CONTROL                                                                 0x12f1
8759 #define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_BASE_IDX                                                        2
8760 #define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS                                                              0x12f2
8761 #define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX                                                     2
8762 #define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS                                                            0x12f3
8763 #define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX                                                   2
8764 #define mmCRTCV0_CRTCV_V_BLANK_START_END                                                               0x12f4
8765 #define mmCRTCV0_CRTCV_V_BLANK_START_END_BASE_IDX                                                      2
8766 #define mmCRTCV0_CRTCV_V_SYNC_A                                                                        0x12f5
8767 #define mmCRTCV0_CRTCV_V_SYNC_A_BASE_IDX                                                               2
8768 #define mmCRTCV0_CRTCV_V_SYNC_A_CNTL                                                                   0x12f6
8769 #define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_BASE_IDX                                                          2
8770 #define mmCRTCV0_CRTCV_V_SYNC_B                                                                        0x12f7
8771 #define mmCRTCV0_CRTCV_V_SYNC_B_BASE_IDX                                                               2
8772 #define mmCRTCV0_CRTCV_V_SYNC_B_CNTL                                                                   0x12f8
8773 #define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_BASE_IDX                                                          2
8774 #define mmCRTCV0_CRTCV_DTMTEST_CNTL                                                                    0x12f9
8775 #define mmCRTCV0_CRTCV_DTMTEST_CNTL_BASE_IDX                                                           2
8776 #define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION                                                         0x12fa
8777 #define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX                                                2
8778 #define mmCRTCV0_CRTCV_TRIGA_CNTL                                                                      0x12fb
8779 #define mmCRTCV0_CRTCV_TRIGA_CNTL_BASE_IDX                                                             2
8780 #define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG                                                               0x12fc
8781 #define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX                                                      2
8782 #define mmCRTCV0_CRTCV_TRIGB_CNTL                                                                      0x12fd
8783 #define mmCRTCV0_CRTCV_TRIGB_CNTL_BASE_IDX                                                             2
8784 #define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG                                                               0x12fe
8785 #define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX                                                      2
8786 #define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL                                                            0x12ff
8787 #define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                   2
8788 #define mmCRTCV0_CRTCV_FLOW_CONTROL                                                                    0x1300
8789 #define mmCRTCV0_CRTCV_FLOW_CONTROL_BASE_IDX                                                           2
8790 #define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE                                                           0x1301
8791 #define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                  2
8792 #define mmCRTCV0_CRTCV_AVSYNC_COUNTER                                                                  0x1302
8793 #define mmCRTCV0_CRTCV_AVSYNC_COUNTER_BASE_IDX                                                         2
8794 #define mmCRTCV0_CRTCV_CONTROL                                                                         0x1303
8795 #define mmCRTCV0_CRTCV_CONTROL_BASE_IDX                                                                2
8796 #define mmCRTCV0_CRTCV_BLANK_CONTROL                                                                   0x1304
8797 #define mmCRTCV0_CRTCV_BLANK_CONTROL_BASE_IDX                                                          2
8798 #define mmCRTCV0_CRTCV_INTERLACE_CONTROL                                                               0x1305
8799 #define mmCRTCV0_CRTCV_INTERLACE_CONTROL_BASE_IDX                                                      2
8800 #define mmCRTCV0_CRTCV_INTERLACE_STATUS                                                                0x1306
8801 #define mmCRTCV0_CRTCV_INTERLACE_STATUS_BASE_IDX                                                       2
8802 #define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL                                                        0x1307
8803 #define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX                                               2
8804 #define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0                                                            0x1308
8805 #define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX                                                   2
8806 #define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1                                                            0x1309
8807 #define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX                                                   2
8808 #define mmCRTCV0_CRTCV_STATUS                                                                          0x130a
8809 #define mmCRTCV0_CRTCV_STATUS_BASE_IDX                                                                 2
8810 #define mmCRTCV0_CRTCV_STATUS_POSITION                                                                 0x130b
8811 #define mmCRTCV0_CRTCV_STATUS_POSITION_BASE_IDX                                                        2
8812 #define mmCRTCV0_CRTCV_NOM_VERT_POSITION                                                               0x130c
8813 #define mmCRTCV0_CRTCV_NOM_VERT_POSITION_BASE_IDX                                                      2
8814 #define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT                                                              0x130d
8815 #define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_BASE_IDX                                                     2
8816 #define mmCRTCV0_CRTCV_STATUS_VF_COUNT                                                                 0x130e
8817 #define mmCRTCV0_CRTCV_STATUS_VF_COUNT_BASE_IDX                                                        2
8818 #define mmCRTCV0_CRTCV_STATUS_HV_COUNT                                                                 0x130f
8819 #define mmCRTCV0_CRTCV_STATUS_HV_COUNT_BASE_IDX                                                        2
8820 #define mmCRTCV0_CRTCV_COUNT_CONTROL                                                                   0x1310
8821 #define mmCRTCV0_CRTCV_COUNT_CONTROL_BASE_IDX                                                          2
8822 #define mmCRTCV0_CRTCV_COUNT_RESET                                                                     0x1311
8823 #define mmCRTCV0_CRTCV_COUNT_RESET_BASE_IDX                                                            2
8824 #define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE                                                    0x1312
8825 #define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                           2
8826 #define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL                                                               0x1313
8827 #define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_BASE_IDX                                                      2
8828 #define mmCRTCV0_CRTCV_STEREO_STATUS                                                                   0x1314
8829 #define mmCRTCV0_CRTCV_STEREO_STATUS_BASE_IDX                                                          2
8830 #define mmCRTCV0_CRTCV_STEREO_CONTROL                                                                  0x1315
8831 #define mmCRTCV0_CRTCV_STEREO_CONTROL_BASE_IDX                                                         2
8832 #define mmCRTCV0_CRTCV_SNAPSHOT_STATUS                                                                 0x1316
8833 #define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_BASE_IDX                                                        2
8834 #define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL                                                                0x1317
8835 #define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_BASE_IDX                                                       2
8836 #define mmCRTCV0_CRTCV_SNAPSHOT_POSITION                                                               0x1318
8837 #define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_BASE_IDX                                                      2
8838 #define mmCRTCV0_CRTCV_SNAPSHOT_FRAME                                                                  0x1319
8839 #define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_BASE_IDX                                                         2
8840 #define mmCRTCV0_CRTCV_START_LINE_CONTROL                                                              0x131a
8841 #define mmCRTCV0_CRTCV_START_LINE_CONTROL_BASE_IDX                                                     2
8842 #define mmCRTCV0_CRTCV_INTERRUPT_CONTROL                                                               0x131b
8843 #define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_BASE_IDX                                                      2
8844 #define mmCRTCV0_CRTCV_UPDATE_LOCK                                                                     0x131c
8845 #define mmCRTCV0_CRTCV_UPDATE_LOCK_BASE_IDX                                                            2
8846 #define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL                                                           0x131d
8847 #define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                  2
8848 #define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE                                                      0x131e
8849 #define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX                                             2
8850 #define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL                                                            0x131f
8851 #define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX                                                   2
8852 #define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS                                                         0x1320
8853 #define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX                                                2
8854 #define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR                                                              0x1321
8855 #define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_BASE_IDX                                                     2
8856 #define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK                                                              0x1322
8857 #define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX                                                     2
8858 #define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE                                                              0x1323
8859 #define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_BASE_IDX                                                     2
8860 #define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT                                                          0x1324
8861 #define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX                                                 2
8862 #define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER                                                    0x1325
8863 #define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX                                           2
8864 #define mmCRTCV0_CRTCV_MVP_STATUS                                                                      0x1326
8865 #define mmCRTCV0_CRTCV_MVP_STATUS_BASE_IDX                                                             2
8866 #define mmCRTCV0_CRTCV_MASTER_EN                                                                       0x1327
8867 #define mmCRTCV0_CRTCV_MASTER_EN_BASE_IDX                                                              2
8868 #define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT                                                            0x1328
8869 #define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX                                                   2
8870 #define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS                                                             0x1329
8871 #define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX                                                    2
8872 #define mmCRTCV0_CRTCV_OVERSCAN_COLOR                                                                  0x132b
8873 #define mmCRTCV0_CRTCV_OVERSCAN_COLOR_BASE_IDX                                                         2
8874 #define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT                                                              0x132c
8875 #define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX                                                     2
8876 #define mmCRTCV0_CRTCV_BLANK_DATA_COLOR                                                                0x132d
8877 #define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_BASE_IDX                                                       2
8878 #define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT                                                            0x132e
8879 #define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX                                                   2
8880 #define mmCRTCV0_CRTCV_BLACK_COLOR                                                                     0x132f
8881 #define mmCRTCV0_CRTCV_BLACK_COLOR_BASE_IDX                                                            2
8882 #define mmCRTCV0_CRTCV_BLACK_COLOR_EXT                                                                 0x1330
8883 #define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_BASE_IDX                                                        2
8884 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION                                                    0x1331
8885 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                           2
8886 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL                                                     0x1332
8887 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                            2
8888 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION                                                    0x1333
8889 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                           2
8890 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL                                                     0x1334
8891 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                            2
8892 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION                                                    0x1335
8893 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                           2
8894 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL                                                     0x1336
8895 #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                            2
8896 #define mmCRTCV0_CRTCV_CRC_CNTL                                                                        0x1337
8897 #define mmCRTCV0_CRTCV_CRC_CNTL_BASE_IDX                                                               2
8898 #define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL                                                          0x1338
8899 #define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                 2
8900 #define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL                                                          0x1339
8901 #define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                 2
8902 #define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL                                                          0x133a
8903 #define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                 2
8904 #define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL                                                          0x133b
8905 #define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                 2
8906 #define mmCRTCV0_CRTCV_CRC0_DATA_RG                                                                    0x133c
8907 #define mmCRTCV0_CRTCV_CRC0_DATA_RG_BASE_IDX                                                           2
8908 #define mmCRTCV0_CRTCV_CRC0_DATA_B                                                                     0x133d
8909 #define mmCRTCV0_CRTCV_CRC0_DATA_B_BASE_IDX                                                            2
8910 #define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL                                                          0x133e
8911 #define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                 2
8912 #define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL                                                          0x133f
8913 #define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                 2
8914 #define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL                                                          0x1340
8915 #define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                 2
8916 #define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL                                                          0x1341
8917 #define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                 2
8918 #define mmCRTCV0_CRTCV_CRC1_DATA_RG                                                                    0x1342
8919 #define mmCRTCV0_CRTCV_CRC1_DATA_RG_BASE_IDX                                                           2
8920 #define mmCRTCV0_CRTCV_CRC1_DATA_B                                                                     0x1343
8921 #define mmCRTCV0_CRTCV_CRC1_DATA_B_BASE_IDX                                                            2
8922 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL                                                         0x1344
8923 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX                                                2
8924 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START                                                    0x1345
8925 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX                                           2
8926 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END                                                      0x1346
8927 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX                                             2
8928 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                                          0x1347
8929 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX                                 2
8930 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                               0x1348
8931 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX                                      2
8932 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                                        0x1349
8933 #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX                               2
8934 #define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL                                                           0x134a
8935 #define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX                                                  2
8936 #define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL                                                            0x134b
8937 #define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX                                                   2
8938 #define mmCRTCV0_CRTCV_GSL_VSYNC_GAP                                                                   0x134c
8939 #define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_BASE_IDX                                                          2
8940 #define mmCRTCV0_CRTCV_GSL_WINDOW                                                                      0x134d
8941 #define mmCRTCV0_CRTCV_GSL_WINDOW_BASE_IDX                                                             2
8942 #define mmCRTCV0_CRTCV_GSL_CONTROL                                                                     0x134e
8943 #define mmCRTCV0_CRTCV_GSL_CONTROL_BASE_IDX                                                            2
8944 
8945 
8946 // addressBlock: dce_dc_unp1_dispdec
8947 // base address: 0x800
8948 #define mmUNP1_UNP_GRPH_ENABLE                                                                         0x135a
8949 #define mmUNP1_UNP_GRPH_ENABLE_BASE_IDX                                                                2
8950 #define mmUNP1_UNP_GRPH_CONTROL                                                                        0x135b
8951 #define mmUNP1_UNP_GRPH_CONTROL_BASE_IDX                                                               2
8952 #define mmUNP1_UNP_GRPH_CONTROL_C                                                                      0x135c
8953 #define mmUNP1_UNP_GRPH_CONTROL_C_BASE_IDX                                                             2
8954 #define mmUNP1_UNP_GRPH_CONTROL_EXP                                                                    0x135d
8955 #define mmUNP1_UNP_GRPH_CONTROL_EXP_BASE_IDX                                                           2
8956 #define mmUNP1_UNP_GRPH_SWAP_CNTL                                                                      0x135e
8957 #define mmUNP1_UNP_GRPH_SWAP_CNTL_BASE_IDX                                                             2
8958 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L                                                      0x135f
8959 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX                                             2
8960 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C                                                      0x1360
8961 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                             2
8962 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L                                                 0x1361
8963 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX                                        2
8964 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C                                                 0x1362
8965 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                        2
8966 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L                                               0x1363
8967 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX                                      2
8968 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C                                               0x1364
8969 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX                                      2
8970 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                                          0x1365
8971 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX                                 2
8972 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                                          0x1366
8973 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
8974 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L                                                    0x1367
8975 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX                                           2
8976 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C                                                    0x1368
8977 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
8978 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L                                               0x1369
8979 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX                                      2
8980 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C                                               0x136a
8981 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
8982 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L                                             0x136b
8983 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX                                    2
8984 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C                                             0x136c
8985 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX                                    2
8986 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L                                        0x136d
8987 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX                               2
8988 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C                                        0x136e
8989 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
8990 #define mmUNP1_UNP_GRPH_PITCH_L                                                                        0x136f
8991 #define mmUNP1_UNP_GRPH_PITCH_L_BASE_IDX                                                               2
8992 #define mmUNP1_UNP_GRPH_PITCH_C                                                                        0x1370
8993 #define mmUNP1_UNP_GRPH_PITCH_C_BASE_IDX                                                               2
8994 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L                                                             0x1371
8995 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX                                                    2
8996 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C                                                             0x1372
8997 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX                                                    2
8998 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L                                                             0x1373
8999 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX                                                    2
9000 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C                                                             0x1374
9001 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX                                                    2
9002 #define mmUNP1_UNP_GRPH_X_START_L                                                                      0x1375
9003 #define mmUNP1_UNP_GRPH_X_START_L_BASE_IDX                                                             2
9004 #define mmUNP1_UNP_GRPH_X_START_C                                                                      0x1376
9005 #define mmUNP1_UNP_GRPH_X_START_C_BASE_IDX                                                             2
9006 #define mmUNP1_UNP_GRPH_Y_START_L                                                                      0x1377
9007 #define mmUNP1_UNP_GRPH_Y_START_L_BASE_IDX                                                             2
9008 #define mmUNP1_UNP_GRPH_Y_START_C                                                                      0x1378
9009 #define mmUNP1_UNP_GRPH_Y_START_C_BASE_IDX                                                             2
9010 #define mmUNP1_UNP_GRPH_X_END_L                                                                        0x1379
9011 #define mmUNP1_UNP_GRPH_X_END_L_BASE_IDX                                                               2
9012 #define mmUNP1_UNP_GRPH_X_END_C                                                                        0x137a
9013 #define mmUNP1_UNP_GRPH_X_END_C_BASE_IDX                                                               2
9014 #define mmUNP1_UNP_GRPH_Y_END_L                                                                        0x137b
9015 #define mmUNP1_UNP_GRPH_Y_END_L_BASE_IDX                                                               2
9016 #define mmUNP1_UNP_GRPH_Y_END_C                                                                        0x137c
9017 #define mmUNP1_UNP_GRPH_Y_END_C_BASE_IDX                                                               2
9018 #define mmUNP1_UNP_GRPH_UPDATE                                                                         0x137d
9019 #define mmUNP1_UNP_GRPH_UPDATE_BASE_IDX                                                                2
9020 #define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT                                                      0x137e
9021 #define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX                                             2
9022 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L                                                        0x137f
9023 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX                                               2
9024 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C                                                        0x1380
9025 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX                                               2
9026 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L                                                   0x1381
9027 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX                                          2
9028 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C                                                   0x1382
9029 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX                                          2
9030 #define mmUNP1_UNP_DVMM_PTE_CONTROL                                                                    0x1383
9031 #define mmUNP1_UNP_DVMM_PTE_CONTROL_BASE_IDX                                                           2
9032 #define mmUNP1_UNP_DVMM_PTE_CONTROL_C                                                                  0x1384
9033 #define mmUNP1_UNP_DVMM_PTE_CONTROL_C_BASE_IDX                                                         2
9034 #define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL                                                                0x1385
9035 #define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX                                                       2
9036 #define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C                                                              0x1386
9037 #define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX                                                     2
9038 #define mmUNP1_UNP_GRPH_INTERRUPT_STATUS                                                               0x1387
9039 #define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX                                                      2
9040 #define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL                                                              0x1388
9041 #define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX                                                     2
9042 #define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP                                                                0x1389
9043 #define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX                                                       2
9044 #define mmUNP1_UNP_FLIP_CONTROL                                                                        0x138a
9045 #define mmUNP1_UNP_FLIP_CONTROL_BASE_IDX                                                               2
9046 #define mmUNP1_UNP_CRC_CONTROL                                                                         0x138b
9047 #define mmUNP1_UNP_CRC_CONTROL_BASE_IDX                                                                2
9048 #define mmUNP1_UNP_CRC_MASK                                                                            0x138c
9049 #define mmUNP1_UNP_CRC_MASK_BASE_IDX                                                                   2
9050 #define mmUNP1_UNP_CRC_CURRENT                                                                         0x138d
9051 #define mmUNP1_UNP_CRC_CURRENT_BASE_IDX                                                                2
9052 #define mmUNP1_UNP_CRC_LAST                                                                            0x138e
9053 #define mmUNP1_UNP_CRC_LAST_BASE_IDX                                                                   2
9054 #define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK                                                           0x138f
9055 #define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX                                                  2
9056 #define mmUNP1_UNP_HW_ROTATION                                                                         0x1390
9057 #define mmUNP1_UNP_HW_ROTATION_BASE_IDX                                                                2
9058 
9059 
9060 // addressBlock: dce_dc_lbv1_dispdec
9061 // base address: 0x800
9062 #define mmLBV1_LBV_DATA_FORMAT                                                                         0x1396
9063 #define mmLBV1_LBV_DATA_FORMAT_BASE_IDX                                                                2
9064 #define mmLBV1_LBV_MEMORY_CTRL                                                                         0x1397
9065 #define mmLBV1_LBV_MEMORY_CTRL_BASE_IDX                                                                2
9066 #define mmLBV1_LBV_MEMORY_SIZE_STATUS                                                                  0x1398
9067 #define mmLBV1_LBV_MEMORY_SIZE_STATUS_BASE_IDX                                                         2
9068 #define mmLBV1_LBV_DESKTOP_HEIGHT                                                                      0x1399
9069 #define mmLBV1_LBV_DESKTOP_HEIGHT_BASE_IDX                                                             2
9070 #define mmLBV1_LBV_VLINE_START_END                                                                     0x139a
9071 #define mmLBV1_LBV_VLINE_START_END_BASE_IDX                                                            2
9072 #define mmLBV1_LBV_VLINE2_START_END                                                                    0x139b
9073 #define mmLBV1_LBV_VLINE2_START_END_BASE_IDX                                                           2
9074 #define mmLBV1_LBV_V_COUNTER                                                                           0x139c
9075 #define mmLBV1_LBV_V_COUNTER_BASE_IDX                                                                  2
9076 #define mmLBV1_LBV_SNAPSHOT_V_COUNTER                                                                  0x139d
9077 #define mmLBV1_LBV_SNAPSHOT_V_COUNTER_BASE_IDX                                                         2
9078 #define mmLBV1_LBV_V_COUNTER_CHROMA                                                                    0x139e
9079 #define mmLBV1_LBV_V_COUNTER_CHROMA_BASE_IDX                                                           2
9080 #define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA                                                           0x139f
9081 #define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX                                                  2
9082 #define mmLBV1_LBV_INTERRUPT_MASK                                                                      0x13a0
9083 #define mmLBV1_LBV_INTERRUPT_MASK_BASE_IDX                                                             2
9084 #define mmLBV1_LBV_VLINE_STATUS                                                                        0x13a1
9085 #define mmLBV1_LBV_VLINE_STATUS_BASE_IDX                                                               2
9086 #define mmLBV1_LBV_VLINE2_STATUS                                                                       0x13a2
9087 #define mmLBV1_LBV_VLINE2_STATUS_BASE_IDX                                                              2
9088 #define mmLBV1_LBV_VBLANK_STATUS                                                                       0x13a3
9089 #define mmLBV1_LBV_VBLANK_STATUS_BASE_IDX                                                              2
9090 #define mmLBV1_LBV_SYNC_RESET_SEL                                                                      0x13a4
9091 #define mmLBV1_LBV_SYNC_RESET_SEL_BASE_IDX                                                             2
9092 #define mmLBV1_LBV_BLACK_KEYER_R_CR                                                                    0x13a5
9093 #define mmLBV1_LBV_BLACK_KEYER_R_CR_BASE_IDX                                                           2
9094 #define mmLBV1_LBV_BLACK_KEYER_G_Y                                                                     0x13a6
9095 #define mmLBV1_LBV_BLACK_KEYER_G_Y_BASE_IDX                                                            2
9096 #define mmLBV1_LBV_BLACK_KEYER_B_CB                                                                    0x13a7
9097 #define mmLBV1_LBV_BLACK_KEYER_B_CB_BASE_IDX                                                           2
9098 #define mmLBV1_LBV_KEYER_COLOR_CTRL                                                                    0x13a8
9099 #define mmLBV1_LBV_KEYER_COLOR_CTRL_BASE_IDX                                                           2
9100 #define mmLBV1_LBV_KEYER_COLOR_R_CR                                                                    0x13a9
9101 #define mmLBV1_LBV_KEYER_COLOR_R_CR_BASE_IDX                                                           2
9102 #define mmLBV1_LBV_KEYER_COLOR_G_Y                                                                     0x13aa
9103 #define mmLBV1_LBV_KEYER_COLOR_G_Y_BASE_IDX                                                            2
9104 #define mmLBV1_LBV_KEYER_COLOR_B_CB                                                                    0x13ab
9105 #define mmLBV1_LBV_KEYER_COLOR_B_CB_BASE_IDX                                                           2
9106 #define mmLBV1_LBV_KEYER_COLOR_REP_R_CR                                                                0x13ac
9107 #define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX                                                       2
9108 #define mmLBV1_LBV_KEYER_COLOR_REP_G_Y                                                                 0x13ad
9109 #define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX                                                        2
9110 #define mmLBV1_LBV_KEYER_COLOR_REP_B_CB                                                                0x13ae
9111 #define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX                                                       2
9112 #define mmLBV1_LBV_BUFFER_LEVEL_STATUS                                                                 0x13af
9113 #define mmLBV1_LBV_BUFFER_LEVEL_STATUS_BASE_IDX                                                        2
9114 #define mmLBV1_LBV_BUFFER_URGENCY_CTRL                                                                 0x13b0
9115 #define mmLBV1_LBV_BUFFER_URGENCY_CTRL_BASE_IDX                                                        2
9116 #define mmLBV1_LBV_BUFFER_URGENCY_STATUS                                                               0x13b1
9117 #define mmLBV1_LBV_BUFFER_URGENCY_STATUS_BASE_IDX                                                      2
9118 #define mmLBV1_LBV_BUFFER_STATUS                                                                       0x13b2
9119 #define mmLBV1_LBV_BUFFER_STATUS_BASE_IDX                                                              2
9120 #define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS                                                           0x13b3
9121 #define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX                                                  2
9122 
9123 
9124 // addressBlock: dce_dc_sclv1_dispdec
9125 // base address: 0x800
9126 #define mmSCLV1_SCLV_COEF_RAM_SELECT                                                                   0x13ca
9127 #define mmSCLV1_SCLV_COEF_RAM_SELECT_BASE_IDX                                                          2
9128 #define mmSCLV1_SCLV_COEF_RAM_TAP_DATA                                                                 0x13cb
9129 #define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_BASE_IDX                                                        2
9130 #define mmSCLV1_SCLV_MODE                                                                              0x13cc
9131 #define mmSCLV1_SCLV_MODE_BASE_IDX                                                                     2
9132 #define mmSCLV1_SCLV_TAP_CONTROL                                                                       0x13cd
9133 #define mmSCLV1_SCLV_TAP_CONTROL_BASE_IDX                                                              2
9134 #define mmSCLV1_SCLV_CONTROL                                                                           0x13ce
9135 #define mmSCLV1_SCLV_CONTROL_BASE_IDX                                                                  2
9136 #define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL                                                          0x13cf
9137 #define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                 2
9138 #define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL                                                            0x13d0
9139 #define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX                                                   2
9140 #define mmSCLV1_SCLV_HORZ_FILTER_CONTROL                                                               0x13d1
9141 #define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_BASE_IDX                                                      2
9142 #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO                                                           0x13d2
9143 #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                  2
9144 #define mmSCLV1_SCLV_HORZ_FILTER_INIT                                                                  0x13d3
9145 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BASE_IDX                                                         2
9146 #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C                                                         0x13d4
9147 #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                2
9148 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_C                                                                0x13d5
9149 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_BASE_IDX                                                       2
9150 #define mmSCLV1_SCLV_VERT_FILTER_CONTROL                                                               0x13d6
9151 #define mmSCLV1_SCLV_VERT_FILTER_CONTROL_BASE_IDX                                                      2
9152 #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO                                                           0x13d7
9153 #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                  2
9154 #define mmSCLV1_SCLV_VERT_FILTER_INIT                                                                  0x13d8
9155 #define mmSCLV1_SCLV_VERT_FILTER_INIT_BASE_IDX                                                         2
9156 #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT                                                              0x13d9
9157 #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX                                                     2
9158 #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C                                                         0x13da
9159 #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                2
9160 #define mmSCLV1_SCLV_VERT_FILTER_INIT_C                                                                0x13db
9161 #define mmSCLV1_SCLV_VERT_FILTER_INIT_C_BASE_IDX                                                       2
9162 #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C                                                            0x13dc
9163 #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                   2
9164 #define mmSCLV1_SCLV_ROUND_OFFSET                                                                      0x13dd
9165 #define mmSCLV1_SCLV_ROUND_OFFSET_BASE_IDX                                                             2
9166 #define mmSCLV1_SCLV_UPDATE                                                                            0x13de
9167 #define mmSCLV1_SCLV_UPDATE_BASE_IDX                                                                   2
9168 #define mmSCLV1_SCLV_ALU_CONTROL                                                                       0x13df
9169 #define mmSCLV1_SCLV_ALU_CONTROL_BASE_IDX                                                              2
9170 #define mmSCLV1_SCLV_VIEWPORT_START                                                                    0x13e0
9171 #define mmSCLV1_SCLV_VIEWPORT_START_BASE_IDX                                                           2
9172 #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY                                                          0x13e1
9173 #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX                                                 2
9174 #define mmSCLV1_SCLV_VIEWPORT_SIZE                                                                     0x13e2
9175 #define mmSCLV1_SCLV_VIEWPORT_SIZE_BASE_IDX                                                            2
9176 #define mmSCLV1_SCLV_VIEWPORT_START_C                                                                  0x13e3
9177 #define mmSCLV1_SCLV_VIEWPORT_START_C_BASE_IDX                                                         2
9178 #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C                                                        0x13e4
9179 #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX                                               2
9180 #define mmSCLV1_SCLV_VIEWPORT_SIZE_C                                                                   0x13e5
9181 #define mmSCLV1_SCLV_VIEWPORT_SIZE_C_BASE_IDX                                                          2
9182 #define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT                                                           0x13e6
9183 #define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
9184 #define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM                                                           0x13e7
9185 #define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
9186 #define mmSCLV1_SCLV_MODE_CHANGE_DET1                                                                  0x13e8
9187 #define mmSCLV1_SCLV_MODE_CHANGE_DET1_BASE_IDX                                                         2
9188 #define mmSCLV1_SCLV_MODE_CHANGE_DET2                                                                  0x13e9
9189 #define mmSCLV1_SCLV_MODE_CHANGE_DET2_BASE_IDX                                                         2
9190 #define mmSCLV1_SCLV_MODE_CHANGE_DET3                                                                  0x13ea
9191 #define mmSCLV1_SCLV_MODE_CHANGE_DET3_BASE_IDX                                                         2
9192 #define mmSCLV1_SCLV_MODE_CHANGE_MASK                                                                  0x13eb
9193 #define mmSCLV1_SCLV_MODE_CHANGE_MASK_BASE_IDX                                                         2
9194 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT                                                              0x13ec
9195 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX                                                     2
9196 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C                                                            0x13ed
9197 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX                                                   2
9198 
9199 
9200 // addressBlock: dce_dc_col_man1_dispdec
9201 // base address: 0x800
9202 #define mmCOL_MAN1_COL_MAN_UPDATE                                                                      0x13fe
9203 #define mmCOL_MAN1_COL_MAN_UPDATE_BASE_IDX                                                             2
9204 #define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL                                                           0x13ff
9205 #define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX                                                  2
9206 #define mmCOL_MAN1_INPUT_CSC_C11_C12_A                                                                 0x1400
9207 #define mmCOL_MAN1_INPUT_CSC_C11_C12_A_BASE_IDX                                                        2
9208 #define mmCOL_MAN1_INPUT_CSC_C13_C14_A                                                                 0x1401
9209 #define mmCOL_MAN1_INPUT_CSC_C13_C14_A_BASE_IDX                                                        2
9210 #define mmCOL_MAN1_INPUT_CSC_C21_C22_A                                                                 0x1402
9211 #define mmCOL_MAN1_INPUT_CSC_C21_C22_A_BASE_IDX                                                        2
9212 #define mmCOL_MAN1_INPUT_CSC_C23_C24_A                                                                 0x1403
9213 #define mmCOL_MAN1_INPUT_CSC_C23_C24_A_BASE_IDX                                                        2
9214 #define mmCOL_MAN1_INPUT_CSC_C31_C32_A                                                                 0x1404
9215 #define mmCOL_MAN1_INPUT_CSC_C31_C32_A_BASE_IDX                                                        2
9216 #define mmCOL_MAN1_INPUT_CSC_C33_C34_A                                                                 0x1405
9217 #define mmCOL_MAN1_INPUT_CSC_C33_C34_A_BASE_IDX                                                        2
9218 #define mmCOL_MAN1_INPUT_CSC_C11_C12_B                                                                 0x1406
9219 #define mmCOL_MAN1_INPUT_CSC_C11_C12_B_BASE_IDX                                                        2
9220 #define mmCOL_MAN1_INPUT_CSC_C13_C14_B                                                                 0x1407
9221 #define mmCOL_MAN1_INPUT_CSC_C13_C14_B_BASE_IDX                                                        2
9222 #define mmCOL_MAN1_INPUT_CSC_C21_C22_B                                                                 0x1408
9223 #define mmCOL_MAN1_INPUT_CSC_C21_C22_B_BASE_IDX                                                        2
9224 #define mmCOL_MAN1_INPUT_CSC_C23_C24_B                                                                 0x1409
9225 #define mmCOL_MAN1_INPUT_CSC_C23_C24_B_BASE_IDX                                                        2
9226 #define mmCOL_MAN1_INPUT_CSC_C31_C32_B                                                                 0x140a
9227 #define mmCOL_MAN1_INPUT_CSC_C31_C32_B_BASE_IDX                                                        2
9228 #define mmCOL_MAN1_INPUT_CSC_C33_C34_B                                                                 0x140b
9229 #define mmCOL_MAN1_INPUT_CSC_C33_C34_B_BASE_IDX                                                        2
9230 #define mmCOL_MAN1_PRESCALE_CONTROL                                                                    0x140c
9231 #define mmCOL_MAN1_PRESCALE_CONTROL_BASE_IDX                                                           2
9232 #define mmCOL_MAN1_PRESCALE_VALUES_R                                                                   0x140d
9233 #define mmCOL_MAN1_PRESCALE_VALUES_R_BASE_IDX                                                          2
9234 #define mmCOL_MAN1_PRESCALE_VALUES_G                                                                   0x140e
9235 #define mmCOL_MAN1_PRESCALE_VALUES_G_BASE_IDX                                                          2
9236 #define mmCOL_MAN1_PRESCALE_VALUES_B                                                                   0x140f
9237 #define mmCOL_MAN1_PRESCALE_VALUES_B_BASE_IDX                                                          2
9238 #define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL                                                          0x1410
9239 #define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX                                                 2
9240 #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A                                                                0x1411
9241 #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_BASE_IDX                                                       2
9242 #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A                                                                0x1412
9243 #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_BASE_IDX                                                       2
9244 #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A                                                                0x1413
9245 #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_BASE_IDX                                                       2
9246 #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A                                                                0x1414
9247 #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_BASE_IDX                                                       2
9248 #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A                                                                0x1415
9249 #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_BASE_IDX                                                       2
9250 #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A                                                                0x1416
9251 #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_BASE_IDX                                                       2
9252 #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B                                                                0x1417
9253 #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_BASE_IDX                                                       2
9254 #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B                                                                0x1418
9255 #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_BASE_IDX                                                       2
9256 #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B                                                                0x1419
9257 #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_BASE_IDX                                                       2
9258 #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B                                                                0x141a
9259 #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_BASE_IDX                                                       2
9260 #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B                                                                0x141b
9261 #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_BASE_IDX                                                       2
9262 #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B                                                                0x141c
9263 #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_BASE_IDX                                                       2
9264 #define mmCOL_MAN1_DENORM_CLAMP_CONTROL                                                                0x141d
9265 #define mmCOL_MAN1_DENORM_CLAMP_CONTROL_BASE_IDX                                                       2
9266 #define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR                                                             0x141e
9267 #define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_BASE_IDX                                                    2
9268 #define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y                                                              0x141f
9269 #define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_BASE_IDX                                                     2
9270 #define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB                                                             0x1420
9271 #define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_BASE_IDX                                                    2
9272 #define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD                                                          0x1421
9273 #define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX                                                 2
9274 #define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL                                                             0x1422
9275 #define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_BASE_IDX                                                    2
9276 #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX                                                           0x1423
9277 #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX                                                  2
9278 #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA                                                            0x1424
9279 #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX                                                   2
9280 #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK                                                   0x1425
9281 #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX                                          2
9282 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL                                                    0x1426
9283 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX                                           2
9284 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL                                                    0x1427
9285 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX                                           2
9286 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1                                                     0x1428
9287 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX                                            2
9288 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2                                                     0x1429
9289 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX                                            2
9290 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1                                                    0x142a
9291 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX                                           2
9292 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3                                                    0x142b
9293 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX                                           2
9294 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5                                                    0x142c
9295 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX                                           2
9296 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7                                                    0x142d
9297 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX                                           2
9298 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9                                                    0x142e
9299 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX                                           2
9300 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11                                                  0x142f
9301 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX                                         2
9302 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13                                                  0x1430
9303 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX                                         2
9304 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15                                                  0x1431
9305 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX                                         2
9306 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL                                                    0x1432
9307 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX                                           2
9308 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL                                                    0x1433
9309 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX                                           2
9310 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1                                                     0x1434
9311 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX                                            2
9312 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2                                                     0x1435
9313 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX                                            2
9314 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1                                                    0x1436
9315 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX                                           2
9316 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3                                                    0x1437
9317 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX                                           2
9318 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5                                                    0x1438
9319 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX                                           2
9320 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7                                                    0x1439
9321 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX                                           2
9322 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9                                                    0x143a
9323 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX                                           2
9324 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11                                                  0x143b
9325 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX                                         2
9326 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13                                                  0x143c
9327 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX                                         2
9328 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15                                                  0x143d
9329 #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX                                         2
9330 #define mmCOL_MAN1_PACK_FIFO_ERROR                                                                     0x143e
9331 #define mmCOL_MAN1_PACK_FIFO_ERROR_BASE_IDX                                                            2
9332 #define mmCOL_MAN1_OUTPUT_FIFO_ERROR                                                                   0x143f
9333 #define mmCOL_MAN1_OUTPUT_FIFO_ERROR_BASE_IDX                                                          2
9334 #define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL                                                            0x1440
9335 #define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX                                                   2
9336 #define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX                                                            0x1441
9337 #define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX                                                   2
9338 #define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR                                                           0x1442
9339 #define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX                                                  2
9340 #define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA                                                            0x1443
9341 #define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX                                                   2
9342 #define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR                                                            0x1444
9343 #define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX                                                   2
9344 #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1                                                        0x1445
9345 #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX                                               2
9346 #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2                                                        0x1446
9347 #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX                                               2
9348 #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B                                                            0x1447
9349 #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX                                                   2
9350 #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G                                                            0x1448
9351 #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX                                                   2
9352 #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R                                                            0x1449
9353 #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX                                                   2
9354 #define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL                                                             0x144a
9355 #define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_BASE_IDX                                                    2
9356 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL                                                         0x144b
9357 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX                                                2
9358 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12                                                         0x144c
9359 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX                                                2
9360 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14                                                         0x144d
9361 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX                                                2
9362 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22                                                         0x144e
9363 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX                                                2
9364 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24                                                         0x144f
9365 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX                                                2
9366 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32                                                         0x1450
9367 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX                                                2
9368 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34                                                         0x1451
9369 #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX                                                2
9370 
9371 
9372 // addressBlock: dce_dc_dcfev1_dispdec
9373 // base address: 0x800
9374 #define mmDCFEV1_DCFEV_CLOCK_CONTROL                                                                   0x147e
9375 #define mmDCFEV1_DCFEV_CLOCK_CONTROL_BASE_IDX                                                          2
9376 #define mmDCFEV1_DCFEV_SOFT_RESET                                                                      0x147f
9377 #define mmDCFEV1_DCFEV_SOFT_RESET_BASE_IDX                                                             2
9378 #define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL                                                             0x1480
9379 #define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX                                                    2
9380 #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL                                                              0x1482
9381 #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX                                                     2
9382 #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS                                                            0x1483
9383 #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX                                                   2
9384 #define mmDCFEV1_DCFEV_MEM_PWR_CTRL                                                                    0x1484
9385 #define mmDCFEV1_DCFEV_MEM_PWR_CTRL_BASE_IDX                                                           2
9386 #define mmDCFEV1_DCFEV_MEM_PWR_CTRL2                                                                   0x1485
9387 #define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_BASE_IDX                                                          2
9388 #define mmDCFEV1_DCFEV_MEM_PWR_STATUS                                                                  0x1486
9389 #define mmDCFEV1_DCFEV_MEM_PWR_STATUS_BASE_IDX                                                         2
9390 #define mmDCFEV1_DCFEV_L_FLUSH                                                                         0x1487
9391 #define mmDCFEV1_DCFEV_L_FLUSH_BASE_IDX                                                                2
9392 #define mmDCFEV1_DCFEV_C_FLUSH                                                                         0x1488
9393 #define mmDCFEV1_DCFEV_C_FLUSH_BASE_IDX                                                                2
9394 #define mmDCFEV1_DCFEV_MISC                                                                            0x148a
9395 #define mmDCFEV1_DCFEV_MISC_BASE_IDX                                                                   2
9396 
9397 
9398 // addressBlock: dce_dc_dc_perfmon12_dispdec
9399 // base address: 0x51c8
9400 #define mmDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x1492
9401 #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
9402 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x1493
9403 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
9404 #define mmDC_PERFMON12_PERFCOUNTER_STATE                                                               0x1494
9405 #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
9406 #define mmDC_PERFMON12_PERFMON_CNTL                                                                    0x1495
9407 #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
9408 #define mmDC_PERFMON12_PERFMON_CNTL2                                                                   0x1496
9409 #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
9410 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x1497
9411 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
9412 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x1498
9413 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
9414 #define mmDC_PERFMON12_PERFMON_HI                                                                      0x1499
9415 #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
9416 #define mmDC_PERFMON12_PERFMON_LOW                                                                     0x149a
9417 #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
9418 
9419 
9420 // addressBlock: dce_dc_dmifv_pg1_dispdec
9421 // base address: 0x800
9422 #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1                                                    0x149e
9423 #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                           2
9424 #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2                                                    0x149f
9425 #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                           2
9426 #define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL                                                       0x14a0
9427 #define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX                                              2
9428 #define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL                                                         0x14a1
9429 #define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX                                                2
9430 #define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL                                                             0x14a2
9431 #define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_BASE_IDX                                                    2
9432 #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL                                                         0x14a3
9433 #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX                                                2
9434 #define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL                                                0x14a4
9435 #define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX                                       2
9436 #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH                                                0x14a5
9437 #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX                                       2
9438 #define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM                                                             0x14a6
9439 #define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_BASE_IDX                                                    2
9440 #define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL                                                            0x14aa
9441 #define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX                                                   2
9442 #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1                                                    0x14ab
9443 #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX                                           2
9444 #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2                                                    0x14ac
9445 #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX                                           2
9446 #define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL                                                       0x14ad
9447 #define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX                                              2
9448 #define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL                                                         0x14ae
9449 #define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX                                                2
9450 #define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL                                                             0x14af
9451 #define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_BASE_IDX                                                    2
9452 #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL                                                         0x14b0
9453 #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX                                                2
9454 #define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL                                                0x14b1
9455 #define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX                                       2
9456 #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH                                                0x14b2
9457 #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX                                       2
9458 #define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM                                                             0x14b3
9459 #define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_BASE_IDX                                                    2
9460 #define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL                                                            0x14b7
9461 #define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX                                                   2
9462 
9463 
9464 // addressBlock: dce_dc_blndv1_dispdec
9465 // base address: 0x800
9466 #define mmBLNDV1_BLNDV_CONTROL                                                                         0x14db
9467 #define mmBLNDV1_BLNDV_CONTROL_BASE_IDX                                                                2
9468 #define mmBLNDV1_BLNDV_SM_CONTROL2                                                                     0x14dc
9469 #define mmBLNDV1_BLNDV_SM_CONTROL2_BASE_IDX                                                            2
9470 #define mmBLNDV1_BLNDV_CONTROL2                                                                        0x14dd
9471 #define mmBLNDV1_BLNDV_CONTROL2_BASE_IDX                                                               2
9472 #define mmBLNDV1_BLNDV_UPDATE                                                                          0x14de
9473 #define mmBLNDV1_BLNDV_UPDATE_BASE_IDX                                                                 2
9474 #define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT                                                             0x14df
9475 #define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX                                                    2
9476 #define mmBLNDV1_BLNDV_V_UPDATE_LOCK                                                                   0x14e0
9477 #define mmBLNDV1_BLNDV_V_UPDATE_LOCK_BASE_IDX                                                          2
9478 #define mmBLNDV1_BLNDV_REG_UPDATE_STATUS                                                               0x14e1
9479 #define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_BASE_IDX                                                      2
9480 
9481 
9482 // addressBlock: dce_dc_crtcv1_dispdec
9483 // base address: 0x800
9484 #define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM                                                               0x14e6
9485 #define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX                                                      2
9486 #define mmCRTCV1_CRTCV_H_TOTAL                                                                         0x14e7
9487 #define mmCRTCV1_CRTCV_H_TOTAL_BASE_IDX                                                                2
9488 #define mmCRTCV1_CRTCV_H_BLANK_START_END                                                               0x14e8
9489 #define mmCRTCV1_CRTCV_H_BLANK_START_END_BASE_IDX                                                      2
9490 #define mmCRTCV1_CRTCV_H_SYNC_A                                                                        0x14e9
9491 #define mmCRTCV1_CRTCV_H_SYNC_A_BASE_IDX                                                               2
9492 #define mmCRTCV1_CRTCV_H_SYNC_A_CNTL                                                                   0x14ea
9493 #define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_BASE_IDX                                                          2
9494 #define mmCRTCV1_CRTCV_H_SYNC_B                                                                        0x14eb
9495 #define mmCRTCV1_CRTCV_H_SYNC_B_BASE_IDX                                                               2
9496 #define mmCRTCV1_CRTCV_H_SYNC_B_CNTL                                                                   0x14ec
9497 #define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_BASE_IDX                                                          2
9498 #define mmCRTCV1_CRTCV_VBI_END                                                                         0x14ed
9499 #define mmCRTCV1_CRTCV_VBI_END_BASE_IDX                                                                2
9500 #define mmCRTCV1_CRTCV_V_TOTAL                                                                         0x14ee
9501 #define mmCRTCV1_CRTCV_V_TOTAL_BASE_IDX                                                                2
9502 #define mmCRTCV1_CRTCV_V_TOTAL_MIN                                                                     0x14ef
9503 #define mmCRTCV1_CRTCV_V_TOTAL_MIN_BASE_IDX                                                            2
9504 #define mmCRTCV1_CRTCV_V_TOTAL_MAX                                                                     0x14f0
9505 #define mmCRTCV1_CRTCV_V_TOTAL_MAX_BASE_IDX                                                            2
9506 #define mmCRTCV1_CRTCV_V_TOTAL_CONTROL                                                                 0x14f1
9507 #define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_BASE_IDX                                                        2
9508 #define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS                                                              0x14f2
9509 #define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX                                                     2
9510 #define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS                                                            0x14f3
9511 #define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX                                                   2
9512 #define mmCRTCV1_CRTCV_V_BLANK_START_END                                                               0x14f4
9513 #define mmCRTCV1_CRTCV_V_BLANK_START_END_BASE_IDX                                                      2
9514 #define mmCRTCV1_CRTCV_V_SYNC_A                                                                        0x14f5
9515 #define mmCRTCV1_CRTCV_V_SYNC_A_BASE_IDX                                                               2
9516 #define mmCRTCV1_CRTCV_V_SYNC_A_CNTL                                                                   0x14f6
9517 #define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_BASE_IDX                                                          2
9518 #define mmCRTCV1_CRTCV_V_SYNC_B                                                                        0x14f7
9519 #define mmCRTCV1_CRTCV_V_SYNC_B_BASE_IDX                                                               2
9520 #define mmCRTCV1_CRTCV_V_SYNC_B_CNTL                                                                   0x14f8
9521 #define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_BASE_IDX                                                          2
9522 #define mmCRTCV1_CRTCV_DTMTEST_CNTL                                                                    0x14f9
9523 #define mmCRTCV1_CRTCV_DTMTEST_CNTL_BASE_IDX                                                           2
9524 #define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION                                                         0x14fa
9525 #define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX                                                2
9526 #define mmCRTCV1_CRTCV_TRIGA_CNTL                                                                      0x14fb
9527 #define mmCRTCV1_CRTCV_TRIGA_CNTL_BASE_IDX                                                             2
9528 #define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG                                                               0x14fc
9529 #define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX                                                      2
9530 #define mmCRTCV1_CRTCV_TRIGB_CNTL                                                                      0x14fd
9531 #define mmCRTCV1_CRTCV_TRIGB_CNTL_BASE_IDX                                                             2
9532 #define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG                                                               0x14fe
9533 #define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX                                                      2
9534 #define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL                                                            0x14ff
9535 #define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                   2
9536 #define mmCRTCV1_CRTCV_FLOW_CONTROL                                                                    0x1500
9537 #define mmCRTCV1_CRTCV_FLOW_CONTROL_BASE_IDX                                                           2
9538 #define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE                                                           0x1501
9539 #define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                  2
9540 #define mmCRTCV1_CRTCV_AVSYNC_COUNTER                                                                  0x1502
9541 #define mmCRTCV1_CRTCV_AVSYNC_COUNTER_BASE_IDX                                                         2
9542 #define mmCRTCV1_CRTCV_CONTROL                                                                         0x1503
9543 #define mmCRTCV1_CRTCV_CONTROL_BASE_IDX                                                                2
9544 #define mmCRTCV1_CRTCV_BLANK_CONTROL                                                                   0x1504
9545 #define mmCRTCV1_CRTCV_BLANK_CONTROL_BASE_IDX                                                          2
9546 #define mmCRTCV1_CRTCV_INTERLACE_CONTROL                                                               0x1505
9547 #define mmCRTCV1_CRTCV_INTERLACE_CONTROL_BASE_IDX                                                      2
9548 #define mmCRTCV1_CRTCV_INTERLACE_STATUS                                                                0x1506
9549 #define mmCRTCV1_CRTCV_INTERLACE_STATUS_BASE_IDX                                                       2
9550 #define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL                                                        0x1507
9551 #define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX                                               2
9552 #define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0                                                            0x1508
9553 #define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX                                                   2
9554 #define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1                                                            0x1509
9555 #define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX                                                   2
9556 #define mmCRTCV1_CRTCV_STATUS                                                                          0x150a
9557 #define mmCRTCV1_CRTCV_STATUS_BASE_IDX                                                                 2
9558 #define mmCRTCV1_CRTCV_STATUS_POSITION                                                                 0x150b
9559 #define mmCRTCV1_CRTCV_STATUS_POSITION_BASE_IDX                                                        2
9560 #define mmCRTCV1_CRTCV_NOM_VERT_POSITION                                                               0x150c
9561 #define mmCRTCV1_CRTCV_NOM_VERT_POSITION_BASE_IDX                                                      2
9562 #define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT                                                              0x150d
9563 #define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_BASE_IDX                                                     2
9564 #define mmCRTCV1_CRTCV_STATUS_VF_COUNT                                                                 0x150e
9565 #define mmCRTCV1_CRTCV_STATUS_VF_COUNT_BASE_IDX                                                        2
9566 #define mmCRTCV1_CRTCV_STATUS_HV_COUNT                                                                 0x150f
9567 #define mmCRTCV1_CRTCV_STATUS_HV_COUNT_BASE_IDX                                                        2
9568 #define mmCRTCV1_CRTCV_COUNT_CONTROL                                                                   0x1510
9569 #define mmCRTCV1_CRTCV_COUNT_CONTROL_BASE_IDX                                                          2
9570 #define mmCRTCV1_CRTCV_COUNT_RESET                                                                     0x1511
9571 #define mmCRTCV1_CRTCV_COUNT_RESET_BASE_IDX                                                            2
9572 #define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE                                                    0x1512
9573 #define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                           2
9574 #define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL                                                               0x1513
9575 #define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_BASE_IDX                                                      2
9576 #define mmCRTCV1_CRTCV_STEREO_STATUS                                                                   0x1514
9577 #define mmCRTCV1_CRTCV_STEREO_STATUS_BASE_IDX                                                          2
9578 #define mmCRTCV1_CRTCV_STEREO_CONTROL                                                                  0x1515
9579 #define mmCRTCV1_CRTCV_STEREO_CONTROL_BASE_IDX                                                         2
9580 #define mmCRTCV1_CRTCV_SNAPSHOT_STATUS                                                                 0x1516
9581 #define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_BASE_IDX                                                        2
9582 #define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL                                                                0x1517
9583 #define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_BASE_IDX                                                       2
9584 #define mmCRTCV1_CRTCV_SNAPSHOT_POSITION                                                               0x1518
9585 #define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_BASE_IDX                                                      2
9586 #define mmCRTCV1_CRTCV_SNAPSHOT_FRAME                                                                  0x1519
9587 #define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_BASE_IDX                                                         2
9588 #define mmCRTCV1_CRTCV_START_LINE_CONTROL                                                              0x151a
9589 #define mmCRTCV1_CRTCV_START_LINE_CONTROL_BASE_IDX                                                     2
9590 #define mmCRTCV1_CRTCV_INTERRUPT_CONTROL                                                               0x151b
9591 #define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_BASE_IDX                                                      2
9592 #define mmCRTCV1_CRTCV_UPDATE_LOCK                                                                     0x151c
9593 #define mmCRTCV1_CRTCV_UPDATE_LOCK_BASE_IDX                                                            2
9594 #define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL                                                           0x151d
9595 #define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                  2
9596 #define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE                                                      0x151e
9597 #define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX                                             2
9598 #define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL                                                            0x151f
9599 #define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX                                                   2
9600 #define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS                                                         0x1520
9601 #define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX                                                2
9602 #define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR                                                              0x1521
9603 #define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_BASE_IDX                                                     2
9604 #define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK                                                              0x1522
9605 #define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX                                                     2
9606 #define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE                                                              0x1523
9607 #define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_BASE_IDX                                                     2
9608 #define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT                                                          0x1524
9609 #define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX                                                 2
9610 #define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER                                                    0x1525
9611 #define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX                                           2
9612 #define mmCRTCV1_CRTCV_MVP_STATUS                                                                      0x1526
9613 #define mmCRTCV1_CRTCV_MVP_STATUS_BASE_IDX                                                             2
9614 #define mmCRTCV1_CRTCV_MASTER_EN                                                                       0x1527
9615 #define mmCRTCV1_CRTCV_MASTER_EN_BASE_IDX                                                              2
9616 #define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT                                                            0x1528
9617 #define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX                                                   2
9618 #define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS                                                             0x1529
9619 #define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX                                                    2
9620 #define mmCRTCV1_CRTCV_OVERSCAN_COLOR                                                                  0x152b
9621 #define mmCRTCV1_CRTCV_OVERSCAN_COLOR_BASE_IDX                                                         2
9622 #define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT                                                              0x152c
9623 #define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX                                                     2
9624 #define mmCRTCV1_CRTCV_BLANK_DATA_COLOR                                                                0x152d
9625 #define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_BASE_IDX                                                       2
9626 #define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT                                                            0x152e
9627 #define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX                                                   2
9628 #define mmCRTCV1_CRTCV_BLACK_COLOR                                                                     0x152f
9629 #define mmCRTCV1_CRTCV_BLACK_COLOR_BASE_IDX                                                            2
9630 #define mmCRTCV1_CRTCV_BLACK_COLOR_EXT                                                                 0x1530
9631 #define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_BASE_IDX                                                        2
9632 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION                                                    0x1531
9633 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                           2
9634 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL                                                     0x1532
9635 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                            2
9636 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION                                                    0x1533
9637 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                           2
9638 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL                                                     0x1534
9639 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                            2
9640 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION                                                    0x1535
9641 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                           2
9642 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL                                                     0x1536
9643 #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                            2
9644 #define mmCRTCV1_CRTCV_CRC_CNTL                                                                        0x1537
9645 #define mmCRTCV1_CRTCV_CRC_CNTL_BASE_IDX                                                               2
9646 #define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL                                                          0x1538
9647 #define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                 2
9648 #define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL                                                          0x1539
9649 #define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                 2
9650 #define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL                                                          0x153a
9651 #define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                 2
9652 #define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL                                                          0x153b
9653 #define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                 2
9654 #define mmCRTCV1_CRTCV_CRC0_DATA_RG                                                                    0x153c
9655 #define mmCRTCV1_CRTCV_CRC0_DATA_RG_BASE_IDX                                                           2
9656 #define mmCRTCV1_CRTCV_CRC0_DATA_B                                                                     0x153d
9657 #define mmCRTCV1_CRTCV_CRC0_DATA_B_BASE_IDX                                                            2
9658 #define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL                                                          0x153e
9659 #define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                 2
9660 #define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL                                                          0x153f
9661 #define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                 2
9662 #define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL                                                          0x1540
9663 #define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                 2
9664 #define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL                                                          0x1541
9665 #define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                 2
9666 #define mmCRTCV1_CRTCV_CRC1_DATA_RG                                                                    0x1542
9667 #define mmCRTCV1_CRTCV_CRC1_DATA_RG_BASE_IDX                                                           2
9668 #define mmCRTCV1_CRTCV_CRC1_DATA_B                                                                     0x1543
9669 #define mmCRTCV1_CRTCV_CRC1_DATA_B_BASE_IDX                                                            2
9670 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL                                                         0x1544
9671 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX                                                2
9672 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START                                                    0x1545
9673 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX                                           2
9674 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END                                                      0x1546
9675 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX                                             2
9676 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL                                          0x1547
9677 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX                                 2
9678 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL                                               0x1548
9679 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX                                      2
9680 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL                                        0x1549
9681 #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX                               2
9682 #define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL                                                           0x154a
9683 #define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX                                                  2
9684 #define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL                                                            0x154b
9685 #define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX                                                   2
9686 #define mmCRTCV1_CRTCV_GSL_VSYNC_GAP                                                                   0x154c
9687 #define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_BASE_IDX                                                          2
9688 #define mmCRTCV1_CRTCV_GSL_WINDOW                                                                      0x154d
9689 #define mmCRTCV1_CRTCV_GSL_WINDOW_BASE_IDX                                                             2
9690 #define mmCRTCV1_CRTCV_GSL_CONTROL                                                                     0x154e
9691 #define mmCRTCV1_CRTCV_GSL_CONTROL_BASE_IDX                                                            2
9692 
9693 
9694 // addressBlock: dce_dc_hpd0_dispdec
9695 // base address: 0x0
9696 #define mmHPD0_DC_HPD_INT_STATUS                                                                       0x1600
9697 #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9698 #define mmHPD0_DC_HPD_INT_CONTROL                                                                      0x1601
9699 #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9700 #define mmHPD0_DC_HPD_CONTROL                                                                          0x1602
9701 #define mmHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
9702 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1603
9703 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9704 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1604
9705 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9706 
9707 
9708 // addressBlock: dce_dc_hpd1_dispdec
9709 // base address: 0x20
9710 #define mmHPD1_DC_HPD_INT_STATUS                                                                       0x1608
9711 #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9712 #define mmHPD1_DC_HPD_INT_CONTROL                                                                      0x1609
9713 #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9714 #define mmHPD1_DC_HPD_CONTROL                                                                          0x160a
9715 #define mmHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
9716 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x160b
9717 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9718 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x160c
9719 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9720 
9721 
9722 // addressBlock: dce_dc_hpd2_dispdec
9723 // base address: 0x40
9724 #define mmHPD2_DC_HPD_INT_STATUS                                                                       0x1610
9725 #define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9726 #define mmHPD2_DC_HPD_INT_CONTROL                                                                      0x1611
9727 #define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9728 #define mmHPD2_DC_HPD_CONTROL                                                                          0x1612
9729 #define mmHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
9730 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1613
9731 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9732 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1614
9733 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9734 
9735 
9736 // addressBlock: dce_dc_hpd3_dispdec
9737 // base address: 0x60
9738 #define mmHPD3_DC_HPD_INT_STATUS                                                                       0x1618
9739 #define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9740 #define mmHPD3_DC_HPD_INT_CONTROL                                                                      0x1619
9741 #define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9742 #define mmHPD3_DC_HPD_CONTROL                                                                          0x161a
9743 #define mmHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
9744 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x161b
9745 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9746 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x161c
9747 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9748 
9749 
9750 // addressBlock: dce_dc_hpd4_dispdec
9751 // base address: 0x80
9752 #define mmHPD4_DC_HPD_INT_STATUS                                                                       0x1620
9753 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9754 #define mmHPD4_DC_HPD_INT_CONTROL                                                                      0x1621
9755 #define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9756 #define mmHPD4_DC_HPD_CONTROL                                                                          0x1622
9757 #define mmHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
9758 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1623
9759 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9760 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1624
9761 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9762 
9763 
9764 // addressBlock: dce_dc_hpd5_dispdec
9765 // base address: 0xa0
9766 #define mmHPD5_DC_HPD_INT_STATUS                                                                       0x1628
9767 #define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX                                                              2
9768 #define mmHPD5_DC_HPD_INT_CONTROL                                                                      0x1629
9769 #define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
9770 #define mmHPD5_DC_HPD_CONTROL                                                                          0x162a
9771 #define mmHPD5_DC_HPD_CONTROL_BASE_IDX                                                                 2
9772 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL                                                                  0x162b
9773 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
9774 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x162c
9775 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
9776 
9777 
9778 // addressBlock: dce_dc_dc_perfmon2_dispdec
9779 // base address: 0x5840
9780 #define mmDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x1630
9781 #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
9782 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x1631
9783 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
9784 #define mmDC_PERFMON2_PERFCOUNTER_STATE                                                                0x1632
9785 #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
9786 #define mmDC_PERFMON2_PERFMON_CNTL                                                                     0x1633
9787 #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
9788 #define mmDC_PERFMON2_PERFMON_CNTL2                                                                    0x1634
9789 #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
9790 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x1635
9791 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
9792 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x1636
9793 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
9794 #define mmDC_PERFMON2_PERFMON_HI                                                                       0x1637
9795 #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
9796 #define mmDC_PERFMON2_PERFMON_LOW                                                                      0x1638
9797 #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
9798 
9799 
9800 // addressBlock: dce_dc_dp_aux0_dispdec
9801 // base address: 0x0
9802 #define mmDP_AUX0_AUX_CONTROL                                                                          0x1766
9803 #define mmDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
9804 #define mmDP_AUX0_AUX_SW_CONTROL                                                                       0x1767
9805 #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
9806 #define mmDP_AUX0_AUX_ARB_CONTROL                                                                      0x1768
9807 #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
9808 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1769
9809 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9810 #define mmDP_AUX0_AUX_SW_STATUS                                                                        0x176a
9811 #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
9812 #define mmDP_AUX0_AUX_LS_STATUS                                                                        0x176b
9813 #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
9814 #define mmDP_AUX0_AUX_SW_DATA                                                                          0x176c
9815 #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
9816 #define mmDP_AUX0_AUX_LS_DATA                                                                          0x176d
9817 #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
9818 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x176e
9819 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9820 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x176f
9821 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9822 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1770
9823 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9824 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1771
9825 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9826 #define mmDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1772
9827 #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9828 #define mmDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1773
9829 #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9830 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1775
9831 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9832 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1776
9833 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9834 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1777
9835 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9836 
9837 
9838 // addressBlock: dce_dc_dp_aux1_dispdec
9839 // base address: 0x70
9840 #define mmDP_AUX1_AUX_CONTROL                                                                          0x1782
9841 #define mmDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
9842 #define mmDP_AUX1_AUX_SW_CONTROL                                                                       0x1783
9843 #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
9844 #define mmDP_AUX1_AUX_ARB_CONTROL                                                                      0x1784
9845 #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
9846 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1785
9847 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9848 #define mmDP_AUX1_AUX_SW_STATUS                                                                        0x1786
9849 #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
9850 #define mmDP_AUX1_AUX_LS_STATUS                                                                        0x1787
9851 #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
9852 #define mmDP_AUX1_AUX_SW_DATA                                                                          0x1788
9853 #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
9854 #define mmDP_AUX1_AUX_LS_DATA                                                                          0x1789
9855 #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
9856 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x178a
9857 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9858 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x178b
9859 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9860 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x178c
9861 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9862 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x178d
9863 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9864 #define mmDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x178e
9865 #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9866 #define mmDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x178f
9867 #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9868 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1791
9869 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9870 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1792
9871 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9872 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1793
9873 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9874 
9875 
9876 // addressBlock: dce_dc_dp_aux2_dispdec
9877 // base address: 0xe0
9878 #define mmDP_AUX2_AUX_CONTROL                                                                          0x179e
9879 #define mmDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
9880 #define mmDP_AUX2_AUX_SW_CONTROL                                                                       0x179f
9881 #define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
9882 #define mmDP_AUX2_AUX_ARB_CONTROL                                                                      0x17a0
9883 #define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
9884 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x17a1
9885 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9886 #define mmDP_AUX2_AUX_SW_STATUS                                                                        0x17a2
9887 #define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
9888 #define mmDP_AUX2_AUX_LS_STATUS                                                                        0x17a3
9889 #define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
9890 #define mmDP_AUX2_AUX_SW_DATA                                                                          0x17a4
9891 #define mmDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
9892 #define mmDP_AUX2_AUX_LS_DATA                                                                          0x17a5
9893 #define mmDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
9894 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x17a6
9895 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9896 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x17a7
9897 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9898 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x17a8
9899 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9900 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x17a9
9901 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9902 #define mmDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x17aa
9903 #define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9904 #define mmDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x17ab
9905 #define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9906 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x17ad
9907 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9908 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x17ae
9909 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9910 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x17af
9911 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9912 
9913 
9914 // addressBlock: dce_dc_dp_aux3_dispdec
9915 // base address: 0x150
9916 #define mmDP_AUX3_AUX_CONTROL                                                                          0x17ba
9917 #define mmDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
9918 #define mmDP_AUX3_AUX_SW_CONTROL                                                                       0x17bb
9919 #define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
9920 #define mmDP_AUX3_AUX_ARB_CONTROL                                                                      0x17bc
9921 #define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
9922 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x17bd
9923 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9924 #define mmDP_AUX3_AUX_SW_STATUS                                                                        0x17be
9925 #define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
9926 #define mmDP_AUX3_AUX_LS_STATUS                                                                        0x17bf
9927 #define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
9928 #define mmDP_AUX3_AUX_SW_DATA                                                                          0x17c0
9929 #define mmDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
9930 #define mmDP_AUX3_AUX_LS_DATA                                                                          0x17c1
9931 #define mmDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
9932 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x17c2
9933 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9934 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x17c3
9935 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9936 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x17c4
9937 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9938 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x17c5
9939 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9940 #define mmDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x17c6
9941 #define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9942 #define mmDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x17c7
9943 #define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9944 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x17c9
9945 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9946 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x17ca
9947 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9948 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x17cb
9949 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9950 
9951 
9952 // addressBlock: dce_dc_dp_aux4_dispdec
9953 // base address: 0x1c0
9954 #define mmDP_AUX4_AUX_CONTROL                                                                          0x17d6
9955 #define mmDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
9956 #define mmDP_AUX4_AUX_SW_CONTROL                                                                       0x17d7
9957 #define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
9958 #define mmDP_AUX4_AUX_ARB_CONTROL                                                                      0x17d8
9959 #define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
9960 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x17d9
9961 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
9962 #define mmDP_AUX4_AUX_SW_STATUS                                                                        0x17da
9963 #define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
9964 #define mmDP_AUX4_AUX_LS_STATUS                                                                        0x17db
9965 #define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
9966 #define mmDP_AUX4_AUX_SW_DATA                                                                          0x17dc
9967 #define mmDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
9968 #define mmDP_AUX4_AUX_LS_DATA                                                                          0x17dd
9969 #define mmDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
9970 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x17de
9971 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
9972 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x17df
9973 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
9974 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x17e0
9975 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
9976 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x17e1
9977 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
9978 #define mmDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x17e2
9979 #define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
9980 #define mmDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x17e3
9981 #define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
9982 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x17e5
9983 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
9984 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x17e6
9985 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
9986 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x17e7
9987 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
9988 
9989 
9990 // addressBlock: dce_dc_dp_aux5_dispdec
9991 // base address: 0x230
9992 #define mmDP_AUX5_AUX_CONTROL                                                                          0x17f2
9993 #define mmDP_AUX5_AUX_CONTROL_BASE_IDX                                                                 2
9994 #define mmDP_AUX5_AUX_SW_CONTROL                                                                       0x17f3
9995 #define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX                                                              2
9996 #define mmDP_AUX5_AUX_ARB_CONTROL                                                                      0x17f4
9997 #define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX                                                             2
9998 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL                                                                0x17f5
9999 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
10000 #define mmDP_AUX5_AUX_SW_STATUS                                                                        0x17f6
10001 #define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX                                                               2
10002 #define mmDP_AUX5_AUX_LS_STATUS                                                                        0x17f7
10003 #define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX                                                               2
10004 #define mmDP_AUX5_AUX_SW_DATA                                                                          0x17f8
10005 #define mmDP_AUX5_AUX_SW_DATA_BASE_IDX                                                                 2
10006 #define mmDP_AUX5_AUX_LS_DATA                                                                          0x17f9
10007 #define mmDP_AUX5_AUX_LS_DATA_BASE_IDX                                                                 2
10008 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL                                                              0x17fa
10009 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
10010 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL                                                                  0x17fb
10011 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
10012 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0                                                                 0x17fc
10013 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
10014 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1                                                                 0x17fd
10015 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
10016 #define mmDP_AUX5_AUX_DPHY_TX_STATUS                                                                   0x17fe
10017 #define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
10018 #define mmDP_AUX5_AUX_DPHY_RX_STATUS                                                                   0x17ff
10019 #define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
10020 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1801
10021 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
10022 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1802
10023 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
10024 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS                                                                  0x1803
10025 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
10026 
10027 
10028 // addressBlock: dce_dc_dig0_dispdec
10029 // base address: 0x0
10030 #define mmDIG0_DIG_FE_CNTL                                                                             0x187e
10031 #define mmDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
10032 #define mmDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x187f
10033 #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10034 #define mmDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x1880
10035 #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10036 #define mmDIG0_DIG_CLOCK_PATTERN                                                                       0x1881
10037 #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10038 #define mmDIG0_DIG_TEST_PATTERN                                                                        0x1882
10039 #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
10040 #define mmDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x1883
10041 #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10042 #define mmDIG0_DIG_FIFO_STATUS                                                                         0x1884
10043 #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
10044 #define mmDIG0_HDMI_CONTROL                                                                            0x1887
10045 #define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
10046 #define mmDIG0_HDMI_STATUS                                                                             0x1888
10047 #define mmDIG0_HDMI_STATUS_BASE_IDX                                                                    2
10048 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x1889
10049 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10050 #define mmDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x188a
10051 #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10052 #define mmDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x188b
10053 #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10054 #define mmDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x188c
10055 #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10056 #define mmDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x188d
10057 #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10058 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x188e
10059 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10060 #define mmDIG0_AFMT_INTERRUPT_STATUS                                                                   0x188f
10061 #define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
10062 #define mmDIG0_HDMI_GC                                                                                 0x1891
10063 #define mmDIG0_HDMI_GC_BASE_IDX                                                                        2
10064 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                                              0x1892
10065 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
10066 #define mmDIG0_AFMT_ISRC1_0                                                                            0x1893
10067 #define mmDIG0_AFMT_ISRC1_0_BASE_IDX                                                                   2
10068 #define mmDIG0_AFMT_ISRC1_1                                                                            0x1894
10069 #define mmDIG0_AFMT_ISRC1_1_BASE_IDX                                                                   2
10070 #define mmDIG0_AFMT_ISRC1_2                                                                            0x1895
10071 #define mmDIG0_AFMT_ISRC1_2_BASE_IDX                                                                   2
10072 #define mmDIG0_AFMT_ISRC1_3                                                                            0x1896
10073 #define mmDIG0_AFMT_ISRC1_3_BASE_IDX                                                                   2
10074 #define mmDIG0_AFMT_ISRC1_4                                                                            0x1897
10075 #define mmDIG0_AFMT_ISRC1_4_BASE_IDX                                                                   2
10076 #define mmDIG0_AFMT_ISRC2_0                                                                            0x1898
10077 #define mmDIG0_AFMT_ISRC2_0_BASE_IDX                                                                   2
10078 #define mmDIG0_AFMT_ISRC2_1                                                                            0x1899
10079 #define mmDIG0_AFMT_ISRC2_1_BASE_IDX                                                                   2
10080 #define mmDIG0_AFMT_ISRC2_2                                                                            0x189a
10081 #define mmDIG0_AFMT_ISRC2_2_BASE_IDX                                                                   2
10082 #define mmDIG0_AFMT_ISRC2_3                                                                            0x189b
10083 #define mmDIG0_AFMT_ISRC2_3_BASE_IDX                                                                   2
10084 #define mmDIG0_AFMT_AVI_INFO0                                                                          0x189c
10085 #define mmDIG0_AFMT_AVI_INFO0_BASE_IDX                                                                 2
10086 #define mmDIG0_AFMT_AVI_INFO1                                                                          0x189d
10087 #define mmDIG0_AFMT_AVI_INFO1_BASE_IDX                                                                 2
10088 #define mmDIG0_AFMT_AVI_INFO2                                                                          0x189e
10089 #define mmDIG0_AFMT_AVI_INFO2_BASE_IDX                                                                 2
10090 #define mmDIG0_AFMT_AVI_INFO3                                                                          0x189f
10091 #define mmDIG0_AFMT_AVI_INFO3_BASE_IDX                                                                 2
10092 #define mmDIG0_AFMT_MPEG_INFO0                                                                         0x18a0
10093 #define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX                                                                2
10094 #define mmDIG0_AFMT_MPEG_INFO1                                                                         0x18a1
10095 #define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX                                                                2
10096 #define mmDIG0_AFMT_GENERIC_HDR                                                                        0x18a2
10097 #define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX                                                               2
10098 #define mmDIG0_AFMT_GENERIC_0                                                                          0x18a3
10099 #define mmDIG0_AFMT_GENERIC_0_BASE_IDX                                                                 2
10100 #define mmDIG0_AFMT_GENERIC_1                                                                          0x18a4
10101 #define mmDIG0_AFMT_GENERIC_1_BASE_IDX                                                                 2
10102 #define mmDIG0_AFMT_GENERIC_2                                                                          0x18a5
10103 #define mmDIG0_AFMT_GENERIC_2_BASE_IDX                                                                 2
10104 #define mmDIG0_AFMT_GENERIC_3                                                                          0x18a6
10105 #define mmDIG0_AFMT_GENERIC_3_BASE_IDX                                                                 2
10106 #define mmDIG0_AFMT_GENERIC_4                                                                          0x18a7
10107 #define mmDIG0_AFMT_GENERIC_4_BASE_IDX                                                                 2
10108 #define mmDIG0_AFMT_GENERIC_5                                                                          0x18a8
10109 #define mmDIG0_AFMT_GENERIC_5_BASE_IDX                                                                 2
10110 #define mmDIG0_AFMT_GENERIC_6                                                                          0x18a9
10111 #define mmDIG0_AFMT_GENERIC_6_BASE_IDX                                                                 2
10112 #define mmDIG0_AFMT_GENERIC_7                                                                          0x18aa
10113 #define mmDIG0_AFMT_GENERIC_7_BASE_IDX                                                                 2
10114 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x18ab
10115 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10116 #define mmDIG0_HDMI_ACR_32_0                                                                           0x18ac
10117 #define mmDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
10118 #define mmDIG0_HDMI_ACR_32_1                                                                           0x18ad
10119 #define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
10120 #define mmDIG0_HDMI_ACR_44_0                                                                           0x18ae
10121 #define mmDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
10122 #define mmDIG0_HDMI_ACR_44_1                                                                           0x18af
10123 #define mmDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
10124 #define mmDIG0_HDMI_ACR_48_0                                                                           0x18b0
10125 #define mmDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
10126 #define mmDIG0_HDMI_ACR_48_1                                                                           0x18b1
10127 #define mmDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
10128 #define mmDIG0_HDMI_ACR_STATUS_0                                                                       0x18b2
10129 #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10130 #define mmDIG0_HDMI_ACR_STATUS_1                                                                       0x18b3
10131 #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10132 #define mmDIG0_AFMT_AUDIO_INFO0                                                                        0x18b4
10133 #define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
10134 #define mmDIG0_AFMT_AUDIO_INFO1                                                                        0x18b5
10135 #define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
10136 #define mmDIG0_AFMT_60958_0                                                                            0x18b6
10137 #define mmDIG0_AFMT_60958_0_BASE_IDX                                                                   2
10138 #define mmDIG0_AFMT_60958_1                                                                            0x18b7
10139 #define mmDIG0_AFMT_60958_1_BASE_IDX                                                                   2
10140 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL                                                                  0x18b8
10141 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
10142 #define mmDIG0_AFMT_RAMP_CONTROL0                                                                      0x18b9
10143 #define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
10144 #define mmDIG0_AFMT_RAMP_CONTROL1                                                                      0x18ba
10145 #define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
10146 #define mmDIG0_AFMT_RAMP_CONTROL2                                                                      0x18bb
10147 #define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
10148 #define mmDIG0_AFMT_RAMP_CONTROL3                                                                      0x18bc
10149 #define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
10150 #define mmDIG0_AFMT_60958_2                                                                            0x18bd
10151 #define mmDIG0_AFMT_60958_2_BASE_IDX                                                                   2
10152 #define mmDIG0_AFMT_AUDIO_CRC_RESULT                                                                   0x18be
10153 #define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
10154 #define mmDIG0_AFMT_STATUS                                                                             0x18bf
10155 #define mmDIG0_AFMT_STATUS_BASE_IDX                                                                    2
10156 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                                               0x18c0
10157 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10158 #define mmDIG0_AFMT_VBI_PACKET_CONTROL                                                                 0x18c1
10159 #define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10160 #define mmDIG0_AFMT_INFOFRAME_CONTROL0                                                                 0x18c2
10161 #define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10162 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL                                                                  0x18c3
10163 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
10164 #define mmDIG0_DIG_BE_CNTL                                                                             0x18c5
10165 #define mmDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
10166 #define mmDIG0_DIG_BE_EN_CNTL                                                                          0x18c6
10167 #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
10168 #define mmDIG0_TMDS_CNTL                                                                               0x18e9
10169 #define mmDIG0_TMDS_CNTL_BASE_IDX                                                                      2
10170 #define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x18ea
10171 #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
10172 #define mmDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x18eb
10173 #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
10174 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x18ec
10175 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
10176 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x18ed
10177 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
10178 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x18ee
10179 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
10180 #define mmDIG0_TMDS_CTL_BITS                                                                           0x18f0
10181 #define mmDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
10182 #define mmDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x18f1
10183 #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
10184 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x18f3
10185 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
10186 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x18f4
10187 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
10188 #define mmDIG0_DIG_VERSION                                                                             0x18f6
10189 #define mmDIG0_DIG_VERSION_BASE_IDX                                                                    2
10190 #define mmDIG0_DIG_LANE_ENABLE                                                                         0x18f7
10191 #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX                                                                2
10192 #define mmDIG0_AFMT_CNTL                                                                               0x18fc
10193 #define mmDIG0_AFMT_CNTL_BASE_IDX                                                                      2
10194 
10195 
10196 // addressBlock: dce_dc_dp0_dispdec
10197 // base address: 0x0
10198 #define mmDP0_DP_LINK_CNTL                                                                             0x191e
10199 #define mmDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
10200 #define mmDP0_DP_PIXEL_FORMAT                                                                          0x191f
10201 #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
10202 #define mmDP0_DP_MSA_COLORIMETRY                                                                       0x1920
10203 #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
10204 #define mmDP0_DP_CONFIG                                                                                0x1921
10205 #define mmDP0_DP_CONFIG_BASE_IDX                                                                       2
10206 #define mmDP0_DP_VID_STREAM_CNTL                                                                       0x1922
10207 #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
10208 #define mmDP0_DP_STEER_FIFO                                                                            0x1923
10209 #define mmDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
10210 #define mmDP0_DP_MSA_MISC                                                                              0x1924
10211 #define mmDP0_DP_MSA_MISC_BASE_IDX                                                                     2
10212 #define mmDP0_DP_VID_TIMING                                                                            0x1926
10213 #define mmDP0_DP_VID_TIMING_BASE_IDX                                                                   2
10214 #define mmDP0_DP_VID_N                                                                                 0x1927
10215 #define mmDP0_DP_VID_N_BASE_IDX                                                                        2
10216 #define mmDP0_DP_VID_M                                                                                 0x1928
10217 #define mmDP0_DP_VID_M_BASE_IDX                                                                        2
10218 #define mmDP0_DP_LINK_FRAMING_CNTL                                                                     0x1929
10219 #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
10220 #define mmDP0_DP_HBR2_EYE_PATTERN                                                                      0x192a
10221 #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
10222 #define mmDP0_DP_VID_MSA_VBID                                                                          0x192b
10223 #define mmDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
10224 #define mmDP0_DP_VID_INTERRUPT_CNTL                                                                    0x192c
10225 #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
10226 #define mmDP0_DP_DPHY_CNTL                                                                             0x192d
10227 #define mmDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
10228 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x192e
10229 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
10230 #define mmDP0_DP_DPHY_SYM0                                                                             0x192f
10231 #define mmDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
10232 #define mmDP0_DP_DPHY_SYM1                                                                             0x1930
10233 #define mmDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
10234 #define mmDP0_DP_DPHY_SYM2                                                                             0x1931
10235 #define mmDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
10236 #define mmDP0_DP_DPHY_8B10B_CNTL                                                                       0x1932
10237 #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
10238 #define mmDP0_DP_DPHY_PRBS_CNTL                                                                        0x1933
10239 #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
10240 #define mmDP0_DP_DPHY_SCRAM_CNTL                                                                       0x1934
10241 #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
10242 #define mmDP0_DP_DPHY_CRC_EN                                                                           0x1935
10243 #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
10244 #define mmDP0_DP_DPHY_CRC_CNTL                                                                         0x1936
10245 #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
10246 #define mmDP0_DP_DPHY_CRC_RESULT                                                                       0x1937
10247 #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
10248 #define mmDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x1938
10249 #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
10250 #define mmDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x1939
10251 #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
10252 #define mmDP0_DP_DPHY_FAST_TRAINING                                                                    0x193a
10253 #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
10254 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x193b
10255 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
10256 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1                                                                0x193c
10257 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX                                                       2
10258 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2                                                                0x193d
10259 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX                                                       2
10260 #define mmDP0_DP_SEC_CNTL                                                                              0x1941
10261 #define mmDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
10262 #define mmDP0_DP_SEC_CNTL1                                                                             0x1942
10263 #define mmDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
10264 #define mmDP0_DP_SEC_FRAMING1                                                                          0x1943
10265 #define mmDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
10266 #define mmDP0_DP_SEC_FRAMING2                                                                          0x1944
10267 #define mmDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
10268 #define mmDP0_DP_SEC_FRAMING3                                                                          0x1945
10269 #define mmDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
10270 #define mmDP0_DP_SEC_FRAMING4                                                                          0x1946
10271 #define mmDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
10272 #define mmDP0_DP_SEC_AUD_N                                                                             0x1947
10273 #define mmDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
10274 #define mmDP0_DP_SEC_AUD_N_READBACK                                                                    0x1948
10275 #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
10276 #define mmDP0_DP_SEC_AUD_M                                                                             0x1949
10277 #define mmDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
10278 #define mmDP0_DP_SEC_AUD_M_READBACK                                                                    0x194a
10279 #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
10280 #define mmDP0_DP_SEC_TIMESTAMP                                                                         0x194b
10281 #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
10282 #define mmDP0_DP_SEC_PACKET_CNTL                                                                       0x194c
10283 #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
10284 #define mmDP0_DP_MSE_RATE_CNTL                                                                         0x194d
10285 #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
10286 #define mmDP0_DP_MSE_RATE_UPDATE                                                                       0x194f
10287 #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
10288 #define mmDP0_DP_MSE_SAT0                                                                              0x1950
10289 #define mmDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
10290 #define mmDP0_DP_MSE_SAT1                                                                              0x1951
10291 #define mmDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
10292 #define mmDP0_DP_MSE_SAT2                                                                              0x1952
10293 #define mmDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
10294 #define mmDP0_DP_MSE_SAT_UPDATE                                                                        0x1953
10295 #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
10296 #define mmDP0_DP_MSE_LINK_TIMING                                                                       0x1954
10297 #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
10298 #define mmDP0_DP_MSE_MISC_CNTL                                                                         0x1955
10299 #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
10300 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x195a
10301 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
10302 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x195b
10303 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
10304 #define mmDP0_DP_MSE_SAT0_STATUS                                                                       0x195d
10305 #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
10306 #define mmDP0_DP_MSE_SAT1_STATUS                                                                       0x195e
10307 #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
10308 #define mmDP0_DP_MSE_SAT2_STATUS                                                                       0x195f
10309 #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
10310 
10311 
10312 // addressBlock: dce_dc_dig1_dispdec
10313 // base address: 0x400
10314 #define mmDIG1_DIG_FE_CNTL                                                                             0x197e
10315 #define mmDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
10316 #define mmDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x197f
10317 #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10318 #define mmDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x1980
10319 #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10320 #define mmDIG1_DIG_CLOCK_PATTERN                                                                       0x1981
10321 #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10322 #define mmDIG1_DIG_TEST_PATTERN                                                                        0x1982
10323 #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
10324 #define mmDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x1983
10325 #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10326 #define mmDIG1_DIG_FIFO_STATUS                                                                         0x1984
10327 #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
10328 #define mmDIG1_HDMI_CONTROL                                                                            0x1987
10329 #define mmDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
10330 #define mmDIG1_HDMI_STATUS                                                                             0x1988
10331 #define mmDIG1_HDMI_STATUS_BASE_IDX                                                                    2
10332 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x1989
10333 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10334 #define mmDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x198a
10335 #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10336 #define mmDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x198b
10337 #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10338 #define mmDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x198c
10339 #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10340 #define mmDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x198d
10341 #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10342 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x198e
10343 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10344 #define mmDIG1_AFMT_INTERRUPT_STATUS                                                                   0x198f
10345 #define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
10346 #define mmDIG1_HDMI_GC                                                                                 0x1991
10347 #define mmDIG1_HDMI_GC_BASE_IDX                                                                        2
10348 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                                              0x1992
10349 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
10350 #define mmDIG1_AFMT_ISRC1_0                                                                            0x1993
10351 #define mmDIG1_AFMT_ISRC1_0_BASE_IDX                                                                   2
10352 #define mmDIG1_AFMT_ISRC1_1                                                                            0x1994
10353 #define mmDIG1_AFMT_ISRC1_1_BASE_IDX                                                                   2
10354 #define mmDIG1_AFMT_ISRC1_2                                                                            0x1995
10355 #define mmDIG1_AFMT_ISRC1_2_BASE_IDX                                                                   2
10356 #define mmDIG1_AFMT_ISRC1_3                                                                            0x1996
10357 #define mmDIG1_AFMT_ISRC1_3_BASE_IDX                                                                   2
10358 #define mmDIG1_AFMT_ISRC1_4                                                                            0x1997
10359 #define mmDIG1_AFMT_ISRC1_4_BASE_IDX                                                                   2
10360 #define mmDIG1_AFMT_ISRC2_0                                                                            0x1998
10361 #define mmDIG1_AFMT_ISRC2_0_BASE_IDX                                                                   2
10362 #define mmDIG1_AFMT_ISRC2_1                                                                            0x1999
10363 #define mmDIG1_AFMT_ISRC2_1_BASE_IDX                                                                   2
10364 #define mmDIG1_AFMT_ISRC2_2                                                                            0x199a
10365 #define mmDIG1_AFMT_ISRC2_2_BASE_IDX                                                                   2
10366 #define mmDIG1_AFMT_ISRC2_3                                                                            0x199b
10367 #define mmDIG1_AFMT_ISRC2_3_BASE_IDX                                                                   2
10368 #define mmDIG1_AFMT_AVI_INFO0                                                                          0x199c
10369 #define mmDIG1_AFMT_AVI_INFO0_BASE_IDX                                                                 2
10370 #define mmDIG1_AFMT_AVI_INFO1                                                                          0x199d
10371 #define mmDIG1_AFMT_AVI_INFO1_BASE_IDX                                                                 2
10372 #define mmDIG1_AFMT_AVI_INFO2                                                                          0x199e
10373 #define mmDIG1_AFMT_AVI_INFO2_BASE_IDX                                                                 2
10374 #define mmDIG1_AFMT_AVI_INFO3                                                                          0x199f
10375 #define mmDIG1_AFMT_AVI_INFO3_BASE_IDX                                                                 2
10376 #define mmDIG1_AFMT_MPEG_INFO0                                                                         0x19a0
10377 #define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX                                                                2
10378 #define mmDIG1_AFMT_MPEG_INFO1                                                                         0x19a1
10379 #define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX                                                                2
10380 #define mmDIG1_AFMT_GENERIC_HDR                                                                        0x19a2
10381 #define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX                                                               2
10382 #define mmDIG1_AFMT_GENERIC_0                                                                          0x19a3
10383 #define mmDIG1_AFMT_GENERIC_0_BASE_IDX                                                                 2
10384 #define mmDIG1_AFMT_GENERIC_1                                                                          0x19a4
10385 #define mmDIG1_AFMT_GENERIC_1_BASE_IDX                                                                 2
10386 #define mmDIG1_AFMT_GENERIC_2                                                                          0x19a5
10387 #define mmDIG1_AFMT_GENERIC_2_BASE_IDX                                                                 2
10388 #define mmDIG1_AFMT_GENERIC_3                                                                          0x19a6
10389 #define mmDIG1_AFMT_GENERIC_3_BASE_IDX                                                                 2
10390 #define mmDIG1_AFMT_GENERIC_4                                                                          0x19a7
10391 #define mmDIG1_AFMT_GENERIC_4_BASE_IDX                                                                 2
10392 #define mmDIG1_AFMT_GENERIC_5                                                                          0x19a8
10393 #define mmDIG1_AFMT_GENERIC_5_BASE_IDX                                                                 2
10394 #define mmDIG1_AFMT_GENERIC_6                                                                          0x19a9
10395 #define mmDIG1_AFMT_GENERIC_6_BASE_IDX                                                                 2
10396 #define mmDIG1_AFMT_GENERIC_7                                                                          0x19aa
10397 #define mmDIG1_AFMT_GENERIC_7_BASE_IDX                                                                 2
10398 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x19ab
10399 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10400 #define mmDIG1_HDMI_ACR_32_0                                                                           0x19ac
10401 #define mmDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
10402 #define mmDIG1_HDMI_ACR_32_1                                                                           0x19ad
10403 #define mmDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
10404 #define mmDIG1_HDMI_ACR_44_0                                                                           0x19ae
10405 #define mmDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
10406 #define mmDIG1_HDMI_ACR_44_1                                                                           0x19af
10407 #define mmDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
10408 #define mmDIG1_HDMI_ACR_48_0                                                                           0x19b0
10409 #define mmDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
10410 #define mmDIG1_HDMI_ACR_48_1                                                                           0x19b1
10411 #define mmDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
10412 #define mmDIG1_HDMI_ACR_STATUS_0                                                                       0x19b2
10413 #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10414 #define mmDIG1_HDMI_ACR_STATUS_1                                                                       0x19b3
10415 #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10416 #define mmDIG1_AFMT_AUDIO_INFO0                                                                        0x19b4
10417 #define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
10418 #define mmDIG1_AFMT_AUDIO_INFO1                                                                        0x19b5
10419 #define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
10420 #define mmDIG1_AFMT_60958_0                                                                            0x19b6
10421 #define mmDIG1_AFMT_60958_0_BASE_IDX                                                                   2
10422 #define mmDIG1_AFMT_60958_1                                                                            0x19b7
10423 #define mmDIG1_AFMT_60958_1_BASE_IDX                                                                   2
10424 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL                                                                  0x19b8
10425 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
10426 #define mmDIG1_AFMT_RAMP_CONTROL0                                                                      0x19b9
10427 #define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
10428 #define mmDIG1_AFMT_RAMP_CONTROL1                                                                      0x19ba
10429 #define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
10430 #define mmDIG1_AFMT_RAMP_CONTROL2                                                                      0x19bb
10431 #define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
10432 #define mmDIG1_AFMT_RAMP_CONTROL3                                                                      0x19bc
10433 #define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
10434 #define mmDIG1_AFMT_60958_2                                                                            0x19bd
10435 #define mmDIG1_AFMT_60958_2_BASE_IDX                                                                   2
10436 #define mmDIG1_AFMT_AUDIO_CRC_RESULT                                                                   0x19be
10437 #define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
10438 #define mmDIG1_AFMT_STATUS                                                                             0x19bf
10439 #define mmDIG1_AFMT_STATUS_BASE_IDX                                                                    2
10440 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                                               0x19c0
10441 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10442 #define mmDIG1_AFMT_VBI_PACKET_CONTROL                                                                 0x19c1
10443 #define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10444 #define mmDIG1_AFMT_INFOFRAME_CONTROL0                                                                 0x19c2
10445 #define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10446 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL                                                                  0x19c3
10447 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
10448 #define mmDIG1_DIG_BE_CNTL                                                                             0x19c5
10449 #define mmDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
10450 #define mmDIG1_DIG_BE_EN_CNTL                                                                          0x19c6
10451 #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
10452 #define mmDIG1_TMDS_CNTL                                                                               0x19e9
10453 #define mmDIG1_TMDS_CNTL_BASE_IDX                                                                      2
10454 #define mmDIG1_TMDS_CONTROL_CHAR                                                                       0x19ea
10455 #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
10456 #define mmDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x19eb
10457 #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
10458 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x19ec
10459 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
10460 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x19ed
10461 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
10462 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x19ee
10463 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
10464 #define mmDIG1_TMDS_CTL_BITS                                                                           0x19f0
10465 #define mmDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
10466 #define mmDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x19f1
10467 #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
10468 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x19f3
10469 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
10470 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x19f4
10471 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
10472 #define mmDIG1_DIG_VERSION                                                                             0x19f6
10473 #define mmDIG1_DIG_VERSION_BASE_IDX                                                                    2
10474 #define mmDIG1_DIG_LANE_ENABLE                                                                         0x19f7
10475 #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX                                                                2
10476 #define mmDIG1_AFMT_CNTL                                                                               0x19fc
10477 #define mmDIG1_AFMT_CNTL_BASE_IDX                                                                      2
10478 
10479 
10480 // addressBlock: dce_dc_dp1_dispdec
10481 // base address: 0x400
10482 #define mmDP1_DP_LINK_CNTL                                                                             0x1a1e
10483 #define mmDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
10484 #define mmDP1_DP_PIXEL_FORMAT                                                                          0x1a1f
10485 #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
10486 #define mmDP1_DP_MSA_COLORIMETRY                                                                       0x1a20
10487 #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
10488 #define mmDP1_DP_CONFIG                                                                                0x1a21
10489 #define mmDP1_DP_CONFIG_BASE_IDX                                                                       2
10490 #define mmDP1_DP_VID_STREAM_CNTL                                                                       0x1a22
10491 #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
10492 #define mmDP1_DP_STEER_FIFO                                                                            0x1a23
10493 #define mmDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
10494 #define mmDP1_DP_MSA_MISC                                                                              0x1a24
10495 #define mmDP1_DP_MSA_MISC_BASE_IDX                                                                     2
10496 #define mmDP1_DP_VID_TIMING                                                                            0x1a26
10497 #define mmDP1_DP_VID_TIMING_BASE_IDX                                                                   2
10498 #define mmDP1_DP_VID_N                                                                                 0x1a27
10499 #define mmDP1_DP_VID_N_BASE_IDX                                                                        2
10500 #define mmDP1_DP_VID_M                                                                                 0x1a28
10501 #define mmDP1_DP_VID_M_BASE_IDX                                                                        2
10502 #define mmDP1_DP_LINK_FRAMING_CNTL                                                                     0x1a29
10503 #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
10504 #define mmDP1_DP_HBR2_EYE_PATTERN                                                                      0x1a2a
10505 #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
10506 #define mmDP1_DP_VID_MSA_VBID                                                                          0x1a2b
10507 #define mmDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
10508 #define mmDP1_DP_VID_INTERRUPT_CNTL                                                                    0x1a2c
10509 #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
10510 #define mmDP1_DP_DPHY_CNTL                                                                             0x1a2d
10511 #define mmDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
10512 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x1a2e
10513 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
10514 #define mmDP1_DP_DPHY_SYM0                                                                             0x1a2f
10515 #define mmDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
10516 #define mmDP1_DP_DPHY_SYM1                                                                             0x1a30
10517 #define mmDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
10518 #define mmDP1_DP_DPHY_SYM2                                                                             0x1a31
10519 #define mmDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
10520 #define mmDP1_DP_DPHY_8B10B_CNTL                                                                       0x1a32
10521 #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
10522 #define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x1a33
10523 #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
10524 #define mmDP1_DP_DPHY_SCRAM_CNTL                                                                       0x1a34
10525 #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
10526 #define mmDP1_DP_DPHY_CRC_EN                                                                           0x1a35
10527 #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
10528 #define mmDP1_DP_DPHY_CRC_CNTL                                                                         0x1a36
10529 #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
10530 #define mmDP1_DP_DPHY_CRC_RESULT                                                                       0x1a37
10531 #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
10532 #define mmDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x1a38
10533 #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
10534 #define mmDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x1a39
10535 #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
10536 #define mmDP1_DP_DPHY_FAST_TRAINING                                                                    0x1a3a
10537 #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
10538 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x1a3b
10539 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
10540 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1                                                                0x1a3c
10541 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX                                                       2
10542 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2                                                                0x1a3d
10543 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX                                                       2
10544 #define mmDP1_DP_SEC_CNTL                                                                              0x1a41
10545 #define mmDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
10546 #define mmDP1_DP_SEC_CNTL1                                                                             0x1a42
10547 #define mmDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
10548 #define mmDP1_DP_SEC_FRAMING1                                                                          0x1a43
10549 #define mmDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
10550 #define mmDP1_DP_SEC_FRAMING2                                                                          0x1a44
10551 #define mmDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
10552 #define mmDP1_DP_SEC_FRAMING3                                                                          0x1a45
10553 #define mmDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
10554 #define mmDP1_DP_SEC_FRAMING4                                                                          0x1a46
10555 #define mmDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
10556 #define mmDP1_DP_SEC_AUD_N                                                                             0x1a47
10557 #define mmDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
10558 #define mmDP1_DP_SEC_AUD_N_READBACK                                                                    0x1a48
10559 #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
10560 #define mmDP1_DP_SEC_AUD_M                                                                             0x1a49
10561 #define mmDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
10562 #define mmDP1_DP_SEC_AUD_M_READBACK                                                                    0x1a4a
10563 #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
10564 #define mmDP1_DP_SEC_TIMESTAMP                                                                         0x1a4b
10565 #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
10566 #define mmDP1_DP_SEC_PACKET_CNTL                                                                       0x1a4c
10567 #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
10568 #define mmDP1_DP_MSE_RATE_CNTL                                                                         0x1a4d
10569 #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
10570 #define mmDP1_DP_MSE_RATE_UPDATE                                                                       0x1a4f
10571 #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
10572 #define mmDP1_DP_MSE_SAT0                                                                              0x1a50
10573 #define mmDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
10574 #define mmDP1_DP_MSE_SAT1                                                                              0x1a51
10575 #define mmDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
10576 #define mmDP1_DP_MSE_SAT2                                                                              0x1a52
10577 #define mmDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
10578 #define mmDP1_DP_MSE_SAT_UPDATE                                                                        0x1a53
10579 #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
10580 #define mmDP1_DP_MSE_LINK_TIMING                                                                       0x1a54
10581 #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
10582 #define mmDP1_DP_MSE_MISC_CNTL                                                                         0x1a55
10583 #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
10584 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x1a5a
10585 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
10586 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x1a5b
10587 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
10588 #define mmDP1_DP_MSE_SAT0_STATUS                                                                       0x1a5d
10589 #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
10590 #define mmDP1_DP_MSE_SAT1_STATUS                                                                       0x1a5e
10591 #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
10592 #define mmDP1_DP_MSE_SAT2_STATUS                                                                       0x1a5f
10593 #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
10594 
10595 
10596 // addressBlock: dce_dc_dig2_dispdec
10597 // base address: 0x800
10598 #define mmDIG2_DIG_FE_CNTL                                                                             0x1a7e
10599 #define mmDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
10600 #define mmDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x1a7f
10601 #define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10602 #define mmDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x1a80
10603 #define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10604 #define mmDIG2_DIG_CLOCK_PATTERN                                                                       0x1a81
10605 #define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10606 #define mmDIG2_DIG_TEST_PATTERN                                                                        0x1a82
10607 #define mmDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
10608 #define mmDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x1a83
10609 #define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10610 #define mmDIG2_DIG_FIFO_STATUS                                                                         0x1a84
10611 #define mmDIG2_DIG_FIFO_STATUS_BASE_IDX                                                                2
10612 #define mmDIG2_HDMI_CONTROL                                                                            0x1a87
10613 #define mmDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
10614 #define mmDIG2_HDMI_STATUS                                                                             0x1a88
10615 #define mmDIG2_HDMI_STATUS_BASE_IDX                                                                    2
10616 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x1a89
10617 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10618 #define mmDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x1a8a
10619 #define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10620 #define mmDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x1a8b
10621 #define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10622 #define mmDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x1a8c
10623 #define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10624 #define mmDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x1a8d
10625 #define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10626 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x1a8e
10627 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10628 #define mmDIG2_AFMT_INTERRUPT_STATUS                                                                   0x1a8f
10629 #define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
10630 #define mmDIG2_HDMI_GC                                                                                 0x1a91
10631 #define mmDIG2_HDMI_GC_BASE_IDX                                                                        2
10632 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                                              0x1a92
10633 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
10634 #define mmDIG2_AFMT_ISRC1_0                                                                            0x1a93
10635 #define mmDIG2_AFMT_ISRC1_0_BASE_IDX                                                                   2
10636 #define mmDIG2_AFMT_ISRC1_1                                                                            0x1a94
10637 #define mmDIG2_AFMT_ISRC1_1_BASE_IDX                                                                   2
10638 #define mmDIG2_AFMT_ISRC1_2                                                                            0x1a95
10639 #define mmDIG2_AFMT_ISRC1_2_BASE_IDX                                                                   2
10640 #define mmDIG2_AFMT_ISRC1_3                                                                            0x1a96
10641 #define mmDIG2_AFMT_ISRC1_3_BASE_IDX                                                                   2
10642 #define mmDIG2_AFMT_ISRC1_4                                                                            0x1a97
10643 #define mmDIG2_AFMT_ISRC1_4_BASE_IDX                                                                   2
10644 #define mmDIG2_AFMT_ISRC2_0                                                                            0x1a98
10645 #define mmDIG2_AFMT_ISRC2_0_BASE_IDX                                                                   2
10646 #define mmDIG2_AFMT_ISRC2_1                                                                            0x1a99
10647 #define mmDIG2_AFMT_ISRC2_1_BASE_IDX                                                                   2
10648 #define mmDIG2_AFMT_ISRC2_2                                                                            0x1a9a
10649 #define mmDIG2_AFMT_ISRC2_2_BASE_IDX                                                                   2
10650 #define mmDIG2_AFMT_ISRC2_3                                                                            0x1a9b
10651 #define mmDIG2_AFMT_ISRC2_3_BASE_IDX                                                                   2
10652 #define mmDIG2_AFMT_AVI_INFO0                                                                          0x1a9c
10653 #define mmDIG2_AFMT_AVI_INFO0_BASE_IDX                                                                 2
10654 #define mmDIG2_AFMT_AVI_INFO1                                                                          0x1a9d
10655 #define mmDIG2_AFMT_AVI_INFO1_BASE_IDX                                                                 2
10656 #define mmDIG2_AFMT_AVI_INFO2                                                                          0x1a9e
10657 #define mmDIG2_AFMT_AVI_INFO2_BASE_IDX                                                                 2
10658 #define mmDIG2_AFMT_AVI_INFO3                                                                          0x1a9f
10659 #define mmDIG2_AFMT_AVI_INFO3_BASE_IDX                                                                 2
10660 #define mmDIG2_AFMT_MPEG_INFO0                                                                         0x1aa0
10661 #define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX                                                                2
10662 #define mmDIG2_AFMT_MPEG_INFO1                                                                         0x1aa1
10663 #define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX                                                                2
10664 #define mmDIG2_AFMT_GENERIC_HDR                                                                        0x1aa2
10665 #define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX                                                               2
10666 #define mmDIG2_AFMT_GENERIC_0                                                                          0x1aa3
10667 #define mmDIG2_AFMT_GENERIC_0_BASE_IDX                                                                 2
10668 #define mmDIG2_AFMT_GENERIC_1                                                                          0x1aa4
10669 #define mmDIG2_AFMT_GENERIC_1_BASE_IDX                                                                 2
10670 #define mmDIG2_AFMT_GENERIC_2                                                                          0x1aa5
10671 #define mmDIG2_AFMT_GENERIC_2_BASE_IDX                                                                 2
10672 #define mmDIG2_AFMT_GENERIC_3                                                                          0x1aa6
10673 #define mmDIG2_AFMT_GENERIC_3_BASE_IDX                                                                 2
10674 #define mmDIG2_AFMT_GENERIC_4                                                                          0x1aa7
10675 #define mmDIG2_AFMT_GENERIC_4_BASE_IDX                                                                 2
10676 #define mmDIG2_AFMT_GENERIC_5                                                                          0x1aa8
10677 #define mmDIG2_AFMT_GENERIC_5_BASE_IDX                                                                 2
10678 #define mmDIG2_AFMT_GENERIC_6                                                                          0x1aa9
10679 #define mmDIG2_AFMT_GENERIC_6_BASE_IDX                                                                 2
10680 #define mmDIG2_AFMT_GENERIC_7                                                                          0x1aaa
10681 #define mmDIG2_AFMT_GENERIC_7_BASE_IDX                                                                 2
10682 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x1aab
10683 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10684 #define mmDIG2_HDMI_ACR_32_0                                                                           0x1aac
10685 #define mmDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
10686 #define mmDIG2_HDMI_ACR_32_1                                                                           0x1aad
10687 #define mmDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
10688 #define mmDIG2_HDMI_ACR_44_0                                                                           0x1aae
10689 #define mmDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
10690 #define mmDIG2_HDMI_ACR_44_1                                                                           0x1aaf
10691 #define mmDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
10692 #define mmDIG2_HDMI_ACR_48_0                                                                           0x1ab0
10693 #define mmDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
10694 #define mmDIG2_HDMI_ACR_48_1                                                                           0x1ab1
10695 #define mmDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
10696 #define mmDIG2_HDMI_ACR_STATUS_0                                                                       0x1ab2
10697 #define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10698 #define mmDIG2_HDMI_ACR_STATUS_1                                                                       0x1ab3
10699 #define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10700 #define mmDIG2_AFMT_AUDIO_INFO0                                                                        0x1ab4
10701 #define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
10702 #define mmDIG2_AFMT_AUDIO_INFO1                                                                        0x1ab5
10703 #define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
10704 #define mmDIG2_AFMT_60958_0                                                                            0x1ab6
10705 #define mmDIG2_AFMT_60958_0_BASE_IDX                                                                   2
10706 #define mmDIG2_AFMT_60958_1                                                                            0x1ab7
10707 #define mmDIG2_AFMT_60958_1_BASE_IDX                                                                   2
10708 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL                                                                  0x1ab8
10709 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
10710 #define mmDIG2_AFMT_RAMP_CONTROL0                                                                      0x1ab9
10711 #define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
10712 #define mmDIG2_AFMT_RAMP_CONTROL1                                                                      0x1aba
10713 #define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
10714 #define mmDIG2_AFMT_RAMP_CONTROL2                                                                      0x1abb
10715 #define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
10716 #define mmDIG2_AFMT_RAMP_CONTROL3                                                                      0x1abc
10717 #define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
10718 #define mmDIG2_AFMT_60958_2                                                                            0x1abd
10719 #define mmDIG2_AFMT_60958_2_BASE_IDX                                                                   2
10720 #define mmDIG2_AFMT_AUDIO_CRC_RESULT                                                                   0x1abe
10721 #define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
10722 #define mmDIG2_AFMT_STATUS                                                                             0x1abf
10723 #define mmDIG2_AFMT_STATUS_BASE_IDX                                                                    2
10724 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                                               0x1ac0
10725 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10726 #define mmDIG2_AFMT_VBI_PACKET_CONTROL                                                                 0x1ac1
10727 #define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10728 #define mmDIG2_AFMT_INFOFRAME_CONTROL0                                                                 0x1ac2
10729 #define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10730 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL                                                                  0x1ac3
10731 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
10732 #define mmDIG2_DIG_BE_CNTL                                                                             0x1ac5
10733 #define mmDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
10734 #define mmDIG2_DIG_BE_EN_CNTL                                                                          0x1ac6
10735 #define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
10736 #define mmDIG2_TMDS_CNTL                                                                               0x1ae9
10737 #define mmDIG2_TMDS_CNTL_BASE_IDX                                                                      2
10738 #define mmDIG2_TMDS_CONTROL_CHAR                                                                       0x1aea
10739 #define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
10740 #define mmDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x1aeb
10741 #define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
10742 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x1aec
10743 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
10744 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x1aed
10745 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
10746 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x1aee
10747 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
10748 #define mmDIG2_TMDS_CTL_BITS                                                                           0x1af0
10749 #define mmDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
10750 #define mmDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x1af1
10751 #define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
10752 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x1af3
10753 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
10754 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x1af4
10755 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
10756 #define mmDIG2_DIG_VERSION                                                                             0x1af6
10757 #define mmDIG2_DIG_VERSION_BASE_IDX                                                                    2
10758 #define mmDIG2_DIG_LANE_ENABLE                                                                         0x1af7
10759 #define mmDIG2_DIG_LANE_ENABLE_BASE_IDX                                                                2
10760 #define mmDIG2_AFMT_CNTL                                                                               0x1afc
10761 #define mmDIG2_AFMT_CNTL_BASE_IDX                                                                      2
10762 
10763 
10764 // addressBlock: dce_dc_dp2_dispdec
10765 // base address: 0x800
10766 #define mmDP2_DP_LINK_CNTL                                                                             0x1b1e
10767 #define mmDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
10768 #define mmDP2_DP_PIXEL_FORMAT                                                                          0x1b1f
10769 #define mmDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
10770 #define mmDP2_DP_MSA_COLORIMETRY                                                                       0x1b20
10771 #define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
10772 #define mmDP2_DP_CONFIG                                                                                0x1b21
10773 #define mmDP2_DP_CONFIG_BASE_IDX                                                                       2
10774 #define mmDP2_DP_VID_STREAM_CNTL                                                                       0x1b22
10775 #define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
10776 #define mmDP2_DP_STEER_FIFO                                                                            0x1b23
10777 #define mmDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
10778 #define mmDP2_DP_MSA_MISC                                                                              0x1b24
10779 #define mmDP2_DP_MSA_MISC_BASE_IDX                                                                     2
10780 #define mmDP2_DP_VID_TIMING                                                                            0x1b26
10781 #define mmDP2_DP_VID_TIMING_BASE_IDX                                                                   2
10782 #define mmDP2_DP_VID_N                                                                                 0x1b27
10783 #define mmDP2_DP_VID_N_BASE_IDX                                                                        2
10784 #define mmDP2_DP_VID_M                                                                                 0x1b28
10785 #define mmDP2_DP_VID_M_BASE_IDX                                                                        2
10786 #define mmDP2_DP_LINK_FRAMING_CNTL                                                                     0x1b29
10787 #define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
10788 #define mmDP2_DP_HBR2_EYE_PATTERN                                                                      0x1b2a
10789 #define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
10790 #define mmDP2_DP_VID_MSA_VBID                                                                          0x1b2b
10791 #define mmDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
10792 #define mmDP2_DP_VID_INTERRUPT_CNTL                                                                    0x1b2c
10793 #define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
10794 #define mmDP2_DP_DPHY_CNTL                                                                             0x1b2d
10795 #define mmDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
10796 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x1b2e
10797 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
10798 #define mmDP2_DP_DPHY_SYM0                                                                             0x1b2f
10799 #define mmDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
10800 #define mmDP2_DP_DPHY_SYM1                                                                             0x1b30
10801 #define mmDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
10802 #define mmDP2_DP_DPHY_SYM2                                                                             0x1b31
10803 #define mmDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
10804 #define mmDP2_DP_DPHY_8B10B_CNTL                                                                       0x1b32
10805 #define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
10806 #define mmDP2_DP_DPHY_PRBS_CNTL                                                                        0x1b33
10807 #define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
10808 #define mmDP2_DP_DPHY_SCRAM_CNTL                                                                       0x1b34
10809 #define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
10810 #define mmDP2_DP_DPHY_CRC_EN                                                                           0x1b35
10811 #define mmDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
10812 #define mmDP2_DP_DPHY_CRC_CNTL                                                                         0x1b36
10813 #define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
10814 #define mmDP2_DP_DPHY_CRC_RESULT                                                                       0x1b37
10815 #define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
10816 #define mmDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x1b38
10817 #define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
10818 #define mmDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x1b39
10819 #define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
10820 #define mmDP2_DP_DPHY_FAST_TRAINING                                                                    0x1b3a
10821 #define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
10822 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x1b3b
10823 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
10824 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1                                                                0x1b3c
10825 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX                                                       2
10826 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2                                                                0x1b3d
10827 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX                                                       2
10828 #define mmDP2_DP_SEC_CNTL                                                                              0x1b41
10829 #define mmDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
10830 #define mmDP2_DP_SEC_CNTL1                                                                             0x1b42
10831 #define mmDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
10832 #define mmDP2_DP_SEC_FRAMING1                                                                          0x1b43
10833 #define mmDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
10834 #define mmDP2_DP_SEC_FRAMING2                                                                          0x1b44
10835 #define mmDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
10836 #define mmDP2_DP_SEC_FRAMING3                                                                          0x1b45
10837 #define mmDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
10838 #define mmDP2_DP_SEC_FRAMING4                                                                          0x1b46
10839 #define mmDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
10840 #define mmDP2_DP_SEC_AUD_N                                                                             0x1b47
10841 #define mmDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
10842 #define mmDP2_DP_SEC_AUD_N_READBACK                                                                    0x1b48
10843 #define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
10844 #define mmDP2_DP_SEC_AUD_M                                                                             0x1b49
10845 #define mmDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
10846 #define mmDP2_DP_SEC_AUD_M_READBACK                                                                    0x1b4a
10847 #define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
10848 #define mmDP2_DP_SEC_TIMESTAMP                                                                         0x1b4b
10849 #define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
10850 #define mmDP2_DP_SEC_PACKET_CNTL                                                                       0x1b4c
10851 #define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
10852 #define mmDP2_DP_MSE_RATE_CNTL                                                                         0x1b4d
10853 #define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
10854 #define mmDP2_DP_MSE_RATE_UPDATE                                                                       0x1b4f
10855 #define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
10856 #define mmDP2_DP_MSE_SAT0                                                                              0x1b50
10857 #define mmDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
10858 #define mmDP2_DP_MSE_SAT1                                                                              0x1b51
10859 #define mmDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
10860 #define mmDP2_DP_MSE_SAT2                                                                              0x1b52
10861 #define mmDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
10862 #define mmDP2_DP_MSE_SAT_UPDATE                                                                        0x1b53
10863 #define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
10864 #define mmDP2_DP_MSE_LINK_TIMING                                                                       0x1b54
10865 #define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
10866 #define mmDP2_DP_MSE_MISC_CNTL                                                                         0x1b55
10867 #define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
10868 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x1b5a
10869 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
10870 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x1b5b
10871 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
10872 #define mmDP2_DP_MSE_SAT0_STATUS                                                                       0x1b5d
10873 #define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
10874 #define mmDP2_DP_MSE_SAT1_STATUS                                                                       0x1b5e
10875 #define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
10876 #define mmDP2_DP_MSE_SAT2_STATUS                                                                       0x1b5f
10877 #define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
10878 
10879 
10880 // addressBlock: dce_dc_dig3_dispdec
10881 // base address: 0xc00
10882 #define mmDIG3_DIG_FE_CNTL                                                                             0x1b7e
10883 #define mmDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
10884 #define mmDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x1b7f
10885 #define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
10886 #define mmDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x1b80
10887 #define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
10888 #define mmDIG3_DIG_CLOCK_PATTERN                                                                       0x1b81
10889 #define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
10890 #define mmDIG3_DIG_TEST_PATTERN                                                                        0x1b82
10891 #define mmDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
10892 #define mmDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x1b83
10893 #define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
10894 #define mmDIG3_DIG_FIFO_STATUS                                                                         0x1b84
10895 #define mmDIG3_DIG_FIFO_STATUS_BASE_IDX                                                                2
10896 #define mmDIG3_HDMI_CONTROL                                                                            0x1b87
10897 #define mmDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
10898 #define mmDIG3_HDMI_STATUS                                                                             0x1b88
10899 #define mmDIG3_HDMI_STATUS_BASE_IDX                                                                    2
10900 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x1b89
10901 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
10902 #define mmDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x1b8a
10903 #define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
10904 #define mmDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x1b8b
10905 #define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
10906 #define mmDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x1b8c
10907 #define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
10908 #define mmDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x1b8d
10909 #define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
10910 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x1b8e
10911 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
10912 #define mmDIG3_AFMT_INTERRUPT_STATUS                                                                   0x1b8f
10913 #define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
10914 #define mmDIG3_HDMI_GC                                                                                 0x1b91
10915 #define mmDIG3_HDMI_GC_BASE_IDX                                                                        2
10916 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                                              0x1b92
10917 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
10918 #define mmDIG3_AFMT_ISRC1_0                                                                            0x1b93
10919 #define mmDIG3_AFMT_ISRC1_0_BASE_IDX                                                                   2
10920 #define mmDIG3_AFMT_ISRC1_1                                                                            0x1b94
10921 #define mmDIG3_AFMT_ISRC1_1_BASE_IDX                                                                   2
10922 #define mmDIG3_AFMT_ISRC1_2                                                                            0x1b95
10923 #define mmDIG3_AFMT_ISRC1_2_BASE_IDX                                                                   2
10924 #define mmDIG3_AFMT_ISRC1_3                                                                            0x1b96
10925 #define mmDIG3_AFMT_ISRC1_3_BASE_IDX                                                                   2
10926 #define mmDIG3_AFMT_ISRC1_4                                                                            0x1b97
10927 #define mmDIG3_AFMT_ISRC1_4_BASE_IDX                                                                   2
10928 #define mmDIG3_AFMT_ISRC2_0                                                                            0x1b98
10929 #define mmDIG3_AFMT_ISRC2_0_BASE_IDX                                                                   2
10930 #define mmDIG3_AFMT_ISRC2_1                                                                            0x1b99
10931 #define mmDIG3_AFMT_ISRC2_1_BASE_IDX                                                                   2
10932 #define mmDIG3_AFMT_ISRC2_2                                                                            0x1b9a
10933 #define mmDIG3_AFMT_ISRC2_2_BASE_IDX                                                                   2
10934 #define mmDIG3_AFMT_ISRC2_3                                                                            0x1b9b
10935 #define mmDIG3_AFMT_ISRC2_3_BASE_IDX                                                                   2
10936 #define mmDIG3_AFMT_AVI_INFO0                                                                          0x1b9c
10937 #define mmDIG3_AFMT_AVI_INFO0_BASE_IDX                                                                 2
10938 #define mmDIG3_AFMT_AVI_INFO1                                                                          0x1b9d
10939 #define mmDIG3_AFMT_AVI_INFO1_BASE_IDX                                                                 2
10940 #define mmDIG3_AFMT_AVI_INFO2                                                                          0x1b9e
10941 #define mmDIG3_AFMT_AVI_INFO2_BASE_IDX                                                                 2
10942 #define mmDIG3_AFMT_AVI_INFO3                                                                          0x1b9f
10943 #define mmDIG3_AFMT_AVI_INFO3_BASE_IDX                                                                 2
10944 #define mmDIG3_AFMT_MPEG_INFO0                                                                         0x1ba0
10945 #define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX                                                                2
10946 #define mmDIG3_AFMT_MPEG_INFO1                                                                         0x1ba1
10947 #define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX                                                                2
10948 #define mmDIG3_AFMT_GENERIC_HDR                                                                        0x1ba2
10949 #define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX                                                               2
10950 #define mmDIG3_AFMT_GENERIC_0                                                                          0x1ba3
10951 #define mmDIG3_AFMT_GENERIC_0_BASE_IDX                                                                 2
10952 #define mmDIG3_AFMT_GENERIC_1                                                                          0x1ba4
10953 #define mmDIG3_AFMT_GENERIC_1_BASE_IDX                                                                 2
10954 #define mmDIG3_AFMT_GENERIC_2                                                                          0x1ba5
10955 #define mmDIG3_AFMT_GENERIC_2_BASE_IDX                                                                 2
10956 #define mmDIG3_AFMT_GENERIC_3                                                                          0x1ba6
10957 #define mmDIG3_AFMT_GENERIC_3_BASE_IDX                                                                 2
10958 #define mmDIG3_AFMT_GENERIC_4                                                                          0x1ba7
10959 #define mmDIG3_AFMT_GENERIC_4_BASE_IDX                                                                 2
10960 #define mmDIG3_AFMT_GENERIC_5                                                                          0x1ba8
10961 #define mmDIG3_AFMT_GENERIC_5_BASE_IDX                                                                 2
10962 #define mmDIG3_AFMT_GENERIC_6                                                                          0x1ba9
10963 #define mmDIG3_AFMT_GENERIC_6_BASE_IDX                                                                 2
10964 #define mmDIG3_AFMT_GENERIC_7                                                                          0x1baa
10965 #define mmDIG3_AFMT_GENERIC_7_BASE_IDX                                                                 2
10966 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x1bab
10967 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
10968 #define mmDIG3_HDMI_ACR_32_0                                                                           0x1bac
10969 #define mmDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
10970 #define mmDIG3_HDMI_ACR_32_1                                                                           0x1bad
10971 #define mmDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
10972 #define mmDIG3_HDMI_ACR_44_0                                                                           0x1bae
10973 #define mmDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
10974 #define mmDIG3_HDMI_ACR_44_1                                                                           0x1baf
10975 #define mmDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
10976 #define mmDIG3_HDMI_ACR_48_0                                                                           0x1bb0
10977 #define mmDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
10978 #define mmDIG3_HDMI_ACR_48_1                                                                           0x1bb1
10979 #define mmDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
10980 #define mmDIG3_HDMI_ACR_STATUS_0                                                                       0x1bb2
10981 #define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
10982 #define mmDIG3_HDMI_ACR_STATUS_1                                                                       0x1bb3
10983 #define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
10984 #define mmDIG3_AFMT_AUDIO_INFO0                                                                        0x1bb4
10985 #define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
10986 #define mmDIG3_AFMT_AUDIO_INFO1                                                                        0x1bb5
10987 #define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
10988 #define mmDIG3_AFMT_60958_0                                                                            0x1bb6
10989 #define mmDIG3_AFMT_60958_0_BASE_IDX                                                                   2
10990 #define mmDIG3_AFMT_60958_1                                                                            0x1bb7
10991 #define mmDIG3_AFMT_60958_1_BASE_IDX                                                                   2
10992 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL                                                                  0x1bb8
10993 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
10994 #define mmDIG3_AFMT_RAMP_CONTROL0                                                                      0x1bb9
10995 #define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
10996 #define mmDIG3_AFMT_RAMP_CONTROL1                                                                      0x1bba
10997 #define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
10998 #define mmDIG3_AFMT_RAMP_CONTROL2                                                                      0x1bbb
10999 #define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
11000 #define mmDIG3_AFMT_RAMP_CONTROL3                                                                      0x1bbc
11001 #define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
11002 #define mmDIG3_AFMT_60958_2                                                                            0x1bbd
11003 #define mmDIG3_AFMT_60958_2_BASE_IDX                                                                   2
11004 #define mmDIG3_AFMT_AUDIO_CRC_RESULT                                                                   0x1bbe
11005 #define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
11006 #define mmDIG3_AFMT_STATUS                                                                             0x1bbf
11007 #define mmDIG3_AFMT_STATUS_BASE_IDX                                                                    2
11008 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                                               0x1bc0
11009 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11010 #define mmDIG3_AFMT_VBI_PACKET_CONTROL                                                                 0x1bc1
11011 #define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11012 #define mmDIG3_AFMT_INFOFRAME_CONTROL0                                                                 0x1bc2
11013 #define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11014 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL                                                                  0x1bc3
11015 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
11016 #define mmDIG3_DIG_BE_CNTL                                                                             0x1bc5
11017 #define mmDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
11018 #define mmDIG3_DIG_BE_EN_CNTL                                                                          0x1bc6
11019 #define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
11020 #define mmDIG3_TMDS_CNTL                                                                               0x1be9
11021 #define mmDIG3_TMDS_CNTL_BASE_IDX                                                                      2
11022 #define mmDIG3_TMDS_CONTROL_CHAR                                                                       0x1bea
11023 #define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
11024 #define mmDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x1beb
11025 #define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
11026 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x1bec
11027 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
11028 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x1bed
11029 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
11030 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x1bee
11031 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
11032 #define mmDIG3_TMDS_CTL_BITS                                                                           0x1bf0
11033 #define mmDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
11034 #define mmDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x1bf1
11035 #define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
11036 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x1bf3
11037 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
11038 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x1bf4
11039 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
11040 #define mmDIG3_DIG_VERSION                                                                             0x1bf6
11041 #define mmDIG3_DIG_VERSION_BASE_IDX                                                                    2
11042 #define mmDIG3_DIG_LANE_ENABLE                                                                         0x1bf7
11043 #define mmDIG3_DIG_LANE_ENABLE_BASE_IDX                                                                2
11044 #define mmDIG3_AFMT_CNTL                                                                               0x1bfc
11045 #define mmDIG3_AFMT_CNTL_BASE_IDX                                                                      2
11046 
11047 
11048 // addressBlock: dce_dc_dp3_dispdec
11049 // base address: 0xc00
11050 #define mmDP3_DP_LINK_CNTL                                                                             0x1c1e
11051 #define mmDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
11052 #define mmDP3_DP_PIXEL_FORMAT                                                                          0x1c1f
11053 #define mmDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
11054 #define mmDP3_DP_MSA_COLORIMETRY                                                                       0x1c20
11055 #define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
11056 #define mmDP3_DP_CONFIG                                                                                0x1c21
11057 #define mmDP3_DP_CONFIG_BASE_IDX                                                                       2
11058 #define mmDP3_DP_VID_STREAM_CNTL                                                                       0x1c22
11059 #define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
11060 #define mmDP3_DP_STEER_FIFO                                                                            0x1c23
11061 #define mmDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
11062 #define mmDP3_DP_MSA_MISC                                                                              0x1c24
11063 #define mmDP3_DP_MSA_MISC_BASE_IDX                                                                     2
11064 #define mmDP3_DP_VID_TIMING                                                                            0x1c26
11065 #define mmDP3_DP_VID_TIMING_BASE_IDX                                                                   2
11066 #define mmDP3_DP_VID_N                                                                                 0x1c27
11067 #define mmDP3_DP_VID_N_BASE_IDX                                                                        2
11068 #define mmDP3_DP_VID_M                                                                                 0x1c28
11069 #define mmDP3_DP_VID_M_BASE_IDX                                                                        2
11070 #define mmDP3_DP_LINK_FRAMING_CNTL                                                                     0x1c29
11071 #define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
11072 #define mmDP3_DP_HBR2_EYE_PATTERN                                                                      0x1c2a
11073 #define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
11074 #define mmDP3_DP_VID_MSA_VBID                                                                          0x1c2b
11075 #define mmDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
11076 #define mmDP3_DP_VID_INTERRUPT_CNTL                                                                    0x1c2c
11077 #define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
11078 #define mmDP3_DP_DPHY_CNTL                                                                             0x1c2d
11079 #define mmDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
11080 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x1c2e
11081 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
11082 #define mmDP3_DP_DPHY_SYM0                                                                             0x1c2f
11083 #define mmDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
11084 #define mmDP3_DP_DPHY_SYM1                                                                             0x1c30
11085 #define mmDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
11086 #define mmDP3_DP_DPHY_SYM2                                                                             0x1c31
11087 #define mmDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
11088 #define mmDP3_DP_DPHY_8B10B_CNTL                                                                       0x1c32
11089 #define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
11090 #define mmDP3_DP_DPHY_PRBS_CNTL                                                                        0x1c33
11091 #define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
11092 #define mmDP3_DP_DPHY_SCRAM_CNTL                                                                       0x1c34
11093 #define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
11094 #define mmDP3_DP_DPHY_CRC_EN                                                                           0x1c35
11095 #define mmDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
11096 #define mmDP3_DP_DPHY_CRC_CNTL                                                                         0x1c36
11097 #define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
11098 #define mmDP3_DP_DPHY_CRC_RESULT                                                                       0x1c37
11099 #define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
11100 #define mmDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x1c38
11101 #define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
11102 #define mmDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x1c39
11103 #define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
11104 #define mmDP3_DP_DPHY_FAST_TRAINING                                                                    0x1c3a
11105 #define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
11106 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x1c3b
11107 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
11108 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1                                                                0x1c3c
11109 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX                                                       2
11110 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2                                                                0x1c3d
11111 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX                                                       2
11112 #define mmDP3_DP_SEC_CNTL                                                                              0x1c41
11113 #define mmDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
11114 #define mmDP3_DP_SEC_CNTL1                                                                             0x1c42
11115 #define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
11116 #define mmDP3_DP_SEC_FRAMING1                                                                          0x1c43
11117 #define mmDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
11118 #define mmDP3_DP_SEC_FRAMING2                                                                          0x1c44
11119 #define mmDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
11120 #define mmDP3_DP_SEC_FRAMING3                                                                          0x1c45
11121 #define mmDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
11122 #define mmDP3_DP_SEC_FRAMING4                                                                          0x1c46
11123 #define mmDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
11124 #define mmDP3_DP_SEC_AUD_N                                                                             0x1c47
11125 #define mmDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
11126 #define mmDP3_DP_SEC_AUD_N_READBACK                                                                    0x1c48
11127 #define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
11128 #define mmDP3_DP_SEC_AUD_M                                                                             0x1c49
11129 #define mmDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
11130 #define mmDP3_DP_SEC_AUD_M_READBACK                                                                    0x1c4a
11131 #define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
11132 #define mmDP3_DP_SEC_TIMESTAMP                                                                         0x1c4b
11133 #define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
11134 #define mmDP3_DP_SEC_PACKET_CNTL                                                                       0x1c4c
11135 #define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
11136 #define mmDP3_DP_MSE_RATE_CNTL                                                                         0x1c4d
11137 #define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
11138 #define mmDP3_DP_MSE_RATE_UPDATE                                                                       0x1c4f
11139 #define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
11140 #define mmDP3_DP_MSE_SAT0                                                                              0x1c50
11141 #define mmDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
11142 #define mmDP3_DP_MSE_SAT1                                                                              0x1c51
11143 #define mmDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
11144 #define mmDP3_DP_MSE_SAT2                                                                              0x1c52
11145 #define mmDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
11146 #define mmDP3_DP_MSE_SAT_UPDATE                                                                        0x1c53
11147 #define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
11148 #define mmDP3_DP_MSE_LINK_TIMING                                                                       0x1c54
11149 #define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
11150 #define mmDP3_DP_MSE_MISC_CNTL                                                                         0x1c55
11151 #define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
11152 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x1c5a
11153 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
11154 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x1c5b
11155 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
11156 #define mmDP3_DP_MSE_SAT0_STATUS                                                                       0x1c5d
11157 #define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
11158 #define mmDP3_DP_MSE_SAT1_STATUS                                                                       0x1c5e
11159 #define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
11160 #define mmDP3_DP_MSE_SAT2_STATUS                                                                       0x1c5f
11161 #define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
11162 
11163 
11164 // addressBlock: dce_dc_dig4_dispdec
11165 // base address: 0x1000
11166 #define mmDIG4_DIG_FE_CNTL                                                                             0x1c7e
11167 #define mmDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
11168 #define mmDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x1c7f
11169 #define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
11170 #define mmDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x1c80
11171 #define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
11172 #define mmDIG4_DIG_CLOCK_PATTERN                                                                       0x1c81
11173 #define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
11174 #define mmDIG4_DIG_TEST_PATTERN                                                                        0x1c82
11175 #define mmDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
11176 #define mmDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x1c83
11177 #define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
11178 #define mmDIG4_DIG_FIFO_STATUS                                                                         0x1c84
11179 #define mmDIG4_DIG_FIFO_STATUS_BASE_IDX                                                                2
11180 #define mmDIG4_HDMI_CONTROL                                                                            0x1c87
11181 #define mmDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
11182 #define mmDIG4_HDMI_STATUS                                                                             0x1c88
11183 #define mmDIG4_HDMI_STATUS_BASE_IDX                                                                    2
11184 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x1c89
11185 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11186 #define mmDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x1c8a
11187 #define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
11188 #define mmDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x1c8b
11189 #define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11190 #define mmDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x1c8c
11191 #define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11192 #define mmDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x1c8d
11193 #define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
11194 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x1c8e
11195 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
11196 #define mmDIG4_AFMT_INTERRUPT_STATUS                                                                   0x1c8f
11197 #define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
11198 #define mmDIG4_HDMI_GC                                                                                 0x1c91
11199 #define mmDIG4_HDMI_GC_BASE_IDX                                                                        2
11200 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                                              0x1c92
11201 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
11202 #define mmDIG4_AFMT_ISRC1_0                                                                            0x1c93
11203 #define mmDIG4_AFMT_ISRC1_0_BASE_IDX                                                                   2
11204 #define mmDIG4_AFMT_ISRC1_1                                                                            0x1c94
11205 #define mmDIG4_AFMT_ISRC1_1_BASE_IDX                                                                   2
11206 #define mmDIG4_AFMT_ISRC1_2                                                                            0x1c95
11207 #define mmDIG4_AFMT_ISRC1_2_BASE_IDX                                                                   2
11208 #define mmDIG4_AFMT_ISRC1_3                                                                            0x1c96
11209 #define mmDIG4_AFMT_ISRC1_3_BASE_IDX                                                                   2
11210 #define mmDIG4_AFMT_ISRC1_4                                                                            0x1c97
11211 #define mmDIG4_AFMT_ISRC1_4_BASE_IDX                                                                   2
11212 #define mmDIG4_AFMT_ISRC2_0                                                                            0x1c98
11213 #define mmDIG4_AFMT_ISRC2_0_BASE_IDX                                                                   2
11214 #define mmDIG4_AFMT_ISRC2_1                                                                            0x1c99
11215 #define mmDIG4_AFMT_ISRC2_1_BASE_IDX                                                                   2
11216 #define mmDIG4_AFMT_ISRC2_2                                                                            0x1c9a
11217 #define mmDIG4_AFMT_ISRC2_2_BASE_IDX                                                                   2
11218 #define mmDIG4_AFMT_ISRC2_3                                                                            0x1c9b
11219 #define mmDIG4_AFMT_ISRC2_3_BASE_IDX                                                                   2
11220 #define mmDIG4_AFMT_AVI_INFO0                                                                          0x1c9c
11221 #define mmDIG4_AFMT_AVI_INFO0_BASE_IDX                                                                 2
11222 #define mmDIG4_AFMT_AVI_INFO1                                                                          0x1c9d
11223 #define mmDIG4_AFMT_AVI_INFO1_BASE_IDX                                                                 2
11224 #define mmDIG4_AFMT_AVI_INFO2                                                                          0x1c9e
11225 #define mmDIG4_AFMT_AVI_INFO2_BASE_IDX                                                                 2
11226 #define mmDIG4_AFMT_AVI_INFO3                                                                          0x1c9f
11227 #define mmDIG4_AFMT_AVI_INFO3_BASE_IDX                                                                 2
11228 #define mmDIG4_AFMT_MPEG_INFO0                                                                         0x1ca0
11229 #define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX                                                                2
11230 #define mmDIG4_AFMT_MPEG_INFO1                                                                         0x1ca1
11231 #define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX                                                                2
11232 #define mmDIG4_AFMT_GENERIC_HDR                                                                        0x1ca2
11233 #define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX                                                               2
11234 #define mmDIG4_AFMT_GENERIC_0                                                                          0x1ca3
11235 #define mmDIG4_AFMT_GENERIC_0_BASE_IDX                                                                 2
11236 #define mmDIG4_AFMT_GENERIC_1                                                                          0x1ca4
11237 #define mmDIG4_AFMT_GENERIC_1_BASE_IDX                                                                 2
11238 #define mmDIG4_AFMT_GENERIC_2                                                                          0x1ca5
11239 #define mmDIG4_AFMT_GENERIC_2_BASE_IDX                                                                 2
11240 #define mmDIG4_AFMT_GENERIC_3                                                                          0x1ca6
11241 #define mmDIG4_AFMT_GENERIC_3_BASE_IDX                                                                 2
11242 #define mmDIG4_AFMT_GENERIC_4                                                                          0x1ca7
11243 #define mmDIG4_AFMT_GENERIC_4_BASE_IDX                                                                 2
11244 #define mmDIG4_AFMT_GENERIC_5                                                                          0x1ca8
11245 #define mmDIG4_AFMT_GENERIC_5_BASE_IDX                                                                 2
11246 #define mmDIG4_AFMT_GENERIC_6                                                                          0x1ca9
11247 #define mmDIG4_AFMT_GENERIC_6_BASE_IDX                                                                 2
11248 #define mmDIG4_AFMT_GENERIC_7                                                                          0x1caa
11249 #define mmDIG4_AFMT_GENERIC_7_BASE_IDX                                                                 2
11250 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x1cab
11251 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
11252 #define mmDIG4_HDMI_ACR_32_0                                                                           0x1cac
11253 #define mmDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
11254 #define mmDIG4_HDMI_ACR_32_1                                                                           0x1cad
11255 #define mmDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
11256 #define mmDIG4_HDMI_ACR_44_0                                                                           0x1cae
11257 #define mmDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
11258 #define mmDIG4_HDMI_ACR_44_1                                                                           0x1caf
11259 #define mmDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
11260 #define mmDIG4_HDMI_ACR_48_0                                                                           0x1cb0
11261 #define mmDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
11262 #define mmDIG4_HDMI_ACR_48_1                                                                           0x1cb1
11263 #define mmDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
11264 #define mmDIG4_HDMI_ACR_STATUS_0                                                                       0x1cb2
11265 #define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
11266 #define mmDIG4_HDMI_ACR_STATUS_1                                                                       0x1cb3
11267 #define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
11268 #define mmDIG4_AFMT_AUDIO_INFO0                                                                        0x1cb4
11269 #define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
11270 #define mmDIG4_AFMT_AUDIO_INFO1                                                                        0x1cb5
11271 #define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
11272 #define mmDIG4_AFMT_60958_0                                                                            0x1cb6
11273 #define mmDIG4_AFMT_60958_0_BASE_IDX                                                                   2
11274 #define mmDIG4_AFMT_60958_1                                                                            0x1cb7
11275 #define mmDIG4_AFMT_60958_1_BASE_IDX                                                                   2
11276 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL                                                                  0x1cb8
11277 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
11278 #define mmDIG4_AFMT_RAMP_CONTROL0                                                                      0x1cb9
11279 #define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
11280 #define mmDIG4_AFMT_RAMP_CONTROL1                                                                      0x1cba
11281 #define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
11282 #define mmDIG4_AFMT_RAMP_CONTROL2                                                                      0x1cbb
11283 #define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
11284 #define mmDIG4_AFMT_RAMP_CONTROL3                                                                      0x1cbc
11285 #define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
11286 #define mmDIG4_AFMT_60958_2                                                                            0x1cbd
11287 #define mmDIG4_AFMT_60958_2_BASE_IDX                                                                   2
11288 #define mmDIG4_AFMT_AUDIO_CRC_RESULT                                                                   0x1cbe
11289 #define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
11290 #define mmDIG4_AFMT_STATUS                                                                             0x1cbf
11291 #define mmDIG4_AFMT_STATUS_BASE_IDX                                                                    2
11292 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                                               0x1cc0
11293 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11294 #define mmDIG4_AFMT_VBI_PACKET_CONTROL                                                                 0x1cc1
11295 #define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11296 #define mmDIG4_AFMT_INFOFRAME_CONTROL0                                                                 0x1cc2
11297 #define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11298 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL                                                                  0x1cc3
11299 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
11300 #define mmDIG4_DIG_BE_CNTL                                                                             0x1cc5
11301 #define mmDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
11302 #define mmDIG4_DIG_BE_EN_CNTL                                                                          0x1cc6
11303 #define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
11304 #define mmDIG4_TMDS_CNTL                                                                               0x1ce9
11305 #define mmDIG4_TMDS_CNTL_BASE_IDX                                                                      2
11306 #define mmDIG4_TMDS_CONTROL_CHAR                                                                       0x1cea
11307 #define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
11308 #define mmDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x1ceb
11309 #define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
11310 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x1cec
11311 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
11312 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x1ced
11313 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
11314 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x1cee
11315 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
11316 #define mmDIG4_TMDS_CTL_BITS                                                                           0x1cf0
11317 #define mmDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
11318 #define mmDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x1cf1
11319 #define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
11320 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x1cf3
11321 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
11322 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x1cf4
11323 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
11324 #define mmDIG4_DIG_VERSION                                                                             0x1cf6
11325 #define mmDIG4_DIG_VERSION_BASE_IDX                                                                    2
11326 #define mmDIG4_DIG_LANE_ENABLE                                                                         0x1cf7
11327 #define mmDIG4_DIG_LANE_ENABLE_BASE_IDX                                                                2
11328 #define mmDIG4_AFMT_CNTL                                                                               0x1cfc
11329 #define mmDIG4_AFMT_CNTL_BASE_IDX                                                                      2
11330 
11331 
11332 // addressBlock: dce_dc_dp4_dispdec
11333 // base address: 0x1000
11334 #define mmDP4_DP_LINK_CNTL                                                                             0x1d1e
11335 #define mmDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
11336 #define mmDP4_DP_PIXEL_FORMAT                                                                          0x1d1f
11337 #define mmDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
11338 #define mmDP4_DP_MSA_COLORIMETRY                                                                       0x1d20
11339 #define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
11340 #define mmDP4_DP_CONFIG                                                                                0x1d21
11341 #define mmDP4_DP_CONFIG_BASE_IDX                                                                       2
11342 #define mmDP4_DP_VID_STREAM_CNTL                                                                       0x1d22
11343 #define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
11344 #define mmDP4_DP_STEER_FIFO                                                                            0x1d23
11345 #define mmDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
11346 #define mmDP4_DP_MSA_MISC                                                                              0x1d24
11347 #define mmDP4_DP_MSA_MISC_BASE_IDX                                                                     2
11348 #define mmDP4_DP_VID_TIMING                                                                            0x1d26
11349 #define mmDP4_DP_VID_TIMING_BASE_IDX                                                                   2
11350 #define mmDP4_DP_VID_N                                                                                 0x1d27
11351 #define mmDP4_DP_VID_N_BASE_IDX                                                                        2
11352 #define mmDP4_DP_VID_M                                                                                 0x1d28
11353 #define mmDP4_DP_VID_M_BASE_IDX                                                                        2
11354 #define mmDP4_DP_LINK_FRAMING_CNTL                                                                     0x1d29
11355 #define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
11356 #define mmDP4_DP_HBR2_EYE_PATTERN                                                                      0x1d2a
11357 #define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
11358 #define mmDP4_DP_VID_MSA_VBID                                                                          0x1d2b
11359 #define mmDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
11360 #define mmDP4_DP_VID_INTERRUPT_CNTL                                                                    0x1d2c
11361 #define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
11362 #define mmDP4_DP_DPHY_CNTL                                                                             0x1d2d
11363 #define mmDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
11364 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x1d2e
11365 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
11366 #define mmDP4_DP_DPHY_SYM0                                                                             0x1d2f
11367 #define mmDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
11368 #define mmDP4_DP_DPHY_SYM1                                                                             0x1d30
11369 #define mmDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
11370 #define mmDP4_DP_DPHY_SYM2                                                                             0x1d31
11371 #define mmDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
11372 #define mmDP4_DP_DPHY_8B10B_CNTL                                                                       0x1d32
11373 #define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
11374 #define mmDP4_DP_DPHY_PRBS_CNTL                                                                        0x1d33
11375 #define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
11376 #define mmDP4_DP_DPHY_SCRAM_CNTL                                                                       0x1d34
11377 #define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
11378 #define mmDP4_DP_DPHY_CRC_EN                                                                           0x1d35
11379 #define mmDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
11380 #define mmDP4_DP_DPHY_CRC_CNTL                                                                         0x1d36
11381 #define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
11382 #define mmDP4_DP_DPHY_CRC_RESULT                                                                       0x1d37
11383 #define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
11384 #define mmDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x1d38
11385 #define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
11386 #define mmDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x1d39
11387 #define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
11388 #define mmDP4_DP_DPHY_FAST_TRAINING                                                                    0x1d3a
11389 #define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
11390 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x1d3b
11391 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
11392 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1                                                                0x1d3c
11393 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX                                                       2
11394 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2                                                                0x1d3d
11395 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX                                                       2
11396 #define mmDP4_DP_SEC_CNTL                                                                              0x1d41
11397 #define mmDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
11398 #define mmDP4_DP_SEC_CNTL1                                                                             0x1d42
11399 #define mmDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
11400 #define mmDP4_DP_SEC_FRAMING1                                                                          0x1d43
11401 #define mmDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
11402 #define mmDP4_DP_SEC_FRAMING2                                                                          0x1d44
11403 #define mmDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
11404 #define mmDP4_DP_SEC_FRAMING3                                                                          0x1d45
11405 #define mmDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
11406 #define mmDP4_DP_SEC_FRAMING4                                                                          0x1d46
11407 #define mmDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
11408 #define mmDP4_DP_SEC_AUD_N                                                                             0x1d47
11409 #define mmDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
11410 #define mmDP4_DP_SEC_AUD_N_READBACK                                                                    0x1d48
11411 #define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
11412 #define mmDP4_DP_SEC_AUD_M                                                                             0x1d49
11413 #define mmDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
11414 #define mmDP4_DP_SEC_AUD_M_READBACK                                                                    0x1d4a
11415 #define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
11416 #define mmDP4_DP_SEC_TIMESTAMP                                                                         0x1d4b
11417 #define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
11418 #define mmDP4_DP_SEC_PACKET_CNTL                                                                       0x1d4c
11419 #define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
11420 #define mmDP4_DP_MSE_RATE_CNTL                                                                         0x1d4d
11421 #define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
11422 #define mmDP4_DP_MSE_RATE_UPDATE                                                                       0x1d4f
11423 #define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
11424 #define mmDP4_DP_MSE_SAT0                                                                              0x1d50
11425 #define mmDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
11426 #define mmDP4_DP_MSE_SAT1                                                                              0x1d51
11427 #define mmDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
11428 #define mmDP4_DP_MSE_SAT2                                                                              0x1d52
11429 #define mmDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
11430 #define mmDP4_DP_MSE_SAT_UPDATE                                                                        0x1d53
11431 #define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
11432 #define mmDP4_DP_MSE_LINK_TIMING                                                                       0x1d54
11433 #define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
11434 #define mmDP4_DP_MSE_MISC_CNTL                                                                         0x1d55
11435 #define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
11436 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x1d5a
11437 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
11438 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x1d5b
11439 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
11440 #define mmDP4_DP_MSE_SAT0_STATUS                                                                       0x1d5d
11441 #define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
11442 #define mmDP4_DP_MSE_SAT1_STATUS                                                                       0x1d5e
11443 #define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
11444 #define mmDP4_DP_MSE_SAT2_STATUS                                                                       0x1d5f
11445 #define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
11446 
11447 
11448 // addressBlock: dce_dc_dig5_dispdec
11449 // base address: 0x1400
11450 #define mmDIG5_DIG_FE_CNTL                                                                             0x1d7e
11451 #define mmDIG5_DIG_FE_CNTL_BASE_IDX                                                                    2
11452 #define mmDIG5_DIG_OUTPUT_CRC_CNTL                                                                     0x1d7f
11453 #define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
11454 #define mmDIG5_DIG_OUTPUT_CRC_RESULT                                                                   0x1d80
11455 #define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
11456 #define mmDIG5_DIG_CLOCK_PATTERN                                                                       0x1d81
11457 #define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
11458 #define mmDIG5_DIG_TEST_PATTERN                                                                        0x1d82
11459 #define mmDIG5_DIG_TEST_PATTERN_BASE_IDX                                                               2
11460 #define mmDIG5_DIG_RANDOM_PATTERN_SEED                                                                 0x1d83
11461 #define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
11462 #define mmDIG5_DIG_FIFO_STATUS                                                                         0x1d84
11463 #define mmDIG5_DIG_FIFO_STATUS_BASE_IDX                                                                2
11464 #define mmDIG5_HDMI_CONTROL                                                                            0x1d87
11465 #define mmDIG5_HDMI_CONTROL_BASE_IDX                                                                   2
11466 #define mmDIG5_HDMI_STATUS                                                                             0x1d88
11467 #define mmDIG5_HDMI_STATUS_BASE_IDX                                                                    2
11468 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL                                                               0x1d89
11469 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11470 #define mmDIG5_HDMI_ACR_PACKET_CONTROL                                                                 0x1d8a
11471 #define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
11472 #define mmDIG5_HDMI_VBI_PACKET_CONTROL                                                                 0x1d8b
11473 #define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11474 #define mmDIG5_HDMI_INFOFRAME_CONTROL0                                                                 0x1d8c
11475 #define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11476 #define mmDIG5_HDMI_INFOFRAME_CONTROL1                                                                 0x1d8d
11477 #define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
11478 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0                                                            0x1d8e
11479 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
11480 #define mmDIG5_AFMT_INTERRUPT_STATUS                                                                   0x1d8f
11481 #define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
11482 #define mmDIG5_HDMI_GC                                                                                 0x1d91
11483 #define mmDIG5_HDMI_GC_BASE_IDX                                                                        2
11484 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2                                                              0x1d92
11485 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
11486 #define mmDIG5_AFMT_ISRC1_0                                                                            0x1d93
11487 #define mmDIG5_AFMT_ISRC1_0_BASE_IDX                                                                   2
11488 #define mmDIG5_AFMT_ISRC1_1                                                                            0x1d94
11489 #define mmDIG5_AFMT_ISRC1_1_BASE_IDX                                                                   2
11490 #define mmDIG5_AFMT_ISRC1_2                                                                            0x1d95
11491 #define mmDIG5_AFMT_ISRC1_2_BASE_IDX                                                                   2
11492 #define mmDIG5_AFMT_ISRC1_3                                                                            0x1d96
11493 #define mmDIG5_AFMT_ISRC1_3_BASE_IDX                                                                   2
11494 #define mmDIG5_AFMT_ISRC1_4                                                                            0x1d97
11495 #define mmDIG5_AFMT_ISRC1_4_BASE_IDX                                                                   2
11496 #define mmDIG5_AFMT_ISRC2_0                                                                            0x1d98
11497 #define mmDIG5_AFMT_ISRC2_0_BASE_IDX                                                                   2
11498 #define mmDIG5_AFMT_ISRC2_1                                                                            0x1d99
11499 #define mmDIG5_AFMT_ISRC2_1_BASE_IDX                                                                   2
11500 #define mmDIG5_AFMT_ISRC2_2                                                                            0x1d9a
11501 #define mmDIG5_AFMT_ISRC2_2_BASE_IDX                                                                   2
11502 #define mmDIG5_AFMT_ISRC2_3                                                                            0x1d9b
11503 #define mmDIG5_AFMT_ISRC2_3_BASE_IDX                                                                   2
11504 #define mmDIG5_AFMT_AVI_INFO0                                                                          0x1d9c
11505 #define mmDIG5_AFMT_AVI_INFO0_BASE_IDX                                                                 2
11506 #define mmDIG5_AFMT_AVI_INFO1                                                                          0x1d9d
11507 #define mmDIG5_AFMT_AVI_INFO1_BASE_IDX                                                                 2
11508 #define mmDIG5_AFMT_AVI_INFO2                                                                          0x1d9e
11509 #define mmDIG5_AFMT_AVI_INFO2_BASE_IDX                                                                 2
11510 #define mmDIG5_AFMT_AVI_INFO3                                                                          0x1d9f
11511 #define mmDIG5_AFMT_AVI_INFO3_BASE_IDX                                                                 2
11512 #define mmDIG5_AFMT_MPEG_INFO0                                                                         0x1da0
11513 #define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX                                                                2
11514 #define mmDIG5_AFMT_MPEG_INFO1                                                                         0x1da1
11515 #define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX                                                                2
11516 #define mmDIG5_AFMT_GENERIC_HDR                                                                        0x1da2
11517 #define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX                                                               2
11518 #define mmDIG5_AFMT_GENERIC_0                                                                          0x1da3
11519 #define mmDIG5_AFMT_GENERIC_0_BASE_IDX                                                                 2
11520 #define mmDIG5_AFMT_GENERIC_1                                                                          0x1da4
11521 #define mmDIG5_AFMT_GENERIC_1_BASE_IDX                                                                 2
11522 #define mmDIG5_AFMT_GENERIC_2                                                                          0x1da5
11523 #define mmDIG5_AFMT_GENERIC_2_BASE_IDX                                                                 2
11524 #define mmDIG5_AFMT_GENERIC_3                                                                          0x1da6
11525 #define mmDIG5_AFMT_GENERIC_3_BASE_IDX                                                                 2
11526 #define mmDIG5_AFMT_GENERIC_4                                                                          0x1da7
11527 #define mmDIG5_AFMT_GENERIC_4_BASE_IDX                                                                 2
11528 #define mmDIG5_AFMT_GENERIC_5                                                                          0x1da8
11529 #define mmDIG5_AFMT_GENERIC_5_BASE_IDX                                                                 2
11530 #define mmDIG5_AFMT_GENERIC_6                                                                          0x1da9
11531 #define mmDIG5_AFMT_GENERIC_6_BASE_IDX                                                                 2
11532 #define mmDIG5_AFMT_GENERIC_7                                                                          0x1daa
11533 #define mmDIG5_AFMT_GENERIC_7_BASE_IDX                                                                 2
11534 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1                                                            0x1dab
11535 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
11536 #define mmDIG5_HDMI_ACR_32_0                                                                           0x1dac
11537 #define mmDIG5_HDMI_ACR_32_0_BASE_IDX                                                                  2
11538 #define mmDIG5_HDMI_ACR_32_1                                                                           0x1dad
11539 #define mmDIG5_HDMI_ACR_32_1_BASE_IDX                                                                  2
11540 #define mmDIG5_HDMI_ACR_44_0                                                                           0x1dae
11541 #define mmDIG5_HDMI_ACR_44_0_BASE_IDX                                                                  2
11542 #define mmDIG5_HDMI_ACR_44_1                                                                           0x1daf
11543 #define mmDIG5_HDMI_ACR_44_1_BASE_IDX                                                                  2
11544 #define mmDIG5_HDMI_ACR_48_0                                                                           0x1db0
11545 #define mmDIG5_HDMI_ACR_48_0_BASE_IDX                                                                  2
11546 #define mmDIG5_HDMI_ACR_48_1                                                                           0x1db1
11547 #define mmDIG5_HDMI_ACR_48_1_BASE_IDX                                                                  2
11548 #define mmDIG5_HDMI_ACR_STATUS_0                                                                       0x1db2
11549 #define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
11550 #define mmDIG5_HDMI_ACR_STATUS_1                                                                       0x1db3
11551 #define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
11552 #define mmDIG5_AFMT_AUDIO_INFO0                                                                        0x1db4
11553 #define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
11554 #define mmDIG5_AFMT_AUDIO_INFO1                                                                        0x1db5
11555 #define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
11556 #define mmDIG5_AFMT_60958_0                                                                            0x1db6
11557 #define mmDIG5_AFMT_60958_0_BASE_IDX                                                                   2
11558 #define mmDIG5_AFMT_60958_1                                                                            0x1db7
11559 #define mmDIG5_AFMT_60958_1_BASE_IDX                                                                   2
11560 #define mmDIG5_AFMT_AUDIO_CRC_CONTROL                                                                  0x1db8
11561 #define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
11562 #define mmDIG5_AFMT_RAMP_CONTROL0                                                                      0x1db9
11563 #define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
11564 #define mmDIG5_AFMT_RAMP_CONTROL1                                                                      0x1dba
11565 #define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
11566 #define mmDIG5_AFMT_RAMP_CONTROL2                                                                      0x1dbb
11567 #define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
11568 #define mmDIG5_AFMT_RAMP_CONTROL3                                                                      0x1dbc
11569 #define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
11570 #define mmDIG5_AFMT_60958_2                                                                            0x1dbd
11571 #define mmDIG5_AFMT_60958_2_BASE_IDX                                                                   2
11572 #define mmDIG5_AFMT_AUDIO_CRC_RESULT                                                                   0x1dbe
11573 #define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
11574 #define mmDIG5_AFMT_STATUS                                                                             0x1dbf
11575 #define mmDIG5_AFMT_STATUS_BASE_IDX                                                                    2
11576 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL                                                               0x1dc0
11577 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11578 #define mmDIG5_AFMT_VBI_PACKET_CONTROL                                                                 0x1dc1
11579 #define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11580 #define mmDIG5_AFMT_INFOFRAME_CONTROL0                                                                 0x1dc2
11581 #define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11582 #define mmDIG5_AFMT_AUDIO_SRC_CONTROL                                                                  0x1dc3
11583 #define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
11584 #define mmDIG5_DIG_BE_CNTL                                                                             0x1dc5
11585 #define mmDIG5_DIG_BE_CNTL_BASE_IDX                                                                    2
11586 #define mmDIG5_DIG_BE_EN_CNTL                                                                          0x1dc6
11587 #define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
11588 #define mmDIG5_TMDS_CNTL                                                                               0x1de9
11589 #define mmDIG5_TMDS_CNTL_BASE_IDX                                                                      2
11590 #define mmDIG5_TMDS_CONTROL_CHAR                                                                       0x1dea
11591 #define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
11592 #define mmDIG5_TMDS_CONTROL0_FEEDBACK                                                                  0x1deb
11593 #define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
11594 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL                                                                 0x1dec
11595 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
11596 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x1ded
11597 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
11598 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x1dee
11599 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
11600 #define mmDIG5_TMDS_CTL_BITS                                                                           0x1df0
11601 #define mmDIG5_TMDS_CTL_BITS_BASE_IDX                                                                  2
11602 #define mmDIG5_TMDS_DCBALANCER_CONTROL                                                                 0x1df1
11603 #define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
11604 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL                                                                    0x1df3
11605 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
11606 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL                                                                    0x1df4
11607 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
11608 #define mmDIG5_DIG_VERSION                                                                             0x1df6
11609 #define mmDIG5_DIG_VERSION_BASE_IDX                                                                    2
11610 #define mmDIG5_DIG_LANE_ENABLE                                                                         0x1df7
11611 #define mmDIG5_DIG_LANE_ENABLE_BASE_IDX                                                                2
11612 #define mmDIG5_AFMT_CNTL                                                                               0x1dfc
11613 #define mmDIG5_AFMT_CNTL_BASE_IDX                                                                      2
11614 
11615 
11616 // addressBlock: dce_dc_dp5_dispdec
11617 // base address: 0x1400
11618 #define mmDP5_DP_LINK_CNTL                                                                             0x1e1e
11619 #define mmDP5_DP_LINK_CNTL_BASE_IDX                                                                    2
11620 #define mmDP5_DP_PIXEL_FORMAT                                                                          0x1e1f
11621 #define mmDP5_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
11622 #define mmDP5_DP_MSA_COLORIMETRY                                                                       0x1e20
11623 #define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
11624 #define mmDP5_DP_CONFIG                                                                                0x1e21
11625 #define mmDP5_DP_CONFIG_BASE_IDX                                                                       2
11626 #define mmDP5_DP_VID_STREAM_CNTL                                                                       0x1e22
11627 #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
11628 #define mmDP5_DP_STEER_FIFO                                                                            0x1e23
11629 #define mmDP5_DP_STEER_FIFO_BASE_IDX                                                                   2
11630 #define mmDP5_DP_MSA_MISC                                                                              0x1e24
11631 #define mmDP5_DP_MSA_MISC_BASE_IDX                                                                     2
11632 #define mmDP5_DP_VID_TIMING                                                                            0x1e26
11633 #define mmDP5_DP_VID_TIMING_BASE_IDX                                                                   2
11634 #define mmDP5_DP_VID_N                                                                                 0x1e27
11635 #define mmDP5_DP_VID_N_BASE_IDX                                                                        2
11636 #define mmDP5_DP_VID_M                                                                                 0x1e28
11637 #define mmDP5_DP_VID_M_BASE_IDX                                                                        2
11638 #define mmDP5_DP_LINK_FRAMING_CNTL                                                                     0x1e29
11639 #define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
11640 #define mmDP5_DP_HBR2_EYE_PATTERN                                                                      0x1e2a
11641 #define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
11642 #define mmDP5_DP_VID_MSA_VBID                                                                          0x1e2b
11643 #define mmDP5_DP_VID_MSA_VBID_BASE_IDX                                                                 2
11644 #define mmDP5_DP_VID_INTERRUPT_CNTL                                                                    0x1e2c
11645 #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
11646 #define mmDP5_DP_DPHY_CNTL                                                                             0x1e2d
11647 #define mmDP5_DP_DPHY_CNTL_BASE_IDX                                                                    2
11648 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x1e2e
11649 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
11650 #define mmDP5_DP_DPHY_SYM0                                                                             0x1e2f
11651 #define mmDP5_DP_DPHY_SYM0_BASE_IDX                                                                    2
11652 #define mmDP5_DP_DPHY_SYM1                                                                             0x1e30
11653 #define mmDP5_DP_DPHY_SYM1_BASE_IDX                                                                    2
11654 #define mmDP5_DP_DPHY_SYM2                                                                             0x1e31
11655 #define mmDP5_DP_DPHY_SYM2_BASE_IDX                                                                    2
11656 #define mmDP5_DP_DPHY_8B10B_CNTL                                                                       0x1e32
11657 #define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
11658 #define mmDP5_DP_DPHY_PRBS_CNTL                                                                        0x1e33
11659 #define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
11660 #define mmDP5_DP_DPHY_SCRAM_CNTL                                                                       0x1e34
11661 #define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
11662 #define mmDP5_DP_DPHY_CRC_EN                                                                           0x1e35
11663 #define mmDP5_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
11664 #define mmDP5_DP_DPHY_CRC_CNTL                                                                         0x1e36
11665 #define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
11666 #define mmDP5_DP_DPHY_CRC_RESULT                                                                       0x1e37
11667 #define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
11668 #define mmDP5_DP_DPHY_CRC_MST_CNTL                                                                     0x1e38
11669 #define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
11670 #define mmDP5_DP_DPHY_CRC_MST_STATUS                                                                   0x1e39
11671 #define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
11672 #define mmDP5_DP_DPHY_FAST_TRAINING                                                                    0x1e3a
11673 #define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
11674 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS                                                             0x1e3b
11675 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
11676 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1                                                                0x1e3c
11677 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX                                                       2
11678 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2                                                                0x1e3d
11679 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX                                                       2
11680 #define mmDP5_DP_SEC_CNTL                                                                              0x1e41
11681 #define mmDP5_DP_SEC_CNTL_BASE_IDX                                                                     2
11682 #define mmDP5_DP_SEC_CNTL1                                                                             0x1e42
11683 #define mmDP5_DP_SEC_CNTL1_BASE_IDX                                                                    2
11684 #define mmDP5_DP_SEC_FRAMING1                                                                          0x1e43
11685 #define mmDP5_DP_SEC_FRAMING1_BASE_IDX                                                                 2
11686 #define mmDP5_DP_SEC_FRAMING2                                                                          0x1e44
11687 #define mmDP5_DP_SEC_FRAMING2_BASE_IDX                                                                 2
11688 #define mmDP5_DP_SEC_FRAMING3                                                                          0x1e45
11689 #define mmDP5_DP_SEC_FRAMING3_BASE_IDX                                                                 2
11690 #define mmDP5_DP_SEC_FRAMING4                                                                          0x1e46
11691 #define mmDP5_DP_SEC_FRAMING4_BASE_IDX                                                                 2
11692 #define mmDP5_DP_SEC_AUD_N                                                                             0x1e47
11693 #define mmDP5_DP_SEC_AUD_N_BASE_IDX                                                                    2
11694 #define mmDP5_DP_SEC_AUD_N_READBACK                                                                    0x1e48
11695 #define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
11696 #define mmDP5_DP_SEC_AUD_M                                                                             0x1e49
11697 #define mmDP5_DP_SEC_AUD_M_BASE_IDX                                                                    2
11698 #define mmDP5_DP_SEC_AUD_M_READBACK                                                                    0x1e4a
11699 #define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
11700 #define mmDP5_DP_SEC_TIMESTAMP                                                                         0x1e4b
11701 #define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
11702 #define mmDP5_DP_SEC_PACKET_CNTL                                                                       0x1e4c
11703 #define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
11704 #define mmDP5_DP_MSE_RATE_CNTL                                                                         0x1e4d
11705 #define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
11706 #define mmDP5_DP_MSE_RATE_UPDATE                                                                       0x1e4f
11707 #define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
11708 #define mmDP5_DP_MSE_SAT0                                                                              0x1e50
11709 #define mmDP5_DP_MSE_SAT0_BASE_IDX                                                                     2
11710 #define mmDP5_DP_MSE_SAT1                                                                              0x1e51
11711 #define mmDP5_DP_MSE_SAT1_BASE_IDX                                                                     2
11712 #define mmDP5_DP_MSE_SAT2                                                                              0x1e52
11713 #define mmDP5_DP_MSE_SAT2_BASE_IDX                                                                     2
11714 #define mmDP5_DP_MSE_SAT_UPDATE                                                                        0x1e53
11715 #define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
11716 #define mmDP5_DP_MSE_LINK_TIMING                                                                       0x1e54
11717 #define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
11718 #define mmDP5_DP_MSE_MISC_CNTL                                                                         0x1e55
11719 #define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
11720 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x1e5a
11721 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
11722 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x1e5b
11723 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
11724 #define mmDP5_DP_MSE_SAT0_STATUS                                                                       0x1e5d
11725 #define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
11726 #define mmDP5_DP_MSE_SAT1_STATUS                                                                       0x1e5e
11727 #define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
11728 #define mmDP5_DP_MSE_SAT2_STATUS                                                                       0x1e5f
11729 #define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
11730 
11731 
11732 // addressBlock: dce_dc_dig6_dispdec
11733 // base address: 0x1800
11734 #define mmDIG6_DIG_FE_CNTL                                                                             0x1e7e
11735 #define mmDIG6_DIG_FE_CNTL_BASE_IDX                                                                    2
11736 #define mmDIG6_DIG_OUTPUT_CRC_CNTL                                                                     0x1e7f
11737 #define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
11738 #define mmDIG6_DIG_OUTPUT_CRC_RESULT                                                                   0x1e80
11739 #define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
11740 #define mmDIG6_DIG_CLOCK_PATTERN                                                                       0x1e81
11741 #define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
11742 #define mmDIG6_DIG_TEST_PATTERN                                                                        0x1e82
11743 #define mmDIG6_DIG_TEST_PATTERN_BASE_IDX                                                               2
11744 #define mmDIG6_DIG_RANDOM_PATTERN_SEED                                                                 0x1e83
11745 #define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
11746 #define mmDIG6_DIG_FIFO_STATUS                                                                         0x1e84
11747 #define mmDIG6_DIG_FIFO_STATUS_BASE_IDX                                                                2
11748 #define mmDIG6_HDMI_CONTROL                                                                            0x1e87
11749 #define mmDIG6_HDMI_CONTROL_BASE_IDX                                                                   2
11750 #define mmDIG6_HDMI_STATUS                                                                             0x1e88
11751 #define mmDIG6_HDMI_STATUS_BASE_IDX                                                                    2
11752 #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL                                                               0x1e89
11753 #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11754 #define mmDIG6_HDMI_ACR_PACKET_CONTROL                                                                 0x1e8a
11755 #define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
11756 #define mmDIG6_HDMI_VBI_PACKET_CONTROL                                                                 0x1e8b
11757 #define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11758 #define mmDIG6_HDMI_INFOFRAME_CONTROL0                                                                 0x1e8c
11759 #define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11760 #define mmDIG6_HDMI_INFOFRAME_CONTROL1                                                                 0x1e8d
11761 #define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
11762 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0                                                            0x1e8e
11763 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
11764 #define mmDIG6_AFMT_INTERRUPT_STATUS                                                                   0x1e8f
11765 #define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
11766 #define mmDIG6_HDMI_GC                                                                                 0x1e91
11767 #define mmDIG6_HDMI_GC_BASE_IDX                                                                        2
11768 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2                                                              0x1e92
11769 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
11770 #define mmDIG6_AFMT_ISRC1_0                                                                            0x1e93
11771 #define mmDIG6_AFMT_ISRC1_0_BASE_IDX                                                                   2
11772 #define mmDIG6_AFMT_ISRC1_1                                                                            0x1e94
11773 #define mmDIG6_AFMT_ISRC1_1_BASE_IDX                                                                   2
11774 #define mmDIG6_AFMT_ISRC1_2                                                                            0x1e95
11775 #define mmDIG6_AFMT_ISRC1_2_BASE_IDX                                                                   2
11776 #define mmDIG6_AFMT_ISRC1_3                                                                            0x1e96
11777 #define mmDIG6_AFMT_ISRC1_3_BASE_IDX                                                                   2
11778 #define mmDIG6_AFMT_ISRC1_4                                                                            0x1e97
11779 #define mmDIG6_AFMT_ISRC1_4_BASE_IDX                                                                   2
11780 #define mmDIG6_AFMT_ISRC2_0                                                                            0x1e98
11781 #define mmDIG6_AFMT_ISRC2_0_BASE_IDX                                                                   2
11782 #define mmDIG6_AFMT_ISRC2_1                                                                            0x1e99
11783 #define mmDIG6_AFMT_ISRC2_1_BASE_IDX                                                                   2
11784 #define mmDIG6_AFMT_ISRC2_2                                                                            0x1e9a
11785 #define mmDIG6_AFMT_ISRC2_2_BASE_IDX                                                                   2
11786 #define mmDIG6_AFMT_ISRC2_3                                                                            0x1e9b
11787 #define mmDIG6_AFMT_ISRC2_3_BASE_IDX                                                                   2
11788 #define mmDIG6_AFMT_AVI_INFO0                                                                          0x1e9c
11789 #define mmDIG6_AFMT_AVI_INFO0_BASE_IDX                                                                 2
11790 #define mmDIG6_AFMT_AVI_INFO1                                                                          0x1e9d
11791 #define mmDIG6_AFMT_AVI_INFO1_BASE_IDX                                                                 2
11792 #define mmDIG6_AFMT_AVI_INFO2                                                                          0x1e9e
11793 #define mmDIG6_AFMT_AVI_INFO2_BASE_IDX                                                                 2
11794 #define mmDIG6_AFMT_AVI_INFO3                                                                          0x1e9f
11795 #define mmDIG6_AFMT_AVI_INFO3_BASE_IDX                                                                 2
11796 #define mmDIG6_AFMT_MPEG_INFO0                                                                         0x1ea0
11797 #define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX                                                                2
11798 #define mmDIG6_AFMT_MPEG_INFO1                                                                         0x1ea1
11799 #define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX                                                                2
11800 #define mmDIG6_AFMT_GENERIC_HDR                                                                        0x1ea2
11801 #define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX                                                               2
11802 #define mmDIG6_AFMT_GENERIC_0                                                                          0x1ea3
11803 #define mmDIG6_AFMT_GENERIC_0_BASE_IDX                                                                 2
11804 #define mmDIG6_AFMT_GENERIC_1                                                                          0x1ea4
11805 #define mmDIG6_AFMT_GENERIC_1_BASE_IDX                                                                 2
11806 #define mmDIG6_AFMT_GENERIC_2                                                                          0x1ea5
11807 #define mmDIG6_AFMT_GENERIC_2_BASE_IDX                                                                 2
11808 #define mmDIG6_AFMT_GENERIC_3                                                                          0x1ea6
11809 #define mmDIG6_AFMT_GENERIC_3_BASE_IDX                                                                 2
11810 #define mmDIG6_AFMT_GENERIC_4                                                                          0x1ea7
11811 #define mmDIG6_AFMT_GENERIC_4_BASE_IDX                                                                 2
11812 #define mmDIG6_AFMT_GENERIC_5                                                                          0x1ea8
11813 #define mmDIG6_AFMT_GENERIC_5_BASE_IDX                                                                 2
11814 #define mmDIG6_AFMT_GENERIC_6                                                                          0x1ea9
11815 #define mmDIG6_AFMT_GENERIC_6_BASE_IDX                                                                 2
11816 #define mmDIG6_AFMT_GENERIC_7                                                                          0x1eaa
11817 #define mmDIG6_AFMT_GENERIC_7_BASE_IDX                                                                 2
11818 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1                                                            0x1eab
11819 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
11820 #define mmDIG6_HDMI_ACR_32_0                                                                           0x1eac
11821 #define mmDIG6_HDMI_ACR_32_0_BASE_IDX                                                                  2
11822 #define mmDIG6_HDMI_ACR_32_1                                                                           0x1ead
11823 #define mmDIG6_HDMI_ACR_32_1_BASE_IDX                                                                  2
11824 #define mmDIG6_HDMI_ACR_44_0                                                                           0x1eae
11825 #define mmDIG6_HDMI_ACR_44_0_BASE_IDX                                                                  2
11826 #define mmDIG6_HDMI_ACR_44_1                                                                           0x1eaf
11827 #define mmDIG6_HDMI_ACR_44_1_BASE_IDX                                                                  2
11828 #define mmDIG6_HDMI_ACR_48_0                                                                           0x1eb0
11829 #define mmDIG6_HDMI_ACR_48_0_BASE_IDX                                                                  2
11830 #define mmDIG6_HDMI_ACR_48_1                                                                           0x1eb1
11831 #define mmDIG6_HDMI_ACR_48_1_BASE_IDX                                                                  2
11832 #define mmDIG6_HDMI_ACR_STATUS_0                                                                       0x1eb2
11833 #define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
11834 #define mmDIG6_HDMI_ACR_STATUS_1                                                                       0x1eb3
11835 #define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
11836 #define mmDIG6_AFMT_AUDIO_INFO0                                                                        0x1eb4
11837 #define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
11838 #define mmDIG6_AFMT_AUDIO_INFO1                                                                        0x1eb5
11839 #define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
11840 #define mmDIG6_AFMT_60958_0                                                                            0x1eb6
11841 #define mmDIG6_AFMT_60958_0_BASE_IDX                                                                   2
11842 #define mmDIG6_AFMT_60958_1                                                                            0x1eb7
11843 #define mmDIG6_AFMT_60958_1_BASE_IDX                                                                   2
11844 #define mmDIG6_AFMT_AUDIO_CRC_CONTROL                                                                  0x1eb8
11845 #define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
11846 #define mmDIG6_AFMT_RAMP_CONTROL0                                                                      0x1eb9
11847 #define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
11848 #define mmDIG6_AFMT_RAMP_CONTROL1                                                                      0x1eba
11849 #define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
11850 #define mmDIG6_AFMT_RAMP_CONTROL2                                                                      0x1ebb
11851 #define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
11852 #define mmDIG6_AFMT_RAMP_CONTROL3                                                                      0x1ebc
11853 #define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
11854 #define mmDIG6_AFMT_60958_2                                                                            0x1ebd
11855 #define mmDIG6_AFMT_60958_2_BASE_IDX                                                                   2
11856 #define mmDIG6_AFMT_AUDIO_CRC_RESULT                                                                   0x1ebe
11857 #define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
11858 #define mmDIG6_AFMT_STATUS                                                                             0x1ebf
11859 #define mmDIG6_AFMT_STATUS_BASE_IDX                                                                    2
11860 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL                                                               0x1ec0
11861 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
11862 #define mmDIG6_AFMT_VBI_PACKET_CONTROL                                                                 0x1ec1
11863 #define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
11864 #define mmDIG6_AFMT_INFOFRAME_CONTROL0                                                                 0x1ec2
11865 #define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
11866 #define mmDIG6_AFMT_AUDIO_SRC_CONTROL                                                                  0x1ec3
11867 #define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
11868 #define mmDIG6_DIG_BE_CNTL                                                                             0x1ec5
11869 #define mmDIG6_DIG_BE_CNTL_BASE_IDX                                                                    2
11870 #define mmDIG6_DIG_BE_EN_CNTL                                                                          0x1ec6
11871 #define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
11872 #define mmDIG6_TMDS_CNTL                                                                               0x1ee9
11873 #define mmDIG6_TMDS_CNTL_BASE_IDX                                                                      2
11874 #define mmDIG6_TMDS_CONTROL_CHAR                                                                       0x1eea
11875 #define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
11876 #define mmDIG6_TMDS_CONTROL0_FEEDBACK                                                                  0x1eeb
11877 #define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
11878 #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL                                                                 0x1eec
11879 #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
11880 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x1eed
11881 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
11882 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x1eee
11883 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
11884 #define mmDIG6_TMDS_CTL_BITS                                                                           0x1ef0
11885 #define mmDIG6_TMDS_CTL_BITS_BASE_IDX                                                                  2
11886 #define mmDIG6_TMDS_DCBALANCER_CONTROL                                                                 0x1ef1
11887 #define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
11888 #define mmDIG6_TMDS_CTL0_1_GEN_CNTL                                                                    0x1ef3
11889 #define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
11890 #define mmDIG6_TMDS_CTL2_3_GEN_CNTL                                                                    0x1ef4
11891 #define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
11892 #define mmDIG6_DIG_VERSION                                                                             0x1ef6
11893 #define mmDIG6_DIG_VERSION_BASE_IDX                                                                    2
11894 #define mmDIG6_DIG_LANE_ENABLE                                                                         0x1ef7
11895 #define mmDIG6_DIG_LANE_ENABLE_BASE_IDX                                                                2
11896 #define mmDIG6_AFMT_CNTL                                                                               0x1efc
11897 #define mmDIG6_AFMT_CNTL_BASE_IDX                                                                      2
11898 
11899 
11900 // addressBlock: dce_dc_dp6_dispdec
11901 // base address: 0x1800
11902 #define mmDP6_DP_LINK_CNTL                                                                             0x1f1e
11903 #define mmDP6_DP_LINK_CNTL_BASE_IDX                                                                    2
11904 #define mmDP6_DP_PIXEL_FORMAT                                                                          0x1f1f
11905 #define mmDP6_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
11906 #define mmDP6_DP_MSA_COLORIMETRY                                                                       0x1f20
11907 #define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
11908 #define mmDP6_DP_CONFIG                                                                                0x1f21
11909 #define mmDP6_DP_CONFIG_BASE_IDX                                                                       2
11910 #define mmDP6_DP_VID_STREAM_CNTL                                                                       0x1f22
11911 #define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
11912 #define mmDP6_DP_STEER_FIFO                                                                            0x1f23
11913 #define mmDP6_DP_STEER_FIFO_BASE_IDX                                                                   2
11914 #define mmDP6_DP_MSA_MISC                                                                              0x1f24
11915 #define mmDP6_DP_MSA_MISC_BASE_IDX                                                                     2
11916 #define mmDP6_DP_VID_TIMING                                                                            0x1f26
11917 #define mmDP6_DP_VID_TIMING_BASE_IDX                                                                   2
11918 #define mmDP6_DP_VID_N                                                                                 0x1f27
11919 #define mmDP6_DP_VID_N_BASE_IDX                                                                        2
11920 #define mmDP6_DP_VID_M                                                                                 0x1f28
11921 #define mmDP6_DP_VID_M_BASE_IDX                                                                        2
11922 #define mmDP6_DP_LINK_FRAMING_CNTL                                                                     0x1f29
11923 #define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
11924 #define mmDP6_DP_HBR2_EYE_PATTERN                                                                      0x1f2a
11925 #define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
11926 #define mmDP6_DP_VID_MSA_VBID                                                                          0x1f2b
11927 #define mmDP6_DP_VID_MSA_VBID_BASE_IDX                                                                 2
11928 #define mmDP6_DP_VID_INTERRUPT_CNTL                                                                    0x1f2c
11929 #define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
11930 #define mmDP6_DP_DPHY_CNTL                                                                             0x1f2d
11931 #define mmDP6_DP_DPHY_CNTL_BASE_IDX                                                                    2
11932 #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x1f2e
11933 #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
11934 #define mmDP6_DP_DPHY_SYM0                                                                             0x1f2f
11935 #define mmDP6_DP_DPHY_SYM0_BASE_IDX                                                                    2
11936 #define mmDP6_DP_DPHY_SYM1                                                                             0x1f30
11937 #define mmDP6_DP_DPHY_SYM1_BASE_IDX                                                                    2
11938 #define mmDP6_DP_DPHY_SYM2                                                                             0x1f31
11939 #define mmDP6_DP_DPHY_SYM2_BASE_IDX                                                                    2
11940 #define mmDP6_DP_DPHY_8B10B_CNTL                                                                       0x1f32
11941 #define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
11942 #define mmDP6_DP_DPHY_PRBS_CNTL                                                                        0x1f33
11943 #define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
11944 #define mmDP6_DP_DPHY_SCRAM_CNTL                                                                       0x1f34
11945 #define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
11946 #define mmDP6_DP_DPHY_CRC_EN                                                                           0x1f35
11947 #define mmDP6_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
11948 #define mmDP6_DP_DPHY_CRC_CNTL                                                                         0x1f36
11949 #define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
11950 #define mmDP6_DP_DPHY_CRC_RESULT                                                                       0x1f37
11951 #define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
11952 #define mmDP6_DP_DPHY_CRC_MST_CNTL                                                                     0x1f38
11953 #define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
11954 #define mmDP6_DP_DPHY_CRC_MST_STATUS                                                                   0x1f39
11955 #define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
11956 #define mmDP6_DP_DPHY_FAST_TRAINING                                                                    0x1f3a
11957 #define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
11958 #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS                                                             0x1f3b
11959 #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
11960 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1                                                                0x1f3c
11961 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX                                                       2
11962 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2                                                                0x1f3d
11963 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX                                                       2
11964 #define mmDP6_DP_SEC_CNTL                                                                              0x1f41
11965 #define mmDP6_DP_SEC_CNTL_BASE_IDX                                                                     2
11966 #define mmDP6_DP_SEC_CNTL1                                                                             0x1f42
11967 #define mmDP6_DP_SEC_CNTL1_BASE_IDX                                                                    2
11968 #define mmDP6_DP_SEC_FRAMING1                                                                          0x1f43
11969 #define mmDP6_DP_SEC_FRAMING1_BASE_IDX                                                                 2
11970 #define mmDP6_DP_SEC_FRAMING2                                                                          0x1f44
11971 #define mmDP6_DP_SEC_FRAMING2_BASE_IDX                                                                 2
11972 #define mmDP6_DP_SEC_FRAMING3                                                                          0x1f45
11973 #define mmDP6_DP_SEC_FRAMING3_BASE_IDX                                                                 2
11974 #define mmDP6_DP_SEC_FRAMING4                                                                          0x1f46
11975 #define mmDP6_DP_SEC_FRAMING4_BASE_IDX                                                                 2
11976 #define mmDP6_DP_SEC_AUD_N                                                                             0x1f47
11977 #define mmDP6_DP_SEC_AUD_N_BASE_IDX                                                                    2
11978 #define mmDP6_DP_SEC_AUD_N_READBACK                                                                    0x1f48
11979 #define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
11980 #define mmDP6_DP_SEC_AUD_M                                                                             0x1f49
11981 #define mmDP6_DP_SEC_AUD_M_BASE_IDX                                                                    2
11982 #define mmDP6_DP_SEC_AUD_M_READBACK                                                                    0x1f4a
11983 #define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
11984 #define mmDP6_DP_SEC_TIMESTAMP                                                                         0x1f4b
11985 #define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
11986 #define mmDP6_DP_SEC_PACKET_CNTL                                                                       0x1f4c
11987 #define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
11988 #define mmDP6_DP_MSE_RATE_CNTL                                                                         0x1f4d
11989 #define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
11990 #define mmDP6_DP_MSE_RATE_UPDATE                                                                       0x1f4f
11991 #define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
11992 #define mmDP6_DP_MSE_SAT0                                                                              0x1f50
11993 #define mmDP6_DP_MSE_SAT0_BASE_IDX                                                                     2
11994 #define mmDP6_DP_MSE_SAT1                                                                              0x1f51
11995 #define mmDP6_DP_MSE_SAT1_BASE_IDX                                                                     2
11996 #define mmDP6_DP_MSE_SAT2                                                                              0x1f52
11997 #define mmDP6_DP_MSE_SAT2_BASE_IDX                                                                     2
11998 #define mmDP6_DP_MSE_SAT_UPDATE                                                                        0x1f53
11999 #define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
12000 #define mmDP6_DP_MSE_LINK_TIMING                                                                       0x1f54
12001 #define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
12002 #define mmDP6_DP_MSE_MISC_CNTL                                                                         0x1f55
12003 #define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
12004 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x1f5a
12005 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
12006 #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x1f5b
12007 #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
12008 #define mmDP6_DP_MSE_SAT0_STATUS                                                                       0x1f5d
12009 #define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
12010 #define mmDP6_DP_MSE_SAT1_STATUS                                                                       0x1f5e
12011 #define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
12012 #define mmDP6_DP_MSE_SAT2_STATUS                                                                       0x1f5f
12013 #define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
12014 
12015 
12016 // addressBlock: dce_dc_dcio_uniphy0_dispdec
12017 // base address: 0x0
12018 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x213e
12019 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
12020 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x213f
12021 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
12022 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2140
12023 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
12024 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2141
12025 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
12026 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2142
12027 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
12028 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2143
12029 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
12030 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2144
12031 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
12032 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2145
12033 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
12034 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2146
12035 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
12036 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2147
12037 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
12038 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2148
12039 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
12040 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2149
12041 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
12042 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x214a
12043 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
12044 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x214b
12045 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
12046 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x214c
12047 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
12048 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x214d
12049 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
12050 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x214e
12051 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
12052 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x214f
12053 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
12054 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2150
12055 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
12056 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2151
12057 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
12058 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2152
12059 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
12060 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2153
12061 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
12062 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2154
12063 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
12064 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2155
12065 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
12066 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2156
12067 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
12068 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2157
12069 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
12070 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2158
12071 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
12072 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2159
12073 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
12074 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x215a
12075 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
12076 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x215b
12077 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
12078 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x215c
12079 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
12080 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x215d
12081 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
12082 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x215e
12083 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
12084 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x215f
12085 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
12086 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2160
12087 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
12088 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2161
12089 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
12090 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2162
12091 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
12092 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2163
12093 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
12094 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2164
12095 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
12096 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2165
12097 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
12098 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2166
12099 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
12100 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2167
12101 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
12102 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2168
12103 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
12104 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2169
12105 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
12106 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x216a
12107 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
12108 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x216b
12109 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
12110 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x216c
12111 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
12112 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x216d
12113 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
12114 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x216e
12115 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
12116 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x216f
12117 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
12118 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2170
12119 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
12120 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2171
12121 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
12122 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2172
12123 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
12124 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2173
12125 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
12126 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2174
12127 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
12128 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2175
12129 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
12130 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2176
12131 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
12132 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2177
12133 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
12134 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58                                                    0x2178
12135 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX                                           2
12136 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59                                                    0x2179
12137 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX                                           2
12138 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60                                                    0x217a
12139 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX                                           2
12140 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61                                                    0x217b
12141 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX                                           2
12142 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62                                                    0x217c
12143 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX                                           2
12144 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63                                                    0x217d
12145 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX                                           2
12146 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64                                                    0x217e
12147 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX                                           2
12148 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65                                                    0x217f
12149 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX                                           2
12150 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66                                                    0x2180
12151 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX                                           2
12152 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67                                                    0x2181
12153 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX                                           2
12154 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68                                                    0x2182
12155 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX                                           2
12156 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69                                                    0x2183
12157 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX                                           2
12158 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70                                                    0x2184
12159 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX                                           2
12160 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71                                                    0x2185
12161 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX                                           2
12162 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72                                                    0x2186
12163 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX                                           2
12164 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73                                                    0x2187
12165 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX                                           2
12166 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74                                                    0x2188
12167 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX                                           2
12168 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75                                                    0x2189
12169 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX                                           2
12170 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76                                                    0x218a
12171 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX                                           2
12172 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77                                                    0x218b
12173 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX                                           2
12174 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78                                                    0x218c
12175 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX                                           2
12176 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79                                                    0x218d
12177 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX                                           2
12178 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80                                                    0x218e
12179 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX                                           2
12180 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81                                                    0x218f
12181 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX                                           2
12182 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82                                                    0x2190
12183 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX                                           2
12184 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83                                                    0x2191
12185 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX                                           2
12186 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84                                                    0x2192
12187 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX                                           2
12188 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85                                                    0x2193
12189 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX                                           2
12190 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86                                                    0x2194
12191 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX                                           2
12192 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87                                                    0x2195
12193 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX                                           2
12194 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88                                                    0x2196
12195 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX                                           2
12196 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89                                                    0x2197
12197 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX                                           2
12198 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90                                                    0x2198
12199 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX                                           2
12200 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91                                                    0x2199
12201 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX                                           2
12202 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92                                                    0x219a
12203 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX                                           2
12204 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93                                                    0x219b
12205 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX                                           2
12206 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94                                                    0x219c
12207 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX                                           2
12208 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95                                                    0x219d
12209 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX                                           2
12210 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96                                                    0x219e
12211 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX                                           2
12212 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97                                                    0x219f
12213 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX                                           2
12214 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98                                                    0x21a0
12215 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX                                           2
12216 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99                                                    0x21a1
12217 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX                                           2
12218 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100                                                   0x21a2
12219 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX                                          2
12220 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101                                                   0x21a3
12221 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX                                          2
12222 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102                                                   0x21a4
12223 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX                                          2
12224 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103                                                   0x21a5
12225 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX                                          2
12226 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104                                                   0x21a6
12227 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX                                          2
12228 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105                                                   0x21a7
12229 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX                                          2
12230 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106                                                   0x21a8
12231 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX                                          2
12232 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107                                                   0x21a9
12233 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX                                          2
12234 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108                                                   0x21aa
12235 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX                                          2
12236 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109                                                   0x21ab
12237 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX                                          2
12238 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110                                                   0x21ac
12239 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX                                          2
12240 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111                                                   0x21ad
12241 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX                                          2
12242 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112                                                   0x21ae
12243 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX                                          2
12244 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113                                                   0x21af
12245 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX                                          2
12246 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114                                                   0x21b0
12247 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX                                          2
12248 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115                                                   0x21b1
12249 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX                                          2
12250 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116                                                   0x21b2
12251 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX                                          2
12252 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117                                                   0x21b3
12253 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX                                          2
12254 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118                                                   0x21b4
12255 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX                                          2
12256 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119                                                   0x21b5
12257 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX                                          2
12258 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120                                                   0x21b6
12259 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX                                          2
12260 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121                                                   0x21b7
12261 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX                                          2
12262 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122                                                   0x21b8
12263 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX                                          2
12264 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123                                                   0x21b9
12265 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX                                          2
12266 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124                                                   0x21ba
12267 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX                                          2
12268 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125                                                   0x21bb
12269 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX                                          2
12270 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126                                                   0x21bc
12271 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX                                          2
12272 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127                                                   0x21bd
12273 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX                                          2
12274 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128                                                   0x21be
12275 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX                                          2
12276 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129                                                   0x21bf
12277 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX                                          2
12278 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130                                                   0x21c0
12279 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX                                          2
12280 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131                                                   0x21c1
12281 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX                                          2
12282 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132                                                   0x21c2
12283 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX                                          2
12284 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133                                                   0x21c3
12285 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX                                          2
12286 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134                                                   0x21c4
12287 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX                                          2
12288 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135                                                   0x21c5
12289 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX                                          2
12290 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136                                                   0x21c6
12291 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX                                          2
12292 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137                                                   0x21c7
12293 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX                                          2
12294 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138                                                   0x21c8
12295 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX                                          2
12296 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139                                                   0x21c9
12297 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX                                          2
12298 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140                                                   0x21ca
12299 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX                                          2
12300 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141                                                   0x21cb
12301 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX                                          2
12302 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142                                                   0x21cc
12303 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX                                          2
12304 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143                                                   0x21cd
12305 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX                                          2
12306 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144                                                   0x21ce
12307 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX                                          2
12308 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145                                                   0x21cf
12309 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX                                          2
12310 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146                                                   0x21d0
12311 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX                                          2
12312 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147                                                   0x21d1
12313 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX                                          2
12314 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148                                                   0x21d2
12315 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX                                          2
12316 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149                                                   0x21d3
12317 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX                                          2
12318 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150                                                   0x21d4
12319 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX                                          2
12320 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151                                                   0x21d5
12321 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX                                          2
12322 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152                                                   0x21d6
12323 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX                                          2
12324 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153                                                   0x21d7
12325 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX                                          2
12326 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154                                                   0x21d8
12327 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX                                          2
12328 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155                                                   0x21d9
12329 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX                                          2
12330 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156                                                   0x21da
12331 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX                                          2
12332 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157                                                   0x21db
12333 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX                                          2
12334 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158                                                   0x21dc
12335 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX                                          2
12336 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159                                                   0x21dd
12337 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX                                          2
12338 
12339 
12340 // addressBlock: dce_dc_dc_combophycmregs0_dispdec
12341 // base address: 0x0
12342 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1                                                              0x213e
12343 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX                                                     2
12344 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2                                                              0x213f
12345 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX                                                     2
12346 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3                                                              0x2140
12347 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX                                                     2
12348 #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM                                                     0x2141
12349 #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX                                            2
12350 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT                                                       0x2142
12351 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX                                              2
12352 #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL                                                            0x2143
12353 #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX                                                   2
12354 #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP                                                               0x2144
12355 #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX                                                      2
12356 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS                                                        0x2145
12357 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX                                               2
12358 #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL                                                      0x2146
12359 #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX                                             2
12360 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1                                                          0x2147
12361 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX                                                 2
12362 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2                                                          0x2148
12363 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX                                                 2
12364 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3                                                          0x2149
12365 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX                                                 2
12366 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4                                                          0x214a
12367 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX                                                 2
12368 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5                                                          0x214b
12369 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX                                                 2
12370 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6                                                          0x214c
12371 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX                                                 2
12372 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7                                                          0x214d
12373 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX                                                 2
12374 
12375 
12376 // addressBlock: dce_dc_dc_combophytxregs0_dispdec
12377 // base address: 0x0
12378 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0                                                  0x215e
12379 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX                                         2
12380 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0                                                       0x215f
12381 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX                                              2
12382 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0                                               0x2160
12383 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX                                      2
12384 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0                                                        0x2161
12385 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX                                               2
12386 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0                                                        0x2162
12387 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX                                               2
12388 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0                                                        0x2163
12389 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX                                               2
12390 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0                                                        0x2164
12391 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX                                               2
12392 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0                                                        0x2165
12393 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX                                               2
12394 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0                                                        0x2166
12395 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX                                               2
12396 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0                                                        0x2167
12397 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX                                               2
12398 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0                                                        0x2168
12399 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX                                               2
12400 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0                                                        0x2169
12401 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX                                               2
12402 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0                                                        0x216a
12403 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX                                               2
12404 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0                                                       0x216b
12405 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX                                              2
12406 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0                                                       0x216c
12407 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX                                              2
12408 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0                                                       0x216d
12409 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX                                              2
12410 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1                                                  0x216e
12411 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX                                         2
12412 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1                                                       0x216f
12413 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX                                              2
12414 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1                                               0x2170
12415 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX                                      2
12416 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1                                                        0x2171
12417 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX                                               2
12418 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1                                                        0x2172
12419 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX                                               2
12420 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1                                                        0x2173
12421 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX                                               2
12422 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1                                                        0x2174
12423 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX                                               2
12424 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1                                                        0x2175
12425 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX                                               2
12426 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1                                                        0x2176
12427 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX                                               2
12428 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1                                                        0x2177
12429 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX                                               2
12430 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1                                                        0x2178
12431 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX                                               2
12432 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1                                                        0x2179
12433 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX                                               2
12434 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1                                                        0x217a
12435 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX                                               2
12436 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1                                                       0x217b
12437 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX                                              2
12438 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1                                                       0x217c
12439 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX                                              2
12440 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1                                                       0x217d
12441 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX                                              2
12442 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2                                                  0x217e
12443 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX                                         2
12444 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2                                                       0x217f
12445 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX                                              2
12446 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2                                               0x2180
12447 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX                                      2
12448 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2                                                        0x2181
12449 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX                                               2
12450 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2                                                        0x2182
12451 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX                                               2
12452 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2                                                        0x2183
12453 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX                                               2
12454 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2                                                        0x2184
12455 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX                                               2
12456 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2                                                        0x2185
12457 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX                                               2
12458 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2                                                        0x2186
12459 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX                                               2
12460 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2                                                        0x2187
12461 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX                                               2
12462 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2                                                        0x2188
12463 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX                                               2
12464 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2                                                        0x2189
12465 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX                                               2
12466 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2                                                        0x218a
12467 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX                                               2
12468 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2                                                       0x218b
12469 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX                                              2
12470 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2                                                       0x218c
12471 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX                                              2
12472 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2                                                       0x218d
12473 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX                                              2
12474 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3                                                  0x218e
12475 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX                                         2
12476 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3                                                       0x218f
12477 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX                                              2
12478 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3                                               0x2190
12479 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX                                      2
12480 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3                                                        0x2191
12481 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX                                               2
12482 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3                                                        0x2192
12483 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX                                               2
12484 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3                                                        0x2193
12485 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX                                               2
12486 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3                                                        0x2194
12487 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX                                               2
12488 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3                                                        0x2195
12489 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX                                               2
12490 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3                                                        0x2196
12491 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX                                               2
12492 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3                                                        0x2197
12493 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX                                               2
12494 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3                                                        0x2198
12495 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX                                               2
12496 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3                                                        0x2199
12497 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX                                               2
12498 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3                                                        0x219a
12499 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX                                               2
12500 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3                                                       0x219b
12501 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX                                              2
12502 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3                                                       0x219c
12503 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX                                              2
12504 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3                                                       0x219d
12505 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX                                              2
12506 
12507 
12508 // addressBlock: dce_dc_dc_combophypllregs0_dispdec
12509 // base address: 0x0
12510 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0                                                               0x219e
12511 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX                                                      2
12512 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1                                                               0x219f
12513 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX                                                      2
12514 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2                                                               0x21a0
12515 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX                                                      2
12516 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3                                                               0x21a1
12517 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX                                                      2
12518 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE                                                           0x21a2
12519 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX                                                  2
12520 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE                                                             0x21a3
12521 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX                                                    2
12522 #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL                                                                 0x21a4
12523 #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX                                                        2
12524 #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL                                                                0x21a5
12525 #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX                                                       2
12526 #define mmDC_COMBOPHYPLLREGS0_VREG_CFG                                                                 0x21a7
12527 #define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX                                                        2
12528 #define mmDC_COMBOPHYPLLREGS0_OBSERVE0                                                                 0x21a8
12529 #define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX                                                        2
12530 #define mmDC_COMBOPHYPLLREGS0_OBSERVE1                                                                 0x21a9
12531 #define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX                                                        2
12532 #define mmDC_COMBOPHYPLLREGS0_DFT_OUT                                                                  0x21aa
12533 #define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX                                                         2
12534 
12535 
12536 // addressBlock: dce_dc_dcio_uniphy1_dispdec
12537 // base address: 0x320
12538 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2206
12539 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
12540 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2207
12541 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
12542 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2208
12543 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
12544 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2209
12545 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
12546 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x220a
12547 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
12548 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x220b
12549 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
12550 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x220c
12551 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
12552 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x220d
12553 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
12554 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x220e
12555 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
12556 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x220f
12557 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
12558 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2210
12559 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
12560 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2211
12561 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
12562 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2212
12563 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
12564 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2213
12565 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
12566 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2214
12567 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
12568 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2215
12569 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
12570 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2216
12571 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
12572 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2217
12573 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
12574 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2218
12575 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
12576 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2219
12577 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
12578 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x221a
12579 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
12580 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x221b
12581 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
12582 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x221c
12583 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
12584 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x221d
12585 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
12586 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x221e
12587 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
12588 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x221f
12589 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
12590 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2220
12591 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
12592 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2221
12593 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
12594 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2222
12595 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
12596 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2223
12597 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
12598 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2224
12599 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
12600 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2225
12601 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
12602 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2226
12603 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
12604 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2227
12605 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
12606 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2228
12607 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
12608 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2229
12609 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
12610 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x222a
12611 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
12612 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x222b
12613 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
12614 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x222c
12615 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
12616 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x222d
12617 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
12618 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x222e
12619 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
12620 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x222f
12621 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
12622 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2230
12623 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
12624 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2231
12625 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
12626 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2232
12627 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
12628 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2233
12629 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
12630 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2234
12631 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
12632 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2235
12633 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
12634 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2236
12635 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
12636 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2237
12637 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
12638 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2238
12639 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
12640 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2239
12641 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
12642 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x223a
12643 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
12644 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x223b
12645 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
12646 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x223c
12647 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
12648 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x223d
12649 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
12650 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x223e
12651 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
12652 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x223f
12653 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
12654 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58                                                    0x2240
12655 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX                                           2
12656 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59                                                    0x2241
12657 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX                                           2
12658 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60                                                    0x2242
12659 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX                                           2
12660 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61                                                    0x2243
12661 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX                                           2
12662 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62                                                    0x2244
12663 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX                                           2
12664 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63                                                    0x2245
12665 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX                                           2
12666 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64                                                    0x2246
12667 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX                                           2
12668 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65                                                    0x2247
12669 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX                                           2
12670 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66                                                    0x2248
12671 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX                                           2
12672 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67                                                    0x2249
12673 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX                                           2
12674 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68                                                    0x224a
12675 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX                                           2
12676 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69                                                    0x224b
12677 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX                                           2
12678 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70                                                    0x224c
12679 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX                                           2
12680 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71                                                    0x224d
12681 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX                                           2
12682 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72                                                    0x224e
12683 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX                                           2
12684 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73                                                    0x224f
12685 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX                                           2
12686 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74                                                    0x2250
12687 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX                                           2
12688 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75                                                    0x2251
12689 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX                                           2
12690 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76                                                    0x2252
12691 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX                                           2
12692 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77                                                    0x2253
12693 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX                                           2
12694 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78                                                    0x2254
12695 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX                                           2
12696 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79                                                    0x2255
12697 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX                                           2
12698 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80                                                    0x2256
12699 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX                                           2
12700 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81                                                    0x2257
12701 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX                                           2
12702 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82                                                    0x2258
12703 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX                                           2
12704 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83                                                    0x2259
12705 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX                                           2
12706 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84                                                    0x225a
12707 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX                                           2
12708 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85                                                    0x225b
12709 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX                                           2
12710 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86                                                    0x225c
12711 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX                                           2
12712 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87                                                    0x225d
12713 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX                                           2
12714 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88                                                    0x225e
12715 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX                                           2
12716 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89                                                    0x225f
12717 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX                                           2
12718 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90                                                    0x2260
12719 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX                                           2
12720 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91                                                    0x2261
12721 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX                                           2
12722 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92                                                    0x2262
12723 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX                                           2
12724 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93                                                    0x2263
12725 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX                                           2
12726 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94                                                    0x2264
12727 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX                                           2
12728 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95                                                    0x2265
12729 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX                                           2
12730 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96                                                    0x2266
12731 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX                                           2
12732 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97                                                    0x2267
12733 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX                                           2
12734 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98                                                    0x2268
12735 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX                                           2
12736 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99                                                    0x2269
12737 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX                                           2
12738 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100                                                   0x226a
12739 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX                                          2
12740 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101                                                   0x226b
12741 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX                                          2
12742 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102                                                   0x226c
12743 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX                                          2
12744 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103                                                   0x226d
12745 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX                                          2
12746 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104                                                   0x226e
12747 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX                                          2
12748 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105                                                   0x226f
12749 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX                                          2
12750 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106                                                   0x2270
12751 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX                                          2
12752 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107                                                   0x2271
12753 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX                                          2
12754 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108                                                   0x2272
12755 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX                                          2
12756 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109                                                   0x2273
12757 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX                                          2
12758 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110                                                   0x2274
12759 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX                                          2
12760 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111                                                   0x2275
12761 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX                                          2
12762 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112                                                   0x2276
12763 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX                                          2
12764 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113                                                   0x2277
12765 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX                                          2
12766 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114                                                   0x2278
12767 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX                                          2
12768 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115                                                   0x2279
12769 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX                                          2
12770 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116                                                   0x227a
12771 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX                                          2
12772 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117                                                   0x227b
12773 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX                                          2
12774 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118                                                   0x227c
12775 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX                                          2
12776 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119                                                   0x227d
12777 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX                                          2
12778 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120                                                   0x227e
12779 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX                                          2
12780 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121                                                   0x227f
12781 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX                                          2
12782 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122                                                   0x2280
12783 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX                                          2
12784 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123                                                   0x2281
12785 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX                                          2
12786 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124                                                   0x2282
12787 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX                                          2
12788 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125                                                   0x2283
12789 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX                                          2
12790 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126                                                   0x2284
12791 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX                                          2
12792 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127                                                   0x2285
12793 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX                                          2
12794 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128                                                   0x2286
12795 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX                                          2
12796 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129                                                   0x2287
12797 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX                                          2
12798 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130                                                   0x2288
12799 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX                                          2
12800 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131                                                   0x2289
12801 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX                                          2
12802 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132                                                   0x228a
12803 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX                                          2
12804 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133                                                   0x228b
12805 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX                                          2
12806 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134                                                   0x228c
12807 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX                                          2
12808 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135                                                   0x228d
12809 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX                                          2
12810 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136                                                   0x228e
12811 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX                                          2
12812 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137                                                   0x228f
12813 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX                                          2
12814 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138                                                   0x2290
12815 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX                                          2
12816 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139                                                   0x2291
12817 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX                                          2
12818 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140                                                   0x2292
12819 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX                                          2
12820 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141                                                   0x2293
12821 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX                                          2
12822 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142                                                   0x2294
12823 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX                                          2
12824 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143                                                   0x2295
12825 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX                                          2
12826 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144                                                   0x2296
12827 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX                                          2
12828 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145                                                   0x2297
12829 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX                                          2
12830 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146                                                   0x2298
12831 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX                                          2
12832 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147                                                   0x2299
12833 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX                                          2
12834 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148                                                   0x229a
12835 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX                                          2
12836 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149                                                   0x229b
12837 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX                                          2
12838 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150                                                   0x229c
12839 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX                                          2
12840 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151                                                   0x229d
12841 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX                                          2
12842 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152                                                   0x229e
12843 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX                                          2
12844 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153                                                   0x229f
12845 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX                                          2
12846 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154                                                   0x22a0
12847 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX                                          2
12848 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155                                                   0x22a1
12849 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX                                          2
12850 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156                                                   0x22a2
12851 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX                                          2
12852 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157                                                   0x22a3
12853 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX                                          2
12854 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158                                                   0x22a4
12855 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX                                          2
12856 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159                                                   0x22a5
12857 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX                                          2
12858 
12859 
12860 // addressBlock: dce_dc_dc_combophycmregs1_dispdec
12861 // base address: 0x320
12862 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1                                                              0x2206
12863 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX                                                     2
12864 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2                                                              0x2207
12865 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX                                                     2
12866 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3                                                              0x2208
12867 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX                                                     2
12868 #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM                                                     0x2209
12869 #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX                                            2
12870 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT                                                       0x220a
12871 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX                                              2
12872 #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL                                                            0x220b
12873 #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX                                                   2
12874 #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP                                                               0x220c
12875 #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX                                                      2
12876 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS                                                        0x220d
12877 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX                                               2
12878 #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL                                                      0x220e
12879 #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX                                             2
12880 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1                                                          0x220f
12881 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX                                                 2
12882 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2                                                          0x2210
12883 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX                                                 2
12884 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3                                                          0x2211
12885 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX                                                 2
12886 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4                                                          0x2212
12887 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX                                                 2
12888 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5                                                          0x2213
12889 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX                                                 2
12890 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6                                                          0x2214
12891 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX                                                 2
12892 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7                                                          0x2215
12893 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX                                                 2
12894 
12895 
12896 // addressBlock: dce_dc_dc_combophytxregs1_dispdec
12897 // base address: 0x320
12898 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0                                                  0x2226
12899 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX                                         2
12900 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0                                                       0x2227
12901 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX                                              2
12902 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0                                               0x2228
12903 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX                                      2
12904 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0                                                        0x2229
12905 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX                                               2
12906 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0                                                        0x222a
12907 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX                                               2
12908 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0                                                        0x222b
12909 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX                                               2
12910 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0                                                        0x222c
12911 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX                                               2
12912 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0                                                        0x222d
12913 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX                                               2
12914 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0                                                        0x222e
12915 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX                                               2
12916 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0                                                        0x222f
12917 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX                                               2
12918 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0                                                        0x2230
12919 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX                                               2
12920 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0                                                        0x2231
12921 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX                                               2
12922 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0                                                        0x2232
12923 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX                                               2
12924 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0                                                       0x2233
12925 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX                                              2
12926 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0                                                       0x2234
12927 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX                                              2
12928 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0                                                       0x2235
12929 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX                                              2
12930 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1                                                  0x2236
12931 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX                                         2
12932 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1                                                       0x2237
12933 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX                                              2
12934 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1                                               0x2238
12935 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX                                      2
12936 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1                                                        0x2239
12937 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX                                               2
12938 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1                                                        0x223a
12939 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX                                               2
12940 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1                                                        0x223b
12941 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX                                               2
12942 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1                                                        0x223c
12943 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX                                               2
12944 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1                                                        0x223d
12945 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX                                               2
12946 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1                                                        0x223e
12947 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX                                               2
12948 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1                                                        0x223f
12949 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX                                               2
12950 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1                                                        0x2240
12951 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX                                               2
12952 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1                                                        0x2241
12953 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX                                               2
12954 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1                                                        0x2242
12955 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX                                               2
12956 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1                                                       0x2243
12957 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX                                              2
12958 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1                                                       0x2244
12959 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX                                              2
12960 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1                                                       0x2245
12961 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX                                              2
12962 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2                                                  0x2246
12963 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX                                         2
12964 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2                                                       0x2247
12965 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX                                              2
12966 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2                                               0x2248
12967 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX                                      2
12968 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2                                                        0x2249
12969 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX                                               2
12970 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2                                                        0x224a
12971 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX                                               2
12972 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2                                                        0x224b
12973 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX                                               2
12974 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2                                                        0x224c
12975 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX                                               2
12976 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2                                                        0x224d
12977 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX                                               2
12978 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2                                                        0x224e
12979 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX                                               2
12980 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2                                                        0x224f
12981 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX                                               2
12982 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2                                                        0x2250
12983 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX                                               2
12984 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2                                                        0x2251
12985 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX                                               2
12986 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2                                                        0x2252
12987 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX                                               2
12988 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2                                                       0x2253
12989 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX                                              2
12990 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2                                                       0x2254
12991 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX                                              2
12992 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2                                                       0x2255
12993 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX                                              2
12994 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3                                                  0x2256
12995 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX                                         2
12996 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3                                                       0x2257
12997 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX                                              2
12998 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3                                               0x2258
12999 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX                                      2
13000 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3                                                        0x2259
13001 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX                                               2
13002 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3                                                        0x225a
13003 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX                                               2
13004 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3                                                        0x225b
13005 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX                                               2
13006 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3                                                        0x225c
13007 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX                                               2
13008 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3                                                        0x225d
13009 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX                                               2
13010 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3                                                        0x225e
13011 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX                                               2
13012 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3                                                        0x225f
13013 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX                                               2
13014 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3                                                        0x2260
13015 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX                                               2
13016 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3                                                        0x2261
13017 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX                                               2
13018 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3                                                        0x2262
13019 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX                                               2
13020 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3                                                       0x2263
13021 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX                                              2
13022 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3                                                       0x2264
13023 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX                                              2
13024 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3                                                       0x2265
13025 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX                                              2
13026 
13027 
13028 // addressBlock: dce_dc_dc_combophypllregs1_dispdec
13029 // base address: 0x320
13030 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0                                                               0x2266
13031 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX                                                      2
13032 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1                                                               0x2267
13033 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX                                                      2
13034 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2                                                               0x2268
13035 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX                                                      2
13036 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3                                                               0x2269
13037 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX                                                      2
13038 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE                                                           0x226a
13039 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX                                                  2
13040 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE                                                             0x226b
13041 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX                                                    2
13042 #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL                                                                 0x226c
13043 #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX                                                        2
13044 #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL                                                                0x226d
13045 #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX                                                       2
13046 #define mmDC_COMBOPHYPLLREGS1_VREG_CFG                                                                 0x226f
13047 #define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX                                                        2
13048 #define mmDC_COMBOPHYPLLREGS1_OBSERVE0                                                                 0x2270
13049 #define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX                                                        2
13050 #define mmDC_COMBOPHYPLLREGS1_OBSERVE1                                                                 0x2271
13051 #define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX                                                        2
13052 #define mmDC_COMBOPHYPLLREGS1_DFT_OUT                                                                  0x2272
13053 #define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX                                                         2
13054 
13055 
13056 // addressBlock: dce_dc_dcio_uniphy2_dispdec
13057 // base address: 0x640
13058 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x22ce
13059 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
13060 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x22cf
13061 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
13062 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x22d0
13063 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
13064 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x22d1
13065 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
13066 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x22d2
13067 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
13068 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x22d3
13069 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
13070 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x22d4
13071 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
13072 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x22d5
13073 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
13074 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x22d6
13075 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
13076 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x22d7
13077 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
13078 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x22d8
13079 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
13080 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x22d9
13081 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
13082 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x22da
13083 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
13084 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x22db
13085 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
13086 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x22dc
13087 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
13088 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x22dd
13089 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
13090 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x22de
13091 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
13092 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x22df
13093 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
13094 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x22e0
13095 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
13096 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x22e1
13097 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
13098 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x22e2
13099 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
13100 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x22e3
13101 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
13102 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x22e4
13103 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
13104 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x22e5
13105 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
13106 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x22e6
13107 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
13108 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x22e7
13109 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
13110 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x22e8
13111 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
13112 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x22e9
13113 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
13114 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x22ea
13115 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
13116 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x22eb
13117 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
13118 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x22ec
13119 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
13120 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x22ed
13121 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
13122 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x22ee
13123 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
13124 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x22ef
13125 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
13126 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x22f0
13127 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
13128 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x22f1
13129 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
13130 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x22f2
13131 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
13132 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x22f3
13133 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
13134 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x22f4
13135 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
13136 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x22f5
13137 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
13138 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x22f6
13139 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
13140 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x22f7
13141 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
13142 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x22f8
13143 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
13144 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x22f9
13145 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
13146 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x22fa
13147 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
13148 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x22fb
13149 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
13150 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x22fc
13151 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
13152 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x22fd
13153 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
13154 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x22fe
13155 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
13156 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x22ff
13157 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
13158 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2300
13159 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
13160 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2301
13161 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
13162 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2302
13163 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
13164 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2303
13165 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
13166 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2304
13167 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
13168 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2305
13169 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
13170 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2306
13171 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
13172 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2307
13173 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
13174 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58                                                    0x2308
13175 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX                                           2
13176 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59                                                    0x2309
13177 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX                                           2
13178 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60                                                    0x230a
13179 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX                                           2
13180 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61                                                    0x230b
13181 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX                                           2
13182 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62                                                    0x230c
13183 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX                                           2
13184 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63                                                    0x230d
13185 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX                                           2
13186 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64                                                    0x230e
13187 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX                                           2
13188 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65                                                    0x230f
13189 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX                                           2
13190 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66                                                    0x2310
13191 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX                                           2
13192 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67                                                    0x2311
13193 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX                                           2
13194 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68                                                    0x2312
13195 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX                                           2
13196 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69                                                    0x2313
13197 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX                                           2
13198 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70                                                    0x2314
13199 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX                                           2
13200 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71                                                    0x2315
13201 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX                                           2
13202 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72                                                    0x2316
13203 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX                                           2
13204 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73                                                    0x2317
13205 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX                                           2
13206 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74                                                    0x2318
13207 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX                                           2
13208 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75                                                    0x2319
13209 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX                                           2
13210 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76                                                    0x231a
13211 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX                                           2
13212 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77                                                    0x231b
13213 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX                                           2
13214 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78                                                    0x231c
13215 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX                                           2
13216 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79                                                    0x231d
13217 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX                                           2
13218 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80                                                    0x231e
13219 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX                                           2
13220 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81                                                    0x231f
13221 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX                                           2
13222 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82                                                    0x2320
13223 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX                                           2
13224 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83                                                    0x2321
13225 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX                                           2
13226 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84                                                    0x2322
13227 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX                                           2
13228 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85                                                    0x2323
13229 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX                                           2
13230 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86                                                    0x2324
13231 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX                                           2
13232 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87                                                    0x2325
13233 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX                                           2
13234 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88                                                    0x2326
13235 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX                                           2
13236 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89                                                    0x2327
13237 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX                                           2
13238 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90                                                    0x2328
13239 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX                                           2
13240 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91                                                    0x2329
13241 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX                                           2
13242 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92                                                    0x232a
13243 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX                                           2
13244 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93                                                    0x232b
13245 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX                                           2
13246 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94                                                    0x232c
13247 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX                                           2
13248 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95                                                    0x232d
13249 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX                                           2
13250 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96                                                    0x232e
13251 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX                                           2
13252 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97                                                    0x232f
13253 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX                                           2
13254 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98                                                    0x2330
13255 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX                                           2
13256 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99                                                    0x2331
13257 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX                                           2
13258 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100                                                   0x2332
13259 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX                                          2
13260 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101                                                   0x2333
13261 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX                                          2
13262 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102                                                   0x2334
13263 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX                                          2
13264 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103                                                   0x2335
13265 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX                                          2
13266 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104                                                   0x2336
13267 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX                                          2
13268 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105                                                   0x2337
13269 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX                                          2
13270 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106                                                   0x2338
13271 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX                                          2
13272 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107                                                   0x2339
13273 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX                                          2
13274 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108                                                   0x233a
13275 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX                                          2
13276 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109                                                   0x233b
13277 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX                                          2
13278 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110                                                   0x233c
13279 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX                                          2
13280 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111                                                   0x233d
13281 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX                                          2
13282 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112                                                   0x233e
13283 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX                                          2
13284 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113                                                   0x233f
13285 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX                                          2
13286 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114                                                   0x2340
13287 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX                                          2
13288 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115                                                   0x2341
13289 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX                                          2
13290 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116                                                   0x2342
13291 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX                                          2
13292 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117                                                   0x2343
13293 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX                                          2
13294 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118                                                   0x2344
13295 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX                                          2
13296 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119                                                   0x2345
13297 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX                                          2
13298 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120                                                   0x2346
13299 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX                                          2
13300 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121                                                   0x2347
13301 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX                                          2
13302 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122                                                   0x2348
13303 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX                                          2
13304 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123                                                   0x2349
13305 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX                                          2
13306 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124                                                   0x234a
13307 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX                                          2
13308 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125                                                   0x234b
13309 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX                                          2
13310 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126                                                   0x234c
13311 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX                                          2
13312 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127                                                   0x234d
13313 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX                                          2
13314 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128                                                   0x234e
13315 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX                                          2
13316 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129                                                   0x234f
13317 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX                                          2
13318 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130                                                   0x2350
13319 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX                                          2
13320 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131                                                   0x2351
13321 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX                                          2
13322 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132                                                   0x2352
13323 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX                                          2
13324 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133                                                   0x2353
13325 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX                                          2
13326 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134                                                   0x2354
13327 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX                                          2
13328 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135                                                   0x2355
13329 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX                                          2
13330 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136                                                   0x2356
13331 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX                                          2
13332 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137                                                   0x2357
13333 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX                                          2
13334 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138                                                   0x2358
13335 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX                                          2
13336 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139                                                   0x2359
13337 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX                                          2
13338 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140                                                   0x235a
13339 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX                                          2
13340 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141                                                   0x235b
13341 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX                                          2
13342 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142                                                   0x235c
13343 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX                                          2
13344 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143                                                   0x235d
13345 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX                                          2
13346 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144                                                   0x235e
13347 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX                                          2
13348 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145                                                   0x235f
13349 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX                                          2
13350 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146                                                   0x2360
13351 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX                                          2
13352 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147                                                   0x2361
13353 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX                                          2
13354 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148                                                   0x2362
13355 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX                                          2
13356 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149                                                   0x2363
13357 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX                                          2
13358 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150                                                   0x2364
13359 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX                                          2
13360 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151                                                   0x2365
13361 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX                                          2
13362 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152                                                   0x2366
13363 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX                                          2
13364 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153                                                   0x2367
13365 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX                                          2
13366 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154                                                   0x2368
13367 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX                                          2
13368 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155                                                   0x2369
13369 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX                                          2
13370 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156                                                   0x236a
13371 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX                                          2
13372 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157                                                   0x236b
13373 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX                                          2
13374 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158                                                   0x236c
13375 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX                                          2
13376 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159                                                   0x236d
13377 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX                                          2
13378 
13379 
13380 // addressBlock: dce_dc_dc_combophycmregs2_dispdec
13381 // base address: 0x640
13382 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1                                                              0x22ce
13383 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX                                                     2
13384 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2                                                              0x22cf
13385 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX                                                     2
13386 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3                                                              0x22d0
13387 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX                                                     2
13388 #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM                                                     0x22d1
13389 #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX                                            2
13390 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT                                                       0x22d2
13391 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX                                              2
13392 #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL                                                            0x22d3
13393 #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX                                                   2
13394 #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP                                                               0x22d4
13395 #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX                                                      2
13396 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS                                                        0x22d5
13397 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX                                               2
13398 #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL                                                      0x22d6
13399 #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX                                             2
13400 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1                                                          0x22d7
13401 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX                                                 2
13402 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2                                                          0x22d8
13403 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX                                                 2
13404 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3                                                          0x22d9
13405 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX                                                 2
13406 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4                                                          0x22da
13407 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX                                                 2
13408 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5                                                          0x22db
13409 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX                                                 2
13410 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6                                                          0x22dc
13411 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX                                                 2
13412 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7                                                          0x22dd
13413 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX                                                 2
13414 
13415 
13416 // addressBlock: dce_dc_dc_combophytxregs2_dispdec
13417 // base address: 0x640
13418 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0                                                  0x22ee
13419 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX                                         2
13420 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0                                                       0x22ef
13421 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX                                              2
13422 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0                                               0x22f0
13423 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX                                      2
13424 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0                                                        0x22f1
13425 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX                                               2
13426 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0                                                        0x22f2
13427 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX                                               2
13428 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0                                                        0x22f3
13429 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX                                               2
13430 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0                                                        0x22f4
13431 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX                                               2
13432 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0                                                        0x22f5
13433 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX                                               2
13434 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0                                                        0x22f6
13435 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX                                               2
13436 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0                                                        0x22f7
13437 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX                                               2
13438 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0                                                        0x22f8
13439 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX                                               2
13440 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0                                                        0x22f9
13441 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX                                               2
13442 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0                                                        0x22fa
13443 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX                                               2
13444 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0                                                       0x22fb
13445 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX                                              2
13446 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0                                                       0x22fc
13447 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX                                              2
13448 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0                                                       0x22fd
13449 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX                                              2
13450 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1                                                  0x22fe
13451 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX                                         2
13452 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1                                                       0x22ff
13453 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX                                              2
13454 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1                                               0x2300
13455 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX                                      2
13456 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1                                                        0x2301
13457 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX                                               2
13458 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1                                                        0x2302
13459 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX                                               2
13460 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1                                                        0x2303
13461 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX                                               2
13462 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1                                                        0x2304
13463 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX                                               2
13464 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1                                                        0x2305
13465 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX                                               2
13466 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1                                                        0x2306
13467 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX                                               2
13468 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1                                                        0x2307
13469 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX                                               2
13470 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1                                                        0x2308
13471 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX                                               2
13472 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1                                                        0x2309
13473 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX                                               2
13474 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1                                                        0x230a
13475 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX                                               2
13476 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1                                                       0x230b
13477 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX                                              2
13478 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1                                                       0x230c
13479 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX                                              2
13480 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1                                                       0x230d
13481 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX                                              2
13482 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2                                                  0x230e
13483 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX                                         2
13484 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2                                                       0x230f
13485 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX                                              2
13486 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2                                               0x2310
13487 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX                                      2
13488 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2                                                        0x2311
13489 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX                                               2
13490 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2                                                        0x2312
13491 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX                                               2
13492 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2                                                        0x2313
13493 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX                                               2
13494 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2                                                        0x2314
13495 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX                                               2
13496 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2                                                        0x2315
13497 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX                                               2
13498 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2                                                        0x2316
13499 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX                                               2
13500 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2                                                        0x2317
13501 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX                                               2
13502 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2                                                        0x2318
13503 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX                                               2
13504 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2                                                        0x2319
13505 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX                                               2
13506 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2                                                        0x231a
13507 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX                                               2
13508 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2                                                       0x231b
13509 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX                                              2
13510 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2                                                       0x231c
13511 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX                                              2
13512 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2                                                       0x231d
13513 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX                                              2
13514 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3                                                  0x231e
13515 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX                                         2
13516 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3                                                       0x231f
13517 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX                                              2
13518 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3                                               0x2320
13519 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX                                      2
13520 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3                                                        0x2321
13521 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX                                               2
13522 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3                                                        0x2322
13523 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX                                               2
13524 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3                                                        0x2323
13525 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX                                               2
13526 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3                                                        0x2324
13527 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX                                               2
13528 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3                                                        0x2325
13529 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX                                               2
13530 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3                                                        0x2326
13531 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX                                               2
13532 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3                                                        0x2327
13533 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX                                               2
13534 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3                                                        0x2328
13535 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX                                               2
13536 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3                                                        0x2329
13537 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX                                               2
13538 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3                                                        0x232a
13539 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX                                               2
13540 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3                                                       0x232b
13541 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX                                              2
13542 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3                                                       0x232c
13543 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX                                              2
13544 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3                                                       0x232d
13545 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX                                              2
13546 
13547 
13548 // addressBlock: dce_dc_dc_combophypllregs2_dispdec
13549 // base address: 0x640
13550 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0                                                               0x232e
13551 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX                                                      2
13552 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1                                                               0x232f
13553 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX                                                      2
13554 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2                                                               0x2330
13555 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX                                                      2
13556 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3                                                               0x2331
13557 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX                                                      2
13558 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE                                                           0x2332
13559 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX                                                  2
13560 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE                                                             0x2333
13561 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX                                                    2
13562 #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL                                                                 0x2334
13563 #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX                                                        2
13564 #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL                                                                0x2335
13565 #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX                                                       2
13566 #define mmDC_COMBOPHYPLLREGS2_VREG_CFG                                                                 0x2337
13567 #define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX                                                        2
13568 #define mmDC_COMBOPHYPLLREGS2_OBSERVE0                                                                 0x2338
13569 #define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX                                                        2
13570 #define mmDC_COMBOPHYPLLREGS2_OBSERVE1                                                                 0x2339
13571 #define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX                                                        2
13572 #define mmDC_COMBOPHYPLLREGS2_DFT_OUT                                                                  0x233a
13573 #define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX                                                         2
13574 
13575 
13576 // addressBlock: dce_dc_dcio_uniphy3_dispdec
13577 // base address: 0x960
13578 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2396
13579 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
13580 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2397
13581 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
13582 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2398
13583 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
13584 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2399
13585 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
13586 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x239a
13587 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
13588 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x239b
13589 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
13590 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x239c
13591 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
13592 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x239d
13593 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
13594 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x239e
13595 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
13596 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x239f
13597 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
13598 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x23a0
13599 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
13600 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x23a1
13601 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
13602 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x23a2
13603 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
13604 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x23a3
13605 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
13606 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x23a4
13607 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
13608 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x23a5
13609 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
13610 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x23a6
13611 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
13612 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x23a7
13613 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
13614 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x23a8
13615 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
13616 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x23a9
13617 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
13618 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x23aa
13619 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
13620 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x23ab
13621 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
13622 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x23ac
13623 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
13624 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x23ad
13625 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
13626 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x23ae
13627 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
13628 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x23af
13629 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
13630 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x23b0
13631 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
13632 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x23b1
13633 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
13634 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x23b2
13635 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
13636 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x23b3
13637 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
13638 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x23b4
13639 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
13640 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x23b5
13641 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
13642 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x23b6
13643 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
13644 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x23b7
13645 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
13646 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x23b8
13647 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
13648 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x23b9
13649 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
13650 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x23ba
13651 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
13652 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x23bb
13653 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
13654 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x23bc
13655 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
13656 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x23bd
13657 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
13658 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x23be
13659 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
13660 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x23bf
13661 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
13662 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x23c0
13663 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
13664 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x23c1
13665 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
13666 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x23c2
13667 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
13668 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x23c3
13669 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
13670 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x23c4
13671 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
13672 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x23c5
13673 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
13674 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x23c6
13675 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
13676 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x23c7
13677 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
13678 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x23c8
13679 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
13680 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x23c9
13681 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
13682 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x23ca
13683 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
13684 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x23cb
13685 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
13686 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x23cc
13687 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
13688 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x23cd
13689 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
13690 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x23ce
13691 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
13692 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x23cf
13693 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
13694 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58                                                    0x23d0
13695 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX                                           2
13696 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59                                                    0x23d1
13697 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX                                           2
13698 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60                                                    0x23d2
13699 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX                                           2
13700 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61                                                    0x23d3
13701 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX                                           2
13702 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62                                                    0x23d4
13703 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX                                           2
13704 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63                                                    0x23d5
13705 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX                                           2
13706 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64                                                    0x23d6
13707 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX                                           2
13708 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65                                                    0x23d7
13709 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX                                           2
13710 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66                                                    0x23d8
13711 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX                                           2
13712 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67                                                    0x23d9
13713 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX                                           2
13714 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68                                                    0x23da
13715 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX                                           2
13716 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69                                                    0x23db
13717 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX                                           2
13718 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70                                                    0x23dc
13719 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX                                           2
13720 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71                                                    0x23dd
13721 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX                                           2
13722 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72                                                    0x23de
13723 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX                                           2
13724 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73                                                    0x23df
13725 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX                                           2
13726 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74                                                    0x23e0
13727 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX                                           2
13728 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75                                                    0x23e1
13729 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX                                           2
13730 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76                                                    0x23e2
13731 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX                                           2
13732 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77                                                    0x23e3
13733 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX                                           2
13734 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78                                                    0x23e4
13735 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX                                           2
13736 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79                                                    0x23e5
13737 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX                                           2
13738 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80                                                    0x23e6
13739 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX                                           2
13740 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81                                                    0x23e7
13741 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX                                           2
13742 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82                                                    0x23e8
13743 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX                                           2
13744 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83                                                    0x23e9
13745 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX                                           2
13746 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84                                                    0x23ea
13747 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX                                           2
13748 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85                                                    0x23eb
13749 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX                                           2
13750 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86                                                    0x23ec
13751 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX                                           2
13752 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87                                                    0x23ed
13753 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX                                           2
13754 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88                                                    0x23ee
13755 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX                                           2
13756 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89                                                    0x23ef
13757 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX                                           2
13758 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90                                                    0x23f0
13759 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX                                           2
13760 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91                                                    0x23f1
13761 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX                                           2
13762 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92                                                    0x23f2
13763 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX                                           2
13764 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93                                                    0x23f3
13765 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX                                           2
13766 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94                                                    0x23f4
13767 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX                                           2
13768 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95                                                    0x23f5
13769 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX                                           2
13770 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96                                                    0x23f6
13771 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX                                           2
13772 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97                                                    0x23f7
13773 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX                                           2
13774 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98                                                    0x23f8
13775 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX                                           2
13776 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99                                                    0x23f9
13777 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX                                           2
13778 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100                                                   0x23fa
13779 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX                                          2
13780 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101                                                   0x23fb
13781 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX                                          2
13782 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102                                                   0x23fc
13783 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX                                          2
13784 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103                                                   0x23fd
13785 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX                                          2
13786 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104                                                   0x23fe
13787 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX                                          2
13788 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105                                                   0x23ff
13789 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX                                          2
13790 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106                                                   0x2400
13791 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX                                          2
13792 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107                                                   0x2401
13793 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX                                          2
13794 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108                                                   0x2402
13795 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX                                          2
13796 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109                                                   0x2403
13797 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX                                          2
13798 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110                                                   0x2404
13799 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX                                          2
13800 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111                                                   0x2405
13801 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX                                          2
13802 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112                                                   0x2406
13803 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX                                          2
13804 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113                                                   0x2407
13805 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX                                          2
13806 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114                                                   0x2408
13807 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX                                          2
13808 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115                                                   0x2409
13809 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX                                          2
13810 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116                                                   0x240a
13811 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX                                          2
13812 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117                                                   0x240b
13813 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX                                          2
13814 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118                                                   0x240c
13815 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX                                          2
13816 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119                                                   0x240d
13817 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX                                          2
13818 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120                                                   0x240e
13819 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX                                          2
13820 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121                                                   0x240f
13821 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX                                          2
13822 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122                                                   0x2410
13823 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX                                          2
13824 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123                                                   0x2411
13825 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX                                          2
13826 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124                                                   0x2412
13827 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX                                          2
13828 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125                                                   0x2413
13829 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX                                          2
13830 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126                                                   0x2414
13831 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX                                          2
13832 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127                                                   0x2415
13833 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX                                          2
13834 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128                                                   0x2416
13835 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX                                          2
13836 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129                                                   0x2417
13837 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX                                          2
13838 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130                                                   0x2418
13839 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX                                          2
13840 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131                                                   0x2419
13841 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX                                          2
13842 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132                                                   0x241a
13843 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX                                          2
13844 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133                                                   0x241b
13845 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX                                          2
13846 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134                                                   0x241c
13847 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX                                          2
13848 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135                                                   0x241d
13849 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX                                          2
13850 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136                                                   0x241e
13851 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX                                          2
13852 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137                                                   0x241f
13853 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX                                          2
13854 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138                                                   0x2420
13855 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX                                          2
13856 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139                                                   0x2421
13857 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX                                          2
13858 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140                                                   0x2422
13859 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX                                          2
13860 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141                                                   0x2423
13861 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX                                          2
13862 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142                                                   0x2424
13863 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX                                          2
13864 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143                                                   0x2425
13865 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX                                          2
13866 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144                                                   0x2426
13867 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX                                          2
13868 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145                                                   0x2427
13869 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX                                          2
13870 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146                                                   0x2428
13871 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX                                          2
13872 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147                                                   0x2429
13873 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX                                          2
13874 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148                                                   0x242a
13875 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX                                          2
13876 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149                                                   0x242b
13877 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX                                          2
13878 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150                                                   0x242c
13879 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX                                          2
13880 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151                                                   0x242d
13881 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX                                          2
13882 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152                                                   0x242e
13883 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX                                          2
13884 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153                                                   0x242f
13885 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX                                          2
13886 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154                                                   0x2430
13887 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX                                          2
13888 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155                                                   0x2431
13889 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX                                          2
13890 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156                                                   0x2432
13891 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX                                          2
13892 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157                                                   0x2433
13893 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX                                          2
13894 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158                                                   0x2434
13895 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX                                          2
13896 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159                                                   0x2435
13897 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX                                          2
13898 
13899 
13900 // addressBlock: dce_dc_dc_combophycmregs3_dispdec
13901 // base address: 0x960
13902 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1                                                              0x2396
13903 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX                                                     2
13904 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2                                                              0x2397
13905 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX                                                     2
13906 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3                                                              0x2398
13907 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX                                                     2
13908 #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM                                                     0x2399
13909 #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX                                            2
13910 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT                                                       0x239a
13911 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX                                              2
13912 #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL                                                            0x239b
13913 #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX                                                   2
13914 #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP                                                               0x239c
13915 #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX                                                      2
13916 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS                                                        0x239d
13917 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX                                               2
13918 #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL                                                      0x239e
13919 #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX                                             2
13920 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1                                                          0x239f
13921 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX                                                 2
13922 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2                                                          0x23a0
13923 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX                                                 2
13924 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3                                                          0x23a1
13925 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX                                                 2
13926 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4                                                          0x23a2
13927 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX                                                 2
13928 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5                                                          0x23a3
13929 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX                                                 2
13930 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6                                                          0x23a4
13931 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX                                                 2
13932 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7                                                          0x23a5
13933 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX                                                 2
13934 
13935 
13936 // addressBlock: dce_dc_dc_combophytxregs3_dispdec
13937 // base address: 0x960
13938 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0                                                  0x23b6
13939 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX                                         2
13940 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0                                                       0x23b7
13941 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX                                              2
13942 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0                                               0x23b8
13943 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX                                      2
13944 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0                                                        0x23b9
13945 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX                                               2
13946 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0                                                        0x23ba
13947 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX                                               2
13948 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0                                                        0x23bb
13949 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX                                               2
13950 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0                                                        0x23bc
13951 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX                                               2
13952 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0                                                        0x23bd
13953 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX                                               2
13954 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0                                                        0x23be
13955 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX                                               2
13956 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0                                                        0x23bf
13957 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX                                               2
13958 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0                                                        0x23c0
13959 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX                                               2
13960 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0                                                        0x23c1
13961 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX                                               2
13962 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0                                                        0x23c2
13963 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX                                               2
13964 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0                                                       0x23c3
13965 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX                                              2
13966 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0                                                       0x23c4
13967 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX                                              2
13968 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0                                                       0x23c5
13969 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX                                              2
13970 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1                                                  0x23c6
13971 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX                                         2
13972 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1                                                       0x23c7
13973 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX                                              2
13974 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1                                               0x23c8
13975 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX                                      2
13976 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1                                                        0x23c9
13977 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX                                               2
13978 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1                                                        0x23ca
13979 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX                                               2
13980 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1                                                        0x23cb
13981 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX                                               2
13982 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1                                                        0x23cc
13983 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX                                               2
13984 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1                                                        0x23cd
13985 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX                                               2
13986 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1                                                        0x23ce
13987 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX                                               2
13988 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1                                                        0x23cf
13989 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX                                               2
13990 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1                                                        0x23d0
13991 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX                                               2
13992 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1                                                        0x23d1
13993 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX                                               2
13994 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1                                                        0x23d2
13995 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX                                               2
13996 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1                                                       0x23d3
13997 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX                                              2
13998 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1                                                       0x23d4
13999 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX                                              2
14000 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1                                                       0x23d5
14001 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX                                              2
14002 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2                                                  0x23d6
14003 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX                                         2
14004 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2                                                       0x23d7
14005 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX                                              2
14006 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2                                               0x23d8
14007 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX                                      2
14008 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2                                                        0x23d9
14009 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX                                               2
14010 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2                                                        0x23da
14011 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX                                               2
14012 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2                                                        0x23db
14013 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX                                               2
14014 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2                                                        0x23dc
14015 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX                                               2
14016 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2                                                        0x23dd
14017 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX                                               2
14018 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2                                                        0x23de
14019 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX                                               2
14020 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2                                                        0x23df
14021 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX                                               2
14022 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2                                                        0x23e0
14023 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX                                               2
14024 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2                                                        0x23e1
14025 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX                                               2
14026 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2                                                        0x23e2
14027 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX                                               2
14028 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2                                                       0x23e3
14029 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX                                              2
14030 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2                                                       0x23e4
14031 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX                                              2
14032 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2                                                       0x23e5
14033 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX                                              2
14034 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3                                                  0x23e6
14035 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX                                         2
14036 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3                                                       0x23e7
14037 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX                                              2
14038 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3                                               0x23e8
14039 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX                                      2
14040 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3                                                        0x23e9
14041 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX                                               2
14042 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3                                                        0x23ea
14043 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX                                               2
14044 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3                                                        0x23eb
14045 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX                                               2
14046 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3                                                        0x23ec
14047 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX                                               2
14048 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3                                                        0x23ed
14049 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX                                               2
14050 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3                                                        0x23ee
14051 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX                                               2
14052 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3                                                        0x23ef
14053 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX                                               2
14054 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3                                                        0x23f0
14055 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX                                               2
14056 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3                                                        0x23f1
14057 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX                                               2
14058 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3                                                        0x23f2
14059 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX                                               2
14060 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3                                                       0x23f3
14061 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX                                              2
14062 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3                                                       0x23f4
14063 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX                                              2
14064 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3                                                       0x23f5
14065 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX                                              2
14066 
14067 
14068 // addressBlock: dce_dc_dc_combophypllregs3_dispdec
14069 // base address: 0x960
14070 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0                                                               0x23f6
14071 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX                                                      2
14072 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1                                                               0x23f7
14073 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX                                                      2
14074 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2                                                               0x23f8
14075 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX                                                      2
14076 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3                                                               0x23f9
14077 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX                                                      2
14078 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE                                                           0x23fa
14079 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX                                                  2
14080 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE                                                             0x23fb
14081 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX                                                    2
14082 #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL                                                                 0x23fc
14083 #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX                                                        2
14084 #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL                                                                0x23fd
14085 #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX                                                       2
14086 #define mmDC_COMBOPHYPLLREGS3_VREG_CFG                                                                 0x23ff
14087 #define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX                                                        2
14088 #define mmDC_COMBOPHYPLLREGS3_OBSERVE0                                                                 0x2400
14089 #define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX                                                        2
14090 #define mmDC_COMBOPHYPLLREGS3_OBSERVE1                                                                 0x2401
14091 #define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX                                                        2
14092 #define mmDC_COMBOPHYPLLREGS3_DFT_OUT                                                                  0x2402
14093 #define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX                                                         2
14094 
14095 
14096 // addressBlock: dce_dc_dcio_uniphy4_dispdec
14097 // base address: 0xc80
14098 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x245e
14099 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
14100 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x245f
14101 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
14102 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2460
14103 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
14104 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2461
14105 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
14106 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2462
14107 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
14108 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2463
14109 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
14110 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2464
14111 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
14112 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2465
14113 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
14114 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2466
14115 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
14116 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2467
14117 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
14118 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2468
14119 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
14120 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2469
14121 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
14122 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x246a
14123 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
14124 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x246b
14125 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
14126 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x246c
14127 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
14128 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x246d
14129 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
14130 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x246e
14131 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
14132 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x246f
14133 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
14134 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2470
14135 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
14136 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2471
14137 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
14138 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2472
14139 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
14140 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2473
14141 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
14142 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2474
14143 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
14144 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2475
14145 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
14146 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2476
14147 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
14148 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2477
14149 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
14150 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2478
14151 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
14152 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2479
14153 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
14154 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x247a
14155 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
14156 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x247b
14157 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
14158 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x247c
14159 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
14160 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x247d
14161 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
14162 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x247e
14163 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
14164 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x247f
14165 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
14166 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2480
14167 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
14168 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2481
14169 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
14170 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2482
14171 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
14172 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2483
14173 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
14174 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2484
14175 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
14176 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2485
14177 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
14178 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2486
14179 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
14180 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2487
14181 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
14182 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2488
14183 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
14184 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2489
14185 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
14186 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x248a
14187 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
14188 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x248b
14189 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
14190 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x248c
14191 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
14192 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x248d
14193 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
14194 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x248e
14195 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
14196 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x248f
14197 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
14198 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2490
14199 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
14200 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2491
14201 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
14202 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2492
14203 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
14204 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2493
14205 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
14206 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2494
14207 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
14208 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2495
14209 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
14210 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2496
14211 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
14212 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2497
14213 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
14214 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58                                                    0x2498
14215 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX                                           2
14216 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59                                                    0x2499
14217 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX                                           2
14218 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60                                                    0x249a
14219 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX                                           2
14220 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61                                                    0x249b
14221 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX                                           2
14222 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62                                                    0x249c
14223 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX                                           2
14224 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63                                                    0x249d
14225 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX                                           2
14226 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64                                                    0x249e
14227 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX                                           2
14228 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65                                                    0x249f
14229 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX                                           2
14230 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66                                                    0x24a0
14231 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX                                           2
14232 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67                                                    0x24a1
14233 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX                                           2
14234 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68                                                    0x24a2
14235 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX                                           2
14236 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69                                                    0x24a3
14237 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX                                           2
14238 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70                                                    0x24a4
14239 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX                                           2
14240 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71                                                    0x24a5
14241 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX                                           2
14242 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72                                                    0x24a6
14243 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX                                           2
14244 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73                                                    0x24a7
14245 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX                                           2
14246 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74                                                    0x24a8
14247 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX                                           2
14248 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75                                                    0x24a9
14249 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX                                           2
14250 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76                                                    0x24aa
14251 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX                                           2
14252 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77                                                    0x24ab
14253 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX                                           2
14254 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78                                                    0x24ac
14255 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX                                           2
14256 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79                                                    0x24ad
14257 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX                                           2
14258 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80                                                    0x24ae
14259 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX                                           2
14260 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81                                                    0x24af
14261 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX                                           2
14262 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82                                                    0x24b0
14263 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX                                           2
14264 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83                                                    0x24b1
14265 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX                                           2
14266 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84                                                    0x24b2
14267 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX                                           2
14268 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85                                                    0x24b3
14269 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX                                           2
14270 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86                                                    0x24b4
14271 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX                                           2
14272 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87                                                    0x24b5
14273 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX                                           2
14274 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88                                                    0x24b6
14275 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX                                           2
14276 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89                                                    0x24b7
14277 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX                                           2
14278 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90                                                    0x24b8
14279 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX                                           2
14280 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91                                                    0x24b9
14281 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX                                           2
14282 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92                                                    0x24ba
14283 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX                                           2
14284 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93                                                    0x24bb
14285 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX                                           2
14286 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94                                                    0x24bc
14287 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX                                           2
14288 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95                                                    0x24bd
14289 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX                                           2
14290 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96                                                    0x24be
14291 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX                                           2
14292 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97                                                    0x24bf
14293 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX                                           2
14294 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98                                                    0x24c0
14295 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX                                           2
14296 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99                                                    0x24c1
14297 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX                                           2
14298 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100                                                   0x24c2
14299 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX                                          2
14300 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101                                                   0x24c3
14301 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX                                          2
14302 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102                                                   0x24c4
14303 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX                                          2
14304 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103                                                   0x24c5
14305 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX                                          2
14306 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104                                                   0x24c6
14307 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX                                          2
14308 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105                                                   0x24c7
14309 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX                                          2
14310 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106                                                   0x24c8
14311 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX                                          2
14312 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107                                                   0x24c9
14313 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX                                          2
14314 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108                                                   0x24ca
14315 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX                                          2
14316 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109                                                   0x24cb
14317 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX                                          2
14318 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110                                                   0x24cc
14319 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX                                          2
14320 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111                                                   0x24cd
14321 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX                                          2
14322 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112                                                   0x24ce
14323 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX                                          2
14324 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113                                                   0x24cf
14325 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX                                          2
14326 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114                                                   0x24d0
14327 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX                                          2
14328 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115                                                   0x24d1
14329 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX                                          2
14330 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116                                                   0x24d2
14331 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX                                          2
14332 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117                                                   0x24d3
14333 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX                                          2
14334 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118                                                   0x24d4
14335 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX                                          2
14336 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119                                                   0x24d5
14337 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX                                          2
14338 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120                                                   0x24d6
14339 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX                                          2
14340 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121                                                   0x24d7
14341 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX                                          2
14342 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122                                                   0x24d8
14343 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX                                          2
14344 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123                                                   0x24d9
14345 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX                                          2
14346 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124                                                   0x24da
14347 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX                                          2
14348 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125                                                   0x24db
14349 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX                                          2
14350 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126                                                   0x24dc
14351 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX                                          2
14352 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127                                                   0x24dd
14353 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX                                          2
14354 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128                                                   0x24de
14355 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX                                          2
14356 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129                                                   0x24df
14357 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX                                          2
14358 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130                                                   0x24e0
14359 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX                                          2
14360 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131                                                   0x24e1
14361 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX                                          2
14362 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132                                                   0x24e2
14363 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX                                          2
14364 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133                                                   0x24e3
14365 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX                                          2
14366 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134                                                   0x24e4
14367 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX                                          2
14368 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135                                                   0x24e5
14369 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX                                          2
14370 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136                                                   0x24e6
14371 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX                                          2
14372 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137                                                   0x24e7
14373 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX                                          2
14374 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138                                                   0x24e8
14375 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX                                          2
14376 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139                                                   0x24e9
14377 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX                                          2
14378 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140                                                   0x24ea
14379 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX                                          2
14380 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141                                                   0x24eb
14381 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX                                          2
14382 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142                                                   0x24ec
14383 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX                                          2
14384 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143                                                   0x24ed
14385 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX                                          2
14386 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144                                                   0x24ee
14387 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX                                          2
14388 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145                                                   0x24ef
14389 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX                                          2
14390 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146                                                   0x24f0
14391 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX                                          2
14392 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147                                                   0x24f1
14393 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX                                          2
14394 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148                                                   0x24f2
14395 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX                                          2
14396 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149                                                   0x24f3
14397 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX                                          2
14398 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150                                                   0x24f4
14399 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX                                          2
14400 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151                                                   0x24f5
14401 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX                                          2
14402 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152                                                   0x24f6
14403 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX                                          2
14404 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153                                                   0x24f7
14405 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX                                          2
14406 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154                                                   0x24f8
14407 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX                                          2
14408 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155                                                   0x24f9
14409 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX                                          2
14410 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156                                                   0x24fa
14411 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX                                          2
14412 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157                                                   0x24fb
14413 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX                                          2
14414 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158                                                   0x24fc
14415 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX                                          2
14416 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159                                                   0x24fd
14417 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX                                          2
14418 
14419 
14420 // addressBlock: dce_dc_dc_combophycmregs4_dispdec
14421 // base address: 0xc80
14422 #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1                                                              0x245e
14423 #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_BASE_IDX                                                     2
14424 #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2                                                              0x245f
14425 #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_BASE_IDX                                                     2
14426 #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3                                                              0x2460
14427 #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_BASE_IDX                                                     2
14428 #define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM                                                     0x2461
14429 #define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_BASE_IDX                                            2
14430 #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT                                                       0x2462
14431 #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_BASE_IDX                                              2
14432 #define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL                                                            0x2463
14433 #define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_BASE_IDX                                                   2
14434 #define mmDC_COMBOPHYCMREGS4_COMMON_TMDP                                                               0x2464
14435 #define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_BASE_IDX                                                      2
14436 #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS                                                        0x2465
14437 #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_BASE_IDX                                               2
14438 #define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL                                                      0x2466
14439 #define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_BASE_IDX                                             2
14440 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1                                                          0x2467
14441 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_BASE_IDX                                                 2
14442 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2                                                          0x2468
14443 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_BASE_IDX                                                 2
14444 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3                                                          0x2469
14445 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_BASE_IDX                                                 2
14446 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4                                                          0x246a
14447 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_BASE_IDX                                                 2
14448 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5                                                          0x246b
14449 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_BASE_IDX                                                 2
14450 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6                                                          0x246c
14451 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_BASE_IDX                                                 2
14452 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7                                                          0x246d
14453 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_BASE_IDX                                                 2
14454 
14455 
14456 // addressBlock: dce_dc_dc_combophytxregs4_dispdec
14457 // base address: 0xc80
14458 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0                                                  0x247e
14459 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX                                         2
14460 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0                                                       0x247f
14461 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_BASE_IDX                                              2
14462 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0                                               0x2480
14463 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX                                      2
14464 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0                                                        0x2481
14465 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_BASE_IDX                                               2
14466 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0                                                        0x2482
14467 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_BASE_IDX                                               2
14468 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0                                                        0x2483
14469 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_BASE_IDX                                               2
14470 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0                                                        0x2484
14471 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_BASE_IDX                                               2
14472 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0                                                        0x2485
14473 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_BASE_IDX                                               2
14474 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0                                                        0x2486
14475 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_BASE_IDX                                               2
14476 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0                                                        0x2487
14477 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_BASE_IDX                                               2
14478 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0                                                        0x2488
14479 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_BASE_IDX                                               2
14480 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0                                                        0x2489
14481 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_BASE_IDX                                               2
14482 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0                                                        0x248a
14483 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_BASE_IDX                                               2
14484 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0                                                       0x248b
14485 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_BASE_IDX                                              2
14486 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0                                                       0x248c
14487 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_BASE_IDX                                              2
14488 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0                                                       0x248d
14489 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_BASE_IDX                                              2
14490 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1                                                  0x248e
14491 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX                                         2
14492 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1                                                       0x248f
14493 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_BASE_IDX                                              2
14494 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1                                               0x2490
14495 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX                                      2
14496 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1                                                        0x2491
14497 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_BASE_IDX                                               2
14498 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1                                                        0x2492
14499 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_BASE_IDX                                               2
14500 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1                                                        0x2493
14501 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_BASE_IDX                                               2
14502 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1                                                        0x2494
14503 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_BASE_IDX                                               2
14504 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1                                                        0x2495
14505 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_BASE_IDX                                               2
14506 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1                                                        0x2496
14507 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_BASE_IDX                                               2
14508 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1                                                        0x2497
14509 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_BASE_IDX                                               2
14510 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1                                                        0x2498
14511 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_BASE_IDX                                               2
14512 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1                                                        0x2499
14513 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_BASE_IDX                                               2
14514 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1                                                        0x249a
14515 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_BASE_IDX                                               2
14516 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1                                                       0x249b
14517 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_BASE_IDX                                              2
14518 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1                                                       0x249c
14519 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_BASE_IDX                                              2
14520 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1                                                       0x249d
14521 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_BASE_IDX                                              2
14522 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2                                                  0x249e
14523 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX                                         2
14524 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2                                                       0x249f
14525 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_BASE_IDX                                              2
14526 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2                                               0x24a0
14527 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX                                      2
14528 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2                                                        0x24a1
14529 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_BASE_IDX                                               2
14530 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2                                                        0x24a2
14531 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_BASE_IDX                                               2
14532 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2                                                        0x24a3
14533 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_BASE_IDX                                               2
14534 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2                                                        0x24a4
14535 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_BASE_IDX                                               2
14536 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2                                                        0x24a5
14537 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_BASE_IDX                                               2
14538 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2                                                        0x24a6
14539 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_BASE_IDX                                               2
14540 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2                                                        0x24a7
14541 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_BASE_IDX                                               2
14542 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2                                                        0x24a8
14543 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_BASE_IDX                                               2
14544 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2                                                        0x24a9
14545 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_BASE_IDX                                               2
14546 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2                                                        0x24aa
14547 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_BASE_IDX                                               2
14548 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2                                                       0x24ab
14549 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_BASE_IDX                                              2
14550 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2                                                       0x24ac
14551 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_BASE_IDX                                              2
14552 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2                                                       0x24ad
14553 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_BASE_IDX                                              2
14554 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3                                                  0x24ae
14555 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX                                         2
14556 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3                                                       0x24af
14557 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_BASE_IDX                                              2
14558 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3                                               0x24b0
14559 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX                                      2
14560 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3                                                        0x24b1
14561 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_BASE_IDX                                               2
14562 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3                                                        0x24b2
14563 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_BASE_IDX                                               2
14564 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3                                                        0x24b3
14565 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_BASE_IDX                                               2
14566 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3                                                        0x24b4
14567 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_BASE_IDX                                               2
14568 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3                                                        0x24b5
14569 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_BASE_IDX                                               2
14570 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3                                                        0x24b6
14571 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_BASE_IDX                                               2
14572 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3                                                        0x24b7
14573 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_BASE_IDX                                               2
14574 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3                                                        0x24b8
14575 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_BASE_IDX                                               2
14576 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3                                                        0x24b9
14577 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_BASE_IDX                                               2
14578 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3                                                        0x24ba
14579 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_BASE_IDX                                               2
14580 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3                                                       0x24bb
14581 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_BASE_IDX                                              2
14582 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3                                                       0x24bc
14583 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_BASE_IDX                                              2
14584 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3                                                       0x24bd
14585 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_BASE_IDX                                              2
14586 
14587 
14588 // addressBlock: dce_dc_dc_combophypllregs4_dispdec
14589 // base address: 0xc80
14590 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0                                                               0x24be
14591 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_BASE_IDX                                                      2
14592 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1                                                               0x24bf
14593 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_BASE_IDX                                                      2
14594 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2                                                               0x24c0
14595 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_BASE_IDX                                                      2
14596 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3                                                               0x24c1
14597 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_BASE_IDX                                                      2
14598 #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE                                                           0x24c2
14599 #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_BASE_IDX                                                  2
14600 #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE                                                             0x24c3
14601 #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_BASE_IDX                                                    2
14602 #define mmDC_COMBOPHYPLLREGS4_CAL_CTRL                                                                 0x24c4
14603 #define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_BASE_IDX                                                        2
14604 #define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL                                                                0x24c5
14605 #define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_BASE_IDX                                                       2
14606 #define mmDC_COMBOPHYPLLREGS4_VREG_CFG                                                                 0x24c7
14607 #define mmDC_COMBOPHYPLLREGS4_VREG_CFG_BASE_IDX                                                        2
14608 #define mmDC_COMBOPHYPLLREGS4_OBSERVE0                                                                 0x24c8
14609 #define mmDC_COMBOPHYPLLREGS4_OBSERVE0_BASE_IDX                                                        2
14610 #define mmDC_COMBOPHYPLLREGS4_OBSERVE1                                                                 0x24c9
14611 #define mmDC_COMBOPHYPLLREGS4_OBSERVE1_BASE_IDX                                                        2
14612 #define mmDC_COMBOPHYPLLREGS4_DFT_OUT                                                                  0x24ca
14613 #define mmDC_COMBOPHYPLLREGS4_DFT_OUT_BASE_IDX                                                         2
14614 
14615 
14616 // addressBlock: dce_dc_dcio_uniphy5_dispdec
14617 // base address: 0xfa0
14618 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2526
14619 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
14620 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2527
14621 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
14622 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2528
14623 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
14624 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2529
14625 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
14626 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x252a
14627 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
14628 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x252b
14629 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
14630 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x252c
14631 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
14632 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x252d
14633 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
14634 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x252e
14635 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
14636 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x252f
14637 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
14638 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2530
14639 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
14640 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2531
14641 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
14642 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2532
14643 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
14644 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2533
14645 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
14646 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2534
14647 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
14648 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2535
14649 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
14650 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2536
14651 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
14652 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2537
14653 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
14654 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2538
14655 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
14656 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2539
14657 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
14658 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x253a
14659 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
14660 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x253b
14661 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
14662 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x253c
14663 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
14664 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x253d
14665 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
14666 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x253e
14667 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
14668 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x253f
14669 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
14670 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2540
14671 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
14672 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2541
14673 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
14674 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2542
14675 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
14676 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2543
14677 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
14678 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2544
14679 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
14680 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2545
14681 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
14682 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2546
14683 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
14684 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2547
14685 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
14686 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2548
14687 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
14688 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2549
14689 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
14690 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x254a
14691 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
14692 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x254b
14693 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
14694 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x254c
14695 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
14696 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x254d
14697 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
14698 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x254e
14699 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
14700 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x254f
14701 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
14702 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2550
14703 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
14704 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2551
14705 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
14706 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2552
14707 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
14708 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2553
14709 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
14710 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2554
14711 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
14712 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2555
14713 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
14714 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2556
14715 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
14716 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2557
14717 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
14718 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2558
14719 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
14720 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2559
14721 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
14722 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x255a
14723 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
14724 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x255b
14725 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
14726 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x255c
14727 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
14728 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x255d
14729 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
14730 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x255e
14731 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
14732 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x255f
14733 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
14734 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58                                                    0x2560
14735 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX                                           2
14736 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59                                                    0x2561
14737 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX                                           2
14738 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60                                                    0x2562
14739 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX                                           2
14740 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61                                                    0x2563
14741 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX                                           2
14742 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62                                                    0x2564
14743 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX                                           2
14744 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63                                                    0x2565
14745 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX                                           2
14746 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64                                                    0x2566
14747 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX                                           2
14748 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65                                                    0x2567
14749 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX                                           2
14750 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66                                                    0x2568
14751 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX                                           2
14752 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67                                                    0x2569
14753 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX                                           2
14754 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68                                                    0x256a
14755 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX                                           2
14756 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69                                                    0x256b
14757 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX                                           2
14758 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70                                                    0x256c
14759 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX                                           2
14760 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71                                                    0x256d
14761 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX                                           2
14762 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72                                                    0x256e
14763 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX                                           2
14764 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73                                                    0x256f
14765 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX                                           2
14766 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74                                                    0x2570
14767 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX                                           2
14768 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75                                                    0x2571
14769 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX                                           2
14770 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76                                                    0x2572
14771 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX                                           2
14772 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77                                                    0x2573
14773 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX                                           2
14774 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78                                                    0x2574
14775 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX                                           2
14776 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79                                                    0x2575
14777 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX                                           2
14778 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80                                                    0x2576
14779 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX                                           2
14780 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81                                                    0x2577
14781 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX                                           2
14782 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82                                                    0x2578
14783 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX                                           2
14784 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83                                                    0x2579
14785 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX                                           2
14786 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84                                                    0x257a
14787 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX                                           2
14788 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85                                                    0x257b
14789 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX                                           2
14790 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86                                                    0x257c
14791 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX                                           2
14792 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87                                                    0x257d
14793 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX                                           2
14794 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88                                                    0x257e
14795 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX                                           2
14796 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89                                                    0x257f
14797 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX                                           2
14798 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90                                                    0x2580
14799 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX                                           2
14800 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91                                                    0x2581
14801 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX                                           2
14802 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92                                                    0x2582
14803 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX                                           2
14804 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93                                                    0x2583
14805 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX                                           2
14806 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94                                                    0x2584
14807 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX                                           2
14808 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95                                                    0x2585
14809 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX                                           2
14810 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96                                                    0x2586
14811 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX                                           2
14812 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97                                                    0x2587
14813 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX                                           2
14814 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98                                                    0x2588
14815 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX                                           2
14816 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99                                                    0x2589
14817 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX                                           2
14818 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100                                                   0x258a
14819 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX                                          2
14820 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101                                                   0x258b
14821 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX                                          2
14822 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102                                                   0x258c
14823 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX                                          2
14824 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103                                                   0x258d
14825 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX                                          2
14826 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104                                                   0x258e
14827 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX                                          2
14828 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105                                                   0x258f
14829 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX                                          2
14830 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106                                                   0x2590
14831 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX                                          2
14832 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107                                                   0x2591
14833 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX                                          2
14834 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108                                                   0x2592
14835 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX                                          2
14836 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109                                                   0x2593
14837 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX                                          2
14838 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110                                                   0x2594
14839 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX                                          2
14840 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111                                                   0x2595
14841 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX                                          2
14842 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112                                                   0x2596
14843 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX                                          2
14844 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113                                                   0x2597
14845 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX                                          2
14846 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114                                                   0x2598
14847 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX                                          2
14848 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115                                                   0x2599
14849 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX                                          2
14850 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116                                                   0x259a
14851 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX                                          2
14852 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117                                                   0x259b
14853 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX                                          2
14854 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118                                                   0x259c
14855 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX                                          2
14856 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119                                                   0x259d
14857 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX                                          2
14858 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120                                                   0x259e
14859 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX                                          2
14860 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121                                                   0x259f
14861 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX                                          2
14862 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122                                                   0x25a0
14863 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX                                          2
14864 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123                                                   0x25a1
14865 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX                                          2
14866 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124                                                   0x25a2
14867 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX                                          2
14868 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125                                                   0x25a3
14869 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX                                          2
14870 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126                                                   0x25a4
14871 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX                                          2
14872 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127                                                   0x25a5
14873 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX                                          2
14874 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128                                                   0x25a6
14875 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX                                          2
14876 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129                                                   0x25a7
14877 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX                                          2
14878 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130                                                   0x25a8
14879 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX                                          2
14880 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131                                                   0x25a9
14881 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX                                          2
14882 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132                                                   0x25aa
14883 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX                                          2
14884 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133                                                   0x25ab
14885 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX                                          2
14886 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134                                                   0x25ac
14887 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX                                          2
14888 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135                                                   0x25ad
14889 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX                                          2
14890 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136                                                   0x25ae
14891 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX                                          2
14892 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137                                                   0x25af
14893 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX                                          2
14894 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138                                                   0x25b0
14895 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX                                          2
14896 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139                                                   0x25b1
14897 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX                                          2
14898 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140                                                   0x25b2
14899 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX                                          2
14900 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141                                                   0x25b3
14901 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX                                          2
14902 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142                                                   0x25b4
14903 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX                                          2
14904 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143                                                   0x25b5
14905 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX                                          2
14906 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144                                                   0x25b6
14907 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX                                          2
14908 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145                                                   0x25b7
14909 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX                                          2
14910 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146                                                   0x25b8
14911 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX                                          2
14912 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147                                                   0x25b9
14913 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX                                          2
14914 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148                                                   0x25ba
14915 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX                                          2
14916 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149                                                   0x25bb
14917 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX                                          2
14918 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150                                                   0x25bc
14919 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX                                          2
14920 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151                                                   0x25bd
14921 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX                                          2
14922 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152                                                   0x25be
14923 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX                                          2
14924 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153                                                   0x25bf
14925 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX                                          2
14926 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154                                                   0x25c0
14927 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX                                          2
14928 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155                                                   0x25c1
14929 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX                                          2
14930 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156                                                   0x25c2
14931 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX                                          2
14932 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157                                                   0x25c3
14933 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX                                          2
14934 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158                                                   0x25c4
14935 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX                                          2
14936 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159                                                   0x25c5
14937 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX                                          2
14938 
14939 
14940 // addressBlock: dce_dc_dc_combophycmregs5_dispdec
14941 // base address: 0xfa0
14942 #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1                                                              0x2526
14943 #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_BASE_IDX                                                     2
14944 #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2                                                              0x2527
14945 #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_BASE_IDX                                                     2
14946 #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3                                                              0x2528
14947 #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_BASE_IDX                                                     2
14948 #define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM                                                     0x2529
14949 #define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_BASE_IDX                                            2
14950 #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT                                                       0x252a
14951 #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_BASE_IDX                                              2
14952 #define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL                                                            0x252b
14953 #define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_BASE_IDX                                                   2
14954 #define mmDC_COMBOPHYCMREGS5_COMMON_TMDP                                                               0x252c
14955 #define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_BASE_IDX                                                      2
14956 #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS                                                        0x252d
14957 #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_BASE_IDX                                               2
14958 #define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL                                                      0x252e
14959 #define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_BASE_IDX                                             2
14960 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1                                                          0x252f
14961 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_BASE_IDX                                                 2
14962 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2                                                          0x2530
14963 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_BASE_IDX                                                 2
14964 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3                                                          0x2531
14965 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_BASE_IDX                                                 2
14966 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4                                                          0x2532
14967 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_BASE_IDX                                                 2
14968 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5                                                          0x2533
14969 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_BASE_IDX                                                 2
14970 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6                                                          0x2534
14971 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_BASE_IDX                                                 2
14972 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7                                                          0x2535
14973 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_BASE_IDX                                                 2
14974 
14975 
14976 // addressBlock: dce_dc_dc_combophytxregs5_dispdec
14977 // base address: 0xfa0
14978 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0                                                  0x2546
14979 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX                                         2
14980 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0                                                       0x2547
14981 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_BASE_IDX                                              2
14982 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0                                               0x2548
14983 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX                                      2
14984 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0                                                        0x2549
14985 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_BASE_IDX                                               2
14986 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0                                                        0x254a
14987 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_BASE_IDX                                               2
14988 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0                                                        0x254b
14989 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_BASE_IDX                                               2
14990 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0                                                        0x254c
14991 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_BASE_IDX                                               2
14992 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0                                                        0x254d
14993 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_BASE_IDX                                               2
14994 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0                                                        0x254e
14995 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_BASE_IDX                                               2
14996 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0                                                        0x254f
14997 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_BASE_IDX                                               2
14998 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0                                                        0x2550
14999 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_BASE_IDX                                               2
15000 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0                                                        0x2551
15001 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_BASE_IDX                                               2
15002 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0                                                        0x2552
15003 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_BASE_IDX                                               2
15004 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0                                                       0x2553
15005 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_BASE_IDX                                              2
15006 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0                                                       0x2554
15007 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_BASE_IDX                                              2
15008 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0                                                       0x2555
15009 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_BASE_IDX                                              2
15010 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1                                                  0x2556
15011 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX                                         2
15012 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1                                                       0x2557
15013 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_BASE_IDX                                              2
15014 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1                                               0x2558
15015 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX                                      2
15016 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1                                                        0x2559
15017 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_BASE_IDX                                               2
15018 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1                                                        0x255a
15019 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_BASE_IDX                                               2
15020 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1                                                        0x255b
15021 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_BASE_IDX                                               2
15022 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1                                                        0x255c
15023 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_BASE_IDX                                               2
15024 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1                                                        0x255d
15025 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_BASE_IDX                                               2
15026 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1                                                        0x255e
15027 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_BASE_IDX                                               2
15028 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1                                                        0x255f
15029 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_BASE_IDX                                               2
15030 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1                                                        0x2560
15031 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_BASE_IDX                                               2
15032 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1                                                        0x2561
15033 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_BASE_IDX                                               2
15034 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1                                                        0x2562
15035 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_BASE_IDX                                               2
15036 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1                                                       0x2563
15037 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_BASE_IDX                                              2
15038 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1                                                       0x2564
15039 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_BASE_IDX                                              2
15040 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1                                                       0x2565
15041 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_BASE_IDX                                              2
15042 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2                                                  0x2566
15043 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX                                         2
15044 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2                                                       0x2567
15045 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_BASE_IDX                                              2
15046 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2                                               0x2568
15047 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX                                      2
15048 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2                                                        0x2569
15049 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_BASE_IDX                                               2
15050 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2                                                        0x256a
15051 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_BASE_IDX                                               2
15052 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2                                                        0x256b
15053 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_BASE_IDX                                               2
15054 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2                                                        0x256c
15055 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_BASE_IDX                                               2
15056 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2                                                        0x256d
15057 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_BASE_IDX                                               2
15058 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2                                                        0x256e
15059 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_BASE_IDX                                               2
15060 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2                                                        0x256f
15061 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_BASE_IDX                                               2
15062 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2                                                        0x2570
15063 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_BASE_IDX                                               2
15064 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2                                                        0x2571
15065 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_BASE_IDX                                               2
15066 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2                                                        0x2572
15067 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_BASE_IDX                                               2
15068 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2                                                       0x2573
15069 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_BASE_IDX                                              2
15070 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2                                                       0x2574
15071 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_BASE_IDX                                              2
15072 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2                                                       0x2575
15073 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_BASE_IDX                                              2
15074 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3                                                  0x2576
15075 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX                                         2
15076 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3                                                       0x2577
15077 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_BASE_IDX                                              2
15078 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3                                               0x2578
15079 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX                                      2
15080 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3                                                        0x2579
15081 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_BASE_IDX                                               2
15082 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3                                                        0x257a
15083 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_BASE_IDX                                               2
15084 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3                                                        0x257b
15085 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_BASE_IDX                                               2
15086 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3                                                        0x257c
15087 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_BASE_IDX                                               2
15088 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3                                                        0x257d
15089 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_BASE_IDX                                               2
15090 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3                                                        0x257e
15091 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_BASE_IDX                                               2
15092 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3                                                        0x257f
15093 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_BASE_IDX                                               2
15094 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3                                                        0x2580
15095 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_BASE_IDX                                               2
15096 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3                                                        0x2581
15097 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_BASE_IDX                                               2
15098 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3                                                        0x2582
15099 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_BASE_IDX                                               2
15100 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3                                                       0x2583
15101 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_BASE_IDX                                              2
15102 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3                                                       0x2584
15103 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_BASE_IDX                                              2
15104 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3                                                       0x2585
15105 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_BASE_IDX                                              2
15106 
15107 
15108 // addressBlock: dce_dc_dc_combophypllregs5_dispdec
15109 // base address: 0xfa0
15110 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0                                                               0x2586
15111 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_BASE_IDX                                                      2
15112 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1                                                               0x2587
15113 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_BASE_IDX                                                      2
15114 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2                                                               0x2588
15115 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_BASE_IDX                                                      2
15116 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3                                                               0x2589
15117 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_BASE_IDX                                                      2
15118 #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE                                                           0x258a
15119 #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_BASE_IDX                                                  2
15120 #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE                                                             0x258b
15121 #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_BASE_IDX                                                    2
15122 #define mmDC_COMBOPHYPLLREGS5_CAL_CTRL                                                                 0x258c
15123 #define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_BASE_IDX                                                        2
15124 #define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL                                                                0x258d
15125 #define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_BASE_IDX                                                       2
15126 #define mmDC_COMBOPHYPLLREGS5_VREG_CFG                                                                 0x258f
15127 #define mmDC_COMBOPHYPLLREGS5_VREG_CFG_BASE_IDX                                                        2
15128 #define mmDC_COMBOPHYPLLREGS5_OBSERVE0                                                                 0x2590
15129 #define mmDC_COMBOPHYPLLREGS5_OBSERVE0_BASE_IDX                                                        2
15130 #define mmDC_COMBOPHYPLLREGS5_OBSERVE1                                                                 0x2591
15131 #define mmDC_COMBOPHYPLLREGS5_OBSERVE1_BASE_IDX                                                        2
15132 #define mmDC_COMBOPHYPLLREGS5_DFT_OUT                                                                  0x2592
15133 #define mmDC_COMBOPHYPLLREGS5_DFT_OUT_BASE_IDX                                                         2
15134 
15135 
15136 // addressBlock: dce_dc_dcio_uniphy6_dispdec
15137 // base address: 0x12c0
15138 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x25ee
15139 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
15140 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x25ef
15141 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
15142 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x25f0
15143 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
15144 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x25f1
15145 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
15146 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x25f2
15147 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
15148 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x25f3
15149 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
15150 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x25f4
15151 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
15152 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x25f5
15153 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
15154 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x25f6
15155 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
15156 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x25f7
15157 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
15158 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x25f8
15159 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
15160 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x25f9
15161 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
15162 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x25fa
15163 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
15164 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x25fb
15165 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
15166 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x25fc
15167 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
15168 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x25fd
15169 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
15170 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x25fe
15171 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
15172 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x25ff
15173 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
15174 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2600
15175 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
15176 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2601
15177 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
15178 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2602
15179 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
15180 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2603
15181 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
15182 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2604
15183 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
15184 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2605
15185 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
15186 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2606
15187 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
15188 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2607
15189 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
15190 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2608
15191 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
15192 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2609
15193 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
15194 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x260a
15195 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
15196 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x260b
15197 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
15198 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x260c
15199 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
15200 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x260d
15201 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
15202 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x260e
15203 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
15204 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x260f
15205 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
15206 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2610
15207 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
15208 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2611
15209 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
15210 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2612
15211 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
15212 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2613
15213 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
15214 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2614
15215 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
15216 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2615
15217 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
15218 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2616
15219 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
15220 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2617
15221 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
15222 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2618
15223 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
15224 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2619
15225 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
15226 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x261a
15227 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
15228 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x261b
15229 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
15230 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x261c
15231 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
15232 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x261d
15233 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
15234 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x261e
15235 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
15236 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x261f
15237 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
15238 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2620
15239 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
15240 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2621
15241 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
15242 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2622
15243 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
15244 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2623
15245 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
15246 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2624
15247 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
15248 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2625
15249 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
15250 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2626
15251 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
15252 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2627
15253 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
15254 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58                                                    0x2628
15255 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX                                           2
15256 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59                                                    0x2629
15257 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX                                           2
15258 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60                                                    0x262a
15259 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX                                           2
15260 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61                                                    0x262b
15261 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX                                           2
15262 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62                                                    0x262c
15263 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX                                           2
15264 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63                                                    0x262d
15265 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX                                           2
15266 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64                                                    0x262e
15267 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX                                           2
15268 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65                                                    0x262f
15269 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX                                           2
15270 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66                                                    0x2630
15271 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX                                           2
15272 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67                                                    0x2631
15273 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX                                           2
15274 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68                                                    0x2632
15275 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX                                           2
15276 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69                                                    0x2633
15277 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX                                           2
15278 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70                                                    0x2634
15279 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX                                           2
15280 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71                                                    0x2635
15281 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX                                           2
15282 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72                                                    0x2636
15283 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX                                           2
15284 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73                                                    0x2637
15285 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX                                           2
15286 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74                                                    0x2638
15287 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX                                           2
15288 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75                                                    0x2639
15289 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX                                           2
15290 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76                                                    0x263a
15291 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX                                           2
15292 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77                                                    0x263b
15293 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX                                           2
15294 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78                                                    0x263c
15295 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX                                           2
15296 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79                                                    0x263d
15297 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX                                           2
15298 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80                                                    0x263e
15299 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX                                           2
15300 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81                                                    0x263f
15301 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX                                           2
15302 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82                                                    0x2640
15303 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX                                           2
15304 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83                                                    0x2641
15305 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX                                           2
15306 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84                                                    0x2642
15307 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX                                           2
15308 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85                                                    0x2643
15309 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX                                           2
15310 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86                                                    0x2644
15311 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX                                           2
15312 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87                                                    0x2645
15313 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX                                           2
15314 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88                                                    0x2646
15315 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX                                           2
15316 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89                                                    0x2647
15317 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX                                           2
15318 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90                                                    0x2648
15319 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX                                           2
15320 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91                                                    0x2649
15321 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX                                           2
15322 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92                                                    0x264a
15323 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX                                           2
15324 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93                                                    0x264b
15325 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX                                           2
15326 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94                                                    0x264c
15327 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX                                           2
15328 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95                                                    0x264d
15329 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX                                           2
15330 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96                                                    0x264e
15331 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX                                           2
15332 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97                                                    0x264f
15333 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX                                           2
15334 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98                                                    0x2650
15335 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX                                           2
15336 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99                                                    0x2651
15337 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX                                           2
15338 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100                                                   0x2652
15339 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX                                          2
15340 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101                                                   0x2653
15341 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX                                          2
15342 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102                                                   0x2654
15343 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX                                          2
15344 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103                                                   0x2655
15345 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX                                          2
15346 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104                                                   0x2656
15347 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX                                          2
15348 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105                                                   0x2657
15349 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX                                          2
15350 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106                                                   0x2658
15351 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX                                          2
15352 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107                                                   0x2659
15353 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX                                          2
15354 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108                                                   0x265a
15355 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX                                          2
15356 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109                                                   0x265b
15357 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX                                          2
15358 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110                                                   0x265c
15359 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX                                          2
15360 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111                                                   0x265d
15361 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX                                          2
15362 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112                                                   0x265e
15363 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX                                          2
15364 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113                                                   0x265f
15365 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX                                          2
15366 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114                                                   0x2660
15367 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX                                          2
15368 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115                                                   0x2661
15369 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX                                          2
15370 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116                                                   0x2662
15371 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX                                          2
15372 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117                                                   0x2663
15373 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX                                          2
15374 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118                                                   0x2664
15375 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX                                          2
15376 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119                                                   0x2665
15377 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX                                          2
15378 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120                                                   0x2666
15379 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX                                          2
15380 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121                                                   0x2667
15381 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX                                          2
15382 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122                                                   0x2668
15383 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX                                          2
15384 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123                                                   0x2669
15385 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX                                          2
15386 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124                                                   0x266a
15387 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX                                          2
15388 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125                                                   0x266b
15389 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX                                          2
15390 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126                                                   0x266c
15391 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX                                          2
15392 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127                                                   0x266d
15393 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX                                          2
15394 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128                                                   0x266e
15395 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX                                          2
15396 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129                                                   0x266f
15397 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX                                          2
15398 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130                                                   0x2670
15399 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX                                          2
15400 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131                                                   0x2671
15401 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX                                          2
15402 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132                                                   0x2672
15403 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX                                          2
15404 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133                                                   0x2673
15405 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX                                          2
15406 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134                                                   0x2674
15407 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX                                          2
15408 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135                                                   0x2675
15409 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX                                          2
15410 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136                                                   0x2676
15411 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX                                          2
15412 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137                                                   0x2677
15413 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX                                          2
15414 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138                                                   0x2678
15415 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX                                          2
15416 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139                                                   0x2679
15417 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX                                          2
15418 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140                                                   0x267a
15419 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX                                          2
15420 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141                                                   0x267b
15421 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX                                          2
15422 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142                                                   0x267c
15423 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX                                          2
15424 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143                                                   0x267d
15425 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX                                          2
15426 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144                                                   0x267e
15427 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX                                          2
15428 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145                                                   0x267f
15429 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX                                          2
15430 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146                                                   0x2680
15431 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX                                          2
15432 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147                                                   0x2681
15433 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX                                          2
15434 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148                                                   0x2682
15435 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX                                          2
15436 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149                                                   0x2683
15437 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX                                          2
15438 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150                                                   0x2684
15439 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX                                          2
15440 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151                                                   0x2685
15441 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX                                          2
15442 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152                                                   0x2686
15443 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX                                          2
15444 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153                                                   0x2687
15445 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX                                          2
15446 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154                                                   0x2688
15447 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX                                          2
15448 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155                                                   0x2689
15449 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX                                          2
15450 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156                                                   0x268a
15451 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX                                          2
15452 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157                                                   0x268b
15453 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX                                          2
15454 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158                                                   0x268c
15455 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX                                          2
15456 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159                                                   0x268d
15457 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX                                          2
15458 
15459 
15460 // addressBlock: dce_dc_dc_combophycmregs6_dispdec
15461 // base address: 0x12c0
15462 #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1                                                              0x25ee
15463 #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_BASE_IDX                                                     2
15464 #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2                                                              0x25ef
15465 #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_BASE_IDX                                                     2
15466 #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3                                                              0x25f0
15467 #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_BASE_IDX                                                     2
15468 #define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM                                                     0x25f1
15469 #define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_BASE_IDX                                            2
15470 #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT                                                       0x25f2
15471 #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_BASE_IDX                                              2
15472 #define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL                                                            0x25f3
15473 #define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_BASE_IDX                                                   2
15474 #define mmDC_COMBOPHYCMREGS6_COMMON_TMDP                                                               0x25f4
15475 #define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_BASE_IDX                                                      2
15476 #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS                                                        0x25f5
15477 #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_BASE_IDX                                               2
15478 #define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL                                                      0x25f6
15479 #define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_BASE_IDX                                             2
15480 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1                                                          0x25f7
15481 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_BASE_IDX                                                 2
15482 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2                                                          0x25f8
15483 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_BASE_IDX                                                 2
15484 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3                                                          0x25f9
15485 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_BASE_IDX                                                 2
15486 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4                                                          0x25fa
15487 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_BASE_IDX                                                 2
15488 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5                                                          0x25fb
15489 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_BASE_IDX                                                 2
15490 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6                                                          0x25fc
15491 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_BASE_IDX                                                 2
15492 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7                                                          0x25fd
15493 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_BASE_IDX                                                 2
15494 
15495 
15496 // addressBlock: dce_dc_dc_combophytxregs6_dispdec
15497 // base address: 0x12c0
15498 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0                                                  0x260e
15499 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX                                         2
15500 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0                                                       0x260f
15501 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_BASE_IDX                                              2
15502 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0                                               0x2610
15503 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX                                      2
15504 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0                                                        0x2611
15505 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_BASE_IDX                                               2
15506 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0                                                        0x2612
15507 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_BASE_IDX                                               2
15508 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0                                                        0x2613
15509 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_BASE_IDX                                               2
15510 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0                                                        0x2614
15511 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_BASE_IDX                                               2
15512 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0                                                        0x2615
15513 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_BASE_IDX                                               2
15514 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0                                                        0x2616
15515 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_BASE_IDX                                               2
15516 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0                                                        0x2617
15517 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_BASE_IDX                                               2
15518 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0                                                        0x2618
15519 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_BASE_IDX                                               2
15520 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0                                                        0x2619
15521 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_BASE_IDX                                               2
15522 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0                                                        0x261a
15523 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_BASE_IDX                                               2
15524 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0                                                       0x261b
15525 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_BASE_IDX                                              2
15526 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0                                                       0x261c
15527 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_BASE_IDX                                              2
15528 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0                                                       0x261d
15529 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_BASE_IDX                                              2
15530 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1                                                  0x261e
15531 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX                                         2
15532 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1                                                       0x261f
15533 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_BASE_IDX                                              2
15534 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1                                               0x2620
15535 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX                                      2
15536 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1                                                        0x2621
15537 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_BASE_IDX                                               2
15538 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1                                                        0x2622
15539 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_BASE_IDX                                               2
15540 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1                                                        0x2623
15541 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_BASE_IDX                                               2
15542 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1                                                        0x2624
15543 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_BASE_IDX                                               2
15544 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1                                                        0x2625
15545 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_BASE_IDX                                               2
15546 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1                                                        0x2626
15547 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_BASE_IDX                                               2
15548 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1                                                        0x2627
15549 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_BASE_IDX                                               2
15550 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1                                                        0x2628
15551 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_BASE_IDX                                               2
15552 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1                                                        0x2629
15553 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_BASE_IDX                                               2
15554 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1                                                        0x262a
15555 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_BASE_IDX                                               2
15556 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1                                                       0x262b
15557 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_BASE_IDX                                              2
15558 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1                                                       0x262c
15559 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_BASE_IDX                                              2
15560 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1                                                       0x262d
15561 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_BASE_IDX                                              2
15562 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2                                                  0x262e
15563 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX                                         2
15564 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2                                                       0x262f
15565 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_BASE_IDX                                              2
15566 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2                                               0x2630
15567 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX                                      2
15568 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2                                                        0x2631
15569 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_BASE_IDX                                               2
15570 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2                                                        0x2632
15571 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_BASE_IDX                                               2
15572 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2                                                        0x2633
15573 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_BASE_IDX                                               2
15574 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2                                                        0x2634
15575 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_BASE_IDX                                               2
15576 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2                                                        0x2635
15577 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_BASE_IDX                                               2
15578 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2                                                        0x2636
15579 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_BASE_IDX                                               2
15580 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2                                                        0x2637
15581 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_BASE_IDX                                               2
15582 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2                                                        0x2638
15583 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_BASE_IDX                                               2
15584 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2                                                        0x2639
15585 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_BASE_IDX                                               2
15586 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2                                                        0x263a
15587 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_BASE_IDX                                               2
15588 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2                                                       0x263b
15589 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_BASE_IDX                                              2
15590 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2                                                       0x263c
15591 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_BASE_IDX                                              2
15592 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2                                                       0x263d
15593 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_BASE_IDX                                              2
15594 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3                                                  0x263e
15595 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX                                         2
15596 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3                                                       0x263f
15597 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_BASE_IDX                                              2
15598 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3                                               0x2640
15599 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX                                      2
15600 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3                                                        0x2641
15601 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_BASE_IDX                                               2
15602 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3                                                        0x2642
15603 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_BASE_IDX                                               2
15604 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3                                                        0x2643
15605 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_BASE_IDX                                               2
15606 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3                                                        0x2644
15607 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_BASE_IDX                                               2
15608 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3                                                        0x2645
15609 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_BASE_IDX                                               2
15610 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3                                                        0x2646
15611 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_BASE_IDX                                               2
15612 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3                                                        0x2647
15613 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_BASE_IDX                                               2
15614 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3                                                        0x2648
15615 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_BASE_IDX                                               2
15616 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3                                                        0x2649
15617 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_BASE_IDX                                               2
15618 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3                                                        0x264a
15619 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_BASE_IDX                                               2
15620 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3                                                       0x264b
15621 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_BASE_IDX                                              2
15622 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3                                                       0x264c
15623 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_BASE_IDX                                              2
15624 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3                                                       0x264d
15625 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_BASE_IDX                                              2
15626 
15627 
15628 // addressBlock: dce_dc_dc_combophypllregs6_dispdec
15629 // base address: 0x12c0
15630 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0                                                               0x264e
15631 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_BASE_IDX                                                      2
15632 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1                                                               0x264f
15633 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_BASE_IDX                                                      2
15634 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2                                                               0x2650
15635 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_BASE_IDX                                                      2
15636 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3                                                               0x2651
15637 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_BASE_IDX                                                      2
15638 #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE                                                           0x2652
15639 #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_BASE_IDX                                                  2
15640 #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE                                                             0x2653
15641 #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_BASE_IDX                                                    2
15642 #define mmDC_COMBOPHYPLLREGS6_CAL_CTRL                                                                 0x2654
15643 #define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_BASE_IDX                                                        2
15644 #define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL                                                                0x2655
15645 #define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_BASE_IDX                                                       2
15646 #define mmDC_COMBOPHYPLLREGS6_VREG_CFG                                                                 0x2657
15647 #define mmDC_COMBOPHYPLLREGS6_VREG_CFG_BASE_IDX                                                        2
15648 #define mmDC_COMBOPHYPLLREGS6_OBSERVE0                                                                 0x2658
15649 #define mmDC_COMBOPHYPLLREGS6_OBSERVE0_BASE_IDX                                                        2
15650 #define mmDC_COMBOPHYPLLREGS6_OBSERVE1                                                                 0x2659
15651 #define mmDC_COMBOPHYPLLREGS6_OBSERVE1_BASE_IDX                                                        2
15652 #define mmDC_COMBOPHYPLLREGS6_DFT_OUT                                                                  0x265a
15653 #define mmDC_COMBOPHYPLLREGS6_DFT_OUT_BASE_IDX                                                         2
15654 
15655 
15656 // addressBlock: dce_dc_dcio_uniphy8_dispdec
15657 // base address: 0x15e0
15658 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x26b6
15659 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
15660 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x26b7
15661 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
15662 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x26b8
15663 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
15664 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x26b9
15665 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
15666 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x26ba
15667 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
15668 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x26bb
15669 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
15670 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x26bc
15671 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
15672 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x26bd
15673 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
15674 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x26be
15675 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
15676 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x26bf
15677 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
15678 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x26c0
15679 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
15680 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x26c1
15681 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
15682 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x26c2
15683 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
15684 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x26c3
15685 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
15686 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x26c4
15687 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
15688 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x26c5
15689 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
15690 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x26c6
15691 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
15692 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x26c7
15693 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
15694 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x26c8
15695 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
15696 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x26c9
15697 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
15698 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x26ca
15699 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
15700 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x26cb
15701 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
15702 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x26cc
15703 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
15704 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x26cd
15705 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
15706 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x26ce
15707 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
15708 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x26cf
15709 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
15710 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x26d0
15711 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
15712 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x26d1
15713 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
15714 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x26d2
15715 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
15716 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x26d3
15717 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
15718 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x26d4
15719 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
15720 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x26d5
15721 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
15722 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x26d6
15723 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
15724 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x26d7
15725 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
15726 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x26d8
15727 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
15728 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x26d9
15729 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
15730 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x26da
15731 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
15732 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x26db
15733 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
15734 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x26dc
15735 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
15736 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x26dd
15737 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
15738 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x26de
15739 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
15740 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x26df
15741 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
15742 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x26e0
15743 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
15744 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x26e1
15745 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
15746 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x26e2
15747 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
15748 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x26e3
15749 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
15750 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x26e4
15751 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
15752 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x26e5
15753 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
15754 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x26e6
15755 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
15756 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x26e7
15757 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
15758 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x26e8
15759 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
15760 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x26e9
15761 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
15762 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x26ea
15763 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
15764 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x26eb
15765 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
15766 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x26ec
15767 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
15768 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x26ed
15769 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
15770 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x26ee
15771 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
15772 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x26ef
15773 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
15774 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58                                                    0x26f0
15775 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX                                           2
15776 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59                                                    0x26f1
15777 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX                                           2
15778 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60                                                    0x26f2
15779 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX                                           2
15780 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61                                                    0x26f3
15781 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX                                           2
15782 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62                                                    0x26f4
15783 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX                                           2
15784 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63                                                    0x26f5
15785 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX                                           2
15786 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64                                                    0x26f6
15787 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX                                           2
15788 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65                                                    0x26f7
15789 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX                                           2
15790 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66                                                    0x26f8
15791 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX                                           2
15792 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67                                                    0x26f9
15793 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX                                           2
15794 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68                                                    0x26fa
15795 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX                                           2
15796 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69                                                    0x26fb
15797 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX                                           2
15798 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70                                                    0x26fc
15799 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX                                           2
15800 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71                                                    0x26fd
15801 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX                                           2
15802 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72                                                    0x26fe
15803 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX                                           2
15804 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73                                                    0x26ff
15805 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX                                           2
15806 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74                                                    0x2700
15807 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX                                           2
15808 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75                                                    0x2701
15809 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX                                           2
15810 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76                                                    0x2702
15811 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX                                           2
15812 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77                                                    0x2703
15813 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX                                           2
15814 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78                                                    0x2704
15815 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX                                           2
15816 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79                                                    0x2705
15817 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX                                           2
15818 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80                                                    0x2706
15819 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX                                           2
15820 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81                                                    0x2707
15821 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX                                           2
15822 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82                                                    0x2708
15823 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX                                           2
15824 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83                                                    0x2709
15825 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX                                           2
15826 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84                                                    0x270a
15827 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX                                           2
15828 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85                                                    0x270b
15829 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX                                           2
15830 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86                                                    0x270c
15831 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX                                           2
15832 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87                                                    0x270d
15833 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX                                           2
15834 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88                                                    0x270e
15835 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX                                           2
15836 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89                                                    0x270f
15837 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX                                           2
15838 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90                                                    0x2710
15839 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX                                           2
15840 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91                                                    0x2711
15841 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX                                           2
15842 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92                                                    0x2712
15843 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX                                           2
15844 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93                                                    0x2713
15845 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX                                           2
15846 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94                                                    0x2714
15847 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX                                           2
15848 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95                                                    0x2715
15849 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX                                           2
15850 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96                                                    0x2716
15851 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX                                           2
15852 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97                                                    0x2717
15853 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX                                           2
15854 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98                                                    0x2718
15855 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX                                           2
15856 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99                                                    0x2719
15857 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX                                           2
15858 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100                                                   0x271a
15859 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX                                          2
15860 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101                                                   0x271b
15861 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX                                          2
15862 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102                                                   0x271c
15863 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX                                          2
15864 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103                                                   0x271d
15865 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX                                          2
15866 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104                                                   0x271e
15867 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX                                          2
15868 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105                                                   0x271f
15869 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX                                          2
15870 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106                                                   0x2720
15871 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX                                          2
15872 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107                                                   0x2721
15873 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX                                          2
15874 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108                                                   0x2722
15875 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX                                          2
15876 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109                                                   0x2723
15877 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX                                          2
15878 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110                                                   0x2724
15879 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX                                          2
15880 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111                                                   0x2725
15881 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX                                          2
15882 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112                                                   0x2726
15883 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX                                          2
15884 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113                                                   0x2727
15885 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX                                          2
15886 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114                                                   0x2728
15887 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX                                          2
15888 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115                                                   0x2729
15889 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX                                          2
15890 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116                                                   0x272a
15891 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX                                          2
15892 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117                                                   0x272b
15893 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX                                          2
15894 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118                                                   0x272c
15895 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX                                          2
15896 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119                                                   0x272d
15897 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX                                          2
15898 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120                                                   0x272e
15899 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX                                          2
15900 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121                                                   0x272f
15901 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX                                          2
15902 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122                                                   0x2730
15903 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX                                          2
15904 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123                                                   0x2731
15905 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX                                          2
15906 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124                                                   0x2732
15907 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX                                          2
15908 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125                                                   0x2733
15909 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX                                          2
15910 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126                                                   0x2734
15911 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX                                          2
15912 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127                                                   0x2735
15913 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX                                          2
15914 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128                                                   0x2736
15915 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX                                          2
15916 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129                                                   0x2737
15917 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX                                          2
15918 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130                                                   0x2738
15919 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX                                          2
15920 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131                                                   0x2739
15921 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX                                          2
15922 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132                                                   0x273a
15923 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX                                          2
15924 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133                                                   0x273b
15925 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX                                          2
15926 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134                                                   0x273c
15927 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX                                          2
15928 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135                                                   0x273d
15929 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX                                          2
15930 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136                                                   0x273e
15931 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX                                          2
15932 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137                                                   0x273f
15933 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX                                          2
15934 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138                                                   0x2740
15935 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX                                          2
15936 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139                                                   0x2741
15937 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX                                          2
15938 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140                                                   0x2742
15939 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX                                          2
15940 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141                                                   0x2743
15941 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX                                          2
15942 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142                                                   0x2744
15943 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX                                          2
15944 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143                                                   0x2745
15945 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX                                          2
15946 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144                                                   0x2746
15947 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX                                          2
15948 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145                                                   0x2747
15949 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX                                          2
15950 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146                                                   0x2748
15951 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX                                          2
15952 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147                                                   0x2749
15953 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX                                          2
15954 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148                                                   0x274a
15955 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX                                          2
15956 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149                                                   0x274b
15957 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX                                          2
15958 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150                                                   0x274c
15959 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX                                          2
15960 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151                                                   0x274d
15961 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX                                          2
15962 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152                                                   0x274e
15963 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX                                          2
15964 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153                                                   0x274f
15965 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX                                          2
15966 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154                                                   0x2750
15967 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX                                          2
15968 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155                                                   0x2751
15969 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX                                          2
15970 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156                                                   0x2752
15971 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX                                          2
15972 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157                                                   0x2753
15973 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX                                          2
15974 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158                                                   0x2754
15975 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX                                          2
15976 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159                                                   0x2755
15977 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX                                          2
15978 
15979 
15980 // addressBlock: dce_dc_dc_combophycmregs8_dispdec
15981 // base address: 0x15e0
15982 #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1                                                              0x26b6
15983 #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_BASE_IDX                                                     2
15984 #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2                                                              0x26b7
15985 #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_BASE_IDX                                                     2
15986 #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3                                                              0x26b8
15987 #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_BASE_IDX                                                     2
15988 #define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM                                                     0x26b9
15989 #define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_BASE_IDX                                            2
15990 #define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT                                                       0x26ba
15991 #define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_BASE_IDX                                              2
15992 #define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL                                                            0x26bb
15993 #define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_BASE_IDX                                                   2
15994 #define mmDC_COMBOPHYCMREGS8_COMMON_TMDP                                                               0x26bc
15995 #define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_BASE_IDX                                                      2
15996 #define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS                                                        0x26bd
15997 #define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_BASE_IDX                                               2
15998 #define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL                                                      0x26be
15999 #define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_BASE_IDX                                             2
16000 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1                                                          0x26bf
16001 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_BASE_IDX                                                 2
16002 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2                                                          0x26c0
16003 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_BASE_IDX                                                 2
16004 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3                                                          0x26c1
16005 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_BASE_IDX                                                 2
16006 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4                                                          0x26c2
16007 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_BASE_IDX                                                 2
16008 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5                                                          0x26c3
16009 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_BASE_IDX                                                 2
16010 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6                                                          0x26c4
16011 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_BASE_IDX                                                 2
16012 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7                                                          0x26c5
16013 #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_BASE_IDX                                                 2
16014 
16015 
16016 // addressBlock: dce_dc_dc_combophytxregs8_dispdec
16017 // base address: 0x15e0
16018 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0                                                  0x26d6
16019 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX                                         2
16020 #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0                                                       0x26d7
16021 #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_BASE_IDX                                              2
16022 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0                                               0x26d8
16023 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX                                      2
16024 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0                                                        0x26d9
16025 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_BASE_IDX                                               2
16026 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0                                                        0x26da
16027 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_BASE_IDX                                               2
16028 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0                                                        0x26db
16029 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_BASE_IDX                                               2
16030 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0                                                        0x26dc
16031 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_BASE_IDX                                               2
16032 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0                                                        0x26dd
16033 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_BASE_IDX                                               2
16034 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0                                                        0x26de
16035 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_BASE_IDX                                               2
16036 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0                                                        0x26df
16037 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_BASE_IDX                                               2
16038 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0                                                        0x26e0
16039 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_BASE_IDX                                               2
16040 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0                                                        0x26e1
16041 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_BASE_IDX                                               2
16042 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0                                                        0x26e2
16043 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_BASE_IDX                                               2
16044 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0                                                       0x26e3
16045 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_BASE_IDX                                              2
16046 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0                                                       0x26e4
16047 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_BASE_IDX                                              2
16048 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0                                                       0x26e5
16049 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_BASE_IDX                                              2
16050 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1                                                  0x26e6
16051 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX                                         2
16052 #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1                                                       0x26e7
16053 #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_BASE_IDX                                              2
16054 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1                                               0x26e8
16055 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX                                      2
16056 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1                                                        0x26e9
16057 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_BASE_IDX                                               2
16058 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1                                                        0x26ea
16059 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_BASE_IDX                                               2
16060 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1                                                        0x26eb
16061 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_BASE_IDX                                               2
16062 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1                                                        0x26ec
16063 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_BASE_IDX                                               2
16064 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1                                                        0x26ed
16065 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_BASE_IDX                                               2
16066 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1                                                        0x26ee
16067 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_BASE_IDX                                               2
16068 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1                                                        0x26ef
16069 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_BASE_IDX                                               2
16070 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1                                                        0x26f0
16071 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_BASE_IDX                                               2
16072 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1                                                        0x26f1
16073 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_BASE_IDX                                               2
16074 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1                                                        0x26f2
16075 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_BASE_IDX                                               2
16076 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1                                                       0x26f3
16077 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_BASE_IDX                                              2
16078 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1                                                       0x26f4
16079 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_BASE_IDX                                              2
16080 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1                                                       0x26f5
16081 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_BASE_IDX                                              2
16082 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2                                                  0x26f6
16083 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX                                         2
16084 #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2                                                       0x26f7
16085 #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_BASE_IDX                                              2
16086 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2                                               0x26f8
16087 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX                                      2
16088 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2                                                        0x26f9
16089 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_BASE_IDX                                               2
16090 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2                                                        0x26fa
16091 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_BASE_IDX                                               2
16092 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2                                                        0x26fb
16093 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_BASE_IDX                                               2
16094 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2                                                        0x26fc
16095 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_BASE_IDX                                               2
16096 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2                                                        0x26fd
16097 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_BASE_IDX                                               2
16098 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2                                                        0x26fe
16099 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_BASE_IDX                                               2
16100 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2                                                        0x26ff
16101 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_BASE_IDX                                               2
16102 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2                                                        0x2700
16103 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_BASE_IDX                                               2
16104 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2                                                        0x2701
16105 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_BASE_IDX                                               2
16106 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2                                                        0x2702
16107 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_BASE_IDX                                               2
16108 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2                                                       0x2703
16109 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_BASE_IDX                                              2
16110 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2                                                       0x2704
16111 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_BASE_IDX                                              2
16112 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2                                                       0x2705
16113 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_BASE_IDX                                              2
16114 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3                                                  0x2706
16115 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX                                         2
16116 #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3                                                       0x2707
16117 #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_BASE_IDX                                              2
16118 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3                                               0x2708
16119 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX                                      2
16120 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3                                                        0x2709
16121 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_BASE_IDX                                               2
16122 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3                                                        0x270a
16123 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_BASE_IDX                                               2
16124 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3                                                        0x270b
16125 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_BASE_IDX                                               2
16126 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3                                                        0x270c
16127 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_BASE_IDX                                               2
16128 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3                                                        0x270d
16129 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_BASE_IDX                                               2
16130 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3                                                        0x270e
16131 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_BASE_IDX                                               2
16132 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3                                                        0x270f
16133 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_BASE_IDX                                               2
16134 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3                                                        0x2710
16135 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_BASE_IDX                                               2
16136 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3                                                        0x2711
16137 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_BASE_IDX                                               2
16138 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3                                                        0x2712
16139 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_BASE_IDX                                               2
16140 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3                                                       0x2713
16141 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_BASE_IDX                                              2
16142 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3                                                       0x2714
16143 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_BASE_IDX                                              2
16144 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3                                                       0x2715
16145 #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_BASE_IDX                                              2
16146 
16147 
16148 // addressBlock: dce_dc_dc_combophypllregs8_dispdec
16149 // base address: 0x15e0
16150 #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0                                                               0x2716
16151 #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_BASE_IDX                                                      2
16152 #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1                                                               0x2717
16153 #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_BASE_IDX                                                      2
16154 #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2                                                               0x2718
16155 #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_BASE_IDX                                                      2
16156 #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3                                                               0x2719
16157 #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_BASE_IDX                                                      2
16158 #define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE                                                           0x271a
16159 #define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_BASE_IDX                                                  2
16160 #define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE                                                             0x271b
16161 #define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_BASE_IDX                                                    2
16162 #define mmDC_COMBOPHYPLLREGS8_CAL_CTRL                                                                 0x271c
16163 #define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_BASE_IDX                                                        2
16164 #define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL                                                                0x271d
16165 #define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_BASE_IDX                                                       2
16166 #define mmDC_COMBOPHYPLLREGS8_VREG_CFG                                                                 0x271f
16167 #define mmDC_COMBOPHYPLLREGS8_VREG_CFG_BASE_IDX                                                        2
16168 #define mmDC_COMBOPHYPLLREGS8_OBSERVE0                                                                 0x2720
16169 #define mmDC_COMBOPHYPLLREGS8_OBSERVE0_BASE_IDX                                                        2
16170 #define mmDC_COMBOPHYPLLREGS8_OBSERVE1                                                                 0x2721
16171 #define mmDC_COMBOPHYPLLREGS8_OBSERVE1_BASE_IDX                                                        2
16172 #define mmDC_COMBOPHYPLLREGS8_DFT_OUT                                                                  0x2722
16173 #define mmDC_COMBOPHYPLLREGS8_DFT_OUT_BASE_IDX                                                         2
16174 
16175 
16176 // addressBlock: dce_dc_dsi0_dispdec
16177 // base address: 0x0
16178 #define mmDSI0_DISP_DSI_CTRL                                                                           0x27be
16179 #define mmDSI0_DISP_DSI_CTRL_BASE_IDX                                                                  2
16180 #define mmDSI0_DISP_DSI_STATUS                                                                         0x27bf
16181 #define mmDSI0_DISP_DSI_STATUS_BASE_IDX                                                                2
16182 #define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL                                                                0x27c0
16183 #define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX                                                       2
16184 #define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE                                                       0x27c1
16185 #define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX                                              2
16186 #define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD                                                       0x27c2
16187 #define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX                                              2
16188 #define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD                                                       0x27c3
16189 #define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX                                              2
16190 #define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE                                                      0x27c4
16191 #define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX                                             2
16192 #define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE                                                   0x27c5
16193 #define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX                                          2
16194 #define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL                                                           0x27c6
16195 #define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX                                                  2
16196 #define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL                                                              0x27c7
16197 #define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX                                                     2
16198 #define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL                                                         0x27c8
16199 #define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX                                                2
16200 #define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL                                                      0x27c9
16201 #define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX                                             2
16202 #define mmDSI0_DISP_DSI_DMA_CMD_OFFSET                                                                 0x27ca
16203 #define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX                                                        2
16204 #define mmDSI0_DISP_DSI_DMA_CMD_LENGTH                                                                 0x27cb
16205 #define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX                                                        2
16206 #define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0                                                              0x27cc
16207 #define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX                                                     2
16208 #define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1                                                              0x27cd
16209 #define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX                                                     2
16210 #define mmDSI0_DISP_DSI_DMA_DATA_PITCH                                                                 0x27ce
16211 #define mmDSI0_DISP_DSI_DMA_DATA_PITCH_BASE_IDX                                                        2
16212 #define mmDSI0_DISP_DSI_DMA_DATA_WIDTH                                                                 0x27cf
16213 #define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX                                                        2
16214 #define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT                                                                0x27d0
16215 #define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX                                                       2
16216 #define mmDSI0_DISP_DSI_DMA_FIFO_CTRL                                                                  0x27d1
16217 #define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX                                                         2
16218 #define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA                                                           0x27d2
16219 #define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX                                                  2
16220 #define mmDSI0_DISP_DSI_DENG_DATA_LENGTH                                                               0x27d3
16221 #define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX                                                      2
16222 #define mmDSI0_DISP_DSI_ACK_ERROR_REPORT                                                               0x27d4
16223 #define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX                                                      2
16224 #define mmDSI0_DISP_DSI_RDBK_DATA0                                                                     0x27d5
16225 #define mmDSI0_DISP_DSI_RDBK_DATA0_BASE_IDX                                                            2
16226 #define mmDSI0_DISP_DSI_RDBK_DATA1                                                                     0x27d6
16227 #define mmDSI0_DISP_DSI_RDBK_DATA1_BASE_IDX                                                            2
16228 #define mmDSI0_DISP_DSI_RDBK_DATA2                                                                     0x27d7
16229 #define mmDSI0_DISP_DSI_RDBK_DATA2_BASE_IDX                                                            2
16230 #define mmDSI0_DISP_DSI_RDBK_DATA3                                                                     0x27d8
16231 #define mmDSI0_DISP_DSI_RDBK_DATA3_BASE_IDX                                                            2
16232 #define mmDSI0_DISP_DSI_RDBK_DATATYPE0                                                                 0x27d9
16233 #define mmDSI0_DISP_DSI_RDBK_DATATYPE0_BASE_IDX                                                        2
16234 #define mmDSI0_DISP_DSI_RDBK_DATATYPE1                                                                 0x27da
16235 #define mmDSI0_DISP_DSI_RDBK_DATATYPE1_BASE_IDX                                                        2
16236 #define mmDSI0_DISP_DSI_TRIG_CTRL                                                                      0x27db
16237 #define mmDSI0_DISP_DSI_TRIG_CTRL_BASE_IDX                                                             2
16238 #define mmDSI0_DISP_DSI_EXT_MUX                                                                        0x27dc
16239 #define mmDSI0_DISP_DSI_EXT_MUX_BASE_IDX                                                               2
16240 #define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL                                                    0x27dd
16241 #define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX                                           2
16242 #define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER                                                        0x27de
16243 #define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX                                               2
16244 #define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER                                                       0x27df
16245 #define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX                                              2
16246 #define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER                                                        0x27e0
16247 #define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX                                               2
16248 #define mmDSI0_DISP_DSI_RESET_SW_TRIGGER                                                               0x27e1
16249 #define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX                                                      2
16250 #define mmDSI0_DISP_DSI_EXT_RESET                                                                      0x27e2
16251 #define mmDSI0_DISP_DSI_EXT_RESET_BASE_IDX                                                             2
16252 #define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE                                                               0x27e3
16253 #define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX                                                      2
16254 #define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE                                                               0x27e4
16255 #define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX                                                      2
16256 #define mmDSI0_DISP_DSI_LANE_CRC_CTRL                                                                  0x27e5
16257 #define mmDSI0_DISP_DSI_LANE_CRC_CTRL_BASE_IDX                                                         2
16258 #define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL                                                                 0x27e6
16259 #define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX                                                        2
16260 #define mmDSI0_DISP_DSI_LANE_CTRL                                                                      0x27e7
16261 #define mmDSI0_DISP_DSI_LANE_CTRL_BASE_IDX                                                             2
16262 #define mmDSI0_DISP_DSI_DLN0_PHY_ERROR                                                                 0x27e8
16263 #define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX                                                        2
16264 #define mmDSI0_DISP_DSI_LP_TIMER_CTRL                                                                  0x27e9
16265 #define mmDSI0_DISP_DSI_LP_TIMER_CTRL_BASE_IDX                                                         2
16266 #define mmDSI0_DISP_DSI_HS_TIMER_CTRL                                                                  0x27ea
16267 #define mmDSI0_DISP_DSI_HS_TIMER_CTRL_BASE_IDX                                                         2
16268 #define mmDSI0_DISP_DSI_TIMEOUT_STATUS                                                                 0x27eb
16269 #define mmDSI0_DISP_DSI_TIMEOUT_STATUS_BASE_IDX                                                        2
16270 #define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL                                                            0x27ec
16271 #define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX                                                   2
16272 #define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2                                                           0x27ed
16273 #define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX                                                  2
16274 #define mmDSI0_DISP_DSI_EOT_PACKET                                                                     0x27ee
16275 #define mmDSI0_DISP_DSI_EOT_PACKET_BASE_IDX                                                            2
16276 #define mmDSI0_DISP_DSI_EOT_PACKET_CTRL                                                                0x27ef
16277 #define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX                                                       2
16278 #define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER                                                         0x27f0
16279 #define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX                                                2
16280 #define mmDSI0_DISP_DSI_MIPI_BIST_CTRL                                                                 0x27f1
16281 #define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX                                                        2
16282 #define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE                                                           0x27f2
16283 #define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX                                                  2
16284 #define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE                                                           0x27f3
16285 #define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX                                                  2
16286 #define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG                                                         0x27f4
16287 #define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX                                                2
16288 #define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL                                                            0x27f5
16289 #define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX                                                   2
16290 #define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT                                                            0x27f6
16291 #define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX                                                   2
16292 #define mmDSI0_DISP_DSI_MIPI_BIST_START                                                                0x27f7
16293 #define mmDSI0_DISP_DSI_MIPI_BIST_START_BASE_IDX                                                       2
16294 #define mmDSI0_DISP_DSI_MIPI_BIST_STATUS                                                               0x27f8
16295 #define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX                                                      2
16296 #define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK                                                           0x27f9
16297 #define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX                                                  2
16298 #define mmDSI0_DISP_DSI_INTERRUPT_CTRL                                                                 0x27fa
16299 #define mmDSI0_DISP_DSI_INTERRUPT_CTRL_BASE_IDX                                                        2
16300 #define mmDSI0_DISP_DSI_CLK_CTRL                                                                       0x27fb
16301 #define mmDSI0_DISP_DSI_CLK_CTRL_BASE_IDX                                                              2
16302 #define mmDSI0_DISP_DSI_CLK_STATUS                                                                     0x27fc
16303 #define mmDSI0_DISP_DSI_CLK_STATUS_BASE_IDX                                                            2
16304 #define mmDSI0_DISP_DSI_DENG_FIFO_STATUS                                                               0x27fd
16305 #define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX                                                      2
16306 #define mmDSI0_DISP_DSI_DENG_FIFO_CTRL                                                                 0x27fe
16307 #define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX                                                        2
16308 #define mmDSI0_DISP_DSI_CMD_FIFO_DATA                                                                  0x27ff
16309 #define mmDSI0_DISP_DSI_CMD_FIFO_DATA_BASE_IDX                                                         2
16310 #define mmDSI0_DISP_DSI_CMD_FIFO_CTRL                                                                  0x2800
16311 #define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX                                                         2
16312 #define mmDSI0_DISP_DSI_TE_CTRL                                                                        0x2801
16313 #define mmDSI0_DISP_DSI_TE_CTRL_BASE_IDX                                                               2
16314 #define mmDSI0_DISP_DSI_LANE_STATUS                                                                    0x2805
16315 #define mmDSI0_DISP_DSI_LANE_STATUS_BASE_IDX                                                           2
16316 #define mmDSI0_DISP_DSI_PERF_CTRL                                                                      0x2806
16317 #define mmDSI0_DISP_DSI_PERF_CTRL_BASE_IDX                                                             2
16318 #define mmDSI0_DISP_DSI_HSYNC_LENGTH                                                                   0x2807
16319 #define mmDSI0_DISP_DSI_HSYNC_LENGTH_BASE_IDX                                                          2
16320 #define mmDSI0_DISP_DSI_RDBK_NUM                                                                       0x2808
16321 #define mmDSI0_DISP_DSI_RDBK_NUM_BASE_IDX                                                              2
16322 #define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL                                                               0x2809
16323 #define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX                                                      2
16324 
16325 
16326 // addressBlock: dce_dc_dsi1_dispdec
16327 // base address: 0x400
16328 #define mmDSI1_DISP_DSI_CTRL                                                                           0x28be
16329 #define mmDSI1_DISP_DSI_CTRL_BASE_IDX                                                                  2
16330 #define mmDSI1_DISP_DSI_STATUS                                                                         0x28bf
16331 #define mmDSI1_DISP_DSI_STATUS_BASE_IDX                                                                2
16332 #define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL                                                                0x28c0
16333 #define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX                                                       2
16334 #define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE                                                       0x28c1
16335 #define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX                                              2
16336 #define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD                                                       0x28c2
16337 #define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX                                              2
16338 #define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD                                                       0x28c3
16339 #define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX                                              2
16340 #define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE                                                      0x28c4
16341 #define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX                                             2
16342 #define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE                                                   0x28c5
16343 #define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX                                          2
16344 #define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL                                                           0x28c6
16345 #define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX                                                  2
16346 #define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL                                                              0x28c7
16347 #define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX                                                     2
16348 #define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL                                                         0x28c8
16349 #define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX                                                2
16350 #define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL                                                      0x28c9
16351 #define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX                                             2
16352 #define mmDSI1_DISP_DSI_DMA_CMD_OFFSET                                                                 0x28ca
16353 #define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX                                                        2
16354 #define mmDSI1_DISP_DSI_DMA_CMD_LENGTH                                                                 0x28cb
16355 #define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX                                                        2
16356 #define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0                                                              0x28cc
16357 #define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX                                                     2
16358 #define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1                                                              0x28cd
16359 #define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX                                                     2
16360 #define mmDSI1_DISP_DSI_DMA_DATA_PITCH                                                                 0x28ce
16361 #define mmDSI1_DISP_DSI_DMA_DATA_PITCH_BASE_IDX                                                        2
16362 #define mmDSI1_DISP_DSI_DMA_DATA_WIDTH                                                                 0x28cf
16363 #define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX                                                        2
16364 #define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT                                                                0x28d0
16365 #define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX                                                       2
16366 #define mmDSI1_DISP_DSI_DMA_FIFO_CTRL                                                                  0x28d1
16367 #define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX                                                         2
16368 #define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA                                                           0x28d2
16369 #define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX                                                  2
16370 #define mmDSI1_DISP_DSI_DENG_DATA_LENGTH                                                               0x28d3
16371 #define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX                                                      2
16372 #define mmDSI1_DISP_DSI_ACK_ERROR_REPORT                                                               0x28d4
16373 #define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX                                                      2
16374 #define mmDSI1_DISP_DSI_RDBK_DATA0                                                                     0x28d5
16375 #define mmDSI1_DISP_DSI_RDBK_DATA0_BASE_IDX                                                            2
16376 #define mmDSI1_DISP_DSI_RDBK_DATA1                                                                     0x28d6
16377 #define mmDSI1_DISP_DSI_RDBK_DATA1_BASE_IDX                                                            2
16378 #define mmDSI1_DISP_DSI_RDBK_DATA2                                                                     0x28d7
16379 #define mmDSI1_DISP_DSI_RDBK_DATA2_BASE_IDX                                                            2
16380 #define mmDSI1_DISP_DSI_RDBK_DATA3                                                                     0x28d8
16381 #define mmDSI1_DISP_DSI_RDBK_DATA3_BASE_IDX                                                            2
16382 #define mmDSI1_DISP_DSI_RDBK_DATATYPE0                                                                 0x28d9
16383 #define mmDSI1_DISP_DSI_RDBK_DATATYPE0_BASE_IDX                                                        2
16384 #define mmDSI1_DISP_DSI_RDBK_DATATYPE1                                                                 0x28da
16385 #define mmDSI1_DISP_DSI_RDBK_DATATYPE1_BASE_IDX                                                        2
16386 #define mmDSI1_DISP_DSI_TRIG_CTRL                                                                      0x28db
16387 #define mmDSI1_DISP_DSI_TRIG_CTRL_BASE_IDX                                                             2
16388 #define mmDSI1_DISP_DSI_EXT_MUX                                                                        0x28dc
16389 #define mmDSI1_DISP_DSI_EXT_MUX_BASE_IDX                                                               2
16390 #define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL                                                    0x28dd
16391 #define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX                                           2
16392 #define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER                                                        0x28de
16393 #define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX                                               2
16394 #define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER                                                       0x28df
16395 #define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX                                              2
16396 #define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER                                                        0x28e0
16397 #define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX                                               2
16398 #define mmDSI1_DISP_DSI_RESET_SW_TRIGGER                                                               0x28e1
16399 #define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX                                                      2
16400 #define mmDSI1_DISP_DSI_EXT_RESET                                                                      0x28e2
16401 #define mmDSI1_DISP_DSI_EXT_RESET_BASE_IDX                                                             2
16402 #define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE                                                               0x28e3
16403 #define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX                                                      2
16404 #define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE                                                               0x28e4
16405 #define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX                                                      2
16406 #define mmDSI1_DISP_DSI_LANE_CRC_CTRL                                                                  0x28e5
16407 #define mmDSI1_DISP_DSI_LANE_CRC_CTRL_BASE_IDX                                                         2
16408 #define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL                                                                 0x28e6
16409 #define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX                                                        2
16410 #define mmDSI1_DISP_DSI_LANE_CTRL                                                                      0x28e7
16411 #define mmDSI1_DISP_DSI_LANE_CTRL_BASE_IDX                                                             2
16412 #define mmDSI1_DISP_DSI_DLN0_PHY_ERROR                                                                 0x28e8
16413 #define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX                                                        2
16414 #define mmDSI1_DISP_DSI_LP_TIMER_CTRL                                                                  0x28e9
16415 #define mmDSI1_DISP_DSI_LP_TIMER_CTRL_BASE_IDX                                                         2
16416 #define mmDSI1_DISP_DSI_HS_TIMER_CTRL                                                                  0x28ea
16417 #define mmDSI1_DISP_DSI_HS_TIMER_CTRL_BASE_IDX                                                         2
16418 #define mmDSI1_DISP_DSI_TIMEOUT_STATUS                                                                 0x28eb
16419 #define mmDSI1_DISP_DSI_TIMEOUT_STATUS_BASE_IDX                                                        2
16420 #define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL                                                            0x28ec
16421 #define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX                                                   2
16422 #define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2                                                           0x28ed
16423 #define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX                                                  2
16424 #define mmDSI1_DISP_DSI_EOT_PACKET                                                                     0x28ee
16425 #define mmDSI1_DISP_DSI_EOT_PACKET_BASE_IDX                                                            2
16426 #define mmDSI1_DISP_DSI_EOT_PACKET_CTRL                                                                0x28ef
16427 #define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX                                                       2
16428 #define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER                                                         0x28f0
16429 #define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX                                                2
16430 #define mmDSI1_DISP_DSI_MIPI_BIST_CTRL                                                                 0x28f1
16431 #define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX                                                        2
16432 #define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE                                                           0x28f2
16433 #define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX                                                  2
16434 #define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE                                                           0x28f3
16435 #define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX                                                  2
16436 #define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG                                                         0x28f4
16437 #define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX                                                2
16438 #define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL                                                            0x28f5
16439 #define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX                                                   2
16440 #define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT                                                            0x28f6
16441 #define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX                                                   2
16442 #define mmDSI1_DISP_DSI_MIPI_BIST_START                                                                0x28f7
16443 #define mmDSI1_DISP_DSI_MIPI_BIST_START_BASE_IDX                                                       2
16444 #define mmDSI1_DISP_DSI_MIPI_BIST_STATUS                                                               0x28f8
16445 #define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX                                                      2
16446 #define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK                                                           0x28f9
16447 #define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX                                                  2
16448 #define mmDSI1_DISP_DSI_INTERRUPT_CTRL                                                                 0x28fa
16449 #define mmDSI1_DISP_DSI_INTERRUPT_CTRL_BASE_IDX                                                        2
16450 #define mmDSI1_DISP_DSI_CLK_CTRL                                                                       0x28fb
16451 #define mmDSI1_DISP_DSI_CLK_CTRL_BASE_IDX                                                              2
16452 #define mmDSI1_DISP_DSI_CLK_STATUS                                                                     0x28fc
16453 #define mmDSI1_DISP_DSI_CLK_STATUS_BASE_IDX                                                            2
16454 #define mmDSI1_DISP_DSI_DENG_FIFO_STATUS                                                               0x28fd
16455 #define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX                                                      2
16456 #define mmDSI1_DISP_DSI_DENG_FIFO_CTRL                                                                 0x28fe
16457 #define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX                                                        2
16458 #define mmDSI1_DISP_DSI_CMD_FIFO_DATA                                                                  0x28ff
16459 #define mmDSI1_DISP_DSI_CMD_FIFO_DATA_BASE_IDX                                                         2
16460 #define mmDSI1_DISP_DSI_CMD_FIFO_CTRL                                                                  0x2900
16461 #define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX                                                         2
16462 #define mmDSI1_DISP_DSI_TE_CTRL                                                                        0x2901
16463 #define mmDSI1_DISP_DSI_TE_CTRL_BASE_IDX                                                               2
16464 #define mmDSI1_DISP_DSI_LANE_STATUS                                                                    0x2905
16465 #define mmDSI1_DISP_DSI_LANE_STATUS_BASE_IDX                                                           2
16466 #define mmDSI1_DISP_DSI_PERF_CTRL                                                                      0x2906
16467 #define mmDSI1_DISP_DSI_PERF_CTRL_BASE_IDX                                                             2
16468 #define mmDSI1_DISP_DSI_HSYNC_LENGTH                                                                   0x2907
16469 #define mmDSI1_DISP_DSI_HSYNC_LENGTH_BASE_IDX                                                          2
16470 #define mmDSI1_DISP_DSI_RDBK_NUM                                                                       0x2908
16471 #define mmDSI1_DISP_DSI_RDBK_NUM_BASE_IDX                                                              2
16472 #define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL                                                               0x2909
16473 #define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX                                                      2
16474 
16475 
16476 // addressBlock: dce_dc_dprx_sd0_dispdec
16477 // base address: 0x0
16478 #define mmDPRX_SD0_DPRX_SD_CONTROL                                                                     0x29be
16479 #define mmDPRX_SD0_DPRX_SD_CONTROL_BASE_IDX                                                            2
16480 #define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE                                                               0x29bf
16481 #define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_BASE_IDX                                                      2
16482 #define mmDPRX_SD0_DPRX_SD_MSA0                                                                        0x29c0
16483 #define mmDPRX_SD0_DPRX_SD_MSA0_BASE_IDX                                                               2
16484 #define mmDPRX_SD0_DPRX_SD_MSA1                                                                        0x29c1
16485 #define mmDPRX_SD0_DPRX_SD_MSA1_BASE_IDX                                                               2
16486 #define mmDPRX_SD0_DPRX_SD_MSA2                                                                        0x29c2
16487 #define mmDPRX_SD0_DPRX_SD_MSA2_BASE_IDX                                                               2
16488 #define mmDPRX_SD0_DPRX_SD_MSA3                                                                        0x29c3
16489 #define mmDPRX_SD0_DPRX_SD_MSA3_BASE_IDX                                                               2
16490 #define mmDPRX_SD0_DPRX_SD_MSA4                                                                        0x29c4
16491 #define mmDPRX_SD0_DPRX_SD_MSA4_BASE_IDX                                                               2
16492 #define mmDPRX_SD0_DPRX_SD_MSA5                                                                        0x29c5
16493 #define mmDPRX_SD0_DPRX_SD_MSA5_BASE_IDX                                                               2
16494 #define mmDPRX_SD0_DPRX_SD_MSA6                                                                        0x29c6
16495 #define mmDPRX_SD0_DPRX_SD_MSA6_BASE_IDX                                                               2
16496 #define mmDPRX_SD0_DPRX_SD_MSA7                                                                        0x29c7
16497 #define mmDPRX_SD0_DPRX_SD_MSA7_BASE_IDX                                                               2
16498 #define mmDPRX_SD0_DPRX_SD_MSA8                                                                        0x29c8
16499 #define mmDPRX_SD0_DPRX_SD_MSA8_BASE_IDX                                                               2
16500 #define mmDPRX_SD0_DPRX_SD_VBID                                                                        0x29c9
16501 #define mmDPRX_SD0_DPRX_SD_VBID_BASE_IDX                                                               2
16502 #define mmDPRX_SD0_DPRX_SD_CURRENT_LINE                                                                0x29ca
16503 #define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_BASE_IDX                                                       2
16504 #define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT                                                      0x29cb
16505 #define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX                                             2
16506 #define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE                                                          0x29cc
16507 #define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX                                                 2
16508 #define mmDPRX_SD0_DPRX_SD_MSE_SAT                                                                     0x29ce
16509 #define mmDPRX_SD0_DPRX_SD_MSE_SAT_BASE_IDX                                                            2
16510 #define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE                                                            0x29cf
16511 #define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX                                                   2
16512 #define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE                                                              0x29d0
16513 #define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX                                                     2
16514 #define mmDPRX_SD0_DPRX_SD_V_PARAMETER                                                                 0x29d1
16515 #define mmDPRX_SD0_DPRX_SD_V_PARAMETER_BASE_IDX                                                        2
16516 #define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT                                                                0x29d2
16517 #define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_BASE_IDX                                                       2
16518 #define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS                                                         0x29d3
16519 #define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX                                                2
16520 #define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED                                                 0x29d4
16521 #define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX                                        2
16522 #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS                                                         0x29d5
16523 #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX                                                2
16524 #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL                                                        0x29d6
16525 #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX                                               2
16526 #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS                                                         0x29d7
16527 #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX                                                2
16528 #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL                                                        0x29d8
16529 #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX                                               2
16530 #define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR                                                        0x29d9
16531 #define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX                                               2
16532 #define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE                                                          0x29da
16533 #define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX                                                 2
16534 #define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR                                                   0x29db
16535 #define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX                                          2
16536 #define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED                                                           0x29dc
16537 #define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX                                                  2
16538 #define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR                                                            0x29dd
16539 #define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX                                                   2
16540 #define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR                                                         0x29de
16541 #define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX                                                2
16542 #define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR                                                            0x29df
16543 #define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX                                                   2
16544 #define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH                                                  0x29e1
16545 #define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX                                         2
16546 #define mmDPRX_SD0_DPRX_SD_SDP_STEER                                                                   0x29e3
16547 #define mmDPRX_SD0_DPRX_SD_SDP_STEER_BASE_IDX                                                          2
16548 #define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS                                                         0x29e4
16549 #define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX                                                2
16550 #define mmDPRX_SD0_DPRX_SD_SDP_LEVEL                                                                   0x29e5
16551 #define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_BASE_IDX                                                          2
16552 #define mmDPRX_SD0_DPRX_SD_SDP_DATA                                                                    0x29e6
16553 #define mmDPRX_SD0_DPRX_SD_SDP_DATA_BASE_IDX                                                           2
16554 #define mmDPRX_SD0_DPRX_SD_SDP_ERROR                                                                   0x29e7
16555 #define mmDPRX_SD0_DPRX_SD_SDP_ERROR_BASE_IDX                                                          2
16556 #define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER                                                                0x29e8
16557 #define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_BASE_IDX                                                       2
16558 #define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR                                                            0x29e9
16559 #define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX                                                   2
16560 #define mmDPRX_SD0_DPRX_SD_SDP_CONTROL                                                                 0x29ea
16561 #define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_BASE_IDX                                                        2
16562 #define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED                                                            0x29eb
16563 #define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX                                                   2
16564 #define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED                                                            0x29ec
16565 #define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX                                                   2
16566 #define mmDPRX_SD0_DPRX_SD_BS_COUNTER                                                                  0x29ed
16567 #define mmDPRX_SD0_DPRX_SD_BS_COUNTER_BASE_IDX                                                         2
16568 #define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED                                                             0x29ee
16569 #define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX                                                    2
16570 
16571 
16572 // addressBlock: dce_dc_dprx_sd1_dispdec
16573 // base address: 0x180
16574 #define mmDPRX_SD1_DPRX_SD_CONTROL                                                                     0x2a1e
16575 #define mmDPRX_SD1_DPRX_SD_CONTROL_BASE_IDX                                                            2
16576 #define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE                                                               0x2a1f
16577 #define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_BASE_IDX                                                      2
16578 #define mmDPRX_SD1_DPRX_SD_MSA0                                                                        0x2a20
16579 #define mmDPRX_SD1_DPRX_SD_MSA0_BASE_IDX                                                               2
16580 #define mmDPRX_SD1_DPRX_SD_MSA1                                                                        0x2a21
16581 #define mmDPRX_SD1_DPRX_SD_MSA1_BASE_IDX                                                               2
16582 #define mmDPRX_SD1_DPRX_SD_MSA2                                                                        0x2a22
16583 #define mmDPRX_SD1_DPRX_SD_MSA2_BASE_IDX                                                               2
16584 #define mmDPRX_SD1_DPRX_SD_MSA3                                                                        0x2a23
16585 #define mmDPRX_SD1_DPRX_SD_MSA3_BASE_IDX                                                               2
16586 #define mmDPRX_SD1_DPRX_SD_MSA4                                                                        0x2a24
16587 #define mmDPRX_SD1_DPRX_SD_MSA4_BASE_IDX                                                               2
16588 #define mmDPRX_SD1_DPRX_SD_MSA5                                                                        0x2a25
16589 #define mmDPRX_SD1_DPRX_SD_MSA5_BASE_IDX                                                               2
16590 #define mmDPRX_SD1_DPRX_SD_MSA6                                                                        0x2a26
16591 #define mmDPRX_SD1_DPRX_SD_MSA6_BASE_IDX                                                               2
16592 #define mmDPRX_SD1_DPRX_SD_MSA7                                                                        0x2a27
16593 #define mmDPRX_SD1_DPRX_SD_MSA7_BASE_IDX                                                               2
16594 #define mmDPRX_SD1_DPRX_SD_MSA8                                                                        0x2a28
16595 #define mmDPRX_SD1_DPRX_SD_MSA8_BASE_IDX                                                               2
16596 #define mmDPRX_SD1_DPRX_SD_VBID                                                                        0x2a29
16597 #define mmDPRX_SD1_DPRX_SD_VBID_BASE_IDX                                                               2
16598 #define mmDPRX_SD1_DPRX_SD_CURRENT_LINE                                                                0x2a2a
16599 #define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_BASE_IDX                                                       2
16600 #define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT                                                      0x2a2b
16601 #define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX                                             2
16602 #define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE                                                          0x2a2c
16603 #define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX                                                 2
16604 #define mmDPRX_SD1_DPRX_SD_MSE_SAT                                                                     0x2a2e
16605 #define mmDPRX_SD1_DPRX_SD_MSE_SAT_BASE_IDX                                                            2
16606 #define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE                                                            0x2a2f
16607 #define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX                                                   2
16608 #define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE                                                              0x2a30
16609 #define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX                                                     2
16610 #define mmDPRX_SD1_DPRX_SD_V_PARAMETER                                                                 0x2a31
16611 #define mmDPRX_SD1_DPRX_SD_V_PARAMETER_BASE_IDX                                                        2
16612 #define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT                                                                0x2a32
16613 #define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_BASE_IDX                                                       2
16614 #define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS                                                         0x2a33
16615 #define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX                                                2
16616 #define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED                                                 0x2a34
16617 #define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX                                        2
16618 #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS                                                         0x2a35
16619 #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX                                                2
16620 #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL                                                        0x2a36
16621 #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX                                               2
16622 #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS                                                         0x2a37
16623 #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX                                                2
16624 #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL                                                        0x2a38
16625 #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX                                               2
16626 #define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR                                                        0x2a39
16627 #define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX                                               2
16628 #define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE                                                          0x2a3a
16629 #define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX                                                 2
16630 #define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR                                                   0x2a3b
16631 #define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX                                          2
16632 #define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED                                                           0x2a3c
16633 #define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX                                                  2
16634 #define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR                                                            0x2a3d
16635 #define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX                                                   2
16636 #define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR                                                         0x2a3e
16637 #define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX                                                2
16638 #define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR                                                            0x2a3f
16639 #define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX                                                   2
16640 #define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH                                                  0x2a41
16641 #define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX                                         2
16642 #define mmDPRX_SD1_DPRX_SD_SDP_STEER                                                                   0x2a43
16643 #define mmDPRX_SD1_DPRX_SD_SDP_STEER_BASE_IDX                                                          2
16644 #define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS                                                         0x2a44
16645 #define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX                                                2
16646 #define mmDPRX_SD1_DPRX_SD_SDP_LEVEL                                                                   0x2a45
16647 #define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_BASE_IDX                                                          2
16648 #define mmDPRX_SD1_DPRX_SD_SDP_DATA                                                                    0x2a46
16649 #define mmDPRX_SD1_DPRX_SD_SDP_DATA_BASE_IDX                                                           2
16650 #define mmDPRX_SD1_DPRX_SD_SDP_ERROR                                                                   0x2a47
16651 #define mmDPRX_SD1_DPRX_SD_SDP_ERROR_BASE_IDX                                                          2
16652 #define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER                                                                0x2a48
16653 #define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_BASE_IDX                                                       2
16654 #define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR                                                            0x2a49
16655 #define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX                                                   2
16656 #define mmDPRX_SD1_DPRX_SD_SDP_CONTROL                                                                 0x2a4a
16657 #define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_BASE_IDX                                                        2
16658 #define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED                                                            0x2a4b
16659 #define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX                                                   2
16660 #define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED                                                            0x2a4c
16661 #define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX                                                   2
16662 #define mmDPRX_SD1_DPRX_SD_BS_COUNTER                                                                  0x2a4d
16663 #define mmDPRX_SD1_DPRX_SD_BS_COUNTER_BASE_IDX                                                         2
16664 #define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED                                                             0x2a4e
16665 #define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX                                                    2
16666 
16667 
16668 // addressBlock: dce_dc_dc_perfmon10_dispdec
16669 // base address: 0xacf8
16670 #define mmDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x2b5e
16671 #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
16672 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x2b5f
16673 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
16674 #define mmDC_PERFMON10_PERFCOUNTER_STATE                                                               0x2b60
16675 #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
16676 #define mmDC_PERFMON10_PERFMON_CNTL                                                                    0x2b61
16677 #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
16678 #define mmDC_PERFMON10_PERFMON_CNTL2                                                                   0x2b62
16679 #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
16680 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x2b63
16681 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
16682 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x2b64
16683 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
16684 #define mmDC_PERFMON10_PERFMON_HI                                                                      0x2b65
16685 #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
16686 #define mmDC_PERFMON10_PERFMON_LOW                                                                     0x2b66
16687 #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
16688 
16689 
16690 // addressBlock: dce_dc_dc_zcalregs_dispdec
16691 // base address: 0x0
16692 #define mmCOMP_EN_CTL                                                                                  0x2d96
16693 #define mmCOMP_EN_CTL_BASE_IDX                                                                         2
16694 #define mmCOMP_EN_DFX                                                                                  0x2d97
16695 #define mmCOMP_EN_DFX_BASE_IDX                                                                         2
16696 #define mmZCAL_FUSES                                                                                   0x2d98
16697 #define mmZCAL_FUSES_BASE_IDX                                                                          2
16698 
16699 
16700 // addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
16701 // base address: 0x48
16702 //#define mmVGA_dispdec_VGA_MEM_WRITE_PAGE_ADDR                                                          0x0012
16703 
16704 
16705 // addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
16706 // base address: 0x4c
16707 //#define mmVGA_dispdec_VGA_MEM_READ_PAGE_ADDR                                                           0x0014
16708 
16709 
16710 // addressBlock: dce_dc_dispdec[948..986]
16711 // base address: 0x3b4
16712 //#define mmVGA_CRTC8_IDX                                                                                0x002d
16713 //#define mmVGA_CRTC8_DATA                                                                               0x002d
16714 //#define mmVGA_GENFC_WT                                                                                 0x002e
16715 //#define mmVGA_GENS1                                                                                    0x002e
16716 //#define mmVGA_ATTRDW                                                                                   0x0030
16717 //#define mmVGA_ATTRX                                                                                    0x0030
16718 //#define mmVGA_ATTRDR                                                                                   0x0030
16719 //#define mmVGA_GENMO_WT                                                                                 0x0030
16720 //#define mmVGA_GENS0                                                                                    0x0030
16721 //#define mmVGA_GENENB                                                                                   0x0030
16722 //#define mmVGA_SEQ8_IDX                                                                                 0x0031
16723 //#define mmVGA_SEQ8_DATA                                                                                0x0031
16724 //#define mmVGA_DAC_MASK                                                                                 0x0031
16725 //#define mmVGA_DAC_R_INDEX                                                                              0x0031
16726 //#define mmVGA_DAC_W_INDEX                                                                              0x0032
16727 //#define mmVGA_DAC_DATA                                                                                 0x0032
16728 //#define mmVGA_GENFC_RD                                                                                 0x0032
16729 //#define mmVGA_GENMO_RD                                                                                 0x0033
16730 //#define mmVGA_GRPH8_IDX                                                                                0x0033
16731 //#define mmVGA_GRPH8_DATA                                                                               0x0033
16732 //#define mmVGA_CRTC8_IDX_1                                                                              0x0035
16733 //#define mmVGA_CRTC8_DATA_1                                                                             0x0035
16734 //#define mmVGA_GENFC_WT_1                                                                               0x0036
16735 //#define mmVGA_GENS1_1                                                                                  0x0036
16736 
16737 
16738 // addressBlock: dce_dc_azdec
16739 // base address: 0x0
16740 #define mmCORB_WRITE_POINTER                                                                           0x0000
16741 #define mmCORB_WRITE_POINTER_BASE_IDX                                                                  0
16742 #define mmCORB_READ_POINTER                                                                            0x0000
16743 #define mmCORB_READ_POINTER_BASE_IDX                                                                   0
16744 #define mmCORB_CONTROL                                                                                 0x0001
16745 #define mmCORB_CONTROL_BASE_IDX                                                                        0
16746 #define mmCORB_STATUS                                                                                  0x0001
16747 #define mmCORB_STATUS_BASE_IDX                                                                         0
16748 #define mmCORB_SIZE                                                                                    0x0001
16749 #define mmCORB_SIZE_BASE_IDX                                                                           0
16750 #define mmRIRB_LOWER_BASE_ADDRESS                                                                      0x0002
16751 #define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX                                                             0
16752 #define mmRIRB_UPPER_BASE_ADDRESS                                                                      0x0003
16753 #define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX                                                             0
16754 #define mmRIRB_WRITE_POINTER                                                                           0x0004
16755 #define mmRIRB_WRITE_POINTER_BASE_IDX                                                                  0
16756 #define mmRESPONSE_INTERRUPT_COUNT                                                                     0x0004
16757 #define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX                                                            0
16758 #define mmRIRB_CONTROL                                                                                 0x0005
16759 #define mmRIRB_CONTROL_BASE_IDX                                                                        0
16760 #define mmRIRB_STATUS                                                                                  0x0005
16761 #define mmRIRB_STATUS_BASE_IDX                                                                         0
16762 #define mmRIRB_SIZE                                                                                    0x0005
16763 #define mmRIRB_SIZE_BASE_IDX                                                                           0
16764 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                                            0x0006
16765 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                                   0
16766 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                                           0x0006
16767 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                                  0
16768 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                           0x0006
16769 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                  0
16770 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                          0x0006
16771 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                 0
16772 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                               0x0006
16773 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                      0
16774 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                              0x0006
16775 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                     0
16776 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                                           0x0006
16777 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                                  0
16778 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                                      0x0006
16779 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                             0
16780 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                                     0x0006
16781 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                            0
16782 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                                           0x0007
16783 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                                  0
16784 #define mmIMMEDIATE_COMMAND_STATUS                                                                     0x0008
16785 #define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX                                                            0
16786 #define mmDMA_POSITION_LOWER_BASE_ADDRESS                                                              0x000a
16787 #define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                                     0
16788 #define mmDMA_POSITION_UPPER_BASE_ADDRESS                                                              0x000b
16789 #define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                                     0
16790 #define mmWALL_CLOCK_COUNTER_ALIAS                                                                     0x074c
16791 #define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                                            1
16792 
16793 
16794 // addressBlock: dce_dc_azstream0_azdec
16795 // base address: 0x0
16796 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x000e
16797 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
16798 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x000f
16799 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
16800 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0010
16801 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
16802 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0011
16803 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
16804 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0012
16805 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
16806 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0012
16807 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
16808 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0014
16809 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
16810 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0015
16811 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
16812 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0761
16813 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
16814 
16815 
16816 // addressBlock: dce_dc_azstream1_azdec
16817 // base address: 0x20
16818 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0016
16819 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
16820 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0017
16821 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
16822 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0018
16823 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
16824 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0019
16825 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
16826 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x001a
16827 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
16828 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x001a
16829 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
16830 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x001c
16831 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
16832 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x001d
16833 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
16834 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0769
16835 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
16836 
16837 
16838 // addressBlock: dce_dc_azstream2_azdec
16839 // base address: 0x40
16840 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x001e
16841 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
16842 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x001f
16843 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
16844 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0020
16845 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
16846 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0021
16847 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
16848 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0022
16849 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
16850 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0022
16851 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
16852 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0024
16853 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
16854 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0025
16855 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
16856 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0771
16857 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
16858 
16859 
16860 // addressBlock: dce_dc_azstream3_azdec
16861 // base address: 0x60
16862 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0026
16863 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
16864 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0027
16865 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
16866 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0028
16867 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
16868 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0029
16869 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
16870 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x002a
16871 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
16872 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x002a
16873 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
16874 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x002c
16875 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
16876 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x002d
16877 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
16878 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0779
16879 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
16880 
16881 
16882 // addressBlock: dce_dc_azstream4_azdec
16883 // base address: 0x80
16884 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x002e
16885 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
16886 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x002f
16887 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
16888 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0030
16889 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
16890 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0031
16891 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
16892 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0032
16893 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
16894 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0032
16895 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
16896 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0034
16897 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
16898 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0035
16899 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
16900 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0781
16901 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
16902 
16903 
16904 // addressBlock: dce_dc_azstream5_azdec
16905 // base address: 0xa0
16906 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0036
16907 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
16908 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0037
16909 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
16910 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0038
16911 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
16912 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0039
16913 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
16914 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x003a
16915 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
16916 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x003a
16917 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
16918 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x003c
16919 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
16920 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x003d
16921 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
16922 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0789
16923 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
16924 
16925 
16926 // addressBlock: dce_dc_azstream6_azdec
16927 // base address: 0xc0
16928 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x003e
16929 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
16930 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x003f
16931 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
16932 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0040
16933 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
16934 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0041
16935 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
16936 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x0042
16937 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
16938 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x0042
16939 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
16940 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x0044
16941 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
16942 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x0045
16943 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
16944 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0791
16945 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
16946 
16947 
16948 // addressBlock: dce_dc_azstream7_azdec
16949 // base address: 0xe0
16950 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                        0x0046
16951 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                               0
16952 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                           0x0047
16953 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                  0
16954 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                      0x0048
16955 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                             0
16956 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                          0x0049
16957 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                                 0
16958 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                                 0x004a
16959 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                        0
16960 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                    0x004a
16961 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                           0
16962 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                            0x004c
16963 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                   0
16964 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                            0x004d
16965 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                   0
16966 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                     0x0799
16967 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX            1
16968 
16969 
16970 // addressBlock: azf0stream0_streamind
16971 // base address: 0x0
16972 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
16973 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
16974 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
16975 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
16976 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
16977 
16978 
16979 // addressBlock: azf0stream1_streamind
16980 // base address: 0x0
16981 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
16982 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
16983 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
16984 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
16985 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
16986 
16987 
16988 // addressBlock: azf0stream2_streamind
16989 // base address: 0x0
16990 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
16991 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
16992 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
16993 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
16994 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
16995 
16996 
16997 // addressBlock: azf0stream3_streamind
16998 // base address: 0x0
16999 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
17000 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
17001 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
17002 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
17003 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
17004 
17005 
17006 // addressBlock: azf0stream4_streamind
17007 // base address: 0x0
17008 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
17009 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
17010 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
17011 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
17012 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
17013 
17014 
17015 // addressBlock: azf0stream5_streamind
17016 // base address: 0x0
17017 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
17018 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
17019 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
17020 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
17021 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
17022 
17023 
17024 // addressBlock: azf0stream6_streamind
17025 // base address: 0x0
17026 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
17027 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
17028 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
17029 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
17030 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
17031 
17032 
17033 // addressBlock: azf0stream7_streamind
17034 // base address: 0x0
17035 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
17036 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
17037 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
17038 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
17039 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
17040 
17041 
17042 // addressBlock: azf0stream8_streamind
17043 // base address: 0x0
17044 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
17045 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
17046 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
17047 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
17048 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
17049 
17050 
17051 // addressBlock: azf0stream9_streamind
17052 // base address: 0x0
17053 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
17054 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
17055 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
17056 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
17057 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
17058 
17059 
17060 // addressBlock: azf0stream10_streamind
17061 // base address: 0x0
17062 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
17063 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
17064 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
17065 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
17066 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
17067 
17068 
17069 // addressBlock: azf0stream11_streamind
17070 // base address: 0x0
17071 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
17072 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
17073 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
17074 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
17075 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
17076 
17077 
17078 // addressBlock: azf0stream12_streamind
17079 // base address: 0x0
17080 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
17081 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
17082 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
17083 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
17084 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
17085 
17086 
17087 // addressBlock: azf0stream13_streamind
17088 // base address: 0x0
17089 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
17090 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
17091 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
17092 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
17093 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
17094 
17095 
17096 // addressBlock: azf0stream14_streamind
17097 // base address: 0x0
17098 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
17099 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
17100 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
17101 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
17102 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
17103 
17104 
17105 // addressBlock: azf0stream15_streamind
17106 // base address: 0x0
17107 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
17108 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
17109 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
17110 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
17111 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
17112 
17113 
17114 // addressBlock: azf0endpoint0_endpointind
17115 // base address: 0x0
17116 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
17117 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
17118 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
17119 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
17120 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
17121 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
17122 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
17123 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
17124 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
17125 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
17126 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
17127 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
17128 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
17129 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
17130 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
17131 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
17132 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
17133 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
17134 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
17135 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
17136 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
17137 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
17138 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
17139 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
17140 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
17141 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
17142 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
17143 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
17144 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
17145 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
17146 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
17147 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
17148 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
17149 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
17150 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
17151 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
17152 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
17153 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
17154 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
17155 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
17156 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
17157 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
17158 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
17159 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
17160 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
17161 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
17162 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
17163 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
17164 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
17165 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
17166 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
17167 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
17168 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
17169 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
17170 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
17171 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
17172 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
17173 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
17174 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
17175 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
17176 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
17177 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
17178 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
17179 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
17180 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
17181 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
17182 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
17183 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
17184 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
17185 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
17186 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
17187 
17188 
17189 // addressBlock: azf0endpoint1_endpointind
17190 // base address: 0x0
17191 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
17192 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
17193 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
17194 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
17195 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
17196 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
17197 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
17198 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
17199 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
17200 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
17201 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
17202 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
17203 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
17204 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
17205 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
17206 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
17207 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
17208 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
17209 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
17210 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
17211 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
17212 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
17213 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
17214 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
17215 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
17216 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
17217 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
17218 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
17219 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
17220 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
17221 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
17222 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
17223 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
17224 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
17225 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
17226 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
17227 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
17228 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
17229 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
17230 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
17231 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
17232 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
17233 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
17234 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
17235 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
17236 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
17237 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
17238 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
17239 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
17240 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
17241 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
17242 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
17243 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
17244 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
17245 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
17246 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
17247 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
17248 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
17249 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
17250 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
17251 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
17252 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
17253 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
17254 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
17255 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
17256 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
17257 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
17258 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
17259 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
17260 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
17261 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
17262 
17263 
17264 // addressBlock: azf0endpoint2_endpointind
17265 // base address: 0x0
17266 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
17267 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
17268 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
17269 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
17270 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
17271 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
17272 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
17273 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
17274 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
17275 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
17276 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
17277 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
17278 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
17279 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
17280 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
17281 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
17282 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
17283 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
17284 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
17285 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
17286 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
17287 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
17288 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
17289 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
17290 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
17291 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
17292 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
17293 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
17294 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
17295 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
17296 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
17297 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
17298 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
17299 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
17300 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
17301 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
17302 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
17303 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
17304 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
17305 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
17306 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
17307 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
17308 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
17309 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
17310 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
17311 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
17312 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
17313 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
17314 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
17315 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
17316 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
17317 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
17318 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
17319 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
17320 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
17321 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
17322 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
17323 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
17324 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
17325 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
17326 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
17327 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
17328 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
17329 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
17330 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
17331 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
17332 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
17333 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
17334 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
17335 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
17336 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
17337 
17338 
17339 // addressBlock: azf0endpoint3_endpointind
17340 // base address: 0x0
17341 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
17342 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
17343 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
17344 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
17345 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
17346 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
17347 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
17348 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
17349 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
17350 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
17351 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
17352 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
17353 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
17354 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
17355 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
17356 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
17357 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
17358 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
17359 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
17360 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
17361 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
17362 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
17363 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
17364 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
17365 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
17366 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
17367 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
17368 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
17369 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
17370 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
17371 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
17372 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
17373 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
17374 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
17375 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
17376 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
17377 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
17378 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
17379 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
17380 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
17381 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
17382 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
17383 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
17384 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
17385 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
17386 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
17387 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
17388 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
17389 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
17390 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
17391 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
17392 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
17393 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
17394 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
17395 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
17396 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
17397 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
17398 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
17399 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
17400 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
17401 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
17402 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
17403 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
17404 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
17405 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
17406 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
17407 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
17408 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
17409 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
17410 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
17411 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
17412 
17413 
17414 // addressBlock: azf0endpoint4_endpointind
17415 // base address: 0x0
17416 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
17417 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
17418 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
17419 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
17420 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
17421 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
17422 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
17423 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
17424 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
17425 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
17426 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
17427 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
17428 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
17429 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
17430 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
17431 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
17432 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
17433 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
17434 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
17435 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
17436 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
17437 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
17438 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
17439 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
17440 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
17441 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
17442 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
17443 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
17444 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
17445 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
17446 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
17447 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
17448 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
17449 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
17450 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
17451 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
17452 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
17453 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
17454 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
17455 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
17456 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
17457 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
17458 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
17459 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
17460 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
17461 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
17462 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
17463 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
17464 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
17465 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
17466 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
17467 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
17468 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
17469 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
17470 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
17471 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
17472 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
17473 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
17474 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
17475 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
17476 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
17477 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
17478 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
17479 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
17480 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
17481 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
17482 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
17483 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
17484 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
17485 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
17486 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
17487 
17488 
17489 // addressBlock: azf0endpoint5_endpointind
17490 // base address: 0x0
17491 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
17492 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
17493 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
17494 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
17495 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
17496 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
17497 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
17498 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
17499 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
17500 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
17501 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
17502 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
17503 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
17504 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
17505 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
17506 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
17507 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
17508 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
17509 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
17510 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
17511 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
17512 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
17513 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
17514 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
17515 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
17516 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
17517 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
17518 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
17519 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
17520 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
17521 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
17522 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
17523 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
17524 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
17525 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
17526 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
17527 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
17528 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
17529 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
17530 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
17531 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
17532 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
17533 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
17534 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
17535 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
17536 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
17537 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
17538 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
17539 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
17540 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
17541 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
17542 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
17543 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
17544 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
17545 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
17546 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
17547 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
17548 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
17549 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
17550 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
17551 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
17552 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
17553 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
17554 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
17555 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
17556 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
17557 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
17558 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
17559 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
17560 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
17561 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
17562 
17563 
17564 // addressBlock: azf0endpoint6_endpointind
17565 // base address: 0x0
17566 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
17567 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
17568 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
17569 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
17570 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
17571 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
17572 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
17573 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
17574 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
17575 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
17576 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
17577 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
17578 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
17579 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
17580 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
17581 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
17582 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
17583 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
17584 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
17585 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
17586 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
17587 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
17588 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
17589 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
17590 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
17591 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
17592 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
17593 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
17594 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
17595 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
17596 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
17597 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
17598 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
17599 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
17600 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
17601 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
17602 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
17603 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
17604 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
17605 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
17606 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
17607 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
17608 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
17609 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
17610 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
17611 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
17612 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
17613 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
17614 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
17615 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
17616 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
17617 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
17618 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
17619 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
17620 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
17621 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
17622 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
17623 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
17624 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
17625 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
17626 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
17627 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
17628 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
17629 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
17630 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
17631 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
17632 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
17633 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
17634 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
17635 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
17636 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
17637 
17638 
17639 // addressBlock: azf0endpoint7_endpointind
17640 // base address: 0x0
17641 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
17642 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
17643 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
17644 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
17645 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
17646 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
17647 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
17648 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
17649 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
17650 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
17651 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
17652 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
17653 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
17654 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
17655 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
17656 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
17657 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
17658 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
17659 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
17660 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
17661 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
17662 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
17663 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
17664 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
17665 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
17666 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
17667 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
17668 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
17669 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
17670 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
17671 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
17672 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
17673 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
17674 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
17675 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
17676 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
17677 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
17678 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
17679 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
17680 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
17681 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
17682 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
17683 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
17684 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
17685 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
17686 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
17687 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
17688 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
17689 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
17690 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
17691 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
17692 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
17693 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
17694 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
17695 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
17696 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
17697 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
17698 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
17699 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
17700 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
17701 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
17702 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
17703 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
17704 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
17705 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
17706 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
17707 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
17708 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
17709 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
17710 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
17711 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
17712 
17713 
17714 // addressBlock: azf0inputendpoint0_inputendpointind
17715 // base address: 0x0
17716 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
17717 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
17718 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
17719 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
17720 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
17721 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
17722 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
17723 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
17724 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
17725 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
17726 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
17727 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
17728 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
17729 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
17730 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
17731 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
17732 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
17733 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
17734 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
17735 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
17736 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
17737 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
17738 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
17739 
17740 
17741 // addressBlock: azf0inputendpoint1_inputendpointind
17742 // base address: 0x0
17743 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
17744 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
17745 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
17746 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
17747 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
17748 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
17749 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
17750 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
17751 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
17752 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
17753 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
17754 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
17755 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
17756 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
17757 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
17758 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
17759 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
17760 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
17761 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
17762 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
17763 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
17764 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
17765 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
17766 
17767 
17768 // addressBlock: azf0inputendpoint2_inputendpointind
17769 // base address: 0x0
17770 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
17771 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
17772 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
17773 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
17774 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
17775 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
17776 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
17777 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
17778 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
17779 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
17780 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
17781 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
17782 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
17783 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
17784 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
17785 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
17786 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
17787 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
17788 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
17789 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
17790 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
17791 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
17792 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
17793 
17794 
17795 // addressBlock: azf0inputendpoint3_inputendpointind
17796 // base address: 0x0
17797 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
17798 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
17799 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
17800 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
17801 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
17802 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
17803 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
17804 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
17805 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
17806 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
17807 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
17808 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
17809 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
17810 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
17811 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
17812 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
17813 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
17814 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
17815 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
17816 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
17817 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
17818 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
17819 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
17820 
17821 
17822 // addressBlock: azf0inputendpoint4_inputendpointind
17823 // base address: 0x0
17824 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
17825 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
17826 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
17827 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
17828 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
17829 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
17830 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
17831 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
17832 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
17833 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
17834 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
17835 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
17836 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
17837 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
17838 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
17839 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
17840 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
17841 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
17842 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
17843 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
17844 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
17845 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
17846 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
17847 
17848 
17849 // addressBlock: azf0inputendpoint5_inputendpointind
17850 // base address: 0x0
17851 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
17852 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
17853 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
17854 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
17855 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
17856 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
17857 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
17858 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
17859 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
17860 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
17861 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
17862 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
17863 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
17864 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
17865 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
17866 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
17867 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
17868 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
17869 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
17870 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
17871 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
17872 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
17873 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
17874 
17875 
17876 // addressBlock: azf0inputendpoint6_inputendpointind
17877 // base address: 0x0
17878 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
17879 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
17880 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
17881 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
17882 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
17883 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
17884 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
17885 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
17886 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
17887 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
17888 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
17889 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
17890 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
17891 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
17892 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
17893 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
17894 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
17895 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
17896 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
17897 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
17898 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
17899 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
17900 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
17901 
17902 
17903 // addressBlock: azf0inputendpoint7_inputendpointind
17904 // base address: 0x0
17905 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
17906 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
17907 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
17908 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
17909 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
17910 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
17911 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
17912 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
17913 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
17914 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
17915 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
17916 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
17917 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
17918 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
17919 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
17920 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
17921 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
17922 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
17923 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
17924 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
17925 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
17926 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
17927 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
17928 
17929 
17930 // addressBlock: f2codecind
17931 // base address: 0x0
17932 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
17933 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
17934 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
17935 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
17936 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
17937 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
17938 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
17939 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
17940 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
17941 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
17942 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
17943 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
17944 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
17945 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
17946 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
17947 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
17948 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
17949 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
17950 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
17951 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
17952 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
17953 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
17954 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
17955 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
17956 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
17957 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
17958 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
17959 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
17960 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
17961 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
17962 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
17963 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
17964 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
17965 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
17966 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
17967 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
17968 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
17969 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
17970 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
17971 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
17972 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
17973 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
17974 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
17975 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
17976 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
17977 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
17978 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
17979 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
17980 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
17981 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
17982 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
17983 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
17984 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
17985 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
17986 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
17987 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
17988 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
17989 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
17990 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
17991 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
17992 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
17993 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
17994 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
17995 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
17996 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
17997 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
17998 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
17999 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
18000 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
18001 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
18002 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
18003 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
18004 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
18005 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
18006 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
18007 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
18008 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
18009 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
18010 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
18011 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
18012 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
18013 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
18014 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
18015 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
18016 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
18017 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
18018 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
18019 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
18020 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
18021 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
18022 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
18023 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
18024 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
18025 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
18026 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
18027 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
18028 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
18029 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
18030 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
18031 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
18032 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
18033 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
18034 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
18035 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
18036 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
18037 
18038 
18039 // addressBlock: descriptorind
18040 // base address: 0x0
18041 #define ixAUDIO_DESCRIPTOR0                                                                            0x0001
18042 #define ixAUDIO_DESCRIPTOR1                                                                            0x0002
18043 #define ixAUDIO_DESCRIPTOR2                                                                            0x0003
18044 #define ixAUDIO_DESCRIPTOR3                                                                            0x0004
18045 #define ixAUDIO_DESCRIPTOR4                                                                            0x0005
18046 #define ixAUDIO_DESCRIPTOR5                                                                            0x0006
18047 #define ixAUDIO_DESCRIPTOR6                                                                            0x0007
18048 #define ixAUDIO_DESCRIPTOR7                                                                            0x0008
18049 #define ixAUDIO_DESCRIPTOR8                                                                            0x0009
18050 #define ixAUDIO_DESCRIPTOR9                                                                            0x000a
18051 #define ixAUDIO_DESCRIPTOR10                                                                           0x000b
18052 #define ixAUDIO_DESCRIPTOR11                                                                           0x000c
18053 #define ixAUDIO_DESCRIPTOR12                                                                           0x000d
18054 #define ixAUDIO_DESCRIPTOR13                                                                           0x000e
18055 
18056 
18057 // addressBlock: sinkinfoind
18058 // base address: 0x0
18059 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
18060 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
18061 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
18062 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
18063 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
18064 #define ixSINK_DESCRIPTION0                                                                            0x0005
18065 #define ixSINK_DESCRIPTION1                                                                            0x0006
18066 #define ixSINK_DESCRIPTION2                                                                            0x0007
18067 #define ixSINK_DESCRIPTION3                                                                            0x0008
18068 #define ixSINK_DESCRIPTION4                                                                            0x0009
18069 #define ixSINK_DESCRIPTION5                                                                            0x000a
18070 #define ixSINK_DESCRIPTION6                                                                            0x000b
18071 #define ixSINK_DESCRIPTION7                                                                            0x000c
18072 #define ixSINK_DESCRIPTION8                                                                            0x000d
18073 #define ixSINK_DESCRIPTION9                                                                            0x000e
18074 #define ixSINK_DESCRIPTION10                                                                           0x000f
18075 #define ixSINK_DESCRIPTION11                                                                           0x0010
18076 #define ixSINK_DESCRIPTION12                                                                           0x0011
18077 #define ixSINK_DESCRIPTION13                                                                           0x0012
18078 #define ixSINK_DESCRIPTION14                                                                           0x0013
18079 #define ixSINK_DESCRIPTION15                                                                           0x0014
18080 #define ixSINK_DESCRIPTION16                                                                           0x0015
18081 #define ixSINK_DESCRIPTION17                                                                           0x0016
18082 
18083 
18084 // addressBlock: azinputcrc0resultind
18085 // base address: 0x0
18086 #define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
18087 #define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
18088 #define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
18089 #define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
18090 #define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
18091 #define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
18092 #define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
18093 #define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
18094 
18095 
18096 // addressBlock: azinputcrc1resultind
18097 // base address: 0x0
18098 #define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
18099 #define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
18100 #define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
18101 #define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
18102 #define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
18103 #define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
18104 #define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
18105 #define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
18106 
18107 
18108 // addressBlock: azcrc0resultind
18109 // base address: 0x0
18110 #define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
18111 #define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
18112 #define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
18113 #define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
18114 #define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
18115 #define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
18116 #define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
18117 #define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
18118 
18119 
18120 // addressBlock: azcrc1resultind
18121 // base address: 0x0
18122 #define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
18123 #define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
18124 #define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
18125 #define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
18126 #define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
18127 #define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
18128 #define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
18129 #define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
18130 
18131 
18132 // addressBlock: vgaseqind
18133 // base address: 0x0
18134 #define ixSEQ00                                                                                        0x0000
18135 #define ixSEQ01                                                                                        0x0001
18136 #define ixSEQ02                                                                                        0x0002
18137 #define ixSEQ03                                                                                        0x0003
18138 #define ixSEQ04                                                                                        0x0004
18139 
18140 
18141 // addressBlock: vgacrtind
18142 // base address: 0x0
18143 #define ixCRT00                                                                                        0x0000
18144 #define ixCRT01                                                                                        0x0001
18145 #define ixCRT02                                                                                        0x0002
18146 #define ixCRT03                                                                                        0x0003
18147 #define ixCRT04                                                                                        0x0004
18148 #define ixCRT05                                                                                        0x0005
18149 #define ixCRT06                                                                                        0x0006
18150 #define ixCRT07                                                                                        0x0007
18151 #define ixCRT08                                                                                        0x0008
18152 #define ixCRT09                                                                                        0x0009
18153 #define ixCRT0A                                                                                        0x000a
18154 #define ixCRT0B                                                                                        0x000b
18155 #define ixCRT0C                                                                                        0x000c
18156 #define ixCRT0D                                                                                        0x000d
18157 #define ixCRT0E                                                                                        0x000e
18158 #define ixCRT0F                                                                                        0x000f
18159 #define ixCRT10                                                                                        0x0010
18160 #define ixCRT11                                                                                        0x0011
18161 #define ixCRT12                                                                                        0x0012
18162 #define ixCRT13                                                                                        0x0013
18163 #define ixCRT14                                                                                        0x0014
18164 #define ixCRT15                                                                                        0x0015
18165 #define ixCRT16                                                                                        0x0016
18166 #define ixCRT17                                                                                        0x0017
18167 #define ixCRT18                                                                                        0x0018
18168 #define ixCRT1E                                                                                        0x001e
18169 #define ixCRT1F                                                                                        0x001f
18170 #define ixCRT22                                                                                        0x0022
18171 
18172 
18173 // addressBlock: vgagrphind
18174 // base address: 0x0
18175 #define ixGRA00                                                                                        0x0000
18176 #define ixGRA01                                                                                        0x0001
18177 #define ixGRA02                                                                                        0x0002
18178 #define ixGRA03                                                                                        0x0003
18179 #define ixGRA04                                                                                        0x0004
18180 #define ixGRA05                                                                                        0x0005
18181 #define ixGRA06                                                                                        0x0006
18182 #define ixGRA07                                                                                        0x0007
18183 #define ixGRA08                                                                                        0x0008
18184 
18185 
18186 // addressBlock: vgaattrind
18187 // base address: 0x0
18188 #define ixATTR00                                                                                       0x0000
18189 #define ixATTR01                                                                                       0x0001
18190 #define ixATTR02                                                                                       0x0002
18191 #define ixATTR03                                                                                       0x0003
18192 #define ixATTR04                                                                                       0x0004
18193 #define ixATTR05                                                                                       0x0005
18194 #define ixATTR06                                                                                       0x0006
18195 #define ixATTR07                                                                                       0x0007
18196 #define ixATTR08                                                                                       0x0008
18197 #define ixATTR09                                                                                       0x0009
18198 #define ixATTR0A                                                                                       0x000a
18199 #define ixATTR0B                                                                                       0x000b
18200 #define ixATTR0C                                                                                       0x000c
18201 #define ixATTR0D                                                                                       0x000d
18202 #define ixATTR0E                                                                                       0x000e
18203 #define ixATTR0F                                                                                       0x000f
18204 #define ixATTR10                                                                                       0x0010
18205 #define ixATTR11                                                                                       0x0011
18206 #define ixATTR12                                                                                       0x0012
18207 #define ixATTR13                                                                                       0x0013
18208 #define ixATTR14                                                                                       0x0014
18209 
18210 
18211 #endif