root/drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h

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INCLUDED FROM

   1 /*
   2  * Volcanic Islands IV SRC Register documentation
   3  *
   4  * Copyright (C) 2015  Advanced Micro Devices, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 
  24 #ifndef _IVSRCID_VISLANDS30_H_
  25 #define _IVSRCID_VISLANDS30_H_
  26 
  27 
  28 // IV Source IDs
  29 
  30 #define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT                         7       // 0x07     
  31 #define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT                  0
  32 
  33 #define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP                           8       // 0x08     
  34 #define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP                    0
  35 
  36 #define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT                         9       // 0x09     
  37 #define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT                  0
  38 
  39 #define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP                           10      // 0x0a     
  40 #define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP                    0
  41 
  42 #define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT                         11      // 0x0b     
  43 #define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT                  0
  44 
  45 #define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP                           12      // 0x0c     
  46 #define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP                    0
  47 
  48 #define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT                         13      // 0x0d     
  49 #define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT                  0
  50 
  51 #define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP                           14      // 0x0e     
  52 #define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP                    0
  53 
  54 #define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT                         15      // 0x0f     
  55 #define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT                  0
  56 
  57 #define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP                           16      // 0x10     
  58 #define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP                    0
  59 
  60 #define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT                         17      // 0x11             
  61 #define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT                  0
  62 
  63 #define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP                           18      // 0x12     
  64 #define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP                    0
  65 
  66 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0           19      // 0x13
  67 #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT0           7
  68 
  69 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT1           19      // 0x13
  70 #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT1           8
  71 
  72 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT2           19      // 0x13
  73 #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT2           9
  74 
  75 #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC_LOSS          19      // 0x13
  76 #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC_LOSS          10
  77 
  78 #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC               19      // 0x13
  79 #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC               11
  80 
  81 #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SIGNAL             19      // 0x13
  82 #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SIGNAL             12
  83 
  84 #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0           20      // 0x14
  85 #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT0           7
  86 
  87 #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT1           20      // 0x14
  88 #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT1           8
  89 
  90 #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT2           20      // 0x14
  91 #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT2           9
  92 
  93 #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC_LOSS          20      // 0x14
  94 #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC_LOSS          10
  95 
  96 #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC               20      // 0x14
  97 #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC               11
  98 
  99 #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SIGNAL             20      // 0x14
 100 #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SIGNAL             12
 101 
 102 #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0           21      // 0x15
 103 #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT0           7
 104 
 105 #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT1           21      // 0x15
 106 #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT1           8
 107 
 108 #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT2           21      // 0x15
 109 #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT2           9
 110 
 111 #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC_LOSS          21      // 0x15
 112 #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC_LOSS          10
 113 
 114 #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC               21      // 0x15
 115 #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC               11
 116 
 117 #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SIGNAL             21      // 0x15
 118 #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SIGNAL             12
 119 
 120 #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0           22      // 0x16
 121 #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT0           7
 122 
 123 #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT1           22      // 0x16
 124 #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT1           8
 125 
 126 #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT2           22      // 0x16
 127 #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT2           9
 128 
 129 #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC_LOSS          22      // 0x16
 130 #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC_LOSS          10
 131 
 132 #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC               22      // 0x16
 133 #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC               11
 134 
 135 #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SIGNAL             22      // 0x16
 136 #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SIGNAL             12
 137 
 138 #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0           23      // 0x17
 139 #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT0           7
 140 
 141 #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT1           23      // 0x17
 142 #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT1           8
 143 
 144 #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT2           23      // 0x17
 145 #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT2           9
 146 
 147 #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC_LOSS          23      // 0x17
 148 #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC_LOSS          10
 149 
 150 #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC               23      // 0x17
 151 #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC               11
 152 
 153 #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SIGNAL             23      // 0x17
 154 #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SIGNAL             12
 155 
 156 #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0           24      // 0x18
 157 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT0           7
 158 
 159 #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT1           24      // 0x18
 160 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT1           8
 161 
 162 #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2           24      // 0x18
 163 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2           9
 164 
 165 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A                        42      // 0x2a     
 166 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A                 0
 167 
 168 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B                    42          // 0x2a             
 169 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B                 1
 170 
 171 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C                    42          // 0x2a             
 172 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C                 2
 173 
 174 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D                    42          // 0x2a             
 175 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D                 3
 176 
 177 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E                        42      // 0x2a             
 178 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E                 4
 179 
 180 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F                        42      // 0x2a             
 181 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F                 5
 182 
 183 #define VISLANDS30_IV_SRCID_HPD_RX_A                                42      // 0x2a             
 184 #define VISLANDS30_IV_EXTID_HPD_RX_A                         6
 185 
 186 #define VISLANDS30_IV_SRCID_HPD_RX_B                                42      // 0x2a             
 187 #define VISLANDS30_IV_EXTID_HPD_RX_B                         7
 188 
 189 #define VISLANDS30_IV_SRCID_HPD_RX_C                                42      // 0x2a             
 190 #define VISLANDS30_IV_EXTID_HPD_RX_C                         8
 191 
 192 #define VISLANDS30_IV_SRCID_HPD_RX_D                                42      // 0x2a             
 193 #define VISLANDS30_IV_EXTID_HPD_RX_D                         9
 194 
 195 #define VISLANDS30_IV_SRCID_HPD_RX_E                                42      // 0x2a             
 196 #define VISLANDS30_IV_EXTID_HPD_RX_E                         10
 197 
 198 #define VISLANDS30_IV_SRCID_HPD_RX_F                                42      // 0x2a             
 199 #define VISLANDS30_IV_EXTID_HPD_RX_F                         11
 200 
 201 #define VISLANDS30_IV_SRCID_GPIO_19                            0x00000053  /* 83 */
 202 
 203 #define VISLANDS30_IV_SRCID_SRBM_READ_TIMEOUT_ERR              0x00000060  /* 96 */
 204 #define VISLANDS30_IV_SRCID_SRBM_CTX_SWITCH                    0x00000061  /* 97 */
 205 
 206 #define VISLANDS30_IV_SRBM_REG_ACCESS_ERROR                    0x00000062  /* 98 */
 207 
 208 
 209 #define VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP                   0x00000077  /* 119 */
 210 #define VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE                 0x0000007c  /* 124 */
 211 
 212 #define VISLANDS30_IV_SRCID_BIF_PF_VF_MSGBUF_VALID             0x00000087  /* 135 */
 213 
 214 #define VISLANDS30_IV_SRCID_BIF_VF_PF_MSGBUF_ACK               0x0000008a  /* 138 */
 215 
 216 #define VISLANDS30_IV_SRCID_SYS_PAGE_INV_FAULT                 0x0000008c  /* 140 */
 217 #define VISLANDS30_IV_SRCID_SYS_MEM_PROT_FAULT                 0x0000008d  /* 141 */
 218 
 219 #define VISLANDS30_IV_SRCID_SEM_PAGE_INV_FAULT                 0x00000090  /* 144 */
 220 #define VISLANDS30_IV_SRCID_SEM_MEM_PROT_FAULT                 0x00000091  /* 145 */
 221 
 222 #define VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT                 0x00000092  /* 146 */
 223 #define VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT                 0x00000093  /* 147 */
 224 
 225 #define VISLANDS30_IV_SRCID_ACP                                0x000000a2  /* 162 */
 226 
 227 #define VISLANDS30_IV_SRCID_VCE_TRAP                           0x000000a7  /* 167 */
 228 #define VISLANDS30_IV_EXTID_VCE_TRAP_GENERAL_PURPOSE           0
 229 #define VISLANDS30_IV_EXTID_VCE_TRAP_LOW_LATENCY               1
 230 #define VISLANDS30_IV_EXTID_VCE_TRAP_REAL_TIME                 2
 231 
 232 #define VISLANDS30_IV_SRCID_CP_INT_RB                          0x000000b0  /* 176 */
 233 #define VISLANDS30_IV_SRCID_CP_INT_IB1                         0x000000b1  /* 177 */
 234 #define VISLANDS30_IV_SRCID_CP_INT_IB2                         0x000000b2  /* 178 */
 235 #define VISLANDS30_IV_SRCID_CP_PM4_RES_BITS_ERR                0x000000b4  /* 180 */
 236 #define VISLANDS30_IV_SRCID_CP_END_OF_PIPE                     0x000000b5  /* 181 */
 237 #define VISLANDS30_IV_SRCID_CP_BAD_OPCODE                      0x000000b7  /* 183 */
 238 #define VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT                  0x000000b8  /* 184 */
 239 #define VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT                0x000000b9  /* 185 */
 240 #define VISLANDS30_IV_SRCID_CP_WAIT_MEM_SEM_FAULT              0x000000ba  /* 186 */
 241 #define VISLANDS30_IV_SRCID_CP_GUI_IDLE                        0x000000bb  /* 187 */
 242 #define VISLANDS30_IV_SRCID_CP_GUI_BUSY                        0x000000bc  /* 188 */
 243 
 244 #define VISLANDS30_IV_SRCID_CP_COMPUTE_QUERY_STATUS            0x000000bf  /* 191 */
 245 #define VISLANDS30_IV_SRCID_CP_ECC_ERROR                       0x000000c5  /* 197 */
 246 
 247 #define CARRIZO_IV_SRCID_CP_COMPUTE_QUERY_STATUS               0x000000c7  /* 199 */
 248 
 249 #define VISLANDS30_IV_SRCID_CP_WAIT_REG_MEM_POLL_TIMEOUT       0x000000c0  /* 192 */
 250 #define VISLANDS30_IV_SRCID_CP_SEM_SIG_INCOMPL                 0x000000c1  /* 193 */
 251 #define VISLANDS30_IV_SRCID_CP_PREEMPT_ACK                     0x000000c2  /* 194 */
 252 #define VISLANDS30_IV_SRCID_CP_GENERAL_PROT_FAULT              0x000000c3  /* 195 */
 253 #define VISLANDS30_IV_SRCID_CP_GDS_ALLOC_ERROR                 0x000000c4  /* 196 */
 254 #define VISLANDS30_IV_SRCID_CP_ECC_ERROR                       0x000000c5  /* 197 */
 255 
 256 #define VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR              0x000000ca  /* 202 */
 257 
 258 #define VISLANDS30_IV_SDMA_ATOMIC_SRC_ID                       0x000000da  /* 218 */
 259 
 260 #define VISLANDS30_IV_SRCID_SDMA_ECC_ERROR                     0x000000dc  /* 220 */
 261 
 262 #define VISLANDS30_IV_SRCID_SDMA_TRAP                          0x000000e0  /* 224 */
 263 #define VISLANDS30_IV_SRCID_SDMA_SEM_INCOMPLETE                0x000000e1  /* 225 */
 264 #define VISLANDS30_IV_SRCID_SDMA_SEM_WAIT                      0x000000e2  /* 226 */
 265 
 266 
 267 #define VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER            0x000000e5  /* 229 */
 268 
 269 #define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH         0x000000e6  /* 230 */
 270 #define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW         0x000000e7  /* 231 */
 271 
 272 #define VISLANDS30_IV_SRCID_GRBM_READ_TIMEOUT_ERR              0x000000e8  /* 232 */
 273 #define VISLANDS30_IV_SRCID_GRBM_REG_GUI_IDLE                  0x000000e9  /* 233 */
 274 
 275 #define VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG                   0x000000ef  /* 239 */
 276 
 277 #define VISLANDS30_IV_SRCID_SDMA_PREEMPT                       0x000000f0  /* 240 */
 278 #define VISLANDS30_IV_SRCID_SDMA_VM_HOLE                       0x000000f2  /* 242 */
 279 #define VISLANDS30_IV_SRCID_SDMA_CTXEMPTY                      0x000000f3  /* 243 */
 280 #define VISLANDS30_IV_SRCID_SDMA_DOORBELL_INVALID              0x000000f4  /* 244 */
 281 #define VISLANDS30_IV_SRCID_SDMA_FROZEN                        0x000000f5  /* 245 */
 282 #define VISLANDS30_IV_SRCID_SDMA_POLL_TIMEOUT                  0x000000f6  /* 246 */
 283 #define VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE                    0x000000f7  /* 247 */
 284 
 285 #define VISLANDS30_IV_SRCID_CG_THERMAL_TRIG                    0x000000f8  /* 248 */
 286 
 287 #define VISLANDS30_IV_SRCID_SMU_DISP_TIMER_TRIGGER             0x000000fd  /* 253 */
 288 
 289 /* These are not "real" source ids defined by HW */
 290 #define VISLANDS30_IV_SRCID_VM_CONTEXT_ALL                     0x00000100  /* 256 */
 291 #define VISLANDS30_IV_EXTID_VM_CONTEXT0_ALL                    0
 292 #define VISLANDS30_IV_EXTID_VM_CONTEXT1_ALL                    1
 293 
 294 
 295 /* IV Extended IDs */
 296 #define VISLANDS30_IV_EXTID_NONE                               0x00000000
 297 #define VISLANDS30_IV_EXTID_INVALID                            0xffffffff
 298 
 299 #endif // _IVSRCID_VISLANDS30_H_
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