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21 #ifndef _navi12_ip_offset_HEADER
22 #define _navi12_ip_offset_HEADER
23
24 #define MAX_INSTANCE 7
25 #define MAX_SEGMENT 5
26
27
28 struct IP_BASE_INSTANCE
29 {
30 unsigned int segment[MAX_SEGMENT];
31 };
32
33 struct IP_BASE
34 {
35 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
36 };
37
38
39 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } } } };
46 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
47 { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
48 { { 0x00017000, 0x02402000, 0, 0, 0 } },
49 { { 0x00017200, 0x02402400, 0, 0, 0 } },
50 { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
51 { { 0x00017E00, 0x0240BC00, 0, 0, 0 } },
52 { { 0, 0, 0, 0, 0 } } } };
53 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
54 { { 0, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0 } },
58 { { 0, 0, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0 } } } };
60 static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
61 { { 0, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0 } },
63 { { 0, 0, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0 } },
65 { { 0, 0, 0, 0, 0 } },
66 { { 0, 0, 0, 0, 0 } } } };
67 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
68 { { 0, 0, 0, 0, 0 } },
69 { { 0, 0, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0 } },
71 { { 0, 0, 0, 0, 0 } },
72 { { 0, 0, 0, 0, 0 } },
73 { { 0, 0, 0, 0, 0 } } } };
74 static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
75 { { 0, 0, 0, 0, 0 } },
76 { { 0, 0, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0 } },
78 { { 0, 0, 0, 0, 0 } },
79 { { 0, 0, 0, 0, 0 } },
80 { { 0, 0, 0, 0, 0 } } } };
81 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
82 { { 0, 0, 0, 0, 0 } },
83 { { 0, 0, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0 } },
86 { { 0, 0, 0, 0, 0 } },
87 { { 0, 0, 0, 0, 0 } } } };
88 static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
89 { { 0, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0 } },
91 { { 0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0 } },
93 { { 0, 0, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0 } } } };
95 static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
96 { { 0, 0, 0, 0, 0 } },
97 { { 0, 0, 0, 0, 0 } },
98 { { 0, 0, 0, 0, 0 } },
99 { { 0, 0, 0, 0, 0 } },
100 { { 0, 0, 0, 0, 0 } },
101 { { 0, 0, 0, 0, 0 } } } };
102 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
103 { { 0, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0 } },
105 { { 0, 0, 0, 0, 0 } },
106 { { 0, 0, 0, 0, 0 } },
107 { { 0, 0, 0, 0, 0 } },
108 { { 0, 0, 0, 0, 0 } } } };
109 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
110 { { 0, 0, 0, 0, 0 } },
111 { { 0, 0, 0, 0, 0 } },
112 { { 0, 0, 0, 0, 0 } },
113 { { 0, 0, 0, 0, 0 } },
114 { { 0, 0, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0 } } } };
116 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
117 { { 0, 0, 0, 0, 0 } },
118 { { 0, 0, 0, 0, 0 } },
119 { { 0, 0, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0 } },
121 { { 0, 0, 0, 0, 0 } },
122 { { 0, 0, 0, 0, 0 } } } };
123 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } },
124 { { 0, 0, 0, 0, 0 } },
125 { { 0, 0, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0 } },
128 { { 0, 0, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0 } } } };
130 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
131 { { 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0 } },
135 { { 0, 0, 0, 0, 0 } },
136 { { 0, 0, 0, 0, 0 } } } };
137 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
138 { { 0, 0, 0, 0, 0 } },
139 { { 0, 0, 0, 0, 0 } },
140 { { 0, 0, 0, 0, 0 } },
141 { { 0, 0, 0, 0, 0 } },
142 { { 0, 0, 0, 0, 0 } },
143 { { 0, 0, 0, 0, 0 } } } };
144 static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
145 { { 0, 0, 0, 0, 0 } },
146 { { 0, 0, 0, 0, 0 } },
147 { { 0, 0, 0, 0, 0 } },
148 { { 0, 0, 0, 0, 0 } },
149 { { 0, 0, 0, 0, 0 } },
150 { { 0, 0, 0, 0, 0 } } } };
151 static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
152 { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
153 { { 0, 0, 0, 0, 0 } },
154 { { 0, 0, 0, 0, 0 } },
155 { { 0, 0, 0, 0, 0 } },
156 { { 0, 0, 0, 0, 0 } },
157 { { 0, 0, 0, 0, 0 } } } };
158 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
159 { { 0, 0, 0, 0, 0 } },
160 { { 0, 0, 0, 0, 0 } },
161 { { 0, 0, 0, 0, 0 } },
162 { { 0, 0, 0, 0, 0 } },
163 { { 0, 0, 0, 0, 0 } },
164 { { 0, 0, 0, 0, 0 } } } };
165 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
166 { { 0, 0, 0, 0, 0 } },
167 { { 0, 0, 0, 0, 0 } },
168 { { 0, 0, 0, 0, 0 } },
169 { { 0, 0, 0, 0, 0 } },
170 { { 0, 0, 0, 0, 0 } },
171 { { 0, 0, 0, 0, 0 } } } };
172 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
173 { { 0x00054000, 0x02425C00, 0, 0, 0 } },
174 { { 0x00094000, 0x02426000, 0, 0, 0 } },
175 { { 0x000D4000, 0x02426400, 0, 0, 0 } },
176 { { 0, 0, 0, 0, 0 } },
177 { { 0, 0, 0, 0, 0 } },
178 { { 0, 0, 0, 0, 0 } } } };
179 static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
180 { { 0, 0, 0, 0, 0 } },
181 { { 0, 0, 0, 0, 0 } },
182 { { 0, 0, 0, 0, 0 } },
183 { { 0, 0, 0, 0, 0 } },
184 { { 0, 0, 0, 0, 0 } },
185 { { 0, 0, 0, 0, 0 } } } };
186 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
187 { { 0, 0, 0, 0, 0 } },
188 { { 0, 0, 0, 0, 0 } },
189 { { 0, 0, 0, 0, 0 } },
190 { { 0, 0, 0, 0, 0 } },
191 { { 0, 0, 0, 0, 0 } },
192 { { 0, 0, 0, 0, 0 } } } };
193
194
195 #define ATHUB_BASE__INST0_SEG0 0x00000C00
196 #define ATHUB_BASE__INST0_SEG1 0x02408C00
197 #define ATHUB_BASE__INST0_SEG2 0
198 #define ATHUB_BASE__INST0_SEG3 0
199 #define ATHUB_BASE__INST0_SEG4 0
200
201 #define ATHUB_BASE__INST1_SEG0 0
202 #define ATHUB_BASE__INST1_SEG1 0
203 #define ATHUB_BASE__INST1_SEG2 0
204 #define ATHUB_BASE__INST1_SEG3 0
205 #define ATHUB_BASE__INST1_SEG4 0
206
207 #define ATHUB_BASE__INST2_SEG0 0
208 #define ATHUB_BASE__INST2_SEG1 0
209 #define ATHUB_BASE__INST2_SEG2 0
210 #define ATHUB_BASE__INST2_SEG3 0
211 #define ATHUB_BASE__INST2_SEG4 0
212
213 #define ATHUB_BASE__INST3_SEG0 0
214 #define ATHUB_BASE__INST3_SEG1 0
215 #define ATHUB_BASE__INST3_SEG2 0
216 #define ATHUB_BASE__INST3_SEG3 0
217 #define ATHUB_BASE__INST3_SEG4 0
218
219 #define ATHUB_BASE__INST4_SEG0 0
220 #define ATHUB_BASE__INST4_SEG1 0
221 #define ATHUB_BASE__INST4_SEG2 0
222 #define ATHUB_BASE__INST4_SEG3 0
223 #define ATHUB_BASE__INST4_SEG4 0
224
225 #define ATHUB_BASE__INST5_SEG0 0
226 #define ATHUB_BASE__INST5_SEG1 0
227 #define ATHUB_BASE__INST5_SEG2 0
228 #define ATHUB_BASE__INST5_SEG3 0
229 #define ATHUB_BASE__INST5_SEG4 0
230
231 #define ATHUB_BASE__INST6_SEG0 0
232 #define ATHUB_BASE__INST6_SEG1 0
233 #define ATHUB_BASE__INST6_SEG2 0
234 #define ATHUB_BASE__INST6_SEG3 0
235 #define ATHUB_BASE__INST6_SEG4 0
236
237 #define CLK_BASE__INST0_SEG0 0x00016C00
238 #define CLK_BASE__INST0_SEG1 0x02401800
239 #define CLK_BASE__INST0_SEG2 0
240 #define CLK_BASE__INST0_SEG3 0
241 #define CLK_BASE__INST0_SEG4 0
242
243 #define CLK_BASE__INST1_SEG0 0x00016E00
244 #define CLK_BASE__INST1_SEG1 0x02401C00
245 #define CLK_BASE__INST1_SEG2 0
246 #define CLK_BASE__INST1_SEG3 0
247 #define CLK_BASE__INST1_SEG4 0
248
249 #define CLK_BASE__INST2_SEG0 0x00017000
250 #define CLK_BASE__INST2_SEG1 0x02402000
251 #define CLK_BASE__INST2_SEG2 0
252 #define CLK_BASE__INST2_SEG3 0
253 #define CLK_BASE__INST2_SEG4 0
254
255 #define CLK_BASE__INST3_SEG0 0x00017200
256 #define CLK_BASE__INST3_SEG1 0x02402400
257 #define CLK_BASE__INST3_SEG2 0
258 #define CLK_BASE__INST3_SEG3 0
259 #define CLK_BASE__INST3_SEG4 0
260
261 #define CLK_BASE__INST4_SEG0 0x0001B000
262 #define CLK_BASE__INST4_SEG1 0x0242D800
263 #define CLK_BASE__INST4_SEG2 0
264 #define CLK_BASE__INST4_SEG3 0
265 #define CLK_BASE__INST4_SEG4 0
266
267 #define CLK_BASE__INST5_SEG0 0x00017E00
268 #define CLK_BASE__INST5_SEG1 0x0240BC00
269 #define CLK_BASE__INST5_SEG2 0
270 #define CLK_BASE__INST5_SEG3 0
271 #define CLK_BASE__INST5_SEG4 0
272
273 #define CLK_BASE__INST6_SEG0 0
274 #define CLK_BASE__INST6_SEG1 0
275 #define CLK_BASE__INST6_SEG2 0
276 #define CLK_BASE__INST6_SEG3 0
277 #define CLK_BASE__INST6_SEG4 0
278
279 #define DF_BASE__INST0_SEG0 0x00007000
280 #define DF_BASE__INST0_SEG1 0x0240B800
281 #define DF_BASE__INST0_SEG2 0
282 #define DF_BASE__INST0_SEG3 0
283 #define DF_BASE__INST0_SEG4 0
284
285 #define DF_BASE__INST1_SEG0 0
286 #define DF_BASE__INST1_SEG1 0
287 #define DF_BASE__INST1_SEG2 0
288 #define DF_BASE__INST1_SEG3 0
289 #define DF_BASE__INST1_SEG4 0
290
291 #define DF_BASE__INST2_SEG0 0
292 #define DF_BASE__INST2_SEG1 0
293 #define DF_BASE__INST2_SEG2 0
294 #define DF_BASE__INST2_SEG3 0
295 #define DF_BASE__INST2_SEG4 0
296
297 #define DF_BASE__INST3_SEG0 0
298 #define DF_BASE__INST3_SEG1 0
299 #define DF_BASE__INST3_SEG2 0
300 #define DF_BASE__INST3_SEG3 0
301 #define DF_BASE__INST3_SEG4 0
302
303 #define DF_BASE__INST4_SEG0 0
304 #define DF_BASE__INST4_SEG1 0
305 #define DF_BASE__INST4_SEG2 0
306 #define DF_BASE__INST4_SEG3 0
307 #define DF_BASE__INST4_SEG4 0
308
309 #define DF_BASE__INST5_SEG0 0
310 #define DF_BASE__INST5_SEG1 0
311 #define DF_BASE__INST5_SEG2 0
312 #define DF_BASE__INST5_SEG3 0
313 #define DF_BASE__INST5_SEG4 0
314
315 #define DF_BASE__INST6_SEG0 0
316 #define DF_BASE__INST6_SEG1 0
317 #define DF_BASE__INST6_SEG2 0
318 #define DF_BASE__INST6_SEG3 0
319 #define DF_BASE__INST6_SEG4 0
320
321 #define DIO_BASE__INST0_SEG0 0x02404000
322 #define DIO_BASE__INST0_SEG1 0
323 #define DIO_BASE__INST0_SEG2 0
324 #define DIO_BASE__INST0_SEG3 0
325 #define DIO_BASE__INST0_SEG4 0
326
327 #define DIO_BASE__INST1_SEG0 0
328 #define DIO_BASE__INST1_SEG1 0
329 #define DIO_BASE__INST1_SEG2 0
330 #define DIO_BASE__INST1_SEG3 0
331 #define DIO_BASE__INST1_SEG4 0
332
333 #define DIO_BASE__INST2_SEG0 0
334 #define DIO_BASE__INST2_SEG1 0
335 #define DIO_BASE__INST2_SEG2 0
336 #define DIO_BASE__INST2_SEG3 0
337 #define DIO_BASE__INST2_SEG4 0
338
339 #define DIO_BASE__INST3_SEG0 0
340 #define DIO_BASE__INST3_SEG1 0
341 #define DIO_BASE__INST3_SEG2 0
342 #define DIO_BASE__INST3_SEG3 0
343 #define DIO_BASE__INST3_SEG4 0
344
345 #define DIO_BASE__INST4_SEG0 0
346 #define DIO_BASE__INST4_SEG1 0
347 #define DIO_BASE__INST4_SEG2 0
348 #define DIO_BASE__INST4_SEG3 0
349 #define DIO_BASE__INST4_SEG4 0
350
351 #define DIO_BASE__INST5_SEG0 0
352 #define DIO_BASE__INST5_SEG1 0
353 #define DIO_BASE__INST5_SEG2 0
354 #define DIO_BASE__INST5_SEG3 0
355 #define DIO_BASE__INST5_SEG4 0
356
357 #define DIO_BASE__INST6_SEG0 0
358 #define DIO_BASE__INST6_SEG1 0
359 #define DIO_BASE__INST6_SEG2 0
360 #define DIO_BASE__INST6_SEG3 0
361 #define DIO_BASE__INST6_SEG4 0
362
363 #define DMU_BASE__INST0_SEG0 0x00000012
364 #define DMU_BASE__INST0_SEG1 0x000000C0
365 #define DMU_BASE__INST0_SEG2 0x000034C0
366 #define DMU_BASE__INST0_SEG3 0x00009000
367 #define DMU_BASE__INST0_SEG4 0x02403C00
368
369 #define DMU_BASE__INST1_SEG0 0
370 #define DMU_BASE__INST1_SEG1 0
371 #define DMU_BASE__INST1_SEG2 0
372 #define DMU_BASE__INST1_SEG3 0
373 #define DMU_BASE__INST1_SEG4 0
374
375 #define DMU_BASE__INST2_SEG0 0
376 #define DMU_BASE__INST2_SEG1 0
377 #define DMU_BASE__INST2_SEG2 0
378 #define DMU_BASE__INST2_SEG3 0
379 #define DMU_BASE__INST2_SEG4 0
380
381 #define DMU_BASE__INST3_SEG0 0
382 #define DMU_BASE__INST3_SEG1 0
383 #define DMU_BASE__INST3_SEG2 0
384 #define DMU_BASE__INST3_SEG3 0
385 #define DMU_BASE__INST3_SEG4 0
386
387 #define DMU_BASE__INST4_SEG0 0
388 #define DMU_BASE__INST4_SEG1 0
389 #define DMU_BASE__INST4_SEG2 0
390 #define DMU_BASE__INST4_SEG3 0
391 #define DMU_BASE__INST4_SEG4 0
392
393 #define DMU_BASE__INST5_SEG0 0
394 #define DMU_BASE__INST5_SEG1 0
395 #define DMU_BASE__INST5_SEG2 0
396 #define DMU_BASE__INST5_SEG3 0
397 #define DMU_BASE__INST5_SEG4 0
398
399 #define DMU_BASE__INST6_SEG0 0
400 #define DMU_BASE__INST6_SEG1 0
401 #define DMU_BASE__INST6_SEG2 0
402 #define DMU_BASE__INST6_SEG3 0
403 #define DMU_BASE__INST6_SEG4 0
404
405 #define DPCS_BASE__INST0_SEG0 0x00000012
406 #define DPCS_BASE__INST0_SEG1 0x000000C0
407 #define DPCS_BASE__INST0_SEG2 0x000034C0
408 #define DPCS_BASE__INST0_SEG3 0x00009000
409 #define DPCS_BASE__INST0_SEG4 0x02403C00
410
411 #define DPCS_BASE__INST1_SEG0 0
412 #define DPCS_BASE__INST1_SEG1 0
413 #define DPCS_BASE__INST1_SEG2 0
414 #define DPCS_BASE__INST1_SEG3 0
415 #define DPCS_BASE__INST1_SEG4 0
416
417 #define DPCS_BASE__INST2_SEG0 0
418 #define DPCS_BASE__INST2_SEG1 0
419 #define DPCS_BASE__INST2_SEG2 0
420 #define DPCS_BASE__INST2_SEG3 0
421 #define DPCS_BASE__INST2_SEG4 0
422
423 #define DPCS_BASE__INST3_SEG0 0
424 #define DPCS_BASE__INST3_SEG1 0
425 #define DPCS_BASE__INST3_SEG2 0
426 #define DPCS_BASE__INST3_SEG3 0
427 #define DPCS_BASE__INST3_SEG4 0
428
429 #define DPCS_BASE__INST4_SEG0 0
430 #define DPCS_BASE__INST4_SEG1 0
431 #define DPCS_BASE__INST4_SEG2 0
432 #define DPCS_BASE__INST4_SEG3 0
433 #define DPCS_BASE__INST4_SEG4 0
434
435 #define DPCS_BASE__INST5_SEG0 0
436 #define DPCS_BASE__INST5_SEG1 0
437 #define DPCS_BASE__INST5_SEG2 0
438 #define DPCS_BASE__INST5_SEG3 0
439 #define DPCS_BASE__INST5_SEG4 0
440
441 #define DPCS_BASE__INST6_SEG0 0
442 #define DPCS_BASE__INST6_SEG1 0
443 #define DPCS_BASE__INST6_SEG2 0
444 #define DPCS_BASE__INST6_SEG3 0
445 #define DPCS_BASE__INST6_SEG4 0
446
447 #define FUSE_BASE__INST0_SEG0 0x00017400
448 #define FUSE_BASE__INST0_SEG1 0x02401400
449 #define FUSE_BASE__INST0_SEG2 0
450 #define FUSE_BASE__INST0_SEG3 0
451 #define FUSE_BASE__INST0_SEG4 0
452
453 #define FUSE_BASE__INST1_SEG0 0
454 #define FUSE_BASE__INST1_SEG1 0
455 #define FUSE_BASE__INST1_SEG2 0
456 #define FUSE_BASE__INST1_SEG3 0
457 #define FUSE_BASE__INST1_SEG4 0
458
459 #define FUSE_BASE__INST2_SEG0 0
460 #define FUSE_BASE__INST2_SEG1 0
461 #define FUSE_BASE__INST2_SEG2 0
462 #define FUSE_BASE__INST2_SEG3 0
463 #define FUSE_BASE__INST2_SEG4 0
464
465 #define FUSE_BASE__INST3_SEG0 0
466 #define FUSE_BASE__INST3_SEG1 0
467 #define FUSE_BASE__INST3_SEG2 0
468 #define FUSE_BASE__INST3_SEG3 0
469 #define FUSE_BASE__INST3_SEG4 0
470
471 #define FUSE_BASE__INST4_SEG0 0
472 #define FUSE_BASE__INST4_SEG1 0
473 #define FUSE_BASE__INST4_SEG2 0
474 #define FUSE_BASE__INST4_SEG3 0
475 #define FUSE_BASE__INST4_SEG4 0
476
477 #define FUSE_BASE__INST5_SEG0 0
478 #define FUSE_BASE__INST5_SEG1 0
479 #define FUSE_BASE__INST5_SEG2 0
480 #define FUSE_BASE__INST5_SEG3 0
481 #define FUSE_BASE__INST5_SEG4 0
482
483 #define FUSE_BASE__INST6_SEG0 0
484 #define FUSE_BASE__INST6_SEG1 0
485 #define FUSE_BASE__INST6_SEG2 0
486 #define FUSE_BASE__INST6_SEG3 0
487 #define FUSE_BASE__INST6_SEG4 0
488
489 #define GC_BASE__INST0_SEG0 0x00001260
490 #define GC_BASE__INST0_SEG1 0x0000A000
491 #define GC_BASE__INST0_SEG2 0x02402C00
492 #define GC_BASE__INST0_SEG3 0
493 #define GC_BASE__INST0_SEG4 0
494
495 #define GC_BASE__INST1_SEG0 0
496 #define GC_BASE__INST1_SEG1 0
497 #define GC_BASE__INST1_SEG2 0
498 #define GC_BASE__INST1_SEG3 0
499 #define GC_BASE__INST1_SEG4 0
500
501 #define GC_BASE__INST2_SEG0 0
502 #define GC_BASE__INST2_SEG1 0
503 #define GC_BASE__INST2_SEG2 0
504 #define GC_BASE__INST2_SEG3 0
505 #define GC_BASE__INST2_SEG4 0
506
507 #define GC_BASE__INST3_SEG0 0
508 #define GC_BASE__INST3_SEG1 0
509 #define GC_BASE__INST3_SEG2 0
510 #define GC_BASE__INST3_SEG3 0
511 #define GC_BASE__INST3_SEG4 0
512
513 #define GC_BASE__INST4_SEG0 0
514 #define GC_BASE__INST4_SEG1 0
515 #define GC_BASE__INST4_SEG2 0
516 #define GC_BASE__INST4_SEG3 0
517 #define GC_BASE__INST4_SEG4 0
518
519 #define GC_BASE__INST5_SEG0 0
520 #define GC_BASE__INST5_SEG1 0
521 #define GC_BASE__INST5_SEG2 0
522 #define GC_BASE__INST5_SEG3 0
523 #define GC_BASE__INST5_SEG4 0
524
525 #define GC_BASE__INST6_SEG0 0
526 #define GC_BASE__INST6_SEG1 0
527 #define GC_BASE__INST6_SEG2 0
528 #define GC_BASE__INST6_SEG3 0
529 #define GC_BASE__INST6_SEG4 0
530
531 #define HDA_BASE__INST0_SEG0 0x004C0000
532 #define HDA_BASE__INST0_SEG1 0x02404800
533 #define HDA_BASE__INST0_SEG2 0
534 #define HDA_BASE__INST0_SEG3 0
535 #define HDA_BASE__INST0_SEG4 0
536
537 #define HDA_BASE__INST1_SEG0 0
538 #define HDA_BASE__INST1_SEG1 0
539 #define HDA_BASE__INST1_SEG2 0
540 #define HDA_BASE__INST1_SEG3 0
541 #define HDA_BASE__INST1_SEG4 0
542
543 #define HDA_BASE__INST2_SEG0 0
544 #define HDA_BASE__INST2_SEG1 0
545 #define HDA_BASE__INST2_SEG2 0
546 #define HDA_BASE__INST2_SEG3 0
547 #define HDA_BASE__INST2_SEG4 0
548
549 #define HDA_BASE__INST3_SEG0 0
550 #define HDA_BASE__INST3_SEG1 0
551 #define HDA_BASE__INST3_SEG2 0
552 #define HDA_BASE__INST3_SEG3 0
553 #define HDA_BASE__INST3_SEG4 0
554
555 #define HDA_BASE__INST4_SEG0 0
556 #define HDA_BASE__INST4_SEG1 0
557 #define HDA_BASE__INST4_SEG2 0
558 #define HDA_BASE__INST4_SEG3 0
559 #define HDA_BASE__INST4_SEG4 0
560
561 #define HDA_BASE__INST5_SEG0 0
562 #define HDA_BASE__INST5_SEG1 0
563 #define HDA_BASE__INST5_SEG2 0
564 #define HDA_BASE__INST5_SEG3 0
565 #define HDA_BASE__INST5_SEG4 0
566
567 #define HDA_BASE__INST6_SEG0 0
568 #define HDA_BASE__INST6_SEG1 0
569 #define HDA_BASE__INST6_SEG2 0
570 #define HDA_BASE__INST6_SEG3 0
571 #define HDA_BASE__INST6_SEG4 0
572
573 #define HDP_BASE__INST0_SEG0 0x00000F20
574 #define HDP_BASE__INST0_SEG1 0x0240A400
575 #define HDP_BASE__INST0_SEG2 0
576 #define HDP_BASE__INST0_SEG3 0
577 #define HDP_BASE__INST0_SEG4 0
578
579 #define HDP_BASE__INST1_SEG0 0
580 #define HDP_BASE__INST1_SEG1 0
581 #define HDP_BASE__INST1_SEG2 0
582 #define HDP_BASE__INST1_SEG3 0
583 #define HDP_BASE__INST1_SEG4 0
584
585 #define HDP_BASE__INST2_SEG0 0
586 #define HDP_BASE__INST2_SEG1 0
587 #define HDP_BASE__INST2_SEG2 0
588 #define HDP_BASE__INST2_SEG3 0
589 #define HDP_BASE__INST2_SEG4 0
590
591 #define HDP_BASE__INST3_SEG0 0
592 #define HDP_BASE__INST3_SEG1 0
593 #define HDP_BASE__INST3_SEG2 0
594 #define HDP_BASE__INST3_SEG3 0
595 #define HDP_BASE__INST3_SEG4 0
596
597 #define HDP_BASE__INST4_SEG0 0
598 #define HDP_BASE__INST4_SEG1 0
599 #define HDP_BASE__INST4_SEG2 0
600 #define HDP_BASE__INST4_SEG3 0
601 #define HDP_BASE__INST4_SEG4 0
602
603 #define HDP_BASE__INST5_SEG0 0
604 #define HDP_BASE__INST5_SEG1 0
605 #define HDP_BASE__INST5_SEG2 0
606 #define HDP_BASE__INST5_SEG3 0
607 #define HDP_BASE__INST5_SEG4 0
608
609 #define HDP_BASE__INST6_SEG0 0
610 #define HDP_BASE__INST6_SEG1 0
611 #define HDP_BASE__INST6_SEG2 0
612 #define HDP_BASE__INST6_SEG3 0
613 #define HDP_BASE__INST6_SEG4 0
614
615 #define MMHUB_BASE__INST0_SEG0 0x0001A000
616 #define MMHUB_BASE__INST0_SEG1 0x02408800
617 #define MMHUB_BASE__INST0_SEG2 0
618 #define MMHUB_BASE__INST0_SEG3 0
619 #define MMHUB_BASE__INST0_SEG4 0
620
621 #define MMHUB_BASE__INST1_SEG0 0
622 #define MMHUB_BASE__INST1_SEG1 0
623 #define MMHUB_BASE__INST1_SEG2 0
624 #define MMHUB_BASE__INST1_SEG3 0
625 #define MMHUB_BASE__INST1_SEG4 0
626
627 #define MMHUB_BASE__INST2_SEG0 0
628 #define MMHUB_BASE__INST2_SEG1 0
629 #define MMHUB_BASE__INST2_SEG2 0
630 #define MMHUB_BASE__INST2_SEG3 0
631 #define MMHUB_BASE__INST2_SEG4 0
632
633 #define MMHUB_BASE__INST3_SEG0 0
634 #define MMHUB_BASE__INST3_SEG1 0
635 #define MMHUB_BASE__INST3_SEG2 0
636 #define MMHUB_BASE__INST3_SEG3 0
637 #define MMHUB_BASE__INST3_SEG4 0
638
639 #define MMHUB_BASE__INST4_SEG0 0
640 #define MMHUB_BASE__INST4_SEG1 0
641 #define MMHUB_BASE__INST4_SEG2 0
642 #define MMHUB_BASE__INST4_SEG3 0
643 #define MMHUB_BASE__INST4_SEG4 0
644
645 #define MMHUB_BASE__INST5_SEG0 0
646 #define MMHUB_BASE__INST5_SEG1 0
647 #define MMHUB_BASE__INST5_SEG2 0
648 #define MMHUB_BASE__INST5_SEG3 0
649 #define MMHUB_BASE__INST5_SEG4 0
650
651 #define MMHUB_BASE__INST6_SEG0 0
652 #define MMHUB_BASE__INST6_SEG1 0
653 #define MMHUB_BASE__INST6_SEG2 0
654 #define MMHUB_BASE__INST6_SEG3 0
655 #define MMHUB_BASE__INST6_SEG4 0
656
657 #define MP0_BASE__INST0_SEG0 0x00016000
658 #define MP0_BASE__INST0_SEG1 0x00DC0000
659 #define MP0_BASE__INST0_SEG2 0x00E00000
660 #define MP0_BASE__INST0_SEG3 0x00E40000
661 #define MP0_BASE__INST0_SEG4 0x0243FC00
662
663 #define MP0_BASE__INST1_SEG0 0
664 #define MP0_BASE__INST1_SEG1 0
665 #define MP0_BASE__INST1_SEG2 0
666 #define MP0_BASE__INST1_SEG3 0
667 #define MP0_BASE__INST1_SEG4 0
668
669 #define MP0_BASE__INST2_SEG0 0
670 #define MP0_BASE__INST2_SEG1 0
671 #define MP0_BASE__INST2_SEG2 0
672 #define MP0_BASE__INST2_SEG3 0
673 #define MP0_BASE__INST2_SEG4 0
674
675 #define MP0_BASE__INST3_SEG0 0
676 #define MP0_BASE__INST3_SEG1 0
677 #define MP0_BASE__INST3_SEG2 0
678 #define MP0_BASE__INST3_SEG3 0
679 #define MP0_BASE__INST3_SEG4 0
680
681 #define MP0_BASE__INST4_SEG0 0
682 #define MP0_BASE__INST4_SEG1 0
683 #define MP0_BASE__INST4_SEG2 0
684 #define MP0_BASE__INST4_SEG3 0
685 #define MP0_BASE__INST4_SEG4 0
686
687 #define MP0_BASE__INST5_SEG0 0
688 #define MP0_BASE__INST5_SEG1 0
689 #define MP0_BASE__INST5_SEG2 0
690 #define MP0_BASE__INST5_SEG3 0
691 #define MP0_BASE__INST5_SEG4 0
692
693 #define MP0_BASE__INST6_SEG0 0
694 #define MP0_BASE__INST6_SEG1 0
695 #define MP0_BASE__INST6_SEG2 0
696 #define MP0_BASE__INST6_SEG3 0
697 #define MP0_BASE__INST6_SEG4 0
698
699 #define MP1_BASE__INST0_SEG0 0x00016200
700 #define MP1_BASE__INST0_SEG1 0x00E80000
701 #define MP1_BASE__INST0_SEG2 0x00EC0000
702 #define MP1_BASE__INST0_SEG3 0x00F00000
703 #define MP1_BASE__INST0_SEG4 0x02400400
704
705 #define MP1_BASE__INST1_SEG0 0
706 #define MP1_BASE__INST1_SEG1 0
707 #define MP1_BASE__INST1_SEG2 0
708 #define MP1_BASE__INST1_SEG3 0
709 #define MP1_BASE__INST1_SEG4 0
710
711 #define MP1_BASE__INST2_SEG0 0
712 #define MP1_BASE__INST2_SEG1 0
713 #define MP1_BASE__INST2_SEG2 0
714 #define MP1_BASE__INST2_SEG3 0
715 #define MP1_BASE__INST2_SEG4 0
716
717 #define MP1_BASE__INST3_SEG0 0
718 #define MP1_BASE__INST3_SEG1 0
719 #define MP1_BASE__INST3_SEG2 0
720 #define MP1_BASE__INST3_SEG3 0
721 #define MP1_BASE__INST3_SEG4 0
722
723 #define MP1_BASE__INST4_SEG0 0
724 #define MP1_BASE__INST4_SEG1 0
725 #define MP1_BASE__INST4_SEG2 0
726 #define MP1_BASE__INST4_SEG3 0
727 #define MP1_BASE__INST4_SEG4 0
728
729 #define MP1_BASE__INST5_SEG0 0
730 #define MP1_BASE__INST5_SEG1 0
731 #define MP1_BASE__INST5_SEG2 0
732 #define MP1_BASE__INST5_SEG3 0
733 #define MP1_BASE__INST5_SEG4 0
734
735 #define MP1_BASE__INST6_SEG0 0
736 #define MP1_BASE__INST6_SEG1 0
737 #define MP1_BASE__INST6_SEG2 0
738 #define MP1_BASE__INST6_SEG3 0
739 #define MP1_BASE__INST6_SEG4 0
740
741 #define NBIF0_BASE__INST0_SEG0 0x00000000
742 #define NBIF0_BASE__INST0_SEG1 0x00000014
743 #define NBIF0_BASE__INST0_SEG2 0x00000D20
744 #define NBIF0_BASE__INST0_SEG3 0x00010400
745 #define NBIF0_BASE__INST0_SEG4 0x0241B000
746
747 #define NBIF0_BASE__INST1_SEG0 0
748 #define NBIF0_BASE__INST1_SEG1 0
749 #define NBIF0_BASE__INST1_SEG2 0
750 #define NBIF0_BASE__INST1_SEG3 0
751 #define NBIF0_BASE__INST1_SEG4 0
752
753 #define NBIF0_BASE__INST2_SEG0 0
754 #define NBIF0_BASE__INST2_SEG1 0
755 #define NBIF0_BASE__INST2_SEG2 0
756 #define NBIF0_BASE__INST2_SEG3 0
757 #define NBIF0_BASE__INST2_SEG4 0
758
759 #define NBIF0_BASE__INST3_SEG0 0
760 #define NBIF0_BASE__INST3_SEG1 0
761 #define NBIF0_BASE__INST3_SEG2 0
762 #define NBIF0_BASE__INST3_SEG3 0
763 #define NBIF0_BASE__INST3_SEG4 0
764
765 #define NBIF0_BASE__INST4_SEG0 0
766 #define NBIF0_BASE__INST4_SEG1 0
767 #define NBIF0_BASE__INST4_SEG2 0
768 #define NBIF0_BASE__INST4_SEG3 0
769 #define NBIF0_BASE__INST4_SEG4 0
770
771 #define NBIF0_BASE__INST5_SEG0 0
772 #define NBIF0_BASE__INST5_SEG1 0
773 #define NBIF0_BASE__INST5_SEG2 0
774 #define NBIF0_BASE__INST5_SEG3 0
775 #define NBIF0_BASE__INST5_SEG4 0
776
777 #define NBIF0_BASE__INST6_SEG0 0
778 #define NBIF0_BASE__INST6_SEG1 0
779 #define NBIF0_BASE__INST6_SEG2 0
780 #define NBIF0_BASE__INST6_SEG3 0
781 #define NBIF0_BASE__INST6_SEG4 0
782
783 #define OSSSYS_BASE__INST0_SEG0 0x000010A0
784 #define OSSSYS_BASE__INST0_SEG1 0x0240A000
785 #define OSSSYS_BASE__INST0_SEG2 0
786 #define OSSSYS_BASE__INST0_SEG3 0
787 #define OSSSYS_BASE__INST0_SEG4 0
788
789 #define OSSSYS_BASE__INST1_SEG0 0
790 #define OSSSYS_BASE__INST1_SEG1 0
791 #define OSSSYS_BASE__INST1_SEG2 0
792 #define OSSSYS_BASE__INST1_SEG3 0
793 #define OSSSYS_BASE__INST1_SEG4 0
794
795 #define OSSSYS_BASE__INST2_SEG0 0
796 #define OSSSYS_BASE__INST2_SEG1 0
797 #define OSSSYS_BASE__INST2_SEG2 0
798 #define OSSSYS_BASE__INST2_SEG3 0
799 #define OSSSYS_BASE__INST2_SEG4 0
800
801 #define OSSSYS_BASE__INST3_SEG0 0
802 #define OSSSYS_BASE__INST3_SEG1 0
803 #define OSSSYS_BASE__INST3_SEG2 0
804 #define OSSSYS_BASE__INST3_SEG3 0
805 #define OSSSYS_BASE__INST3_SEG4 0
806
807 #define OSSSYS_BASE__INST4_SEG0 0
808 #define OSSSYS_BASE__INST4_SEG1 0
809 #define OSSSYS_BASE__INST4_SEG2 0
810 #define OSSSYS_BASE__INST4_SEG3 0
811 #define OSSSYS_BASE__INST4_SEG4 0
812
813 #define OSSSYS_BASE__INST5_SEG0 0
814 #define OSSSYS_BASE__INST5_SEG1 0
815 #define OSSSYS_BASE__INST5_SEG2 0
816 #define OSSSYS_BASE__INST5_SEG3 0
817 #define OSSSYS_BASE__INST5_SEG4 0
818
819 #define OSSSYS_BASE__INST6_SEG0 0
820 #define OSSSYS_BASE__INST6_SEG1 0
821 #define OSSSYS_BASE__INST6_SEG2 0
822 #define OSSSYS_BASE__INST6_SEG3 0
823 #define OSSSYS_BASE__INST6_SEG4 0
824
825 #define PCIE0_BASE__INST0_SEG0 0x02411800
826 #define PCIE0_BASE__INST0_SEG1 0x04440000
827 #define PCIE0_BASE__INST0_SEG2 0
828 #define PCIE0_BASE__INST0_SEG3 0
829 #define PCIE0_BASE__INST0_SEG4 0
830
831 #define PCIE0_BASE__INST1_SEG0 0
832 #define PCIE0_BASE__INST1_SEG1 0
833 #define PCIE0_BASE__INST1_SEG2 0
834 #define PCIE0_BASE__INST1_SEG3 0
835 #define PCIE0_BASE__INST1_SEG4 0
836
837 #define PCIE0_BASE__INST2_SEG0 0
838 #define PCIE0_BASE__INST2_SEG1 0
839 #define PCIE0_BASE__INST2_SEG2 0
840 #define PCIE0_BASE__INST2_SEG3 0
841 #define PCIE0_BASE__INST2_SEG4 0
842
843 #define PCIE0_BASE__INST3_SEG0 0
844 #define PCIE0_BASE__INST3_SEG1 0
845 #define PCIE0_BASE__INST3_SEG2 0
846 #define PCIE0_BASE__INST3_SEG3 0
847 #define PCIE0_BASE__INST3_SEG4 0
848
849 #define PCIE0_BASE__INST4_SEG0 0
850 #define PCIE0_BASE__INST4_SEG1 0
851 #define PCIE0_BASE__INST4_SEG2 0
852 #define PCIE0_BASE__INST4_SEG3 0
853 #define PCIE0_BASE__INST4_SEG4 0
854
855 #define PCIE0_BASE__INST5_SEG0 0
856 #define PCIE0_BASE__INST5_SEG1 0
857 #define PCIE0_BASE__INST5_SEG2 0
858 #define PCIE0_BASE__INST5_SEG3 0
859 #define PCIE0_BASE__INST5_SEG4 0
860
861 #define PCIE0_BASE__INST6_SEG0 0
862 #define PCIE0_BASE__INST6_SEG1 0
863 #define PCIE0_BASE__INST6_SEG2 0
864 #define PCIE0_BASE__INST6_SEG3 0
865 #define PCIE0_BASE__INST6_SEG4 0
866
867 #define SDMA_BASE__INST0_SEG0 0x00001260
868 #define SDMA_BASE__INST0_SEG1 0x0000A000
869 #define SDMA_BASE__INST0_SEG2 0x02402C00
870 #define SDMA_BASE__INST0_SEG3 0
871 #define SDMA_BASE__INST0_SEG4 0
872
873 #define SDMA_BASE__INST1_SEG0 0x00001260
874 #define SDMA_BASE__INST1_SEG1 0x0000A000
875 #define SDMA_BASE__INST1_SEG2 0x02402C00
876 #define SDMA_BASE__INST1_SEG3 0
877 #define SDMA_BASE__INST1_SEG4 0
878
879 #define SDMA_BASE__INST2_SEG0 0
880 #define SDMA_BASE__INST2_SEG1 0
881 #define SDMA_BASE__INST2_SEG2 0
882 #define SDMA_BASE__INST2_SEG3 0
883 #define SDMA_BASE__INST2_SEG4 0
884
885 #define SDMA_BASE__INST3_SEG0 0
886 #define SDMA_BASE__INST3_SEG1 0
887 #define SDMA_BASE__INST3_SEG2 0
888 #define SDMA_BASE__INST3_SEG3 0
889 #define SDMA_BASE__INST3_SEG4 0
890
891 #define SDMA_BASE__INST4_SEG0 0
892 #define SDMA_BASE__INST4_SEG1 0
893 #define SDMA_BASE__INST4_SEG2 0
894 #define SDMA_BASE__INST4_SEG3 0
895 #define SDMA_BASE__INST4_SEG4 0
896
897 #define SDMA_BASE__INST5_SEG0 0
898 #define SDMA_BASE__INST5_SEG1 0
899 #define SDMA_BASE__INST5_SEG2 0
900 #define SDMA_BASE__INST5_SEG3 0
901 #define SDMA_BASE__INST5_SEG4 0
902
903 #define SDMA_BASE__INST6_SEG0 0
904 #define SDMA_BASE__INST6_SEG1 0
905 #define SDMA_BASE__INST6_SEG2 0
906 #define SDMA_BASE__INST6_SEG3 0
907 #define SDMA_BASE__INST6_SEG4 0
908
909 #define SMUIO_BASE__INST0_SEG0 0x00016800
910 #define SMUIO_BASE__INST0_SEG1 0x00016A00
911 #define SMUIO_BASE__INST0_SEG2 0x00440000
912 #define SMUIO_BASE__INST0_SEG3 0x02401000
913 #define SMUIO_BASE__INST0_SEG4 0
914
915 #define SMUIO_BASE__INST1_SEG0 0
916 #define SMUIO_BASE__INST1_SEG1 0
917 #define SMUIO_BASE__INST1_SEG2 0
918 #define SMUIO_BASE__INST1_SEG3 0
919 #define SMUIO_BASE__INST1_SEG4 0
920
921 #define SMUIO_BASE__INST2_SEG0 0
922 #define SMUIO_BASE__INST2_SEG1 0
923 #define SMUIO_BASE__INST2_SEG2 0
924 #define SMUIO_BASE__INST2_SEG3 0
925 #define SMUIO_BASE__INST2_SEG4 0
926
927 #define SMUIO_BASE__INST3_SEG0 0
928 #define SMUIO_BASE__INST3_SEG1 0
929 #define SMUIO_BASE__INST3_SEG2 0
930 #define SMUIO_BASE__INST3_SEG3 0
931 #define SMUIO_BASE__INST3_SEG4 0
932
933 #define SMUIO_BASE__INST4_SEG0 0
934 #define SMUIO_BASE__INST4_SEG1 0
935 #define SMUIO_BASE__INST4_SEG2 0
936 #define SMUIO_BASE__INST4_SEG3 0
937 #define SMUIO_BASE__INST4_SEG4 0
938
939 #define SMUIO_BASE__INST5_SEG0 0
940 #define SMUIO_BASE__INST5_SEG1 0
941 #define SMUIO_BASE__INST5_SEG2 0
942 #define SMUIO_BASE__INST5_SEG3 0
943 #define SMUIO_BASE__INST5_SEG4 0
944
945 #define SMUIO_BASE__INST6_SEG0 0
946 #define SMUIO_BASE__INST6_SEG1 0
947 #define SMUIO_BASE__INST6_SEG2 0
948 #define SMUIO_BASE__INST6_SEG3 0
949 #define SMUIO_BASE__INST6_SEG4 0
950
951 #define THM_BASE__INST0_SEG0 0x00016600
952 #define THM_BASE__INST0_SEG1 0x02400C00
953 #define THM_BASE__INST0_SEG2 0
954 #define THM_BASE__INST0_SEG3 0
955 #define THM_BASE__INST0_SEG4 0
956
957 #define THM_BASE__INST1_SEG0 0
958 #define THM_BASE__INST1_SEG1 0
959 #define THM_BASE__INST1_SEG2 0
960 #define THM_BASE__INST1_SEG3 0
961 #define THM_BASE__INST1_SEG4 0
962
963 #define THM_BASE__INST2_SEG0 0
964 #define THM_BASE__INST2_SEG1 0
965 #define THM_BASE__INST2_SEG2 0
966 #define THM_BASE__INST2_SEG3 0
967 #define THM_BASE__INST2_SEG4 0
968
969 #define THM_BASE__INST3_SEG0 0
970 #define THM_BASE__INST3_SEG1 0
971 #define THM_BASE__INST3_SEG2 0
972 #define THM_BASE__INST3_SEG3 0
973 #define THM_BASE__INST3_SEG4 0
974
975 #define THM_BASE__INST4_SEG0 0
976 #define THM_BASE__INST4_SEG1 0
977 #define THM_BASE__INST4_SEG2 0
978 #define THM_BASE__INST4_SEG3 0
979 #define THM_BASE__INST4_SEG4 0
980
981 #define THM_BASE__INST5_SEG0 0
982 #define THM_BASE__INST5_SEG1 0
983 #define THM_BASE__INST5_SEG2 0
984 #define THM_BASE__INST5_SEG3 0
985 #define THM_BASE__INST5_SEG4 0
986
987 #define THM_BASE__INST6_SEG0 0
988 #define THM_BASE__INST6_SEG1 0
989 #define THM_BASE__INST6_SEG2 0
990 #define THM_BASE__INST6_SEG3 0
991 #define THM_BASE__INST6_SEG4 0
992
993 #define UMC_BASE__INST0_SEG0 0x00014000
994 #define UMC_BASE__INST0_SEG1 0x02425800
995 #define UMC_BASE__INST0_SEG2 0
996 #define UMC_BASE__INST0_SEG3 0
997 #define UMC_BASE__INST0_SEG4 0
998
999 #define UMC_BASE__INST1_SEG0 0x00054000
1000 #define UMC_BASE__INST1_SEG1 0x02425C00
1001 #define UMC_BASE__INST1_SEG2 0
1002 #define UMC_BASE__INST1_SEG3 0
1003 #define UMC_BASE__INST1_SEG4 0
1004
1005 #define UMC_BASE__INST2_SEG0 0x00094000
1006 #define UMC_BASE__INST2_SEG1 0x02426000
1007 #define UMC_BASE__INST2_SEG2 0
1008 #define UMC_BASE__INST2_SEG3 0
1009 #define UMC_BASE__INST2_SEG4 0
1010
1011 #define UMC_BASE__INST3_SEG0 0x000D4000
1012 #define UMC_BASE__INST3_SEG1 0x02426400
1013 #define UMC_BASE__INST3_SEG2 0
1014 #define UMC_BASE__INST3_SEG3 0
1015 #define UMC_BASE__INST3_SEG4 0
1016
1017 #define UMC_BASE__INST4_SEG0 0
1018 #define UMC_BASE__INST4_SEG1 0
1019 #define UMC_BASE__INST4_SEG2 0
1020 #define UMC_BASE__INST4_SEG3 0
1021 #define UMC_BASE__INST4_SEG4 0
1022
1023 #define UMC_BASE__INST5_SEG0 0
1024 #define UMC_BASE__INST5_SEG1 0
1025 #define UMC_BASE__INST5_SEG2 0
1026 #define UMC_BASE__INST5_SEG3 0
1027 #define UMC_BASE__INST5_SEG4 0
1028
1029 #define UMC_BASE__INST6_SEG0 0
1030 #define UMC_BASE__INST6_SEG1 0
1031 #define UMC_BASE__INST6_SEG2 0
1032 #define UMC_BASE__INST6_SEG3 0
1033 #define UMC_BASE__INST6_SEG4 0
1034
1035 #define USB0_BASE__INST0_SEG0 0x0242A800
1036 #define USB0_BASE__INST0_SEG1 0x05B00000
1037 #define USB0_BASE__INST0_SEG2 0
1038 #define USB0_BASE__INST0_SEG3 0
1039 #define USB0_BASE__INST0_SEG4 0
1040
1041 #define USB0_BASE__INST1_SEG0 0
1042 #define USB0_BASE__INST1_SEG1 0
1043 #define USB0_BASE__INST1_SEG2 0
1044 #define USB0_BASE__INST1_SEG3 0
1045 #define USB0_BASE__INST1_SEG4 0
1046
1047 #define USB0_BASE__INST2_SEG0 0
1048 #define USB0_BASE__INST2_SEG1 0
1049 #define USB0_BASE__INST2_SEG2 0
1050 #define USB0_BASE__INST2_SEG3 0
1051 #define USB0_BASE__INST2_SEG4 0
1052
1053 #define USB0_BASE__INST3_SEG0 0
1054 #define USB0_BASE__INST3_SEG1 0
1055 #define USB0_BASE__INST3_SEG2 0
1056 #define USB0_BASE__INST3_SEG3 0
1057 #define USB0_BASE__INST3_SEG4 0
1058
1059 #define USB0_BASE__INST4_SEG0 0
1060 #define USB0_BASE__INST4_SEG1 0
1061 #define USB0_BASE__INST4_SEG2 0
1062 #define USB0_BASE__INST4_SEG3 0
1063 #define USB0_BASE__INST4_SEG4 0
1064
1065 #define USB0_BASE__INST5_SEG0 0
1066 #define USB0_BASE__INST5_SEG1 0
1067 #define USB0_BASE__INST5_SEG2 0
1068 #define USB0_BASE__INST5_SEG3 0
1069 #define USB0_BASE__INST5_SEG4 0
1070
1071 #define USB0_BASE__INST6_SEG0 0
1072 #define USB0_BASE__INST6_SEG1 0
1073 #define USB0_BASE__INST6_SEG2 0
1074 #define USB0_BASE__INST6_SEG3 0
1075 #define USB0_BASE__INST6_SEG4 0
1076
1077 #define UVD0_BASE__INST0_SEG0 0x00007800
1078 #define UVD0_BASE__INST0_SEG1 0x00007E00
1079 #define UVD0_BASE__INST0_SEG2 0x02403000
1080 #define UVD0_BASE__INST0_SEG3 0
1081 #define UVD0_BASE__INST0_SEG4 0
1082
1083 #define UVD0_BASE__INST1_SEG0 0
1084 #define UVD0_BASE__INST1_SEG1 0
1085 #define UVD0_BASE__INST1_SEG2 0
1086 #define UVD0_BASE__INST1_SEG3 0
1087 #define UVD0_BASE__INST1_SEG4 0
1088
1089 #define UVD0_BASE__INST2_SEG0 0
1090 #define UVD0_BASE__INST2_SEG1 0
1091 #define UVD0_BASE__INST2_SEG2 0
1092 #define UVD0_BASE__INST2_SEG3 0
1093 #define UVD0_BASE__INST2_SEG4 0
1094
1095 #define UVD0_BASE__INST3_SEG0 0
1096 #define UVD0_BASE__INST3_SEG1 0
1097 #define UVD0_BASE__INST3_SEG2 0
1098 #define UVD0_BASE__INST3_SEG3 0
1099 #define UVD0_BASE__INST3_SEG4 0
1100
1101 #define UVD0_BASE__INST4_SEG0 0
1102 #define UVD0_BASE__INST4_SEG1 0
1103 #define UVD0_BASE__INST4_SEG2 0
1104 #define UVD0_BASE__INST4_SEG3 0
1105 #define UVD0_BASE__INST4_SEG4 0
1106
1107 #define UVD0_BASE__INST5_SEG0 0
1108 #define UVD0_BASE__INST5_SEG1 0
1109 #define UVD0_BASE__INST5_SEG2 0
1110 #define UVD0_BASE__INST5_SEG3 0
1111 #define UVD0_BASE__INST5_SEG4 0
1112
1113 #define UVD0_BASE__INST6_SEG0 0
1114 #define UVD0_BASE__INST6_SEG1 0
1115 #define UVD0_BASE__INST6_SEG2 0
1116 #define UVD0_BASE__INST6_SEG3 0
1117 #define UVD0_BASE__INST6_SEG4 0
1118
1119 #endif