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28 #ifndef _ATOMFIRMWAREID_H_
29 #define _ATOMFIRMWAREID_H_
30
31 enum atom_master_data_table_id
32 {
33 VBIOS_DATA_TBL_ID__UTILITY_PIPELINE,
34 VBIOS_DATA_TBL_ID__MULTIMEDIA_INF,
35 VBIOS_DATA_TBL_ID__FIRMWARE_INF,
36 VBIOS_DATA_TBL_ID__LCD_INF,
37 VBIOS_DATA_TBL_ID__SMU_INF,
38 VBIOS_DATA_TBL_ID__VRAM_USAGE_BY_FIRMWARE,
39 VBIOS_DATA_TBL_ID__GPIO_PIN_LUT,
40 VBIOS_DATA_TBL_ID__GFX_INF,
41 VBIOS_DATA_TBL_ID__POWER_PLAY_INF,
42 VBIOS_DATA_TBL_ID__DISPLAY_OBJECT_INF,
43 VBIOS_DATA_TBL_ID__INDIRECT_IO_ACCESS,
44 VBIOS_DATA_TBL_ID__UMC_INF,
45 VBIOS_DATA_TBL_ID__DCE_INF,
46 VBIOS_DATA_TBL_ID__VRAM_INF,
47 VBIOS_DATA_TBL_ID__INTEGRATED_SYS_INF,
48 VBIOS_DATA_TBL_ID__ASIC_PROFILING_INF,
49 VBIOS_DATA_TBL_ID__VOLTAGE_OBJ_INF,
50
51 VBIOS_DATA_TBL_ID__UNDEFINED,
52 };
53
54 enum atom_master_command_table_id
55 {
56 VBIOS_CMD_TBL_ID__ASIC_INIT,
57 VBIOS_CMD_TBL_ID__DIGX_ENCODER_CONTROL,
58 VBIOS_CMD_TBL_ID__SET_ENGINE_CLOCK,
59 VBIOS_CMD_TBL_ID__SET_MEMORY_CLOCK,
60 VBIOS_CMD_TBL_ID__SET_PIXEL_CLOCK,
61 VBIOS_CMD_TBL_ID__ENABLE_DISP_POWER_GATING,
62 VBIOS_CMD_TBL_ID__BLANK_CRTC,
63 VBIOS_CMD_TBL_ID__ENABLE_CRTC,
64 VBIOS_CMD_TBL_ID__GET_SMU_CLOCK_INFO,
65 VBIOS_CMD_TBL_ID__SELECT_CRTC_SOURCE,
66 VBIOS_CMD_TBL_ID__SET_DCE_CLOCK,
67 VBIOS_CMD_TBL_ID__GET_MEMORY_CLOCK,
68 VBIOS_CMD_TBL_ID__GET_ENGINE_CLOCK,
69 VBIOS_CMD_TBL_ID__SET_CRTC_USING_DTD_TIMING,
70 VBIOS_CMD_TBL_ID__EXTENAL_ENCODER_CONTROL,
71 VBIOS_CMD_TBL_ID__PROCESS_I2C_CHANNEL_TRANSACTION,
72 VBIOS_CMD_TBL_ID__COMPUTE_GPU_CLOCK_PARAM,
73 VBIOS_CMD_TBL_ID__DYNAMIC_MEMORY_SETTINGS,
74 VBIOS_CMD_TBL_ID__MEMORY_TRAINING,
75 VBIOS_CMD_TBL_ID__SET_VOLTAGE,
76 VBIOS_CMD_TBL_ID__DIG1_TRANSMITTER_CONTROL,
77 VBIOS_CMD_TBL_ID__PROCESS_AUX_CHANNEL_TRANSACTION,
78 VBIOS_CMD_TBL_ID__GET_VOLTAGE_INF,
79
80 VBIOS_CMD_TBL_ID__UNDEFINED,
81 };
82
83
84
85 #endif
86