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9 #ifndef __ASM_SYSREG_H
10 #define __ASM_SYSREG_H
11
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
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24
25 #define Op0_shift 19
26 #define Op0_mask 0x3
27 #define Op1_shift 16
28 #define Op1_mask 0x7
29 #define CRn_shift 12
30 #define CRn_mask 0xf
31 #define CRm_shift 8
32 #define CRm_mask 0xf
33 #define Op2_shift 5
34 #define Op2_mask 0x7
35
36 #define sys_reg(op0, op1, crn, crm, op2) \
37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
39 ((op2) << Op2_shift))
40
41 #define sys_insn sys_reg
42
43 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
44 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
45 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
46 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
47 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
48
49 #ifndef CONFIG_BROKEN_GAS_INST
50
51 #ifdef __ASSEMBLY__
52
53
54 #define __emit_inst(x) .inst(x)
55 #else
56 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
57 #endif
58
59 #else
60
61 #ifndef CONFIG_CPU_BIG_ENDIAN
62 #define __INSTR_BSWAP(x) (x)
63 #else
64 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
65 (((x) << 8) & 0x00ff0000) | \
66 (((x) >> 8) & 0x0000ff00) | \
67 (((x) >> 24) & 0x000000ff))
68 #endif
69
70 #ifdef __ASSEMBLY__
71 #define __emit_inst(x) .long __INSTR_BSWAP(x)
72 #else
73 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
74 #endif
75
76 #endif
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87
88 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
89 #define PSTATE_Imm_shift CRm_shift
90
91 #define PSTATE_PAN pstate_field(0, 4)
92 #define PSTATE_UAO pstate_field(0, 3)
93 #define PSTATE_SSBS pstate_field(3, 1)
94
95 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
96 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
97 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
98
99 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
100 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
101
102 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
103
104 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
105 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
106 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
107
108 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
109 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
110 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
111 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
112 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
113 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
114 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
115 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
116 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
117 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
118 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
119 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
120 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
121 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
122 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
123 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
124 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
125 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
126 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
127 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
128 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
129 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
130
131 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
132 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
133 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
134
135 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
136 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
137 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
138 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
139 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
140 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
141 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
142 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
143
144 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
145 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
146 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
147 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
148 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
149 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
150 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
151
152 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
153 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
154 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
155
156 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
157 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
158 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
159
160 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
161 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
162
163 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
164 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
165
166 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
167 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
168
169 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
170 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
171 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
172
173 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
174 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
175 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
176
177 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
178
179 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
180 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
181 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
182
183 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
184 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
185 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
186 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
187
188 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
189 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
190 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
191 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
192
193 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
194 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
195
196 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
197 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
198
199 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
200
201 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
202 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
203 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
204
205 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
206 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
207 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
208 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
209 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
210 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
211 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
212 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
213
214 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
215 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
216
217 #define SYS_PAR_EL1_F BIT(0)
218 #define SYS_PAR_EL1_FST GENMASK(6, 1)
219
220
221
222 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
223 #define SYS_PMSIDR_EL1_FE_SHIFT 0
224 #define SYS_PMSIDR_EL1_FT_SHIFT 1
225 #define SYS_PMSIDR_EL1_FL_SHIFT 2
226 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
227 #define SYS_PMSIDR_EL1_LDS_SHIFT 4
228 #define SYS_PMSIDR_EL1_ERND_SHIFT 5
229 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8
230 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL
231 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
232 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL
233 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16
234 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL
235
236 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
237 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0
238 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU
239 #define SYS_PMBIDR_EL1_P_SHIFT 4
240 #define SYS_PMBIDR_EL1_F_SHIFT 5
241
242
243 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
244 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0
245 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1
246 #define SYS_PMSCR_EL1_CX_SHIFT 3
247 #define SYS_PMSCR_EL1_PA_SHIFT 4
248 #define SYS_PMSCR_EL1_TS_SHIFT 5
249 #define SYS_PMSCR_EL1_PCT_SHIFT 6
250
251 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
252 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0
253 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1
254 #define SYS_PMSCR_EL2_CX_SHIFT 3
255 #define SYS_PMSCR_EL2_PA_SHIFT 4
256 #define SYS_PMSCR_EL2_TS_SHIFT 5
257 #define SYS_PMSCR_EL2_PCT_SHIFT 6
258
259 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
260
261 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
262 #define SYS_PMSIRR_EL1_RND_SHIFT 0
263 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8
264 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL
265
266
267 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
268 #define SYS_PMSFCR_EL1_FE_SHIFT 0
269 #define SYS_PMSFCR_EL1_FT_SHIFT 1
270 #define SYS_PMSFCR_EL1_FL_SHIFT 2
271 #define SYS_PMSFCR_EL1_B_SHIFT 16
272 #define SYS_PMSFCR_EL1_LD_SHIFT 17
273 #define SYS_PMSFCR_EL1_ST_SHIFT 18
274
275 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
276 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
277
278 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
279 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
280
281
282 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
283 #define SYS_PMBLIMITR_EL1_E_SHIFT 0
284 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1
285 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL
286 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
287
288 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
289
290
291 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
292 #define SYS_PMBSR_EL1_COLL_SHIFT 16
293 #define SYS_PMBSR_EL1_S_SHIFT 17
294 #define SYS_PMBSR_EL1_EA_SHIFT 18
295 #define SYS_PMBSR_EL1_DL_SHIFT 19
296 #define SYS_PMBSR_EL1_EC_SHIFT 26
297 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL
298
299 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
300 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
301 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
302
303 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0
304 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
305
306 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0
307 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL
308
309 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
310
311
312
313 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
314 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
315
316 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
317 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
318
319 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
320 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
321 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
322 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
323 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
324
325 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
326 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
327
328 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
329 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
330 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
331 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
332 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
333 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
334 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
335 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
336 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
337 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
338 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
339 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
340 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
341 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
342 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
343 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
344 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
345 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
346 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
347 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
348 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
349 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
350 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
351 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
352 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
353 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
354 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
355
356 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
357 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
358
359 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
360
361 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
362 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
363 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
364
365 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
366
367 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
368 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
369
370 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
371 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
372 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
373 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
374 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
375 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
376 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
377 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
378 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
379 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
380 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
381 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
382 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
383
384 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
385 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
386
387 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
388
389 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
390 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
391 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
392
393 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
394 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
395
396 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
397 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
398 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
399
400 #define __PMEV_op2(n) ((n) & 0x7)
401 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
402 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
403 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
404 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
405
406 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
407
408 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
409 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
410 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
411 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
412 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
413 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
414 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
415 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
416 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
417
418 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
419 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
420 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
421 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
422 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
423 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
424
425 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
426 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
427 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
428 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
429 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
430
431 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
432 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
433 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
434 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
435 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
436 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
437 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
438 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
439
440 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
441 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
442 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
443 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
444 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
445 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
446 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
447 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
448 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
449
450 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
451 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
452 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
453 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
454 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
455 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
456 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
457 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
458 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
459
460
461 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
462 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
463 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
464 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
465 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
466 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
467 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
468 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
469 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
470 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
471 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
472 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
473 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
474 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
475 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
476 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
477 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
478 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
479 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
480 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
481 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
482 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
483 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
484
485
486 #define SCTLR_ELx_DSSBS (BIT(44))
487 #define SCTLR_ELx_ENIA (BIT(31))
488 #define SCTLR_ELx_ENIB (BIT(30))
489 #define SCTLR_ELx_ENDA (BIT(27))
490 #define SCTLR_ELx_EE (BIT(25))
491 #define SCTLR_ELx_IESB (BIT(21))
492 #define SCTLR_ELx_WXN (BIT(19))
493 #define SCTLR_ELx_ENDB (BIT(13))
494 #define SCTLR_ELx_I (BIT(12))
495 #define SCTLR_ELx_SA (BIT(3))
496 #define SCTLR_ELx_C (BIT(2))
497 #define SCTLR_ELx_A (BIT(1))
498 #define SCTLR_ELx_M (BIT(0))
499
500 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
501 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
502
503
504 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
505 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
506 (BIT(29)))
507
508 #ifdef CONFIG_CPU_BIG_ENDIAN
509 #define ENDIAN_SET_EL2 SCTLR_ELx_EE
510 #else
511 #define ENDIAN_SET_EL2 0
512 #endif
513
514
515 #define SCTLR_EL1_UCI (BIT(26))
516 #define SCTLR_EL1_E0E (BIT(24))
517 #define SCTLR_EL1_SPAN (BIT(23))
518 #define SCTLR_EL1_NTWE (BIT(18))
519 #define SCTLR_EL1_NTWI (BIT(16))
520 #define SCTLR_EL1_UCT (BIT(15))
521 #define SCTLR_EL1_DZE (BIT(14))
522 #define SCTLR_EL1_UMA (BIT(9))
523 #define SCTLR_EL1_SED (BIT(8))
524 #define SCTLR_EL1_ITD (BIT(7))
525 #define SCTLR_EL1_CP15BEN (BIT(5))
526 #define SCTLR_EL1_SA0 (BIT(4))
527
528 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
529 (BIT(29)))
530
531 #ifdef CONFIG_CPU_BIG_ENDIAN
532 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
533 #else
534 #define ENDIAN_SET_EL1 0
535 #endif
536
537 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\
538 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\
539 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\
540 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
541 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1)
542
543
544 #define ID_AA64ISAR0_TS_SHIFT 52
545 #define ID_AA64ISAR0_FHM_SHIFT 48
546 #define ID_AA64ISAR0_DP_SHIFT 44
547 #define ID_AA64ISAR0_SM4_SHIFT 40
548 #define ID_AA64ISAR0_SM3_SHIFT 36
549 #define ID_AA64ISAR0_SHA3_SHIFT 32
550 #define ID_AA64ISAR0_RDM_SHIFT 28
551 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
552 #define ID_AA64ISAR0_CRC32_SHIFT 16
553 #define ID_AA64ISAR0_SHA2_SHIFT 12
554 #define ID_AA64ISAR0_SHA1_SHIFT 8
555 #define ID_AA64ISAR0_AES_SHIFT 4
556
557
558 #define ID_AA64ISAR1_SB_SHIFT 36
559 #define ID_AA64ISAR1_FRINTTS_SHIFT 32
560 #define ID_AA64ISAR1_GPI_SHIFT 28
561 #define ID_AA64ISAR1_GPA_SHIFT 24
562 #define ID_AA64ISAR1_LRCPC_SHIFT 20
563 #define ID_AA64ISAR1_FCMA_SHIFT 16
564 #define ID_AA64ISAR1_JSCVT_SHIFT 12
565 #define ID_AA64ISAR1_API_SHIFT 8
566 #define ID_AA64ISAR1_APA_SHIFT 4
567 #define ID_AA64ISAR1_DPB_SHIFT 0
568
569 #define ID_AA64ISAR1_APA_NI 0x0
570 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1
571 #define ID_AA64ISAR1_API_NI 0x0
572 #define ID_AA64ISAR1_API_IMP_DEF 0x1
573 #define ID_AA64ISAR1_GPA_NI 0x0
574 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1
575 #define ID_AA64ISAR1_GPI_NI 0x0
576 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1
577
578
579 #define ID_AA64PFR0_CSV3_SHIFT 60
580 #define ID_AA64PFR0_CSV2_SHIFT 56
581 #define ID_AA64PFR0_DIT_SHIFT 48
582 #define ID_AA64PFR0_SVE_SHIFT 32
583 #define ID_AA64PFR0_RAS_SHIFT 28
584 #define ID_AA64PFR0_GIC_SHIFT 24
585 #define ID_AA64PFR0_ASIMD_SHIFT 20
586 #define ID_AA64PFR0_FP_SHIFT 16
587 #define ID_AA64PFR0_EL3_SHIFT 12
588 #define ID_AA64PFR0_EL2_SHIFT 8
589 #define ID_AA64PFR0_EL1_SHIFT 4
590 #define ID_AA64PFR0_EL0_SHIFT 0
591
592 #define ID_AA64PFR0_SVE 0x1
593 #define ID_AA64PFR0_RAS_V1 0x1
594 #define ID_AA64PFR0_FP_NI 0xf
595 #define ID_AA64PFR0_FP_SUPPORTED 0x0
596 #define ID_AA64PFR0_ASIMD_NI 0xf
597 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
598 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
599 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
600 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
601
602
603 #define ID_AA64PFR1_SSBS_SHIFT 4
604
605 #define ID_AA64PFR1_SSBS_PSTATE_NI 0
606 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1
607 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2
608
609
610 #define ID_AA64ZFR0_SM4_SHIFT 40
611 #define ID_AA64ZFR0_SHA3_SHIFT 32
612 #define ID_AA64ZFR0_BITPERM_SHIFT 16
613 #define ID_AA64ZFR0_AES_SHIFT 4
614 #define ID_AA64ZFR0_SVEVER_SHIFT 0
615
616 #define ID_AA64ZFR0_SM4 0x1
617 #define ID_AA64ZFR0_SHA3 0x1
618 #define ID_AA64ZFR0_BITPERM 0x1
619 #define ID_AA64ZFR0_AES 0x1
620 #define ID_AA64ZFR0_AES_PMULL 0x2
621 #define ID_AA64ZFR0_SVEVER_SVE2 0x1
622
623
624 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
625 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
626 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
627 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
628 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
629 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
630 #define ID_AA64MMFR0_ASID_SHIFT 4
631 #define ID_AA64MMFR0_PARANGE_SHIFT 0
632
633 #define ID_AA64MMFR0_TGRAN4_NI 0xf
634 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
635 #define ID_AA64MMFR0_TGRAN64_NI 0xf
636 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
637 #define ID_AA64MMFR0_TGRAN16_NI 0x0
638 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
639 #define ID_AA64MMFR0_PARANGE_48 0x5
640 #define ID_AA64MMFR0_PARANGE_52 0x6
641
642 #ifdef CONFIG_ARM64_PA_BITS_52
643 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52
644 #else
645 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48
646 #endif
647
648
649 #define ID_AA64MMFR1_PAN_SHIFT 20
650 #define ID_AA64MMFR1_LOR_SHIFT 16
651 #define ID_AA64MMFR1_HPD_SHIFT 12
652 #define ID_AA64MMFR1_VHE_SHIFT 8
653 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
654 #define ID_AA64MMFR1_HADBS_SHIFT 0
655
656 #define ID_AA64MMFR1_VMIDBITS_8 0
657 #define ID_AA64MMFR1_VMIDBITS_16 2
658
659
660 #define ID_AA64MMFR2_FWB_SHIFT 40
661 #define ID_AA64MMFR2_AT_SHIFT 32
662 #define ID_AA64MMFR2_LVA_SHIFT 16
663 #define ID_AA64MMFR2_IESB_SHIFT 12
664 #define ID_AA64MMFR2_LSM_SHIFT 8
665 #define ID_AA64MMFR2_UAO_SHIFT 4
666 #define ID_AA64MMFR2_CNP_SHIFT 0
667
668
669 #define ID_AA64DFR0_PMSVER_SHIFT 32
670 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
671 #define ID_AA64DFR0_WRPS_SHIFT 20
672 #define ID_AA64DFR0_BRPS_SHIFT 12
673 #define ID_AA64DFR0_PMUVER_SHIFT 8
674 #define ID_AA64DFR0_TRACEVER_SHIFT 4
675 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
676
677 #define ID_ISAR5_RDM_SHIFT 24
678 #define ID_ISAR5_CRC32_SHIFT 16
679 #define ID_ISAR5_SHA2_SHIFT 12
680 #define ID_ISAR5_SHA1_SHIFT 8
681 #define ID_ISAR5_AES_SHIFT 4
682 #define ID_ISAR5_SEVL_SHIFT 0
683
684 #define MVFR0_FPROUND_SHIFT 28
685 #define MVFR0_FPSHVEC_SHIFT 24
686 #define MVFR0_FPSQRT_SHIFT 20
687 #define MVFR0_FPDIVIDE_SHIFT 16
688 #define MVFR0_FPTRAP_SHIFT 12
689 #define MVFR0_FPDP_SHIFT 8
690 #define MVFR0_FPSP_SHIFT 4
691 #define MVFR0_SIMD_SHIFT 0
692
693 #define MVFR1_SIMDFMAC_SHIFT 28
694 #define MVFR1_FPHP_SHIFT 24
695 #define MVFR1_SIMDHP_SHIFT 20
696 #define MVFR1_SIMDSP_SHIFT 16
697 #define MVFR1_SIMDINT_SHIFT 12
698 #define MVFR1_SIMDLS_SHIFT 8
699 #define MVFR1_FPDNAN_SHIFT 4
700 #define MVFR1_FPFTZ_SHIFT 0
701
702
703 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
704 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
705 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
706
707 #define ID_AA64MMFR0_TGRAN4_NI 0xf
708 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
709 #define ID_AA64MMFR0_TGRAN64_NI 0xf
710 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
711 #define ID_AA64MMFR0_TGRAN16_NI 0x0
712 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
713
714 #if defined(CONFIG_ARM64_4K_PAGES)
715 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
716 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
717 #elif defined(CONFIG_ARM64_16K_PAGES)
718 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
719 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
720 #elif defined(CONFIG_ARM64_64K_PAGES)
721 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
722 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
723 #endif
724
725
726
727
728
729
730
731 #define ZCR_ELx_LEN_SHIFT 0
732 #define ZCR_ELx_LEN_SIZE 9
733 #define ZCR_ELx_LEN_MASK 0x1ff
734
735 #define CPACR_EL1_ZEN_EL1EN (BIT(16))
736 #define CPACR_EL1_ZEN_EL0EN (BIT(17))
737 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
738
739
740
741 #define SYS_MPIDR_SAFE_VAL (BIT(31))
742
743 #ifdef __ASSEMBLY__
744
745 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
746 .equ .L__reg_num_x\num, \num
747 .endr
748 .equ .L__reg_num_xzr, 31
749
750 .macro mrs_s, rt, sreg
751 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
752 .endm
753
754 .macro msr_s, sreg, rt
755 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
756 .endm
757
758 #else
759
760 #include <linux/build_bug.h>
761 #include <linux/types.h>
762
763 #define __DEFINE_MRS_MSR_S_REGNUM \
764 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
765 " .equ .L__reg_num_x\\num, \\num\n" \
766 " .endr\n" \
767 " .equ .L__reg_num_xzr, 31\n"
768
769 #define DEFINE_MRS_S \
770 __DEFINE_MRS_MSR_S_REGNUM \
771 " .macro mrs_s, rt, sreg\n" \
772 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \
773 " .endm\n"
774
775 #define DEFINE_MSR_S \
776 __DEFINE_MRS_MSR_S_REGNUM \
777 " .macro msr_s, sreg, rt\n" \
778 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \
779 " .endm\n"
780
781 #define UNDEFINE_MRS_S \
782 " .purgem mrs_s\n"
783
784 #define UNDEFINE_MSR_S \
785 " .purgem msr_s\n"
786
787 #define __mrs_s(v, r) \
788 DEFINE_MRS_S \
789 " mrs_s " v ", " __stringify(r) "\n" \
790 UNDEFINE_MRS_S
791
792 #define __msr_s(r, v) \
793 DEFINE_MSR_S \
794 " msr_s " __stringify(r) ", " v "\n" \
795 UNDEFINE_MSR_S
796
797
798
799
800
801 #define read_sysreg(r) ({ \
802 u64 __val; \
803 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
804 __val; \
805 })
806
807
808
809
810
811 #define write_sysreg(v, r) do { \
812 u64 __val = (u64)(v); \
813 asm volatile("msr " __stringify(r) ", %x0" \
814 : : "rZ" (__val)); \
815 } while (0)
816
817
818
819
820
821 #define read_sysreg_s(r) ({ \
822 u64 __val; \
823 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
824 __val; \
825 })
826
827 #define write_sysreg_s(v, r) do { \
828 u64 __val = (u64)(v); \
829 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \
830 } while (0)
831
832
833
834
835
836 #define sysreg_clear_set(sysreg, clear, set) do { \
837 u64 __scs_val = read_sysreg(sysreg); \
838 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
839 if (__scs_new != __scs_val) \
840 write_sysreg(__scs_new, sysreg); \
841 } while (0)
842
843 #endif
844
845 #endif