drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager

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This source file includes following definitions.
device_queue_manager_init_vi
device_queue_manager_init_vi_tonga
compute_sh_mem_bases_64bit
set_cache_memory_policy_vi
set_cache_memory_policy_vi_tonga
update_qpd_vi
update_qpd_vi_tonga
init_sdma_vm
init_sdma_vm_tonga
   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 
  24 #include "kfd_device_queue_manager.h"
  25 #include "gca/gfx_8_0_enum.h"
  26 #include "gca/gfx_8_0_sh_mask.h"
  27 #include "oss/oss_3_0_sh_mask.h"
  28 
  29 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
  30                                    struct qcm_process_device *qpd,
  31                                    enum cache_policy default_policy,
  32                                    enum cache_policy alternate_policy,
  33                                    void __user *alternate_aperture_base,
  34                                    uint64_t alternate_aperture_size);
  35 static bool set_cache_memory_policy_vi_tonga(struct device_queue_manager *dqm,
  36                         struct qcm_process_device *qpd,
  37                         enum cache_policy default_policy,
  38                         enum cache_policy alternate_policy,
  39                         void __user *alternate_aperture_base,
  40                         uint64_t alternate_aperture_size);
  41 static int update_qpd_vi(struct device_queue_manager *dqm,
  42                                         struct qcm_process_device *qpd);
  43 static int update_qpd_vi_tonga(struct device_queue_manager *dqm,
  44                         struct qcm_process_device *qpd);
  45 static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
  46                                 struct qcm_process_device *qpd);
  47 static void init_sdma_vm_tonga(struct device_queue_manager *dqm,
  48                         struct queue *q,
  49                         struct qcm_process_device *qpd);
  50 
  51 void device_queue_manager_init_vi(
  52                 struct device_queue_manager_asic_ops *asic_ops)
  53 {
  54         asic_ops->set_cache_memory_policy = set_cache_memory_policy_vi;
  55         asic_ops->update_qpd = update_qpd_vi;
  56         asic_ops->init_sdma_vm = init_sdma_vm;
  57         asic_ops->mqd_manager_init = mqd_manager_init_vi;
  58 }
  59 
  60 void device_queue_manager_init_vi_tonga(
  61                 struct device_queue_manager_asic_ops *asic_ops)
  62 {
  63         asic_ops->set_cache_memory_policy = set_cache_memory_policy_vi_tonga;
  64         asic_ops->update_qpd = update_qpd_vi_tonga;
  65         asic_ops->init_sdma_vm = init_sdma_vm_tonga;
  66         asic_ops->mqd_manager_init = mqd_manager_init_vi_tonga;
  67 }
  68 
  69 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
  70 {
  71         /* In 64-bit mode, we can only control the top 3 bits of the LDS,
  72          * scratch and GPUVM apertures.
  73          * The hardware fills in the remaining 59 bits according to the
  74          * following pattern:
  75          * LDS:         X0000000'00000000 - X0000001'00000000 (4GB)
  76          * Scratch:     X0000001'00000000 - X0000002'00000000 (4GB)
  77          * GPUVM:       Y0010000'00000000 - Y0020000'00000000 (1TB)
  78          *
  79          * (where X/Y is the configurable nybble with the low-bit 0)
  80          *
  81          * LDS and scratch will have the same top nybble programmed in the
  82          * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
  83          * GPUVM can have a different top nybble programmed in the
  84          * top 3 bits of SH_MEM_BASES.SHARED_BASE.
  85          * We don't bother to support different top nybbles
  86          * for LDS/Scratch and GPUVM.
  87          */
  88 
  89         WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE ||
  90                 top_address_nybble == 0);
  91 
  92         return top_address_nybble << 12 |
  93                         (top_address_nybble << 12) <<
  94                         SH_MEM_BASES__SHARED_BASE__SHIFT;
  95 }
  96 
  97 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
  98                                    struct qcm_process_device *qpd,
  99                                    enum cache_policy default_policy,
 100                                    enum cache_policy alternate_policy,
 101                                    void __user *alternate_aperture_base,
 102                                    uint64_t alternate_aperture_size)
 103 {
 104         uint32_t default_mtype;
 105         uint32_t ape1_mtype;
 106 
 107         default_mtype = (default_policy == cache_policy_coherent) ?
 108                         MTYPE_CC :
 109                         MTYPE_NC;
 110 
 111         ape1_mtype = (alternate_policy == cache_policy_coherent) ?
 112                         MTYPE_CC :
 113                         MTYPE_NC;
 114 
 115         qpd->sh_mem_config = (qpd->sh_mem_config &
 116                         SH_MEM_CONFIG__ADDRESS_MODE_MASK) |
 117                 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
 118                                 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
 119                 default_mtype << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
 120                 ape1_mtype << SH_MEM_CONFIG__APE1_MTYPE__SHIFT |
 121                 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
 122 
 123         return true;
 124 }
 125 
 126 static bool set_cache_memory_policy_vi_tonga(struct device_queue_manager *dqm,
 127                 struct qcm_process_device *qpd,
 128                 enum cache_policy default_policy,
 129                 enum cache_policy alternate_policy,
 130                 void __user *alternate_aperture_base,
 131                 uint64_t alternate_aperture_size)
 132 {
 133         uint32_t default_mtype;
 134         uint32_t ape1_mtype;
 135 
 136         default_mtype = (default_policy == cache_policy_coherent) ?
 137                         MTYPE_UC :
 138                         MTYPE_NC;
 139 
 140         ape1_mtype = (alternate_policy == cache_policy_coherent) ?
 141                         MTYPE_UC :
 142                         MTYPE_NC;
 143 
 144         qpd->sh_mem_config =
 145                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
 146                                    SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
 147                         default_mtype << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
 148                         ape1_mtype << SH_MEM_CONFIG__APE1_MTYPE__SHIFT;
 149 
 150         return true;
 151 }
 152 
 153 static int update_qpd_vi(struct device_queue_manager *dqm,
 154                                         struct qcm_process_device *qpd)
 155 {
 156         struct kfd_process_device *pdd;
 157         unsigned int temp;
 158 
 159         pdd = qpd_to_pdd(qpd);
 160 
 161         /* check if sh_mem_config register already configured */
 162         if (qpd->sh_mem_config == 0) {
 163                 qpd->sh_mem_config =
 164                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
 165                                 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
 166                         MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
 167                         MTYPE_CC << SH_MEM_CONFIG__APE1_MTYPE__SHIFT |
 168                         SH_MEM_CONFIG__PRIVATE_ATC_MASK;
 169 
 170                 qpd->sh_mem_ape1_limit = 0;
 171                 qpd->sh_mem_ape1_base = 0;
 172         }
 173 
 174         if (qpd->pqm->process->is_32bit_user_mode) {
 175                 temp = get_sh_mem_bases_32(pdd);
 176                 qpd->sh_mem_bases = temp << SH_MEM_BASES__SHARED_BASE__SHIFT;
 177                 qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA32 <<
 178                                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT;
 179         } else {
 180                 temp = get_sh_mem_bases_nybble_64(pdd);
 181                 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
 182                 qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA64 <<
 183                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT;
 184                 qpd->sh_mem_config |= 1  <<
 185                         SH_MEM_CONFIG__PRIVATE_ATC__SHIFT;
 186         }
 187 
 188         pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
 189                 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
 190 
 191         return 0;
 192 }
 193 
 194 static int update_qpd_vi_tonga(struct device_queue_manager *dqm,
 195                         struct qcm_process_device *qpd)
 196 {
 197         struct kfd_process_device *pdd;
 198         unsigned int temp;
 199 
 200         pdd = qpd_to_pdd(qpd);
 201 
 202         /* check if sh_mem_config register already configured */
 203         if (qpd->sh_mem_config == 0) {
 204                 qpd->sh_mem_config =
 205                                 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
 206                                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
 207                                 MTYPE_UC <<
 208                                         SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
 209                                 MTYPE_UC <<
 210                                         SH_MEM_CONFIG__APE1_MTYPE__SHIFT;
 211 
 212                 qpd->sh_mem_ape1_limit = 0;
 213                 qpd->sh_mem_ape1_base = 0;
 214         }
 215 
 216         /* On dGPU we're always in GPUVM64 addressing mode with 64-bit
 217          * aperture addresses.
 218          */
 219         temp = get_sh_mem_bases_nybble_64(pdd);
 220         qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
 221 
 222         pr_debug("sh_mem_bases nybble: 0x%X and register 0x%X\n",
 223                 temp, qpd->sh_mem_bases);
 224 
 225         return 0;
 226 }
 227 
 228 static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
 229                                 struct qcm_process_device *qpd)
 230 {
 231         uint32_t value = (1 << SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT);
 232 
 233         if (q->process->is_32bit_user_mode)
 234                 value |= (1 << SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT) |
 235                                 get_sh_mem_bases_32(qpd_to_pdd(qpd));
 236         else
 237                 value |= ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
 238                                 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &
 239                                 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
 240 
 241         q->properties.sdma_vm_addr = value;
 242 }
 243 
 244 static void init_sdma_vm_tonga(struct device_queue_manager *dqm,
 245                         struct queue *q,
 246                         struct qcm_process_device *qpd)
 247 {
 248         /* On dGPU we're always in GPUVM64 addressing mode with 64-bit
 249          * aperture addresses.
 250          */
 251         q->properties.sdma_vm_addr =
 252                 ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
 253                  SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &
 254                 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
 255 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c

DEFINITIONS
