arch/arm64/include/asm/ptrace.h

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This source file includes following definitions.
compat_psr_to_pstate
pstate_to_compat_psr
in_syscall
forget_syscall
user_stack_pointer
regs_get_register
pt_regs_read_reg
pt_regs_write_reg
kernel_stack_pointer
regs_return_value
regs_set_return_value
regs_get_kernel_argument
instruction_pointer
instruction_pointer_set
frame_pointer
procedure_link_pointer_set
   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Based on arch/arm/include/asm/ptrace.h
   4  *
   5  * Copyright (C) 1996-2003 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8 #ifndef __ASM_PTRACE_H
   9 #define __ASM_PTRACE_H
  10 
  11 #include <asm/cpufeature.h>
  12 
  13 #include <uapi/asm/ptrace.h>
  14 
  15 /* Current Exception Level values, as contained in CurrentEL */
  16 #define CurrentEL_EL1           (1 << 2)
  17 #define CurrentEL_EL2           (2 << 2)
  18 
  19 /*
  20  * PMR values used to mask/unmask interrupts.
  21  *
  22  * GIC priority masking works as follows: if an IRQ's priority is a higher value
  23  * than the value held in PMR, that IRQ is masked. Lowering the value of PMR
  24  * means masking more IRQs (or at least that the same IRQs remain masked).
  25  *
  26  * To mask interrupts, we clear the most significant bit of PMR.
  27  *
  28  * Some code sections either automatically switch back to PSR.I or explicitly
  29  * require to not use priority masking. If bit GIC_PRIO_PSR_I_SET is included
  30  * in the  the priority mask, it indicates that PSR.I should be set and
  31  * interrupt disabling temporarily does not rely on IRQ priorities.
  32  */
  33 #define GIC_PRIO_IRQON                  0xe0
  34 #define GIC_PRIO_IRQOFF                 (GIC_PRIO_IRQON & ~0x80)
  35 #define GIC_PRIO_PSR_I_SET              (1 << 4)
  36 
  37 /* Additional SPSR bits not exposed in the UABI */
  38 #define PSR_IL_BIT              (1 << 20)
  39 
  40 /* AArch32-specific ptrace requests */
  41 #define COMPAT_PTRACE_GETREGS           12
  42 #define COMPAT_PTRACE_SETREGS           13
  43 #define COMPAT_PTRACE_GET_THREAD_AREA   22
  44 #define COMPAT_PTRACE_SET_SYSCALL       23
  45 #define COMPAT_PTRACE_GETVFPREGS        27
  46 #define COMPAT_PTRACE_SETVFPREGS        28
  47 #define COMPAT_PTRACE_GETHBPREGS        29
  48 #define COMPAT_PTRACE_SETHBPREGS        30
  49 
  50 /* SPSR_ELx bits for exceptions taken from AArch32 */
  51 #define PSR_AA32_MODE_MASK      0x0000001f
  52 #define PSR_AA32_MODE_USR       0x00000010
  53 #define PSR_AA32_MODE_FIQ       0x00000011
  54 #define PSR_AA32_MODE_IRQ       0x00000012
  55 #define PSR_AA32_MODE_SVC       0x00000013
  56 #define PSR_AA32_MODE_ABT       0x00000017
  57 #define PSR_AA32_MODE_HYP       0x0000001a
  58 #define PSR_AA32_MODE_UND       0x0000001b
  59 #define PSR_AA32_MODE_SYS       0x0000001f
  60 #define PSR_AA32_T_BIT          0x00000020
  61 #define PSR_AA32_F_BIT          0x00000040
  62 #define PSR_AA32_I_BIT          0x00000080
  63 #define PSR_AA32_A_BIT          0x00000100
  64 #define PSR_AA32_E_BIT          0x00000200
  65 #define PSR_AA32_PAN_BIT        0x00400000
  66 #define PSR_AA32_SSBS_BIT       0x00800000
  67 #define PSR_AA32_DIT_BIT        0x01000000
  68 #define PSR_AA32_Q_BIT          0x08000000
  69 #define PSR_AA32_V_BIT          0x10000000
  70 #define PSR_AA32_C_BIT          0x20000000
  71 #define PSR_AA32_Z_BIT          0x40000000
  72 #define PSR_AA32_N_BIT          0x80000000
  73 #define PSR_AA32_IT_MASK        0x0600fc00      /* If-Then execution state mask */
  74 #define PSR_AA32_GE_MASK        0x000f0000
  75 
  76 #ifdef CONFIG_CPU_BIG_ENDIAN
  77 #define PSR_AA32_ENDSTATE       PSR_AA32_E_BIT
  78 #else
  79 #define PSR_AA32_ENDSTATE       0
  80 #endif
  81 
  82 /* AArch32 CPSR bits, as seen in AArch32 */
  83 #define COMPAT_PSR_DIT_BIT      0x00200000
  84 
  85 /*
  86  * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
  87  * process is located in memory.
  88  */
  89 #define COMPAT_PT_TEXT_ADDR             0x10000
  90 #define COMPAT_PT_DATA_ADDR             0x10004
  91 #define COMPAT_PT_TEXT_END_ADDR         0x10008
  92 
  93 /*
  94  * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
  95  * a syscall -- i.e., its most recent entry into the kernel from
  96  * userspace was not via SVC, or otherwise a tracer cancelled the syscall.
  97  *
  98  * This must have the value -1, for ABI compatibility with ptrace etc.
  99  */
 100 #define NO_SYSCALL (-1)
 101 
 102 #ifndef __ASSEMBLY__
 103 #include <linux/bug.h>
 104 #include <linux/types.h>
 105 
 106 /* sizeof(struct user) for AArch32 */
 107 #define COMPAT_USER_SZ  296
 108 
 109 /* Architecturally defined mapping between AArch32 and AArch64 registers */
 110 #define compat_usr(x)   regs[(x)]
 111 #define compat_fp       regs[11]
 112 #define compat_sp       regs[13]
 113 #define compat_lr       regs[14]
 114 #define compat_sp_hyp   regs[15]
 115 #define compat_lr_irq   regs[16]
 116 #define compat_sp_irq   regs[17]
 117 #define compat_lr_svc   regs[18]
 118 #define compat_sp_svc   regs[19]
 119 #define compat_lr_abt   regs[20]
 120 #define compat_sp_abt   regs[21]
 121 #define compat_lr_und   regs[22]
 122 #define compat_sp_und   regs[23]
 123 #define compat_r8_fiq   regs[24]
 124 #define compat_r9_fiq   regs[25]
 125 #define compat_r10_fiq  regs[26]
 126 #define compat_r11_fiq  regs[27]
 127 #define compat_r12_fiq  regs[28]
 128 #define compat_sp_fiq   regs[29]
 129 #define compat_lr_fiq   regs[30]
 130 
 131 static inline unsigned long compat_psr_to_pstate(const unsigned long psr)
 132 {
 133         unsigned long pstate;
 134 
 135         pstate = psr & ~COMPAT_PSR_DIT_BIT;
 136 
 137         if (psr & COMPAT_PSR_DIT_BIT)
 138                 pstate |= PSR_AA32_DIT_BIT;
 139 
 140         return pstate;
 141 }
 142 
 143 static inline unsigned long pstate_to_compat_psr(const unsigned long pstate)
 144 {
 145         unsigned long psr;
 146 
 147         psr = pstate & ~PSR_AA32_DIT_BIT;
 148 
 149         if (pstate & PSR_AA32_DIT_BIT)
 150                 psr |= COMPAT_PSR_DIT_BIT;
 151 
 152         return psr;
 153 }
 154 
 155 /*
 156  * This struct defines the way the registers are stored on the stack during an
 157  * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
 158  * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
 159  */
 160 struct pt_regs {
 161         union {
 162                 struct user_pt_regs user_regs;
 163                 struct {
 164                         u64 regs[31];
 165                         u64 sp;
 166                         u64 pc;
 167                         u64 pstate;
 168                 };
 169         };
 170         u64 orig_x0;
 171 #ifdef __AARCH64EB__
 172         u32 unused2;
 173         s32 syscallno;
 174 #else
 175         s32 syscallno;
 176         u32 unused2;
 177 #endif
 178 
 179         u64 orig_addr_limit;
 180         /* Only valid when ARM64_HAS_IRQ_PRIO_MASKING is enabled. */
 181         u64 pmr_save;
 182         u64 stackframe[2];
 183 };
 184 
 185 static inline bool in_syscall(struct pt_regs const *regs)
 186 {
 187         return regs->syscallno != NO_SYSCALL;
 188 }
 189 
 190 static inline void forget_syscall(struct pt_regs *regs)
 191 {
 192         regs->syscallno = NO_SYSCALL;
 193 }
 194 
 195 #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate)
 196 
 197 #define arch_has_single_step()  (1)
 198 
 199 #ifdef CONFIG_COMPAT
 200 #define compat_thumb_mode(regs) \
 201         (((regs)->pstate & PSR_AA32_T_BIT))
 202 #else
 203 #define compat_thumb_mode(regs) (0)
 204 #endif
 205 
 206 #define user_mode(regs) \
 207         (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
 208 
 209 #define compat_user_mode(regs)  \
 210         (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
 211          (PSR_MODE32_BIT | PSR_MODE_EL0t))
 212 
 213 #define processor_mode(regs) \
 214         ((regs)->pstate & PSR_MODE_MASK)
 215 
 216 #define irqs_priority_unmasked(regs)                                    \
 217         (system_uses_irq_prio_masking() ?                               \
 218                 (regs)->pmr_save == GIC_PRIO_IRQON :                    \
 219                 true)
 220 
 221 #define interrupts_enabled(regs)                        \
 222         (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
 223 
 224 #define fast_interrupts_enabled(regs) \
 225         (!((regs)->pstate & PSR_F_BIT))
 226 
 227 static inline unsigned long user_stack_pointer(struct pt_regs *regs)
 228 {
 229         if (compat_user_mode(regs))
 230                 return regs->compat_sp;
 231         return regs->sp;
 232 }
 233 
 234 extern int regs_query_register_offset(const char *name);
 235 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
 236                                                unsigned int n);
 237 
 238 /**
 239  * regs_get_register() - get register value from its offset
 240  * @regs:       pt_regs from which register value is gotten
 241  * @offset:     offset of the register.
 242  *
 243  * regs_get_register returns the value of a register whose offset from @regs.
 244  * The @offset is the offset of the register in struct pt_regs.
 245  * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
 246  */
 247 static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset)
 248 {
 249         u64 val = 0;
 250 
 251         WARN_ON(offset & 7);
 252 
 253         offset >>= 3;
 254         switch (offset) {
 255         case 0 ... 30:
 256                 val = regs->regs[offset];
 257                 break;
 258         case offsetof(struct pt_regs, sp) >> 3:
 259                 val = regs->sp;
 260                 break;
 261         case offsetof(struct pt_regs, pc) >> 3:
 262                 val = regs->pc;
 263                 break;
 264         case offsetof(struct pt_regs, pstate) >> 3:
 265                 val = regs->pstate;
 266                 break;
 267         default:
 268                 val = 0;
 269         }
 270 
 271         return val;
 272 }
 273 
 274 /*
 275  * Read a register given an architectural register index r.
 276  * This handles the common case where 31 means XZR, not SP.
 277  */
 278 static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r)
 279 {
 280         return (r == 31) ? 0 : regs->regs[r];
 281 }
 282 
 283 /*
 284  * Write a register given an architectural register index r.
 285  * This handles the common case where 31 means XZR, not SP.
 286  */
 287 static inline void pt_regs_write_reg(struct pt_regs *regs, int r,
 288                                      unsigned long val)
 289 {
 290         if (r != 31)
 291                 regs->regs[r] = val;
 292 }
 293 
 294 /* Valid only for Kernel mode traps. */
 295 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
 296 {
 297         return regs->sp;
 298 }
 299 
 300 static inline unsigned long regs_return_value(struct pt_regs *regs)
 301 {
 302         return regs->regs[0];
 303 }
 304 
 305 static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
 306 {
 307         regs->regs[0] = rc;
 308 }
 309 
 310 /**
 311  * regs_get_kernel_argument() - get Nth function argument in kernel
 312  * @regs:       pt_regs of that context
 313  * @n:          function argument number (start from 0)
 314  *
 315  * regs_get_argument() returns @n th argument of the function call.
 316  *
 317  * Note that this chooses the most likely register mapping. In very rare
 318  * cases this may not return correct data, for example, if one of the
 319  * function parameters is 16 bytes or bigger. In such cases, we cannot
 320  * get access the parameter correctly and the register assignment of
 321  * subsequent parameters will be shifted.
 322  */
 323 static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs,
 324                                                      unsigned int n)
 325 {
 326 #define NR_REG_ARGUMENTS 8
 327         if (n < NR_REG_ARGUMENTS)
 328                 return pt_regs_read_reg(regs, n);
 329         return 0;
 330 }
 331 
 332 /* We must avoid circular header include via sched.h */
 333 struct task_struct;
 334 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task);
 335 
 336 static inline unsigned long instruction_pointer(struct pt_regs *regs)
 337 {
 338         return regs->pc;
 339 }
 340 static inline void instruction_pointer_set(struct pt_regs *regs,
 341                 unsigned long val)
 342 {
 343         regs->pc = val;
 344 }
 345 
 346 static inline unsigned long frame_pointer(struct pt_regs *regs)
 347 {
 348         return regs->regs[29];
 349 }
 350 
 351 #define procedure_link_pointer(regs)    ((regs)->regs[30])
 352 
 353 static inline void procedure_link_pointer_set(struct pt_regs *regs,
 354                                            unsigned long val)
 355 {
 356         procedure_link_pointer(regs) = val;
 357 }
 358 
 359 extern unsigned long profile_pc(struct pt_regs *regs);
 360 
 361 #endif /* __ASSEMBLY__ */
 362 #endif
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root/arch/arm64/include/asm/ptrace.h

INCLUDED FROM

DEFINITIONS
