This source file includes following definitions.
- device_queue_manager_init_v10_navi10
- compute_sh_mem_bases_64bit
- update_qpd_v10
- init_sdma_vm_v10
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24 #include "kfd_device_queue_manager.h"
25 #include "navi10_enum.h"
26 #include "gc/gc_10_1_0_offset.h"
27 #include "gc/gc_10_1_0_sh_mask.h"
28
29 static int update_qpd_v10(struct device_queue_manager *dqm,
30 struct qcm_process_device *qpd);
31 static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
32 struct qcm_process_device *qpd);
33
34 void device_queue_manager_init_v10_navi10(
35 struct device_queue_manager_asic_ops *asic_ops)
36 {
37 asic_ops->update_qpd = update_qpd_v10;
38 asic_ops->init_sdma_vm = init_sdma_vm_v10;
39 asic_ops->mqd_manager_init = mqd_manager_init_v10;
40 }
41
42 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
43 {
44 uint32_t shared_base = pdd->lds_base >> 48;
45 uint32_t private_base = pdd->scratch_base >> 48;
46
47 return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
48 private_base;
49 }
50
51 static int update_qpd_v10(struct device_queue_manager *dqm,
52 struct qcm_process_device *qpd)
53 {
54 struct kfd_process_device *pdd;
55
56 pdd = qpd_to_pdd(qpd);
57
58
59 if (qpd->sh_mem_config == 0) {
60 qpd->sh_mem_config =
61 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
62 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
63 #if 0
64
65
66
67 if (vega10_noretry)
68 qpd->sh_mem_config |=
69 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
70 #endif
71
72 qpd->sh_mem_ape1_limit = 0;
73 qpd->sh_mem_ape1_base = 0;
74 }
75
76 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
77
78 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
79
80 return 0;
81 }
82
83 static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
84 struct qcm_process_device *qpd)
85 {
86
87 q->properties.sdma_vm_addr = 0;
88 }