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24 #ifndef KFD_PM4_HEADERS_H_
25 #define KFD_PM4_HEADERS_H_
26
27 #ifndef PM4_MES_HEADER_DEFINED
28 #define PM4_MES_HEADER_DEFINED
29 union PM4_MES_TYPE_3_HEADER {
30 struct {
31
32 uint32_t reserved1:8;
33
34 uint32_t opcode:8;
35
36 uint32_t count:14;
37
38 uint32_t type:2;
39 };
40 uint32_t u32all;
41 };
42 #endif
43
44
45
46
47 #ifndef PM4_MES_MAP_PROCESS_DEFINED
48 #define PM4_MES_MAP_PROCESS_DEFINED
49
50 struct pm4_map_process {
51 union {
52 union PM4_MES_TYPE_3_HEADER header;
53 uint32_t ordinal1;
54 };
55
56 union {
57 struct {
58 uint32_t pasid:16;
59 uint32_t reserved1:8;
60 uint32_t diq_enable:1;
61 uint32_t process_quantum:7;
62 } bitfields2;
63 uint32_t ordinal2;
64 };
65
66 union {
67 struct {
68 uint32_t page_table_base:28;
69 uint32_t reserved3:4;
70 } bitfields3;
71 uint32_t ordinal3;
72 };
73
74 uint32_t sh_mem_bases;
75 uint32_t sh_mem_ape1_base;
76 uint32_t sh_mem_ape1_limit;
77 uint32_t sh_mem_config;
78 uint32_t gds_addr_lo;
79 uint32_t gds_addr_hi;
80
81 union {
82 struct {
83 uint32_t num_gws:6;
84 uint32_t reserved4:2;
85 uint32_t num_oac:4;
86 uint32_t reserved5:4;
87 uint32_t gds_size:6;
88 uint32_t num_queues:10;
89 } bitfields10;
90 uint32_t ordinal10;
91 };
92
93 };
94 #endif
95
96 #ifndef PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH
97 #define PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH
98
99 struct pm4_map_process_scratch_kv {
100 union {
101 union PM4_MES_TYPE_3_HEADER header;
102 uint32_t ordinal1;
103 };
104
105 union {
106 struct {
107 uint32_t pasid:16;
108 uint32_t reserved1:8;
109 uint32_t diq_enable:1;
110 uint32_t process_quantum:7;
111 } bitfields2;
112 uint32_t ordinal2;
113 };
114
115 union {
116 struct {
117 uint32_t page_table_base:28;
118 uint32_t reserved2:4;
119 } bitfields3;
120 uint32_t ordinal3;
121 };
122
123 uint32_t reserved3;
124 uint32_t sh_mem_bases;
125 uint32_t sh_mem_config;
126 uint32_t sh_mem_ape1_base;
127 uint32_t sh_mem_ape1_limit;
128 uint32_t sh_hidden_private_base_vmid;
129 uint32_t reserved4;
130 uint32_t reserved5;
131 uint32_t gds_addr_lo;
132 uint32_t gds_addr_hi;
133
134 union {
135 struct {
136 uint32_t num_gws:6;
137 uint32_t reserved6:2;
138 uint32_t num_oac:4;
139 uint32_t reserved7:4;
140 uint32_t gds_size:6;
141 uint32_t num_queues:10;
142 } bitfields14;
143 uint32_t ordinal14;
144 };
145
146 uint32_t completion_signal_lo32;
147 uint32_t completion_signal_hi32;
148 };
149 #endif
150
151 enum {
152 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
153 };
154
155 #endif