root/drivers/gpu/drm/amd/amdkfd/cik_regs.h

INCLUDED FROM

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 #ifndef CIK_REGS_H
  24 #define CIK_REGS_H
  25 
  26 /* if PTR32, these are the bases for scratch and lds */
  27 #define PRIVATE_BASE(x)                                 ((x) << 0) /* scratch */
  28 #define SHARED_BASE(x)                                  ((x) << 16) /* LDS */
  29 #define PTR32                                           (1 << 0)
  30 #define ALIGNMENT_MODE(x)                               ((x) << 2)
  31 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED                 3
  32 #define DEFAULT_MTYPE(x)                                ((x) << 4)
  33 #define APE1_MTYPE(x)                                   ((x) << 7)
  34 
  35 /* valid for both DEFAULT_MTYPE and APE1_MTYPE */
  36 #define MTYPE_CACHED_NV                                 0
  37 #define MTYPE_CACHED                                    1
  38 #define MTYPE_NONCACHED                                 3
  39 
  40 #define DEFAULT_CP_HQD_PERSISTENT_STATE                 (0x33U << 8)
  41 #define PRELOAD_REQ                                     (1 << 0)
  42 
  43 #define MQD_CONTROL_PRIV_STATE_EN                       (1U << 8)
  44 
  45 #define DEFAULT_MIN_IB_AVAIL_SIZE                       (3U << 20)
  46 
  47 #define IB_ATC_EN                                       (1U << 23)
  48 
  49 #define QUANTUM_EN                                      1U
  50 #define QUANTUM_SCALE_1MS                               (1U << 4)
  51 #define QUANTUM_DURATION(x)                             ((x) << 8)
  52 
  53 #define RPTR_BLOCK_SIZE(x)                              ((x) << 8)
  54 #define MIN_AVAIL_SIZE(x)                               ((x) << 20)
  55 #define DEFAULT_RPTR_BLOCK_SIZE                         RPTR_BLOCK_SIZE(5)
  56 #define DEFAULT_MIN_AVAIL_SIZE                          MIN_AVAIL_SIZE(3)
  57 
  58 #define PQ_ATC_EN                                       (1 << 23)
  59 #define NO_UPDATE_RPTR                                  (1 << 27)
  60 
  61 #define DOORBELL_OFFSET(x)                              ((x) << 2)
  62 #define DOORBELL_EN                                     (1 << 30)
  63 
  64 #define PRIV_STATE                                      (1 << 30)
  65 #define KMD_QUEUE                                       (1 << 31)
  66 
  67 #define AQL_ENABLE                                      1
  68 
  69 #define GRBM_GFX_INDEX                                  0x30800
  70 
  71 #endif