root/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c

DEFINITIONS

1. allocate_hiq_mqd
2. allocate_sdma_mqd
3. free_mqd_hiq_sdma
4. mqd_symmetrically_map_cu_mask

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 
  24 #include "kfd_mqd_manager.h"
  25 #include "amdgpu_amdkfd.h"
  26 #include "kfd_device_queue_manager.h"
  27 
  28 /* Mapping queue priority to pipe priority, indexed by queue priority */
  29 int pipe_priority_map[] = {
  30         KFD_PIPE_PRIORITY_CS_LOW,
  31         KFD_PIPE_PRIORITY_CS_LOW,
  32         KFD_PIPE_PRIORITY_CS_LOW,
  33         KFD_PIPE_PRIORITY_CS_LOW,
  34         KFD_PIPE_PRIORITY_CS_LOW,
  35         KFD_PIPE_PRIORITY_CS_LOW,
  36         KFD_PIPE_PRIORITY_CS_LOW,
  37         KFD_PIPE_PRIORITY_CS_MEDIUM,
  38         KFD_PIPE_PRIORITY_CS_MEDIUM,
  39         KFD_PIPE_PRIORITY_CS_MEDIUM,
  40         KFD_PIPE_PRIORITY_CS_MEDIUM,
  41         KFD_PIPE_PRIORITY_CS_HIGH,
  42         KFD_PIPE_PRIORITY_CS_HIGH,
  43         KFD_PIPE_PRIORITY_CS_HIGH,
  44         KFD_PIPE_PRIORITY_CS_HIGH,
  45         KFD_PIPE_PRIORITY_CS_HIGH
  46 };
  47 
  48 struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_dev *dev, struct queue_properties *q)
  49 {
  50         struct kfd_mem_obj *mqd_mem_obj = NULL;
  51 
  52         mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
  53         if (!mqd_mem_obj)
  54                 return NULL;
  55 
  56         mqd_mem_obj->gtt_mem = dev->dqm->hiq_sdma_mqd.gtt_mem;
  57         mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr;
  58         mqd_mem_obj->cpu_ptr = dev->dqm->hiq_sdma_mqd.cpu_ptr;
  59 
  60         return mqd_mem_obj;
  61 }
  62 
  63 struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_dev *dev,
  64                                         struct queue_properties *q)
  65 {
  66         struct kfd_mem_obj *mqd_mem_obj = NULL;
  67         uint64_t offset;
  68 
  69         mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
  70         if (!mqd_mem_obj)
  71                 return NULL;
  72 
  73         offset = (q->sdma_engine_id *
  74                 dev->device_info->num_sdma_queues_per_engine +
  75                 q->sdma_queue_id) *
  76                 dev->dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size;
  77 
  78         offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
  79 
  80         mqd_mem_obj->gtt_mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.gtt_mem
  81                                 + offset);
  82         mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;
  83         mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t)
  84                                 dev->dqm->hiq_sdma_mqd.cpu_ptr + offset);
  85 
  86         return mqd_mem_obj;
  87 }
  88 
  89 void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd,
  90                         struct kfd_mem_obj *mqd_mem_obj)
  91 {
  92         WARN_ON(!mqd_mem_obj->gtt_mem);
  93         kfree(mqd_mem_obj);
  94 }
  95 
  96 void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
  97                 const uint32_t *cu_mask, uint32_t cu_mask_count,
  98                 uint32_t *se_mask)
  99 {
 100         struct kfd_cu_info cu_info;
 101         uint32_t cu_per_se[KFD_MAX_NUM_SE] = {0};
 102         int i, se, sh, cu = 0;
 103 
 104         amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info);
 105 
 106         if (cu_mask_count > cu_info.cu_active_number)
 107                 cu_mask_count = cu_info.cu_active_number;
 108 
 109         for (se = 0; se < cu_info.num_shader_engines; se++)
 110                 for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
 111                         cu_per_se[se] += hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]);
 112 
 113         /* Symmetrically map cu_mask to all SEs:
 114          * cu_mask[0] bit0 -> se_mask[0] bit0;
 115          * cu_mask[0] bit1 -> se_mask[1] bit0;
 116          * ... (if # SE is 4)
 117          * cu_mask[0] bit4 -> se_mask[0] bit1;
 118          * ...
 119          */
 120         se = 0;
 121         for (i = 0; i < cu_mask_count; i++) {
 122                 if (cu_mask[i / 32] & (1 << (i % 32)))
 123                         se_mask[se] |= 1 << cu;
 124 
 125                 do {
 126                         se++;
 127                         if (se == cu_info.num_shader_engines) {
 128                                 se = 0;
 129                                 cu++;
 130                         }
 131                 } while (cu >= cu_per_se[se] && cu < 32);
 132         }
 133 }