root/drivers/gpu/drm/amd/display/include/dpcd_defs.h

INCLUDED FROM

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DAL_DPCD_DEFS_H__
  27 #define __DAL_DPCD_DEFS_H__
  28 
  29 #include <drm/drm_dp_helper.h>
  30 #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h
  31 #define DP_SINK_HW_REVISION_START 0x409
  32 #endif
  33 
  34 enum dpcd_revision {
  35         DPCD_REV_10 = 0x10,
  36         DPCD_REV_11 = 0x11,
  37         DPCD_REV_12 = 0x12,
  38         DPCD_REV_13 = 0x13,
  39         DPCD_REV_14 = 0x14
  40 };
  41 
  42 /* these are the types stored at DOWNSTREAMPORT_PRESENT */
  43 enum dpcd_downstream_port_type {
  44         DOWNSTREAM_DP = 0,
  45         DOWNSTREAM_VGA,
  46         DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */
  47         DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
  48 };
  49 
  50 enum dpcd_link_test_patterns {
  51         LINK_TEST_PATTERN_NONE = 0,
  52         LINK_TEST_PATTERN_COLOR_RAMP,
  53         LINK_TEST_PATTERN_VERTICAL_BARS,
  54         LINK_TEST_PATTERN_COLOR_SQUARES
  55 };
  56 
  57 enum dpcd_test_color_format {
  58         TEST_COLOR_FORMAT_RGB = 0,
  59         TEST_COLOR_FORMAT_YCBCR422,
  60         TEST_COLOR_FORMAT_YCBCR444
  61 };
  62 
  63 enum dpcd_test_bit_depth {
  64         TEST_BIT_DEPTH_6 = 0,
  65         TEST_BIT_DEPTH_8,
  66         TEST_BIT_DEPTH_10,
  67         TEST_BIT_DEPTH_12,
  68         TEST_BIT_DEPTH_16
  69 };
  70 
  71 /* PHY (encoder) test patterns
  72 The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
  73 */
  74 enum dpcd_phy_test_patterns {
  75         PHY_TEST_PATTERN_NONE = 0,
  76         PHY_TEST_PATTERN_D10_2,
  77         PHY_TEST_PATTERN_SYMBOL_ERROR,
  78         PHY_TEST_PATTERN_PRBS7,
  79         PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
  80         PHY_TEST_PATTERN_CP2520_1,
  81         PHY_TEST_PATTERN_CP2520_2,
  82         PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */
  83 };
  84 
  85 enum dpcd_test_dyn_range {
  86         TEST_DYN_RANGE_VESA = 0,
  87         TEST_DYN_RANGE_CEA
  88 };
  89 
  90 enum dpcd_audio_test_pattern {
  91         AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
  92         AUDIO_TEST_PATTERN_SAWTOOTH
  93 };
  94 
  95 enum dpcd_audio_sampling_rate {
  96         AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
  97         AUDIO_SAMPLING_RATE_44_1KHZ,
  98         AUDIO_SAMPLING_RATE_48KHZ,
  99         AUDIO_SAMPLING_RATE_88_2KHZ,
 100         AUDIO_SAMPLING_RATE_96KHZ,
 101         AUDIO_SAMPLING_RATE_176_4KHZ,
 102         AUDIO_SAMPLING_RATE_192KHZ
 103 };
 104 
 105 enum dpcd_audio_channels {
 106         AUDIO_CHANNELS_1 = 0,/* direct HW translation */
 107         AUDIO_CHANNELS_2,
 108         AUDIO_CHANNELS_3,
 109         AUDIO_CHANNELS_4,
 110         AUDIO_CHANNELS_5,
 111         AUDIO_CHANNELS_6,
 112         AUDIO_CHANNELS_7,
 113         AUDIO_CHANNELS_8,
 114 
 115         AUDIO_CHANNELS_COUNT
 116 };
 117 
 118 enum dpcd_audio_test_pattern_periods {
 119         DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
 120         DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
 121         DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
 122         DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
 123         DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
 124         DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
 125         DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
 126         DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
 127         DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
 128         DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
 129         DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
 130 };
 131 
 132 /* This enum is for programming DPCD TRAINING_PATTERN_SET */
 133 enum dpcd_training_patterns {
 134         DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
 135         DPCD_TRAINING_PATTERN_1,
 136         DPCD_TRAINING_PATTERN_2,
 137         DPCD_TRAINING_PATTERN_3,
 138         DPCD_TRAINING_PATTERN_4 = 7
 139 };
 140 
 141 /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
 142 It defines the possible PSR states. */
 143 enum dpcd_psr_sink_states {
 144         PSR_SINK_STATE_INACTIVE = 0,
 145         PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
 146         PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
 147         PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
 148         PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
 149         PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
 150 };
 151 
 152 #endif /* __DAL_DPCD_DEFS_H__ */