1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 #ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__
27 #define __DAL_GRPH_OBJECT_CTRL_DEFS_H__
28
29 #include "grph_object_defs.h"
30
31
32
33
34
35
36
37
38
39
40
41
42 enum display_output_bit_depth {
43 PANEL_UNDEFINE = 0,
44 PANEL_6BIT_COLOR = 1,
45 PANEL_8BIT_COLOR = 2,
46 PANEL_10BIT_COLOR = 3,
47 PANEL_12BIT_COLOR = 4,
48 PANEL_16BIT_COLOR = 5,
49 };
50
51
52
53 enum dal_device_type {
54 DEVICE_TYPE_UNKNOWN = 0,
55 DEVICE_TYPE_LCD,
56 DEVICE_TYPE_CRT,
57 DEVICE_TYPE_DFP,
58 DEVICE_TYPE_CV,
59 DEVICE_TYPE_TV,
60 DEVICE_TYPE_CF,
61 DEVICE_TYPE_WIRELESS
62 };
63
64
65 struct device_id {
66 enum dal_device_type device_type:16;
67 uint32_t enum_id:16;
68 uint16_t raw_device_tag;
69 };
70
71 struct graphics_object_i2c_info {
72 struct gpio_info {
73 uint32_t clk_mask_register_index;
74 uint32_t clk_en_register_index;
75 uint32_t clk_y_register_index;
76 uint32_t clk_a_register_index;
77 uint32_t data_mask_register_index;
78 uint32_t data_en_register_index;
79 uint32_t data_y_register_index;
80 uint32_t data_a_register_index;
81
82 uint32_t clk_mask_shift;
83 uint32_t clk_en_shift;
84 uint32_t clk_y_shift;
85 uint32_t clk_a_shift;
86 uint32_t data_mask_shift;
87 uint32_t data_en_shift;
88 uint32_t data_y_shift;
89 uint32_t data_a_shift;
90 } gpio_info;
91
92 bool i2c_hw_assist;
93 uint32_t i2c_line;
94 uint32_t i2c_engine_id;
95 uint32_t i2c_slave_address;
96 };
97
98 struct graphics_object_hpd_info {
99 uint8_t hpd_int_gpio_uid;
100 uint8_t hpd_active;
101 };
102
103 struct connector_device_tag_info {
104 uint32_t acpi_device;
105 struct device_id dev_id;
106 };
107
108 struct device_timing {
109 struct misc_info {
110 uint32_t HORIZONTAL_CUT_OFF:1;
111
112 uint32_t H_SYNC_POLARITY:1;
113
114 uint32_t V_SYNC_POLARITY:1;
115 uint32_t VERTICAL_CUT_OFF:1;
116 uint32_t H_REPLICATION_BY2:1;
117 uint32_t V_REPLICATION_BY2:1;
118 uint32_t COMPOSITE_SYNC:1;
119 uint32_t INTERLACE:1;
120 uint32_t DOUBLE_CLOCK:1;
121 uint32_t RGB888:1;
122 uint32_t GREY_LEVEL:2;
123 uint32_t SPATIAL:1;
124 uint32_t TEMPORAL:1;
125 uint32_t API_ENABLED:1;
126 } misc_info;
127
128 uint32_t pixel_clk;
129 uint32_t horizontal_addressable;
130 uint32_t horizontal_blanking_time;
131 uint32_t vertical_addressable;
132 uint32_t vertical_blanking_time;
133 uint32_t horizontal_sync_offset;
134 uint32_t horizontal_sync_width;
135 uint32_t vertical_sync_offset;
136 uint32_t vertical_sync_width;
137 uint32_t horizontal_border;
138 uint32_t vertical_border;
139 };
140
141 struct supported_refresh_rate {
142 uint32_t REFRESH_RATE_30HZ:1;
143 uint32_t REFRESH_RATE_40HZ:1;
144 uint32_t REFRESH_RATE_48HZ:1;
145 uint32_t REFRESH_RATE_50HZ:1;
146 uint32_t REFRESH_RATE_60HZ:1;
147 };
148
149 struct embedded_panel_info {
150 struct device_timing lcd_timing;
151 uint32_t ss_id;
152 struct supported_refresh_rate supported_rr;
153 uint32_t drr_enabled;
154 uint32_t min_drr_refresh_rate;
155 bool realtek_eDPToLVDS;
156 };
157
158 struct dc_firmware_info {
159 struct pll_info {
160 uint32_t crystal_frequency;
161 uint32_t min_input_pxl_clk_pll_frequency;
162 uint32_t max_input_pxl_clk_pll_frequency;
163 uint32_t min_output_pxl_clk_pll_frequency;
164 uint32_t max_output_pxl_clk_pll_frequency;
165 } pll_info;
166
167 struct firmware_feature {
168 uint32_t memory_clk_ss_percentage;
169 uint32_t engine_clk_ss_percentage;
170 } feature;
171
172 uint32_t default_display_engine_pll_frequency;
173 uint32_t external_clock_source_frequency_for_dp;
174 uint32_t smu_gpu_pll_output_freq;
175 uint8_t min_allowed_bl_level;
176 uint8_t remote_display_config;
177 uint32_t default_memory_clk;
178 uint32_t default_engine_clk;
179 uint32_t dp_phy_ref_clk;
180 uint32_t i2c_engine_ref_clk;
181
182
183 };
184
185 struct step_and_delay_info {
186 uint32_t step;
187 uint32_t delay;
188 uint32_t recommended_ref_div;
189 };
190
191 struct spread_spectrum_info {
192 struct spread_spectrum_type {
193 bool CENTER_MODE:1;
194 bool EXTERNAL:1;
195 bool STEP_AND_DELAY_INFO:1;
196 } type;
197
198
199
200 uint32_t spread_spectrum_percentage;
201 uint32_t spread_percentage_divider;
202 uint32_t spread_spectrum_range;
203
204 union {
205 struct step_and_delay_info step_and_delay_info;
206
207
208
209 uint32_t target_clock_range;
210 };
211
212 };
213
214 struct graphics_object_encoder_cap_info {
215 uint32_t dp_hbr2_cap:1;
216 uint32_t dp_hbr2_validated:1;
217
218
219
220 uint32_t reserved:15;
221 };
222
223 struct din_connector_info {
224 uint32_t gpio_id;
225 bool gpio_tv_active_state;
226 };
227
228
229 enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 };
230
231
232
233
234 union ddi_channel_mapping {
235 struct mapping {
236 uint8_t lane0:2;
237 uint8_t lane1:2;
238 uint8_t lane2:2;
239 uint8_t lane3:2;
240 } mapping;
241 uint8_t raw;
242 };
243
244
245
246
247 struct transmitter_configuration_info {
248
249 enum transmitter transmitter_phy_id;
250
251 union ddi_channel_mapping output_channel_mapping;
252 };
253
254 struct transmitter_configuration {
255
256 struct transmitter_configuration_info primary_transmitter_config;
257
258 struct transmitter_configuration_info secondary_transmitter_config;
259 };
260
261
262 #define NUMBER_OF_UCHAR_FOR_GUID 16
263 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
264 #define NUMBER_OF_CSR_M3_ARB 10
265 #define NUMBER_OF_DISP_CLK_VOLTAGE 4
266 #define NUMBER_OF_AVAILABLE_SCLK 5
267
268 struct i2c_reg_info {
269 unsigned char i2c_reg_index;
270 unsigned char i2c_reg_val;
271 };
272
273 struct ext_hdmi_settings {
274 unsigned char slv_addr;
275 unsigned char reg_num;
276 struct i2c_reg_info reg_settings[9];
277 unsigned char reg_num_6g;
278 struct i2c_reg_info reg_settings_6g[3];
279 };
280
281
282
283 struct integrated_info {
284 struct clock_voltage_caps {
285
286
287 uint32_t voltage_index;
288
289 uint32_t max_supported_clk;
290 } disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE];
291
292 struct display_connection_info {
293 struct external_display_path {
294
295 uint32_t device_tag;
296
297 uint32_t device_acpi_enum;
298
299
300 struct graphics_object_id device_connector_id;
301
302 uint8_t ext_aux_ddc_lut_index;
303
304 uint8_t ext_hpd_pin_lut_index;
305
306 struct graphics_object_id ext_encoder_obj_id;
307
308 union ddi_channel_mapping channel_mapping;
309
310 unsigned short caps;
311 } path[MAX_NUMBER_OF_EXT_DISPLAY_PATH];
312
313 uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];
314 uint8_t checksum;
315 } ext_disp_conn_info;
316
317 struct available_s_clk_list {
318
319 uint32_t supported_s_clk;
320
321 uint32_t voltage_index;
322
323 uint32_t voltage_id;
324 } avail_s_clk[NUMBER_OF_AVAILABLE_SCLK];
325
326 uint8_t memory_type;
327 uint8_t ma_channel_number;
328 uint32_t boot_up_engine_clock;
329 uint32_t dentist_vco_freq;
330 uint32_t boot_up_uma_clock;
331 uint32_t boot_up_req_display_vector;
332 uint32_t other_display_misc;
333 uint32_t gpu_cap_info;
334 uint32_t sb_mmio_base_addr;
335 uint32_t system_config;
336 uint32_t cpu_cap_info;
337 uint32_t max_nb_voltage;
338 uint32_t min_nb_voltage;
339 uint32_t boot_up_nb_voltage;
340 uint32_t ext_disp_conn_info_offset;
341 uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB];
342 uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB];
343 uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB];
344 uint32_t gmc_restore_reset_time;
345 uint32_t minimum_n_clk;
346 uint32_t idle_n_clk;
347 uint32_t ddr_dll_power_up_time;
348 uint32_t ddr_pll_power_up_time;
349
350 uint32_t pcie_clk_ss_type;
351 uint32_t lvds_ss_percentage;
352 uint32_t lvds_sspread_rate_in_10hz;
353 uint32_t hdmi_ss_percentage;
354 uint32_t hdmi_sspread_rate_in_10hz;
355 uint32_t dvi_ss_percentage;
356 uint32_t dvi_sspread_rate_in_10_hz;
357 uint32_t sclk_dpm_boost_margin;
358 uint32_t sclk_dpm_throttle_margin;
359 uint32_t sclk_dpm_tdp_limit_pg;
360 uint32_t sclk_dpm_tdp_limit_boost;
361 uint32_t boost_engine_clock;
362 uint32_t boost_vid_2bit;
363 uint32_t enable_boost;
364 uint32_t gnb_tdp_limit;
365
366 uint32_t max_lvds_pclk_freq_in_single_link;
367 uint32_t lvds_misc;
368 uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms;
369 uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms;
370 uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms;
371 uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms;
372 uint32_t lvds_off_to_on_delay_in_4ms;
373 uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms;
374 uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms;
375 uint32_t lvds_reserved1;
376 uint32_t lvds_bit_depth_control_val;
377
378 unsigned char dp0_ext_hdmi_slv_addr;
379 unsigned char dp0_ext_hdmi_reg_num;
380 struct i2c_reg_info dp0_ext_hdmi_reg_settings[9];
381 unsigned char dp0_ext_hdmi_6g_reg_num;
382 struct i2c_reg_info dp0_ext_hdmi_6g_reg_settings[3];
383 unsigned char dp1_ext_hdmi_slv_addr;
384 unsigned char dp1_ext_hdmi_reg_num;
385 struct i2c_reg_info dp1_ext_hdmi_reg_settings[9];
386 unsigned char dp1_ext_hdmi_6g_reg_num;
387 struct i2c_reg_info dp1_ext_hdmi_6g_reg_settings[3];
388 unsigned char dp2_ext_hdmi_slv_addr;
389 unsigned char dp2_ext_hdmi_reg_num;
390 struct i2c_reg_info dp2_ext_hdmi_reg_settings[9];
391 unsigned char dp2_ext_hdmi_6g_reg_num;
392 struct i2c_reg_info dp2_ext_hdmi_6g_reg_settings[3];
393 unsigned char dp3_ext_hdmi_slv_addr;
394 unsigned char dp3_ext_hdmi_reg_num;
395 struct i2c_reg_info dp3_ext_hdmi_reg_settings[9];
396 unsigned char dp3_ext_hdmi_6g_reg_num;
397 struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3];
398
399 uint32_t dp_ss_control;
400 };
401
402
403
404
405 enum power_source {
406 POWER_SOURCE_AC = 0,
407 POWER_SOURCE_DC,
408 POWER_SOURCE_LIMITED_POWER,
409 POWER_SOURCE_LIMITED_POWER_2,
410 POWER_SOURCE_MAX
411 };
412
413 struct bios_event_info {
414 uint32_t thermal_state;
415 uint32_t backlight_level;
416 enum power_source powerSource;
417 bool has_thermal_state_changed;
418 bool has_power_source_changed;
419 bool has_forced_mode_changed;
420 bool forced_mode;
421 bool backlight_changed;
422 };
423
424
425
426
427
428 enum {
429 DFS_BYPASS_ENABLE = 0x10
430 };
431
432 enum {
433 INVALID_BACKLIGHT = -1
434 };
435
436 struct panel_backlight_boundaries {
437 uint32_t min_signal_level;
438 uint32_t max_signal_level;
439 };
440
441
442 #endif