root/drivers/gpu/drm/amd/display/include/link_service_types.h

INCLUDED FROM

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DAL_LINK_SERVICE_TYPES_H__
  27 #define __DAL_LINK_SERVICE_TYPES_H__
  28 
  29 #include "grph_object_id.h"
  30 #include "dal_types.h"
  31 #include "irq_types.h"
  32 
  33 /*struct mst_mgr_callback_object;*/
  34 struct ddc;
  35 struct irq_manager;
  36 
  37 enum {
  38         MAX_CONTROLLER_NUM = 6
  39 };
  40 
  41 enum dp_power_state {
  42         DP_POWER_STATE_D0 = 1,
  43         DP_POWER_STATE_D3
  44 };
  45 
  46 enum edp_revision {
  47         /* eDP version 1.1 or lower */
  48         EDP_REVISION_11 = 0x00,
  49         /* eDP version 1.2 */
  50         EDP_REVISION_12 = 0x01,
  51         /* eDP version 1.3 */
  52         EDP_REVISION_13 = 0x02
  53 };
  54 
  55 enum {
  56         LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
  57 };
  58 
  59 enum link_training_result {
  60         LINK_TRAINING_SUCCESS,
  61         LINK_TRAINING_CR_FAIL_LANE0,
  62         LINK_TRAINING_CR_FAIL_LANE1,
  63         LINK_TRAINING_CR_FAIL_LANE23,
  64         /* CR DONE bit is cleared during EQ step */
  65         LINK_TRAINING_EQ_FAIL_CR,
  66         /* other failure during EQ step */
  67         LINK_TRAINING_EQ_FAIL_EQ,
  68         LINK_TRAINING_LQA_FAIL,
  69 };
  70 
  71 struct link_training_settings {
  72         struct dc_link_settings link_settings;
  73         struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
  74 
  75         enum dc_voltage_swing *voltage_swing;
  76         enum dc_pre_emphasis *pre_emphasis;
  77         enum dc_post_cursor2 *post_cursor2;
  78 
  79         uint16_t cr_pattern_time;
  80         uint16_t eq_pattern_time;
  81         enum dc_dp_training_pattern pattern_for_eq;
  82 
  83         bool enhanced_framing;
  84         bool allow_invalid_msa_timing_param;
  85 };
  86 
  87 /*TODO: Move this enum test harness*/
  88 /* Test patterns*/
  89 enum dp_test_pattern {
  90         /* Input data is pass through Scrambler
  91          * and 8b10b Encoder straight to output*/
  92         DP_TEST_PATTERN_VIDEO_MODE = 0,
  93 
  94         /* phy test patterns*/
  95         DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
  96         DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
  97         DP_TEST_PATTERN_SYMBOL_ERROR,
  98         DP_TEST_PATTERN_PRBS7,
  99         DP_TEST_PATTERN_80BIT_CUSTOM,
 100         DP_TEST_PATTERN_CP2520_1,
 101         DP_TEST_PATTERN_CP2520_2,
 102         DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
 103         DP_TEST_PATTERN_CP2520_3,
 104 
 105         /* Link Training Patterns */
 106         DP_TEST_PATTERN_TRAINING_PATTERN1,
 107         DP_TEST_PATTERN_TRAINING_PATTERN2,
 108         DP_TEST_PATTERN_TRAINING_PATTERN3,
 109         DP_TEST_PATTERN_TRAINING_PATTERN4,
 110         DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4,
 111 
 112         /* link test patterns*/
 113         DP_TEST_PATTERN_COLOR_SQUARES,
 114         DP_TEST_PATTERN_COLOR_SQUARES_CEA,
 115         DP_TEST_PATTERN_VERTICAL_BARS,
 116         DP_TEST_PATTERN_HORIZONTAL_BARS,
 117         DP_TEST_PATTERN_COLOR_RAMP,
 118 
 119         /* audio test patterns*/
 120         DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
 121         DP_TEST_PATTERN_AUDIO_SAWTOOTH,
 122 
 123         DP_TEST_PATTERN_UNSUPPORTED
 124 };
 125 
 126 enum dp_panel_mode {
 127         /* not required */
 128         DP_PANEL_MODE_DEFAULT,
 129         /* standard mode for eDP */
 130         DP_PANEL_MODE_EDP,
 131         /* external chips specific settings */
 132         DP_PANEL_MODE_SPECIAL
 133 };
 134 
 135 /* DPCD_ADDR_TRAINING_LANEx_SET registers value */
 136 union dpcd_training_lane_set {
 137         struct {
 138 #if defined(LITTLEENDIAN_CPU)
 139                 uint8_t VOLTAGE_SWING_SET:2;
 140                 uint8_t MAX_SWING_REACHED:1;
 141                 uint8_t PRE_EMPHASIS_SET:2;
 142                 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
 143                 /* following is reserved in DP 1.1 */
 144                 uint8_t POST_CURSOR2_SET:2;
 145 #elif defined(BIGENDIAN_CPU)
 146                 uint8_t POST_CURSOR2_SET:2;
 147                 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
 148                 uint8_t PRE_EMPHASIS_SET:2;
 149                 uint8_t MAX_SWING_REACHED:1;
 150                 uint8_t VOLTAGE_SWING_SET:2;
 151 #else
 152         #error ARCH not defined!
 153 #endif
 154         } bits;
 155 
 156         uint8_t raw;
 157 };
 158 
 159 
 160 /* DP MST stream allocation (payload bandwidth number) */
 161 struct dp_mst_stream_allocation {
 162         uint8_t vcp_id;
 163         /* number of slots required for the DP stream in
 164          * transport packet */
 165         uint8_t slot_count;
 166 };
 167 
 168 /* DP MST stream allocation table */
 169 struct dp_mst_stream_allocation_table {
 170         /* number of DP video streams */
 171         int stream_count;
 172         /* array of stream allocations */
 173         struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
 174 };
 175 
 176 #endif /*__DAL_LINK_SERVICE_TYPES_H__*/