drivers/gpu/drm/amd/display/dc/bios/bios

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
destruct
firmware_parser_destroy
get_atom_data_table_revision
bios_parser_get_connectors_number
bios_parser_get_connector_id
bios_parser_get_src_obj
get_bios_object
bios_parser_get_i2c_info
get_gpio_i2c_info
bios_parser_get_hpd_info
get_hpd_record
bios_parser_get_gpio_pin_info
device_type_from_device_id
bios_parser_get_device_tag
get_ss_info_v4_1
get_ss_info_v4_2
bios_parser_get_spread_spectrum_info
get_embedded_panel_info_v2_1
bios_parser_get_embedded_panel_info
get_support_mask_for_device_id
bios_parser_is_device_id_supported
bios_parser_get_ss_entry_number
bios_parser_transmitter_control
bios_parser_encoder_control
bios_parser_set_pixel_clock
bios_parser_set_dce_clock
bios_parser_program_crtc_timing
bios_parser_enable_crtc
bios_parser_enable_disp_power_gating
bios_parser_is_accelerated_mode
bios_parser_set_scratch_critical_state
bios_parser_get_firmware_info
get_firmware_info_v3_1
get_firmware_info_v3_2
bios_parser_get_encoder_cap_info
get_encoder_cap_record
get_integrated_info_v11
construct_integrated_info
bios_parser_create_integrated_info
update_slot_layout_info
get_bracket_layout_record
bios_get_board_layout_info
bios_parser_construct
firmware_parser_create
   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include <linux/slab.h>
  27 
  28 #include "dm_services.h"
  29 
  30 #include "ObjectID.h"
  31 #include "atomfirmware.h"
  32 
  33 #include "dc_bios_types.h"
  34 #include "include/grph_object_ctrl_defs.h"
  35 #include "include/bios_parser_interface.h"
  36 #include "include/i2caux_interface.h"
  37 #include "include/logger_interface.h"
  38 
  39 #include "command_table2.h"
  40 
  41 #include "bios_parser_helper.h"
  42 #include "command_table_helper2.h"
  43 #include "bios_parser2.h"
  44 #include "bios_parser_types_internal2.h"
  45 #include "bios_parser_interface.h"
  46 
  47 #include "bios_parser_common.h"
  48 
  49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */
  50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT
  51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT          0x05
  52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */
  53 
  54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1
  55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1   \
  56         (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
  57         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
  58         GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
  59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */
  60 
  61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2
  62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2   \
  63         (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
  64         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
  65         GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
  66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */
  67 
  68 #define DC_LOGGER \
  69         bp->base.ctx->logger
  70 
  71 #define LAST_RECORD_TYPE 0xff
  72 #define SMU9_SYSPLL0_ID  0
  73 
  74 struct i2c_id_config_access {
  75         uint8_t bfI2C_LineMux:4;
  76         uint8_t bfHW_EngineID:3;
  77         uint8_t bfHW_Capable:1;
  78         uint8_t ucAccess;
  79 };
  80 
  81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
  82         struct atom_i2c_record *record,
  83         struct graphics_object_i2c_info *info);
  84 
  85 static enum bp_result bios_parser_get_firmware_info(
  86         struct dc_bios *dcb,
  87         struct dc_firmware_info *info);
  88 
  89 static enum bp_result bios_parser_get_encoder_cap_info(
  90         struct dc_bios *dcb,
  91         struct graphics_object_id object_id,
  92         struct bp_encoder_cap_info *info);
  93 
  94 static enum bp_result get_firmware_info_v3_1(
  95         struct bios_parser *bp,
  96         struct dc_firmware_info *info);
  97 
  98 static enum bp_result get_firmware_info_v3_2(
  99         struct bios_parser *bp,
 100         struct dc_firmware_info *info);
 101 
 102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
 103                 struct atom_display_object_path_v2 *object);
 104 
 105 static struct atom_encoder_caps_record *get_encoder_cap_record(
 106         struct bios_parser *bp,
 107         struct atom_display_object_path_v2 *object);
 108 
 109 #define BIOS_IMAGE_SIZE_OFFSET 2
 110 #define BIOS_IMAGE_SIZE_UNIT 512
 111 
 112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
 113 
 114 static void destruct(struct bios_parser *bp)
 115 {
 116         kfree(bp->base.bios_local_image);
 117         kfree(bp->base.integrated_info);
 118 }
 119 
 120 static void firmware_parser_destroy(struct dc_bios **dcb)
 121 {
 122         struct bios_parser *bp = BP_FROM_DCB(*dcb);
 123 
 124         if (!bp) {
 125                 BREAK_TO_DEBUGGER();
 126                 return;
 127         }
 128 
 129         destruct(bp);
 130 
 131         kfree(bp);
 132         *dcb = NULL;
 133 }
 134 
 135 static void get_atom_data_table_revision(
 136         struct atom_common_table_header *atom_data_tbl,
 137         struct atom_data_revision *tbl_revision)
 138 {
 139         if (!tbl_revision)
 140                 return;
 141 
 142         /* initialize the revision to 0 which is invalid revision */
 143         tbl_revision->major = 0;
 144         tbl_revision->minor = 0;
 145 
 146         if (!atom_data_tbl)
 147                 return;
 148 
 149         tbl_revision->major =
 150                         (uint32_t) atom_data_tbl->format_revision & 0x3f;
 151         tbl_revision->minor =
 152                         (uint32_t) atom_data_tbl->content_revision & 0x3f;
 153 }
 154 
 155 /* BIOS oject table displaypath is per connector.
 156  * There is extra path not for connector. BIOS fill its encoderid as 0
 157  */
 158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
 159 {
 160         struct bios_parser *bp = BP_FROM_DCB(dcb);
 161         unsigned int count = 0;
 162         unsigned int i;
 163 
 164         for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
 165                 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
 166                         count++;
 167         }
 168         return count;
 169 }
 170 
 171 static struct graphics_object_id bios_parser_get_connector_id(
 172         struct dc_bios *dcb,
 173         uint8_t i)
 174 {
 175         struct bios_parser *bp = BP_FROM_DCB(dcb);
 176         struct graphics_object_id object_id = dal_graphics_object_id_init(
 177                 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
 178         struct object_info_table *tbl = &bp->object_info_tbl;
 179         struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
 180 
 181         if (v1_4->number_of_path > i) {
 182                 /* If display_objid is generic object id,  the encoderObj
 183                  * /extencoderobjId should be 0
 184                  */
 185                 if (v1_4->display_path[i].encoderobjid != 0 &&
 186                                 v1_4->display_path[i].display_objid != 0)
 187                         object_id = object_id_from_bios_object_id(
 188                                         v1_4->display_path[i].display_objid);
 189         }
 190 
 191         return object_id;
 192 }
 193 
 194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
 195         struct graphics_object_id object_id, uint32_t index,
 196         struct graphics_object_id *src_object_id)
 197 {
 198         struct bios_parser *bp = BP_FROM_DCB(dcb);
 199         unsigned int i;
 200         enum bp_result  bp_result = BP_RESULT_BADINPUT;
 201         struct graphics_object_id obj_id = {0};
 202         struct object_info_table *tbl = &bp->object_info_tbl;
 203 
 204         if (!src_object_id)
 205                 return bp_result;
 206 
 207         switch (object_id.type) {
 208         /* Encoder's Source is GPU.  BIOS does not provide GPU, since all
 209          * displaypaths point to same GPU (0x1100).  Hardcode GPU object type
 210          */
 211         case OBJECT_TYPE_ENCODER:
 212                 /* TODO: since num of src must be less than 2.
 213                  * If found in for loop, should break.
 214                  * DAL2 implementation may be changed too
 215                  */
 216                 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
 217                         obj_id = object_id_from_bios_object_id(
 218                         tbl->v1_4->display_path[i].encoderobjid);
 219                         if (object_id.type == obj_id.type &&
 220                                         object_id.id == obj_id.id &&
 221                                                 object_id.enum_id ==
 222                                                         obj_id.enum_id) {
 223                                 *src_object_id =
 224                                 object_id_from_bios_object_id(0x1100);
 225                                 /* break; */
 226                         }
 227                 }
 228                 bp_result = BP_RESULT_OK;
 229                 break;
 230         case OBJECT_TYPE_CONNECTOR:
 231                 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
 232                         obj_id = object_id_from_bios_object_id(
 233                                 tbl->v1_4->display_path[i].display_objid);
 234 
 235                         if (object_id.type == obj_id.type &&
 236                                 object_id.id == obj_id.id &&
 237                                         object_id.enum_id == obj_id.enum_id) {
 238                                 *src_object_id =
 239                                 object_id_from_bios_object_id(
 240                                 tbl->v1_4->display_path[i].encoderobjid);
 241                                 /* break; */
 242                         }
 243                 }
 244                 bp_result = BP_RESULT_OK;
 245                 break;
 246         default:
 247                 break;
 248         }
 249 
 250         return bp_result;
 251 }
 252 
 253 /* from graphics_object_id, find display path which includes the object_id */
 254 static struct atom_display_object_path_v2 *get_bios_object(
 255                 struct bios_parser *bp,
 256                 struct graphics_object_id id)
 257 {
 258         unsigned int i;
 259         struct graphics_object_id obj_id = {0};
 260 
 261         switch (id.type) {
 262         case OBJECT_TYPE_ENCODER:
 263                 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
 264                         obj_id = object_id_from_bios_object_id(
 265                                         bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
 266                         if (id.type == obj_id.type && id.id == obj_id.id
 267                                         && id.enum_id == obj_id.enum_id)
 268                                 return &bp->object_info_tbl.v1_4->display_path[i];
 269                 }
 270                 /* fall through */
 271         case OBJECT_TYPE_CONNECTOR:
 272         case OBJECT_TYPE_GENERIC:
 273                 /* Both Generic and Connector Object ID
 274                  * will be stored on display_objid
 275                  */
 276                 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
 277                         obj_id = object_id_from_bios_object_id(
 278                                         bp->object_info_tbl.v1_4->display_path[i].display_objid);
 279                         if (id.type == obj_id.type && id.id == obj_id.id
 280                                         && id.enum_id == obj_id.enum_id)
 281                                 return &bp->object_info_tbl.v1_4->display_path[i];
 282                 }
 283                 /* fall through */
 284         default:
 285                 return NULL;
 286         }
 287 }
 288 
 289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
 290         struct graphics_object_id id,
 291         struct graphics_object_i2c_info *info)
 292 {
 293         uint32_t offset;
 294         struct atom_display_object_path_v2 *object;
 295         struct atom_common_record_header *header;
 296         struct atom_i2c_record *record;
 297         struct bios_parser *bp = BP_FROM_DCB(dcb);
 298 
 299         if (!info)
 300                 return BP_RESULT_BADINPUT;
 301 
 302         object = get_bios_object(bp, id);
 303 
 304         if (!object)
 305                 return BP_RESULT_BADINPUT;
 306 
 307         offset = object->disp_recordoffset + bp->object_info_tbl_offset;
 308 
 309         for (;;) {
 310                 header = GET_IMAGE(struct atom_common_record_header, offset);
 311 
 312                 if (!header)
 313                         return BP_RESULT_BADBIOSTABLE;
 314 
 315                 if (header->record_type == LAST_RECORD_TYPE ||
 316                         !header->record_size)
 317                         break;
 318 
 319                 if (header->record_type == ATOM_I2C_RECORD_TYPE
 320                         && sizeof(struct atom_i2c_record) <=
 321                                                         header->record_size) {
 322                         /* get the I2C info */
 323                         record = (struct atom_i2c_record *) header;
 324 
 325                         if (get_gpio_i2c_info(bp, record, info) ==
 326                                                                 BP_RESULT_OK)
 327                                 return BP_RESULT_OK;
 328                 }
 329 
 330                 offset += header->record_size;
 331         }
 332 
 333         return BP_RESULT_NORECORD;
 334 }
 335 
 336 static enum bp_result get_gpio_i2c_info(
 337         struct bios_parser *bp,
 338         struct atom_i2c_record *record,
 339         struct graphics_object_i2c_info *info)
 340 {
 341         struct atom_gpio_pin_lut_v2_1 *header;
 342         uint32_t count = 0;
 343         unsigned int table_index = 0;
 344 
 345         if (!info)
 346                 return BP_RESULT_BADINPUT;
 347 
 348         /* get the GPIO_I2C info */
 349         if (!DATA_TABLES(gpio_pin_lut))
 350                 return BP_RESULT_BADBIOSTABLE;
 351 
 352         header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
 353                                         DATA_TABLES(gpio_pin_lut));
 354         if (!header)
 355                 return BP_RESULT_BADBIOSTABLE;
 356 
 357         if (sizeof(struct atom_common_table_header) +
 358                         sizeof(struct atom_gpio_pin_assignment) >
 359                         le16_to_cpu(header->table_header.structuresize))
 360                 return BP_RESULT_BADBIOSTABLE;
 361 
 362         /* TODO: is version change? */
 363         if (header->table_header.content_revision != 1)
 364                 return BP_RESULT_UNSUPPORTED;
 365 
 366         /* get data count */
 367         count = (le16_to_cpu(header->table_header.structuresize)
 368                         - sizeof(struct atom_common_table_header))
 369                                 / sizeof(struct atom_gpio_pin_assignment);
 370 
 371         table_index = record->i2c_id  & I2C_HW_LANE_MUX;
 372 
 373         if (count < table_index) {
 374                 bool find_valid = false;
 375 
 376                 for (table_index = 0; table_index < count; table_index++) {
 377                         if (((record->i2c_id & I2C_HW_CAP) == (
 378                         header->gpio_pin[table_index].gpio_id &
 379                                                         I2C_HW_CAP)) &&
 380                         ((record->i2c_id & I2C_HW_ENGINE_ID_MASK)  ==
 381                         (header->gpio_pin[table_index].gpio_id &
 382                                                 I2C_HW_ENGINE_ID_MASK)) &&
 383                         ((record->i2c_id & I2C_HW_LANE_MUX) ==
 384                         (header->gpio_pin[table_index].gpio_id &
 385                                                         I2C_HW_LANE_MUX))) {
 386                                 /* still valid */
 387                                 find_valid = true;
 388                                 break;
 389                         }
 390                 }
 391                 /* If we don't find the entry that we are looking for then
 392                  *  we will return BP_Result_BadBiosTable.
 393                  */
 394                 if (find_valid == false)
 395                         return BP_RESULT_BADBIOSTABLE;
 396         }
 397 
 398         /* get the GPIO_I2C_INFO */
 399         info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
 400         info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
 401         info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
 402         info->i2c_slave_address = record->i2c_slave_addr;
 403 
 404         /* TODO: check how to get register offset for en, Y, etc. */
 405         info->gpio_info.clk_a_register_index =
 406                         le16_to_cpu(
 407                         header->gpio_pin[table_index].data_a_reg_index);
 408         info->gpio_info.clk_a_shift =
 409                         header->gpio_pin[table_index].gpio_bitshift;
 410 
 411         return BP_RESULT_OK;
 412 }
 413 
 414 static enum bp_result bios_parser_get_hpd_info(
 415         struct dc_bios *dcb,
 416         struct graphics_object_id id,
 417         struct graphics_object_hpd_info *info)
 418 {
 419         struct bios_parser *bp = BP_FROM_DCB(dcb);
 420         struct atom_display_object_path_v2 *object;
 421         struct atom_hpd_int_record *record = NULL;
 422 
 423         if (!info)
 424                 return BP_RESULT_BADINPUT;
 425 
 426         object = get_bios_object(bp, id);
 427 
 428         if (!object)
 429                 return BP_RESULT_BADINPUT;
 430 
 431         record = get_hpd_record(bp, object);
 432 
 433         if (record != NULL) {
 434                 info->hpd_int_gpio_uid = record->pin_id;
 435                 info->hpd_active = record->plugin_pin_state;
 436                 return BP_RESULT_OK;
 437         }
 438 
 439         return BP_RESULT_NORECORD;
 440 }
 441 
 442 static struct atom_hpd_int_record *get_hpd_record(
 443         struct bios_parser *bp,
 444         struct atom_display_object_path_v2 *object)
 445 {
 446         struct atom_common_record_header *header;
 447         uint32_t offset;
 448 
 449         if (!object) {
 450                 BREAK_TO_DEBUGGER(); /* Invalid object */
 451                 return NULL;
 452         }
 453 
 454         offset = le16_to_cpu(object->disp_recordoffset)
 455                         + bp->object_info_tbl_offset;
 456 
 457         for (;;) {
 458                 header = GET_IMAGE(struct atom_common_record_header, offset);
 459 
 460                 if (!header)
 461                         return NULL;
 462 
 463                 if (header->record_type == LAST_RECORD_TYPE ||
 464                         !header->record_size)
 465                         break;
 466 
 467                 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
 468                         && sizeof(struct atom_hpd_int_record) <=
 469                                                         header->record_size)
 470                         return (struct atom_hpd_int_record *) header;
 471 
 472                 offset += header->record_size;
 473         }
 474 
 475         return NULL;
 476 }
 477 
 478 /**
 479  * bios_parser_get_gpio_pin_info
 480  * Get GpioPin information of input gpio id
 481  *
 482  * @param gpio_id, GPIO ID
 483  * @param info, GpioPin information structure
 484  * @return Bios parser result code
 485  * @note
 486  *  to get the GPIO PIN INFO, we need:
 487  *  1. get the GPIO_ID from other object table, see GetHPDInfo()
 488  *  2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
 489  *      to get the registerA  offset/mask
 490  */
 491 static enum bp_result bios_parser_get_gpio_pin_info(
 492         struct dc_bios *dcb,
 493         uint32_t gpio_id,
 494         struct gpio_pin_info *info)
 495 {
 496         struct bios_parser *bp = BP_FROM_DCB(dcb);
 497         struct atom_gpio_pin_lut_v2_1 *header;
 498         uint32_t count = 0;
 499         uint32_t i = 0;
 500 
 501         if (!DATA_TABLES(gpio_pin_lut))
 502                 return BP_RESULT_BADBIOSTABLE;
 503 
 504         header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
 505                                                 DATA_TABLES(gpio_pin_lut));
 506         if (!header)
 507                 return BP_RESULT_BADBIOSTABLE;
 508 
 509         if (sizeof(struct atom_common_table_header) +
 510                         sizeof(struct atom_gpio_pin_assignment)
 511                         > le16_to_cpu(header->table_header.structuresize))
 512                 return BP_RESULT_BADBIOSTABLE;
 513 
 514         if (header->table_header.content_revision != 1)
 515                 return BP_RESULT_UNSUPPORTED;
 516 
 517         /* Temporary hard code gpio pin info */
 518 #if defined(FOR_SIMNOW_BOOT)
 519         {
 520                 struct  atom_gpio_pin_assignment  gpio_pin[8] = {
 521                                 {0x5db5, 0, 0, 1, 0},
 522                                 {0x5db5, 8, 8, 2, 0},
 523                                 {0x5db5, 0x10, 0x10, 3, 0},
 524                                 {0x5db5, 0x18, 0x14, 4, 0},
 525                                 {0x5db5, 0x1A, 0x18, 5, 0},
 526                                 {0x5db5, 0x1C, 0x1C, 6, 0},
 527                 };
 528 
 529                 count = 6;
 530                 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
 531         }
 532 #else
 533         count = (le16_to_cpu(header->table_header.structuresize)
 534                         - sizeof(struct atom_common_table_header))
 535                                 / sizeof(struct atom_gpio_pin_assignment);
 536 #endif
 537         for (i = 0; i < count; ++i) {
 538                 if (header->gpio_pin[i].gpio_id != gpio_id)
 539                         continue;
 540 
 541                 info->offset =
 542                         (uint32_t) le16_to_cpu(
 543                                         header->gpio_pin[i].data_a_reg_index);
 544                 info->offset_y = info->offset + 2;
 545                 info->offset_en = info->offset + 1;
 546                 info->offset_mask = info->offset - 1;
 547 
 548                 info->mask = (uint32_t) (1 <<
 549                         header->gpio_pin[i].gpio_bitshift);
 550                 info->mask_y = info->mask + 2;
 551                 info->mask_en = info->mask + 1;
 552                 info->mask_mask = info->mask - 1;
 553 
 554                 return BP_RESULT_OK;
 555         }
 556 
 557         return BP_RESULT_NORECORD;
 558 }
 559 
 560 static struct device_id device_type_from_device_id(uint16_t device_id)
 561 {
 562 
 563         struct device_id result_device_id;
 564 
 565         result_device_id.raw_device_tag = device_id;
 566 
 567         switch (device_id) {
 568         case ATOM_DISPLAY_LCD1_SUPPORT:
 569                 result_device_id.device_type = DEVICE_TYPE_LCD;
 570                 result_device_id.enum_id = 1;
 571                 break;
 572 
 573         case ATOM_DISPLAY_DFP1_SUPPORT:
 574                 result_device_id.device_type = DEVICE_TYPE_DFP;
 575                 result_device_id.enum_id = 1;
 576                 break;
 577 
 578         case ATOM_DISPLAY_DFP2_SUPPORT:
 579                 result_device_id.device_type = DEVICE_TYPE_DFP;
 580                 result_device_id.enum_id = 2;
 581                 break;
 582 
 583         case ATOM_DISPLAY_DFP3_SUPPORT:
 584                 result_device_id.device_type = DEVICE_TYPE_DFP;
 585                 result_device_id.enum_id = 3;
 586                 break;
 587 
 588         case ATOM_DISPLAY_DFP4_SUPPORT:
 589                 result_device_id.device_type = DEVICE_TYPE_DFP;
 590                 result_device_id.enum_id = 4;
 591                 break;
 592 
 593         case ATOM_DISPLAY_DFP5_SUPPORT:
 594                 result_device_id.device_type = DEVICE_TYPE_DFP;
 595                 result_device_id.enum_id = 5;
 596                 break;
 597 
 598         case ATOM_DISPLAY_DFP6_SUPPORT:
 599                 result_device_id.device_type = DEVICE_TYPE_DFP;
 600                 result_device_id.enum_id = 6;
 601                 break;
 602 
 603         default:
 604                 BREAK_TO_DEBUGGER(); /* Invalid device Id */
 605                 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
 606                 result_device_id.enum_id = 0;
 607         }
 608         return result_device_id;
 609 }
 610 
 611 static enum bp_result bios_parser_get_device_tag(
 612         struct dc_bios *dcb,
 613         struct graphics_object_id connector_object_id,
 614         uint32_t device_tag_index,
 615         struct connector_device_tag_info *info)
 616 {
 617         struct bios_parser *bp = BP_FROM_DCB(dcb);
 618         struct atom_display_object_path_v2 *object;
 619 
 620         if (!info)
 621                 return BP_RESULT_BADINPUT;
 622 
 623         /* getBiosObject will return MXM object */
 624         object = get_bios_object(bp, connector_object_id);
 625 
 626         if (!object) {
 627                 BREAK_TO_DEBUGGER(); /* Invalid object id */
 628                 return BP_RESULT_BADINPUT;
 629         }
 630 
 631         info->acpi_device = 0; /* BIOS no longer provides this */
 632         info->dev_id = device_type_from_device_id(object->device_tag);
 633 
 634         return BP_RESULT_OK;
 635 }
 636 
 637 static enum bp_result get_ss_info_v4_1(
 638         struct bios_parser *bp,
 639         uint32_t id,
 640         uint32_t index,
 641         struct spread_spectrum_info *ss_info)
 642 {
 643         enum bp_result result = BP_RESULT_OK;
 644         struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
 645         struct atom_smu_info_v3_3 *smu_info = NULL;
 646 
 647         if (!ss_info)
 648                 return BP_RESULT_BADINPUT;
 649 
 650         if (!DATA_TABLES(dce_info))
 651                 return BP_RESULT_BADBIOSTABLE;
 652 
 653         disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_1,
 654                                                         DATA_TABLES(dce_info));
 655         if (!disp_cntl_tbl)
 656                 return BP_RESULT_BADBIOSTABLE;
 657 
 658 
 659         ss_info->type.STEP_AND_DELAY_INFO = false;
 660         ss_info->spread_percentage_divider = 1000;
 661         /* BIOS no longer uses target clock.  Always enable for now */
 662         ss_info->target_clock_range = 0xffffffff;
 663 
 664         switch (id) {
 665         case AS_SIGNAL_TYPE_DVI:
 666                 ss_info->spread_spectrum_percentage =
 667                                 disp_cntl_tbl->dvi_ss_percentage;
 668                 ss_info->spread_spectrum_range =
 669                                 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
 670                 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 671                         ss_info->type.CENTER_MODE = true;
 672                 break;
 673         case AS_SIGNAL_TYPE_HDMI:
 674                 ss_info->spread_spectrum_percentage =
 675                                 disp_cntl_tbl->hdmi_ss_percentage;
 676                 ss_info->spread_spectrum_range =
 677                                 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
 678                 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 679                         ss_info->type.CENTER_MODE = true;
 680                 break;
 681         /* TODO LVDS not support anymore? */
 682         case AS_SIGNAL_TYPE_DISPLAY_PORT:
 683                 ss_info->spread_spectrum_percentage =
 684                                 disp_cntl_tbl->dp_ss_percentage;
 685                 ss_info->spread_spectrum_range =
 686                                 disp_cntl_tbl->dp_ss_rate_10hz * 10;
 687                 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 688                         ss_info->type.CENTER_MODE = true;
 689                 break;
 690         case AS_SIGNAL_TYPE_GPU_PLL:
 691                 /* atom_firmware: DAL only get data from dce_info table.
 692                  * if data within smu_info is needed for DAL, VBIOS should
 693                  * copy it into dce_info
 694                  */
 695                 result = BP_RESULT_UNSUPPORTED;
 696                 break;
 697         case AS_SIGNAL_TYPE_XGMI:
 698                 smu_info =  GET_IMAGE(struct atom_smu_info_v3_3,
 699                                       DATA_TABLES(smu_info));
 700                 if (!smu_info)
 701                         return BP_RESULT_BADBIOSTABLE;
 702 
 703                 ss_info->spread_spectrum_percentage =
 704                                 smu_info->waflclk_ss_percentage;
 705                 ss_info->spread_spectrum_range =
 706                                 smu_info->gpuclk_ss_rate_10hz * 10;
 707                 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 708                         ss_info->type.CENTER_MODE = true;
 709                 break;
 710         default:
 711                 result = BP_RESULT_UNSUPPORTED;
 712         }
 713 
 714         return result;
 715 }
 716 
 717 static enum bp_result get_ss_info_v4_2(
 718         struct bios_parser *bp,
 719         uint32_t id,
 720         uint32_t index,
 721         struct spread_spectrum_info *ss_info)
 722 {
 723         enum bp_result result = BP_RESULT_OK;
 724         struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
 725         struct atom_smu_info_v3_1 *smu_info = NULL;
 726 
 727         if (!ss_info)
 728                 return BP_RESULT_BADINPUT;
 729 
 730         if (!DATA_TABLES(dce_info))
 731                 return BP_RESULT_BADBIOSTABLE;
 732 
 733         if (!DATA_TABLES(smu_info))
 734                 return BP_RESULT_BADBIOSTABLE;
 735 
 736         disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_2,
 737                                                         DATA_TABLES(dce_info));
 738         if (!disp_cntl_tbl)
 739                 return BP_RESULT_BADBIOSTABLE;
 740 
 741         smu_info =  GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
 742         if (!smu_info)
 743                 return BP_RESULT_BADBIOSTABLE;
 744 
 745         ss_info->type.STEP_AND_DELAY_INFO = false;
 746         ss_info->spread_percentage_divider = 1000;
 747         /* BIOS no longer uses target clock.  Always enable for now */
 748         ss_info->target_clock_range = 0xffffffff;
 749 
 750         switch (id) {
 751         case AS_SIGNAL_TYPE_DVI:
 752                 ss_info->spread_spectrum_percentage =
 753                                 disp_cntl_tbl->dvi_ss_percentage;
 754                 ss_info->spread_spectrum_range =
 755                                 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
 756                 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 757                         ss_info->type.CENTER_MODE = true;
 758                 break;
 759         case AS_SIGNAL_TYPE_HDMI:
 760                 ss_info->spread_spectrum_percentage =
 761                                 disp_cntl_tbl->hdmi_ss_percentage;
 762                 ss_info->spread_spectrum_range =
 763                                 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
 764                 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 765                         ss_info->type.CENTER_MODE = true;
 766                 break;
 767         /* TODO LVDS not support anymore? */
 768         case AS_SIGNAL_TYPE_DISPLAY_PORT:
 769                 ss_info->spread_spectrum_percentage =
 770                                 smu_info->gpuclk_ss_percentage;
 771                 ss_info->spread_spectrum_range =
 772                                 smu_info->gpuclk_ss_rate_10hz * 10;
 773                 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
 774                         ss_info->type.CENTER_MODE = true;
 775                 break;
 776         case AS_SIGNAL_TYPE_GPU_PLL:
 777                 /* atom_firmware: DAL only get data from dce_info table.
 778                  * if data within smu_info is needed for DAL, VBIOS should
 779                  * copy it into dce_info
 780                  */
 781                 result = BP_RESULT_UNSUPPORTED;
 782                 break;
 783         default:
 784                 result = BP_RESULT_UNSUPPORTED;
 785         }
 786 
 787         return result;
 788 }
 789 
 790 /**
 791  * bios_parser_get_spread_spectrum_info
 792  * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
 793  * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
 794  * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
 795  * ver 3.1,
 796  * there is only one entry for each signal /ss id.  However, there is
 797  * no planning of supporting multiple spread Sprectum entry for EverGreen
 798  * @param [in] this
 799  * @param [in] signal, ASSignalType to be converted to info index
 800  * @param [in] index, number of entries that match the converted info index
 801  * @param [out] ss_info, sprectrum information structure,
 802  * @return Bios parser result code
 803  */
 804 static enum bp_result bios_parser_get_spread_spectrum_info(
 805         struct dc_bios *dcb,
 806         enum as_signal_type signal,
 807         uint32_t index,
 808         struct spread_spectrum_info *ss_info)
 809 {
 810         struct bios_parser *bp = BP_FROM_DCB(dcb);
 811         enum bp_result result = BP_RESULT_UNSUPPORTED;
 812         struct atom_common_table_header *header;
 813         struct atom_data_revision tbl_revision;
 814 
 815         if (!ss_info) /* check for bad input */
 816                 return BP_RESULT_BADINPUT;
 817 
 818         if (!DATA_TABLES(dce_info))
 819                 return BP_RESULT_UNSUPPORTED;
 820 
 821         header = GET_IMAGE(struct atom_common_table_header,
 822                                                 DATA_TABLES(dce_info));
 823         get_atom_data_table_revision(header, &tbl_revision);
 824 
 825         switch (tbl_revision.major) {
 826         case 4:
 827                 switch (tbl_revision.minor) {
 828                 case 1:
 829                         return get_ss_info_v4_1(bp, signal, index, ss_info);
 830                 case 2:
 831                         return get_ss_info_v4_2(bp, signal, index, ss_info);
 832                 default:
 833                         break;
 834                 }
 835                 break;
 836         default:
 837                 break;
 838         }
 839         /* there can not be more then one entry for SS Info table */
 840         return result;
 841 }
 842 
 843 static enum bp_result get_embedded_panel_info_v2_1(
 844                 struct bios_parser *bp,
 845                 struct embedded_panel_info *info)
 846 {
 847         struct lcd_info_v2_1 *lvds;
 848 
 849         if (!info)
 850                 return BP_RESULT_BADINPUT;
 851 
 852         if (!DATA_TABLES(lcd_info))
 853                 return BP_RESULT_UNSUPPORTED;
 854 
 855         lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
 856 
 857         if (!lvds)
 858                 return BP_RESULT_BADBIOSTABLE;
 859 
 860         /* TODO: previous vv1_3, should v2_1 */
 861         if (!((lvds->table_header.format_revision == 2)
 862                         && (lvds->table_header.content_revision >= 1)))
 863                 return BP_RESULT_UNSUPPORTED;
 864 
 865         memset(info, 0, sizeof(struct embedded_panel_info));
 866 
 867         /* We need to convert from 10KHz units into KHz units */
 868         info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
 869         /* usHActive does not include borders, according to VBIOS team */
 870         info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
 871         /* usHBlanking_Time includes borders, so we should really be
 872          * subtractingborders duing this translation, but LVDS generally
 873          * doesn't have borders, so we should be okay leaving this as is for
 874          * now.  May need to revisit if we ever have LVDS with borders
 875          */
 876         info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
 877         /* usVActive does not include borders, according to VBIOS team*/
 878         info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
 879         /* usVBlanking_Time includes borders, so we should really be
 880          * subtracting borders duing this translation, but LVDS generally
 881          * doesn't have borders, so we should be okay leaving this as is for
 882          * now. May need to revisit if we ever have LVDS with borders
 883          */
 884         info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
 885         info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
 886         info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
 887         info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
 888         info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
 889         info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
 890         info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
 891 
 892         /* not provided by VBIOS */
 893         info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
 894 
 895         info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
 896                         & ATOM_HSYNC_POLARITY);
 897         info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
 898                         & ATOM_VSYNC_POLARITY);
 899 
 900         /* not provided by VBIOS */
 901         info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
 902 
 903         info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
 904                         & ATOM_H_REPLICATIONBY2);
 905         info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
 906                         & ATOM_V_REPLICATIONBY2);
 907         info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
 908                         & ATOM_COMPOSITESYNC);
 909         info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
 910 
 911         /* not provided by VBIOS*/
 912         info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
 913         /* not provided by VBIOS*/
 914         info->ss_id = 0;
 915 
 916         info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
 917 
 918         return BP_RESULT_OK;
 919 }
 920 
 921 static enum bp_result bios_parser_get_embedded_panel_info(
 922                 struct dc_bios *dcb,
 923                 struct embedded_panel_info *info)
 924 {
 925         struct bios_parser
 926         *bp = BP_FROM_DCB(dcb);
 927         struct atom_common_table_header *header;
 928         struct atom_data_revision tbl_revision;
 929 
 930         if (!DATA_TABLES(lcd_info))
 931                 return BP_RESULT_FAILURE;
 932 
 933         header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
 934 
 935         if (!header)
 936                 return BP_RESULT_BADBIOSTABLE;
 937 
 938         get_atom_data_table_revision(header, &tbl_revision);
 939 
 940         switch (tbl_revision.major) {
 941         case 2:
 942                 switch (tbl_revision.minor) {
 943                 case 1:
 944                         return get_embedded_panel_info_v2_1(bp, info);
 945                 default:
 946                         break;
 947                 }
 948         default:
 949                 break;
 950         }
 951 
 952         return BP_RESULT_FAILURE;
 953 }
 954 
 955 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
 956 {
 957         enum dal_device_type device_type = device_id.device_type;
 958         uint32_t enum_id = device_id.enum_id;
 959 
 960         switch (device_type) {
 961         case DEVICE_TYPE_LCD:
 962                 switch (enum_id) {
 963                 case 1:
 964                         return ATOM_DISPLAY_LCD1_SUPPORT;
 965                 default:
 966                         break;
 967                 }
 968                 break;
 969         case DEVICE_TYPE_DFP:
 970                 switch (enum_id) {
 971                 case 1:
 972                         return ATOM_DISPLAY_DFP1_SUPPORT;
 973                 case 2:
 974                         return ATOM_DISPLAY_DFP2_SUPPORT;
 975                 case 3:
 976                         return ATOM_DISPLAY_DFP3_SUPPORT;
 977                 case 4:
 978                         return ATOM_DISPLAY_DFP4_SUPPORT;
 979                 case 5:
 980                         return ATOM_DISPLAY_DFP5_SUPPORT;
 981                 case 6:
 982                         return ATOM_DISPLAY_DFP6_SUPPORT;
 983                 default:
 984                         break;
 985                 }
 986                 break;
 987         default:
 988                 break;
 989         };
 990 
 991         /* Unidentified device ID, return empty support mask. */
 992         return 0;
 993 }
 994 
 995 static bool bios_parser_is_device_id_supported(
 996         struct dc_bios *dcb,
 997         struct device_id id)
 998 {
 999         struct bios_parser *bp = BP_FROM_DCB(dcb);
1000 
1001         uint32_t mask = get_support_mask_for_device_id(id);
1002 
1003         return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
1004                                                                 mask) != 0;
1005 }
1006 
1007 static uint32_t bios_parser_get_ss_entry_number(
1008         struct dc_bios *dcb,
1009         enum as_signal_type signal)
1010 {
1011         /* TODO: DAL2 atomfirmware implementation does not need this.
1012          * why DAL3 need this?
1013          */
1014         return 1;
1015 }
1016 
1017 static enum bp_result bios_parser_transmitter_control(
1018         struct dc_bios *dcb,
1019         struct bp_transmitter_control *cntl)
1020 {
1021         struct bios_parser *bp = BP_FROM_DCB(dcb);
1022 
1023         if (!bp->cmd_tbl.transmitter_control)
1024                 return BP_RESULT_FAILURE;
1025 
1026         return bp->cmd_tbl.transmitter_control(bp, cntl);
1027 }
1028 
1029 static enum bp_result bios_parser_encoder_control(
1030         struct dc_bios *dcb,
1031         struct bp_encoder_control *cntl)
1032 {
1033         struct bios_parser *bp = BP_FROM_DCB(dcb);
1034 
1035         if (!bp->cmd_tbl.dig_encoder_control)
1036                 return BP_RESULT_FAILURE;
1037 
1038         return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1039 }
1040 
1041 static enum bp_result bios_parser_set_pixel_clock(
1042         struct dc_bios *dcb,
1043         struct bp_pixel_clock_parameters *bp_params)
1044 {
1045         struct bios_parser *bp = BP_FROM_DCB(dcb);
1046 
1047         if (!bp->cmd_tbl.set_pixel_clock)
1048                 return BP_RESULT_FAILURE;
1049 
1050         return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1051 }
1052 
1053 static enum bp_result bios_parser_set_dce_clock(
1054         struct dc_bios *dcb,
1055         struct bp_set_dce_clock_parameters *bp_params)
1056 {
1057         struct bios_parser *bp = BP_FROM_DCB(dcb);
1058 
1059         if (!bp->cmd_tbl.set_dce_clock)
1060                 return BP_RESULT_FAILURE;
1061 
1062         return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1063 }
1064 
1065 static enum bp_result bios_parser_program_crtc_timing(
1066         struct dc_bios *dcb,
1067         struct bp_hw_crtc_timing_parameters *bp_params)
1068 {
1069         struct bios_parser *bp = BP_FROM_DCB(dcb);
1070 
1071         if (!bp->cmd_tbl.set_crtc_timing)
1072                 return BP_RESULT_FAILURE;
1073 
1074         return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1075 }
1076 
1077 static enum bp_result bios_parser_enable_crtc(
1078         struct dc_bios *dcb,
1079         enum controller_id id,
1080         bool enable)
1081 {
1082         struct bios_parser *bp = BP_FROM_DCB(dcb);
1083 
1084         if (!bp->cmd_tbl.enable_crtc)
1085                 return BP_RESULT_FAILURE;
1086 
1087         return bp->cmd_tbl.enable_crtc(bp, id, enable);
1088 }
1089 
1090 static enum bp_result bios_parser_enable_disp_power_gating(
1091         struct dc_bios *dcb,
1092         enum controller_id controller_id,
1093         enum bp_pipe_control_action action)
1094 {
1095         struct bios_parser *bp = BP_FROM_DCB(dcb);
1096 
1097         if (!bp->cmd_tbl.enable_disp_power_gating)
1098                 return BP_RESULT_FAILURE;
1099 
1100         return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1101                 action);
1102 }
1103 
1104 static bool bios_parser_is_accelerated_mode(
1105         struct dc_bios *dcb)
1106 {
1107         return bios_is_accelerated_mode(dcb);
1108 }
1109 
1110 /**
1111  * bios_parser_set_scratch_critical_state
1112  *
1113  * @brief
1114  *  update critical state bit in VBIOS scratch register
1115  *
1116  * @param
1117  *  bool - to set or reset state
1118  */
1119 static void bios_parser_set_scratch_critical_state(
1120         struct dc_bios *dcb,
1121         bool state)
1122 {
1123         bios_set_scratch_critical_state(dcb, state);
1124 }
1125 
1126 static enum bp_result bios_parser_get_firmware_info(
1127         struct dc_bios *dcb,
1128         struct dc_firmware_info *info)
1129 {
1130         struct bios_parser *bp = BP_FROM_DCB(dcb);
1131         enum bp_result result = BP_RESULT_BADBIOSTABLE;
1132         struct atom_common_table_header *header;
1133 
1134         struct atom_data_revision revision;
1135 
1136         if (info && DATA_TABLES(firmwareinfo)) {
1137                 header = GET_IMAGE(struct atom_common_table_header,
1138                                 DATA_TABLES(firmwareinfo));
1139                 get_atom_data_table_revision(header, &revision);
1140                 switch (revision.major) {
1141                 case 3:
1142                         switch (revision.minor) {
1143                         case 1:
1144                                 result = get_firmware_info_v3_1(bp, info);
1145                                 break;
1146                         case 2:
1147                                 result = get_firmware_info_v3_2(bp, info);
1148                                 break;
1149                         case 3:
1150                                 result = get_firmware_info_v3_2(bp, info);
1151                                 break;
1152                         default:
1153                                 break;
1154                         }
1155                         break;
1156                 default:
1157                         break;
1158                 }
1159         }
1160 
1161         return result;
1162 }
1163 
1164 static enum bp_result get_firmware_info_v3_1(
1165         struct bios_parser *bp,
1166         struct dc_firmware_info *info)
1167 {
1168         struct atom_firmware_info_v3_1 *firmware_info;
1169         struct atom_display_controller_info_v4_1 *dce_info = NULL;
1170 
1171         if (!info)
1172                 return BP_RESULT_BADINPUT;
1173 
1174         firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1175                         DATA_TABLES(firmwareinfo));
1176 
1177         dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1178                         DATA_TABLES(dce_info));
1179 
1180         if (!firmware_info || !dce_info)
1181                 return BP_RESULT_BADBIOSTABLE;
1182 
1183         memset(info, 0, sizeof(*info));
1184 
1185         /* Pixel clock pll information. */
1186          /* We need to convert from 10KHz units into KHz units */
1187         info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1188         info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1189 
1190          /* 27MHz for Vega10: */
1191         info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1192 
1193         /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1194         if (info->pll_info.crystal_frequency == 0)
1195                 info->pll_info.crystal_frequency = 27000;
1196         /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1197         info->dp_phy_ref_clk     = dce_info->dpphy_refclk_10khz * 10;
1198         info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1199 
1200         /* Get GPU PLL VCO Clock */
1201 
1202         if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1203                 /* VBIOS gives in 10KHz */
1204                 info->smu_gpu_pll_output_freq =
1205                                 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1206         }
1207 
1208         return BP_RESULT_OK;
1209 }
1210 
1211 static enum bp_result get_firmware_info_v3_2(
1212         struct bios_parser *bp,
1213         struct dc_firmware_info *info)
1214 {
1215         struct atom_firmware_info_v3_2 *firmware_info;
1216         struct atom_display_controller_info_v4_1 *dce_info = NULL;
1217         struct atom_common_table_header *header;
1218         struct atom_data_revision revision;
1219         struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1220         struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1221 
1222         if (!info)
1223                 return BP_RESULT_BADINPUT;
1224 
1225         firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1226                         DATA_TABLES(firmwareinfo));
1227 
1228         dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1229                         DATA_TABLES(dce_info));
1230 
1231         if (!firmware_info || !dce_info)
1232                 return BP_RESULT_BADBIOSTABLE;
1233 
1234         memset(info, 0, sizeof(*info));
1235 
1236         header = GET_IMAGE(struct atom_common_table_header,
1237                                         DATA_TABLES(smu_info));
1238         get_atom_data_table_revision(header, &revision);
1239 
1240         if (revision.minor == 2) {
1241                 /* Vega12 */
1242                 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1243                                                         DATA_TABLES(smu_info));
1244 
1245                 if (!smu_info_v3_2)
1246                         return BP_RESULT_BADBIOSTABLE;
1247 
1248                 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1249         } else if (revision.minor == 3) {
1250                 /* Vega20 */
1251                 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1252                                                         DATA_TABLES(smu_info));
1253 
1254                 if (!smu_info_v3_3)
1255                         return BP_RESULT_BADBIOSTABLE;
1256 
1257                 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1258         }
1259 
1260          // We need to convert from 10KHz units into KHz units.
1261         info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1262 
1263          /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1264         info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1265         /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1266         if (info->pll_info.crystal_frequency == 0) {
1267                 if (revision.minor == 2)
1268                         info->pll_info.crystal_frequency = 27000;
1269                 else if (revision.minor == 3)
1270                         info->pll_info.crystal_frequency = 100000;
1271         }
1272         /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1273         info->dp_phy_ref_clk     = dce_info->dpphy_refclk_10khz * 10;
1274         info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1275 
1276         /* Get GPU PLL VCO Clock */
1277         if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1278                 if (revision.minor == 2)
1279                         info->smu_gpu_pll_output_freq =
1280                                         bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1281                 else if (revision.minor == 3)
1282                         info->smu_gpu_pll_output_freq =
1283                                         bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1284         }
1285 
1286         return BP_RESULT_OK;
1287 }
1288 
1289 static enum bp_result bios_parser_get_encoder_cap_info(
1290         struct dc_bios *dcb,
1291         struct graphics_object_id object_id,
1292         struct bp_encoder_cap_info *info)
1293 {
1294         struct bios_parser *bp = BP_FROM_DCB(dcb);
1295         struct atom_display_object_path_v2 *object;
1296         struct atom_encoder_caps_record *record = NULL;
1297 
1298         if (!info)
1299                 return BP_RESULT_BADINPUT;
1300 
1301         object = get_bios_object(bp, object_id);
1302 
1303         if (!object)
1304                 return BP_RESULT_BADINPUT;
1305 
1306         record = get_encoder_cap_record(bp, object);
1307         if (!record)
1308                 return BP_RESULT_NORECORD;
1309 
1310         info->DP_HBR2_CAP = (record->encodercaps &
1311                         ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
1312         info->DP_HBR2_EN = (record->encodercaps &
1313                         ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
1314         info->DP_HBR3_EN = (record->encodercaps &
1315                         ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
1316         info->HDMI_6GB_EN = (record->encodercaps &
1317                         ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
1318         info->DP_IS_USB_C = (record->encodercaps &
1319                         ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
1320 
1321         return BP_RESULT_OK;
1322 }
1323 
1324 
1325 static struct atom_encoder_caps_record *get_encoder_cap_record(
1326         struct bios_parser *bp,
1327         struct atom_display_object_path_v2 *object)
1328 {
1329         struct atom_common_record_header *header;
1330         uint32_t offset;
1331 
1332         if (!object) {
1333                 BREAK_TO_DEBUGGER(); /* Invalid object */
1334                 return NULL;
1335         }
1336 
1337         offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
1338 
1339         for (;;) {
1340                 header = GET_IMAGE(struct atom_common_record_header, offset);
1341 
1342                 if (!header)
1343                         return NULL;
1344 
1345                 offset += header->record_size;
1346 
1347                 if (header->record_type == LAST_RECORD_TYPE ||
1348                                 !header->record_size)
1349                         break;
1350 
1351                 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
1352                         continue;
1353 
1354                 if (sizeof(struct atom_encoder_caps_record) <=
1355                                                         header->record_size)
1356                         return (struct atom_encoder_caps_record *)header;
1357         }
1358 
1359         return NULL;
1360 }
1361 
1362 /*
1363  * get_integrated_info_v11
1364  *
1365  * @brief
1366  * Get V8 integrated BIOS information
1367  *
1368  * @param
1369  * bios_parser *bp - [in]BIOS parser handler to get master data table
1370  * integrated_info *info - [out] store and output integrated info
1371  *
1372  * @return
1373  * enum bp_result - BP_RESULT_OK if information is available,
1374  *                  BP_RESULT_BADBIOSTABLE otherwise.
1375  */
1376 static enum bp_result get_integrated_info_v11(
1377         struct bios_parser *bp,
1378         struct integrated_info *info)
1379 {
1380         struct atom_integrated_system_info_v1_11 *info_v11;
1381         uint32_t i;
1382 
1383         info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
1384                                         DATA_TABLES(integratedsysteminfo));
1385 
1386         if (info_v11 == NULL)
1387                 return BP_RESULT_BADBIOSTABLE;
1388 
1389         info->gpu_cap_info =
1390         le32_to_cpu(info_v11->gpucapinfo);
1391         /*
1392         * system_config: Bit[0] = 0 : PCIE power gating disabled
1393         *                       = 1 : PCIE power gating enabled
1394         *                Bit[1] = 0 : DDR-PLL shut down disabled
1395         *                       = 1 : DDR-PLL shut down enabled
1396         *                Bit[2] = 0 : DDR-PLL power down disabled
1397         *                       = 1 : DDR-PLL power down enabled
1398         */
1399         info->system_config = le32_to_cpu(info_v11->system_config);
1400         info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
1401         info->memory_type = info_v11->memorytype;
1402         info->ma_channel_number = info_v11->umachannelnumber;
1403         info->lvds_ss_percentage =
1404         le16_to_cpu(info_v11->lvds_ss_percentage);
1405 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
1406         info->dp_ss_control =
1407         le16_to_cpu(info_v11->reserved1);
1408 #endif
1409         info->lvds_sspread_rate_in_10hz =
1410         le16_to_cpu(info_v11->lvds_ss_rate_10hz);
1411         info->hdmi_ss_percentage =
1412         le16_to_cpu(info_v11->hdmi_ss_percentage);
1413         info->hdmi_sspread_rate_in_10hz =
1414         le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
1415         info->dvi_ss_percentage =
1416         le16_to_cpu(info_v11->dvi_ss_percentage);
1417         info->dvi_sspread_rate_in_10_hz =
1418         le16_to_cpu(info_v11->dvi_ss_rate_10hz);
1419         info->lvds_misc = info_v11->lvds_misc;
1420         for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
1421                 info->ext_disp_conn_info.gu_id[i] =
1422                                 info_v11->extdispconninfo.guid[i];
1423         }
1424 
1425         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
1426                 info->ext_disp_conn_info.path[i].device_connector_id =
1427                 object_id_from_bios_object_id(
1428                 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
1429 
1430                 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
1431                 object_id_from_bios_object_id(
1432                         le16_to_cpu(
1433                         info_v11->extdispconninfo.path[i].ext_encoder_objid));
1434 
1435                 info->ext_disp_conn_info.path[i].device_tag =
1436                         le16_to_cpu(
1437                                 info_v11->extdispconninfo.path[i].device_tag);
1438                 info->ext_disp_conn_info.path[i].device_acpi_enum =
1439                 le16_to_cpu(
1440                         info_v11->extdispconninfo.path[i].device_acpi_enum);
1441                 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
1442                         info_v11->extdispconninfo.path[i].auxddclut_index;
1443                 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
1444                         info_v11->extdispconninfo.path[i].hpdlut_index;
1445                 info->ext_disp_conn_info.path[i].channel_mapping.raw =
1446                         info_v11->extdispconninfo.path[i].channelmapping;
1447                 info->ext_disp_conn_info.path[i].caps =
1448                                 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
1449         }
1450         info->ext_disp_conn_info.checksum =
1451         info_v11->extdispconninfo.checksum;
1452 
1453         info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
1454         info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
1455         for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
1456                 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
1457                                 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1458                 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
1459                                 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1460         }
1461         info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
1462         for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
1463                 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1464                                 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1465                 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1466                                 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1467         }
1468 
1469         info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
1470         info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
1471         for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
1472                 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
1473                                 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1474                 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
1475                                 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1476         }
1477         info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
1478         for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
1479                 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1480                                 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1481                 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1482                                 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1483         }
1484 
1485         info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
1486         info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
1487         for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
1488                 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
1489                                 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1490                 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
1491                                 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1492         }
1493         info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
1494         for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
1495                 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1496                                 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1497                 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1498                                 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1499         }
1500 
1501         info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
1502         info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
1503         for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
1504                 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
1505                                 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
1506                 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
1507                                 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
1508         }
1509         info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
1510         for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
1511                 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
1512                                 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
1513                 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
1514                                 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
1515         }
1516 
1517 
1518         /** TODO - review **/
1519         #if 0
1520         info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
1521                                                                         * 10;
1522         info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
1523         info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
1524 
1525         for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1526                 /* Convert [10KHz] into [KHz] */
1527                 info->disp_clk_voltage[i].max_supported_clk =
1528                 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
1529                         ulMaximumSupportedCLK) * 10;
1530                 info->disp_clk_voltage[i].voltage_index =
1531                 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
1532         }
1533 
1534         info->boot_up_req_display_vector =
1535                         le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
1536         info->boot_up_nb_voltage =
1537                         le16_to_cpu(info_v11->usBootUpNBVoltage);
1538         info->ext_disp_conn_info_offset =
1539                         le16_to_cpu(info_v11->usExtDispConnInfoOffset);
1540         info->gmc_restore_reset_time =
1541                         le32_to_cpu(info_v11->ulGMCRestoreResetTime);
1542         info->minimum_n_clk =
1543                         le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
1544         for (i = 1; i < 4; ++i)
1545                 info->minimum_n_clk =
1546                                 info->minimum_n_clk <
1547                                 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
1548                                 info->minimum_n_clk : le32_to_cpu(
1549                                         info_v11->ulNbpStateNClkFreq[i]);
1550 
1551         info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
1552         info->ddr_dll_power_up_time =
1553             le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
1554         info->ddr_pll_power_up_time =
1555                 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
1556         info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
1557         info->max_lvds_pclk_freq_in_single_link =
1558                 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1559         info->max_lvds_pclk_freq_in_single_link =
1560                 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
1561         info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
1562                 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
1563         info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
1564                 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
1565         info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
1566                 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
1567         info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
1568                 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
1569         info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
1570                 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
1571         info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
1572                 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
1573         info->lvds_off_to_on_delay_in_4ms =
1574                 info_v11->ucLVDSOffToOnDelay_in4Ms;
1575         info->lvds_bit_depth_control_val =
1576                 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
1577 
1578         for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
1579                 /* Convert [10KHz] into [KHz] */
1580                 info->avail_s_clk[i].supported_s_clk =
1581                         le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
1582                                                                         * 10;
1583                 info->avail_s_clk[i].voltage_index =
1584                         le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
1585                 info->avail_s_clk[i].voltage_id =
1586                         le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
1587         }
1588         #endif /* TODO*/
1589 
1590         return BP_RESULT_OK;
1591 }
1592 
1593 
1594 /*
1595  * construct_integrated_info
1596  *
1597  * @brief
1598  * Get integrated BIOS information based on table revision
1599  *
1600  * @param
1601  * bios_parser *bp - [in]BIOS parser handler to get master data table
1602  * integrated_info *info - [out] store and output integrated info
1603  *
1604  * @return
1605  * enum bp_result - BP_RESULT_OK if information is available,
1606  *                  BP_RESULT_BADBIOSTABLE otherwise.
1607  */
1608 static enum bp_result construct_integrated_info(
1609         struct bios_parser *bp,
1610         struct integrated_info *info)
1611 {
1612         enum bp_result result = BP_RESULT_BADBIOSTABLE;
1613 
1614         struct atom_common_table_header *header;
1615         struct atom_data_revision revision;
1616 
1617         struct clock_voltage_caps temp = {0, 0};
1618         uint32_t i;
1619         uint32_t j;
1620 
1621         if (info && DATA_TABLES(integratedsysteminfo)) {
1622                 header = GET_IMAGE(struct atom_common_table_header,
1623                                         DATA_TABLES(integratedsysteminfo));
1624 
1625                 get_atom_data_table_revision(header, &revision);
1626 
1627                 /* Don't need to check major revision as they are all 1 */
1628                 switch (revision.minor) {
1629                 case 11:
1630                         result = get_integrated_info_v11(bp, info);
1631                         break;
1632                 default:
1633                         return result;
1634                 }
1635         }
1636 
1637         if (result != BP_RESULT_OK)
1638                 return result;
1639 
1640         /* Sort voltage table from low to high*/
1641         for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
1642                 for (j = i; j > 0; --j) {
1643                         if (info->disp_clk_voltage[j].max_supported_clk <
1644                                 info->disp_clk_voltage[j-1].max_supported_clk
1645                                 ) {
1646                                 /* swap j and j - 1*/
1647                                 temp = info->disp_clk_voltage[j-1];
1648                                 info->disp_clk_voltage[j-1] =
1649                                         info->disp_clk_voltage[j];
1650                                 info->disp_clk_voltage[j] = temp;
1651                         }
1652                 }
1653         }
1654 
1655         return result;
1656 }
1657 
1658 static struct integrated_info *bios_parser_create_integrated_info(
1659         struct dc_bios *dcb)
1660 {
1661         struct bios_parser *bp = BP_FROM_DCB(dcb);
1662         struct integrated_info *info = NULL;
1663 
1664         info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
1665 
1666         if (info == NULL) {
1667                 ASSERT_CRITICAL(0);
1668                 return NULL;
1669         }
1670 
1671         if (construct_integrated_info(bp, info) == BP_RESULT_OK)
1672                 return info;
1673 
1674         kfree(info);
1675 
1676         return NULL;
1677 }
1678 
1679 static enum bp_result update_slot_layout_info(
1680         struct dc_bios *dcb,
1681         unsigned int i,
1682         struct slot_layout_info *slot_layout_info)
1683 {
1684         unsigned int record_offset;
1685         unsigned int j;
1686         struct atom_display_object_path_v2 *object;
1687         struct atom_bracket_layout_record *record;
1688         struct atom_common_record_header *record_header;
1689         enum bp_result result;
1690         struct bios_parser *bp;
1691         struct object_info_table *tbl;
1692         struct display_object_info_table_v1_4 *v1_4;
1693 
1694         record = NULL;
1695         record_header = NULL;
1696         result = BP_RESULT_NORECORD;
1697 
1698         bp = BP_FROM_DCB(dcb);
1699         tbl = &bp->object_info_tbl;
1700         v1_4 = tbl->v1_4;
1701 
1702         object = &v1_4->display_path[i];
1703         record_offset = (unsigned int)
1704                 (object->disp_recordoffset) +
1705                 (unsigned int)(bp->object_info_tbl_offset);
1706 
1707         for (;;) {
1708 
1709                 record_header = (struct atom_common_record_header *)
1710                         GET_IMAGE(struct atom_common_record_header,
1711                         record_offset);
1712                 if (record_header == NULL) {
1713                         result = BP_RESULT_BADBIOSTABLE;
1714                         break;
1715                 }
1716 
1717                 /* the end of the list */
1718                 if (record_header->record_type == 0xff ||
1719                         record_header->record_size == 0)        {
1720                         break;
1721                 }
1722 
1723                 if (record_header->record_type ==
1724                         ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
1725                         sizeof(struct atom_bracket_layout_record)
1726                         <= record_header->record_size) {
1727                         record = (struct atom_bracket_layout_record *)
1728                                 (record_header);
1729                         result = BP_RESULT_OK;
1730                         break;
1731                 }
1732 
1733                 record_offset += record_header->record_size;
1734         }
1735 
1736         /* return if the record not found */
1737         if (result != BP_RESULT_OK)
1738                 return result;
1739 
1740         /* get slot sizes */
1741         slot_layout_info->length = record->bracketlen;
1742         slot_layout_info->width = record->bracketwidth;
1743 
1744         /* get info for each connector in the slot */
1745         slot_layout_info->num_of_connectors = record->conn_num;
1746         for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
1747                 slot_layout_info->connectors[j].connector_type =
1748                         (enum connector_layout_type)
1749                         (record->conn_info[j].connector_type);
1750                 switch (record->conn_info[j].connector_type) {
1751                 case CONNECTOR_TYPE_DVI_D:
1752                         slot_layout_info->connectors[j].connector_type =
1753                                 CONNECTOR_LAYOUT_TYPE_DVI_D;
1754                         slot_layout_info->connectors[j].length =
1755                                 CONNECTOR_SIZE_DVI;
1756                         break;
1757 
1758                 case CONNECTOR_TYPE_HDMI:
1759                         slot_layout_info->connectors[j].connector_type =
1760                                 CONNECTOR_LAYOUT_TYPE_HDMI;
1761                         slot_layout_info->connectors[j].length =
1762                                 CONNECTOR_SIZE_HDMI;
1763                         break;
1764 
1765                 case CONNECTOR_TYPE_DISPLAY_PORT:
1766                         slot_layout_info->connectors[j].connector_type =
1767                                 CONNECTOR_LAYOUT_TYPE_DP;
1768                         slot_layout_info->connectors[j].length =
1769                                 CONNECTOR_SIZE_DP;
1770                         break;
1771 
1772                 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
1773                         slot_layout_info->connectors[j].connector_type =
1774                                 CONNECTOR_LAYOUT_TYPE_MINI_DP;
1775                         slot_layout_info->connectors[j].length =
1776                                 CONNECTOR_SIZE_MINI_DP;
1777                         break;
1778 
1779                 default:
1780                         slot_layout_info->connectors[j].connector_type =
1781                                 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
1782                         slot_layout_info->connectors[j].length =
1783                                 CONNECTOR_SIZE_UNKNOWN;
1784                 }
1785 
1786                 slot_layout_info->connectors[j].position =
1787                         record->conn_info[j].position;
1788                 slot_layout_info->connectors[j].connector_id =
1789                         object_id_from_bios_object_id(
1790                                 record->conn_info[j].connectorobjid);
1791         }
1792         return result;
1793 }
1794 
1795 
1796 static enum bp_result get_bracket_layout_record(
1797         struct dc_bios *dcb,
1798         unsigned int bracket_layout_id,
1799         struct slot_layout_info *slot_layout_info)
1800 {
1801         unsigned int i;
1802         struct bios_parser *bp = BP_FROM_DCB(dcb);
1803         enum bp_result result;
1804         struct object_info_table *tbl;
1805         struct display_object_info_table_v1_4 *v1_4;
1806 
1807         if (slot_layout_info == NULL) {
1808                 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
1809                 return BP_RESULT_BADINPUT;
1810         }
1811         tbl = &bp->object_info_tbl;
1812         v1_4 = tbl->v1_4;
1813 
1814         result = BP_RESULT_NORECORD;
1815         for (i = 0; i < v1_4->number_of_path; ++i)      {
1816 
1817                 if (bracket_layout_id ==
1818                         v1_4->display_path[i].display_objid) {
1819                         result = update_slot_layout_info(dcb, i,
1820                                 slot_layout_info);
1821                         break;
1822                 }
1823         }
1824         return result;
1825 }
1826 
1827 static enum bp_result bios_get_board_layout_info(
1828         struct dc_bios *dcb,
1829         struct board_layout_info *board_layout_info)
1830 {
1831         unsigned int i;
1832         struct bios_parser *bp;
1833         enum bp_result record_result;
1834 
1835         const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
1836                 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
1837                 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
1838                 0, 0
1839         };
1840 
1841         bp = BP_FROM_DCB(dcb);
1842         if (board_layout_info == NULL) {
1843                 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
1844                 return BP_RESULT_BADINPUT;
1845         }
1846 
1847         board_layout_info->num_of_slots = 0;
1848 
1849         for (i = 0; i < MAX_BOARD_SLOTS; ++i) {
1850                 record_result = get_bracket_layout_record(dcb,
1851                         slot_index_to_vbios_id[i],
1852                         &board_layout_info->slots[i]);
1853 
1854                 if (record_result == BP_RESULT_NORECORD && i > 0)
1855                         break; /* no more slots present in bios */
1856                 else if (record_result != BP_RESULT_OK)
1857                         return record_result;  /* fail */
1858 
1859                 ++board_layout_info->num_of_slots;
1860         }
1861 
1862         /* all data is valid */
1863         board_layout_info->is_number_of_slots_valid = 1;
1864         board_layout_info->is_slots_size_valid = 1;
1865         board_layout_info->is_connector_offsets_valid = 1;
1866         board_layout_info->is_connector_lengths_valid = 1;
1867 
1868         return BP_RESULT_OK;
1869 }
1870 
1871 static const struct dc_vbios_funcs vbios_funcs = {
1872         .get_connectors_number = bios_parser_get_connectors_number,
1873 
1874         .get_connector_id = bios_parser_get_connector_id,
1875 
1876         .get_src_obj = bios_parser_get_src_obj,
1877 
1878         .get_i2c_info = bios_parser_get_i2c_info,
1879 
1880         .get_hpd_info = bios_parser_get_hpd_info,
1881 
1882         .get_device_tag = bios_parser_get_device_tag,
1883 
1884         .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
1885 
1886         .get_ss_entry_number = bios_parser_get_ss_entry_number,
1887 
1888         .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
1889 
1890         .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
1891 
1892         .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
1893 
1894         .is_device_id_supported = bios_parser_is_device_id_supported,
1895 
1896         .is_accelerated_mode = bios_parser_is_accelerated_mode,
1897 
1898         .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
1899 
1900 
1901 /*       COMMANDS */
1902         .encoder_control = bios_parser_encoder_control,
1903 
1904         .transmitter_control = bios_parser_transmitter_control,
1905 
1906         .enable_crtc = bios_parser_enable_crtc,
1907 
1908         .set_pixel_clock = bios_parser_set_pixel_clock,
1909 
1910         .set_dce_clock = bios_parser_set_dce_clock,
1911 
1912         .program_crtc_timing = bios_parser_program_crtc_timing,
1913 
1914         .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
1915 
1916         .bios_parser_destroy = firmware_parser_destroy,
1917 
1918         .get_board_layout_info = bios_get_board_layout_info,
1919 };
1920 
1921 static bool bios_parser_construct(
1922         struct bios_parser *bp,
1923         struct bp_init_data *init,
1924         enum dce_version dce_version)
1925 {
1926         uint16_t *rom_header_offset = NULL;
1927         struct atom_rom_header_v2_2 *rom_header = NULL;
1928         struct display_object_info_table_v1_4 *object_info_tbl;
1929         struct atom_data_revision tbl_rev = {0};
1930 
1931         if (!init)
1932                 return false;
1933 
1934         if (!init->bios)
1935                 return false;
1936 
1937         bp->base.funcs = &vbios_funcs;
1938         bp->base.bios = init->bios;
1939         bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
1940 
1941         bp->base.ctx = init->ctx;
1942 
1943         bp->base.bios_local_image = NULL;
1944 
1945         rom_header_offset =
1946                         GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
1947 
1948         if (!rom_header_offset)
1949                 return false;
1950 
1951         rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
1952 
1953         if (!rom_header)
1954                 return false;
1955 
1956         get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
1957         if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
1958                 return false;
1959 
1960         bp->master_data_tbl =
1961                 GET_IMAGE(struct atom_master_data_table_v2_1,
1962                                 rom_header->masterdatatable_offset);
1963 
1964         if (!bp->master_data_tbl)
1965                 return false;
1966 
1967         bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
1968 
1969         if (!bp->object_info_tbl_offset)
1970                 return false;
1971 
1972         object_info_tbl =
1973                         GET_IMAGE(struct display_object_info_table_v1_4,
1974                                                 bp->object_info_tbl_offset);
1975 
1976         if (!object_info_tbl)
1977                 return false;
1978 
1979         get_atom_data_table_revision(&object_info_tbl->table_header,
1980                 &bp->object_info_tbl.revision);
1981 
1982         if (bp->object_info_tbl.revision.major == 1
1983                 && bp->object_info_tbl.revision.minor >= 4) {
1984                 struct display_object_info_table_v1_4 *tbl_v1_4;
1985 
1986                 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
1987                         bp->object_info_tbl_offset);
1988                 if (!tbl_v1_4)
1989                         return false;
1990 
1991                 bp->object_info_tbl.v1_4 = tbl_v1_4;
1992         } else
1993                 return false;
1994 
1995         dal_firmware_parser_init_cmd_tbl(bp);
1996         dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
1997 
1998         bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
1999         bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
2000 
2001         return true;
2002 }
2003 
2004 struct dc_bios *firmware_parser_create(
2005         struct bp_init_data *init,
2006         enum dce_version dce_version)
2007 {
2008         struct bios_parser *bp = NULL;
2009 
2010         bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
2011         if (!bp)
2012                 return NULL;
2013 
2014         if (bios_parser_construct(bp, init, dce_version))
2015                 return &bp->base;
2016 
2017         kfree(bp);
2018         return NULL;
2019 }
2020 
2021
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

DEFINITIONS
