drivers/gpu/drm/amd/display/dc/dc_hw

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   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef DC_HW_TYPES_H
  27 #define DC_HW_TYPES_H
  28 
  29 #include "os_types.h"
  30 #include "fixed31_32.h"
  31 #include "signal_types.h"
  32 
  33 /******************************************************************************
  34  * Data types for Virtual HW Layer of DAL3.
  35  * (see DAL3 design documents for HW Layer definition)
  36  *
  37  * The intended uses are:
  38  * 1. Generation pseudocode sequences for HW programming.
  39  * 2. Implementation of real HW programming by HW Sequencer of DAL3.
  40  *
  41  * Note: do *not* add any types which are *not* used for HW programming - this
  42  * will ensure separation of Logic layer from HW layer.
  43  ******************************************************************************/
  44 
  45 union large_integer {
  46         struct {
  47                 uint32_t low_part;
  48                 int32_t high_part;
  49         };
  50 
  51         struct {
  52                 uint32_t low_part;
  53                 int32_t high_part;
  54         } u;
  55 
  56         int64_t quad_part;
  57 };
  58 
  59 #define PHYSICAL_ADDRESS_LOC union large_integer
  60 
  61 enum dc_plane_addr_type {
  62         PLN_ADDR_TYPE_GRAPHICS = 0,
  63         PLN_ADDR_TYPE_GRPH_STEREO,
  64         PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
  65 };
  66 
  67 struct dc_plane_address {
  68         enum dc_plane_addr_type type;
  69         bool tmz_surface;
  70         union {
  71                 struct{
  72                         PHYSICAL_ADDRESS_LOC addr;
  73                         PHYSICAL_ADDRESS_LOC meta_addr;
  74                         union large_integer dcc_const_color;
  75                 } grph;
  76 
  77                 /*stereo*/
  78                 struct {
  79                         PHYSICAL_ADDRESS_LOC left_addr;
  80                         PHYSICAL_ADDRESS_LOC left_meta_addr;
  81                         union large_integer left_dcc_const_color;
  82 
  83                         PHYSICAL_ADDRESS_LOC right_addr;
  84                         PHYSICAL_ADDRESS_LOC right_meta_addr;
  85                         union large_integer right_dcc_const_color;
  86 
  87                 } grph_stereo;
  88 
  89                 /*video  progressive*/
  90                 struct {
  91                         PHYSICAL_ADDRESS_LOC luma_addr;
  92                         PHYSICAL_ADDRESS_LOC luma_meta_addr;
  93                         union large_integer luma_dcc_const_color;
  94 
  95                         PHYSICAL_ADDRESS_LOC chroma_addr;
  96                         PHYSICAL_ADDRESS_LOC chroma_meta_addr;
  97                         union large_integer chroma_dcc_const_color;
  98                 } video_progressive;
  99         };
 100 
 101         union large_integer page_table_base;
 102 
 103         uint8_t vmid;
 104 };
 105 
 106 struct dc_size {
 107         int width;
 108         int height;
 109 };
 110 
 111 struct rect {
 112         int x;
 113         int y;
 114         int width;
 115         int height;
 116 };
 117 
 118 struct plane_size {
 119         /* Graphic surface pitch in pixels.
 120          * In LINEAR_GENERAL mode, pitch
 121          * is 32 pixel aligned.
 122          */
 123         int surface_pitch;
 124         int chroma_pitch;
 125         struct rect surface_size;
 126         struct rect chroma_size;
 127 
 128         union {
 129                 struct {
 130                         struct rect surface_size;
 131                         int surface_pitch;
 132                 } grph;
 133 
 134                 struct {
 135                         struct rect luma_size;
 136                         int luma_pitch;
 137                         struct rect chroma_size;
 138                         int chroma_pitch;
 139                 } video;
 140         };
 141 };
 142 
 143 struct dc_plane_dcc_param {
 144         bool enable;
 145 
 146         int meta_pitch;
 147         bool independent_64b_blks;
 148 
 149         int meta_pitch_c;
 150         bool independent_64b_blks_c;
 151 
 152         union {
 153                 struct {
 154                         int meta_pitch;
 155                         bool independent_64b_blks;
 156                 } grph;
 157 
 158                 struct {
 159                         int meta_pitch_l;
 160                         bool independent_64b_blks_l;
 161 
 162                         int meta_pitch_c;
 163                         bool independent_64b_blks_c;
 164                 } video;
 165         };
 166 };
 167 
 168 /*Displayable pixel format in fb*/
 169 enum surface_pixel_format {
 170         SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
 171         /*TOBE REMOVED paletta 256 colors*/
 172         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
 173                 SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
 174         /*16 bpp*/
 175         SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
 176         /*16 bpp*/
 177         SURFACE_PIXEL_FORMAT_GRPH_RGB565,
 178         /*32 bpp*/
 179         SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
 180         /*32 bpp swaped*/
 181         SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
 182 
 183         SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
 184         /*swaped*/
 185         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
 186         /*TOBE REMOVED swaped, XR_BIAS has no differance
 187          * for pixel layout than previous and we can
 188          * delete this after discusion*/
 189         SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
 190         /*64 bpp */
 191         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
 192         /*float*/
 193         SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
 194         /*swaped & float*/
 195         SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
 196         /*grow graphics here if necessary */
 197 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 198         SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX,
 199         SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX,
 200         SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT,
 201         SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT,
 202 #endif
 203         SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 204         SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
 205                 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 206         SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
 207         SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
 208         SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
 209                 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
 210 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 211         SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010,
 212         SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102,
 213 #endif
 214         SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
 215         SURFACE_PIXEL_FORMAT_INVALID
 216 
 217         /*grow 444 video here if necessary */
 218 };
 219 
 220 
 221 
 222 /* Pixel format */
 223 enum pixel_format {
 224         /*graph*/
 225         PIXEL_FORMAT_UNINITIALIZED,
 226         PIXEL_FORMAT_INDEX8,
 227         PIXEL_FORMAT_RGB565,
 228         PIXEL_FORMAT_ARGB8888,
 229         PIXEL_FORMAT_ARGB2101010,
 230         PIXEL_FORMAT_ARGB2101010_XRBIAS,
 231         PIXEL_FORMAT_FP16,
 232         /*video*/
 233         PIXEL_FORMAT_420BPP8,
 234         PIXEL_FORMAT_420BPP10,
 235         /*end of pixel format definition*/
 236         PIXEL_FORMAT_INVALID,
 237 
 238         PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
 239         PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
 240         PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
 241         PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
 242         PIXEL_FORMAT_UNKNOWN
 243 };
 244 
 245 enum tile_split_values {
 246         DC_DISPLAY_MICRO_TILING = 0x0,
 247         DC_THIN_MICRO_TILING = 0x1,
 248         DC_DEPTH_MICRO_TILING = 0x2,
 249         DC_ROTATED_MICRO_TILING = 0x3,
 250 };
 251 
 252 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 253 enum tripleBuffer_enable {
 254         DC_TRIPLEBUFFER_DISABLE = 0x0,
 255         DC_TRIPLEBUFFER_ENABLE = 0x1,
 256 };
 257 #endif
 258 
 259 /* TODO: These values come from hardware spec. We need to readdress this
 260  * if they ever change.
 261  */
 262 enum array_mode_values {
 263         DC_ARRAY_LINEAR_GENERAL = 0,
 264         DC_ARRAY_LINEAR_ALLIGNED,
 265         DC_ARRAY_1D_TILED_THIN1,
 266         DC_ARRAY_1D_TILED_THICK,
 267         DC_ARRAY_2D_TILED_THIN1,
 268         DC_ARRAY_PRT_TILED_THIN1,
 269         DC_ARRAY_PRT_2D_TILED_THIN1,
 270         DC_ARRAY_2D_TILED_THICK,
 271         DC_ARRAY_2D_TILED_X_THICK,
 272         DC_ARRAY_PRT_TILED_THICK,
 273         DC_ARRAY_PRT_2D_TILED_THICK,
 274         DC_ARRAY_PRT_3D_TILED_THIN1,
 275         DC_ARRAY_3D_TILED_THIN1,
 276         DC_ARRAY_3D_TILED_THICK,
 277         DC_ARRAY_3D_TILED_X_THICK,
 278         DC_ARRAY_PRT_3D_TILED_THICK,
 279 };
 280 
 281 enum tile_mode_values {
 282         DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
 283         DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
 284 };
 285 
 286 enum swizzle_mode_values {
 287         DC_SW_LINEAR = 0,
 288         DC_SW_256B_S = 1,
 289         DC_SW_256_D = 2,
 290         DC_SW_256_R = 3,
 291         DC_SW_4KB_S = 5,
 292         DC_SW_4KB_D = 6,
 293         DC_SW_4KB_R = 7,
 294         DC_SW_64KB_S = 9,
 295         DC_SW_64KB_D = 10,
 296         DC_SW_64KB_R = 11,
 297         DC_SW_VAR_S = 13,
 298         DC_SW_VAR_D = 14,
 299         DC_SW_VAR_R = 15,
 300         DC_SW_64KB_S_T = 17,
 301         DC_SW_64KB_D_T = 18,
 302         DC_SW_4KB_S_X = 21,
 303         DC_SW_4KB_D_X = 22,
 304         DC_SW_4KB_R_X = 23,
 305         DC_SW_64KB_S_X = 25,
 306         DC_SW_64KB_D_X = 26,
 307         DC_SW_64KB_R_X = 27,
 308         DC_SW_VAR_S_X = 29,
 309         DC_SW_VAR_D_X = 30,
 310         DC_SW_VAR_R_X = 31,
 311         DC_SW_MAX = 32,
 312         DC_SW_UNKNOWN = DC_SW_MAX
 313 };
 314 
 315 union dc_tiling_info {
 316 
 317         struct {
 318                 /* Specifies the number of memory banks for tiling
 319                  *      purposes.
 320                  * Only applies to 2D and 3D tiling modes.
 321                  *      POSSIBLE VALUES: 2,4,8,16
 322                  */
 323                 unsigned int num_banks;
 324                 /* Specifies the number of tiles in the x direction
 325                  *      to be incorporated into the same bank.
 326                  * Only applies to 2D and 3D tiling modes.
 327                  *      POSSIBLE VALUES: 1,2,4,8
 328                  */
 329                 unsigned int bank_width;
 330                 unsigned int bank_width_c;
 331                 /* Specifies the number of tiles in the y direction to
 332                  *      be incorporated into the same bank.
 333                  * Only applies to 2D and 3D tiling modes.
 334                  *      POSSIBLE VALUES: 1,2,4,8
 335                  */
 336                 unsigned int bank_height;
 337                 unsigned int bank_height_c;
 338                 /* Specifies the macro tile aspect ratio. Only applies
 339                  * to 2D and 3D tiling modes.
 340                  */
 341                 unsigned int tile_aspect;
 342                 unsigned int tile_aspect_c;
 343                 /* Specifies the number of bytes that will be stored
 344                  *      contiguously for each tile.
 345                  * If the tile data requires more storage than this
 346                  *      amount, it is split into multiple slices.
 347                  * This field must not be larger than
 348                  *      GB_ADDR_CONFIG.DRAM_ROW_SIZE.
 349                  * Only applies to 2D and 3D tiling modes.
 350                  * For color render targets, TILE_SPLIT >= 256B.
 351                  */
 352                 enum tile_split_values tile_split;
 353                 enum tile_split_values tile_split_c;
 354                 /* Specifies the addressing within a tile.
 355                  *      0x0 - DISPLAY_MICRO_TILING
 356                  *      0x1 - THIN_MICRO_TILING
 357                  *      0x2 - DEPTH_MICRO_TILING
 358                  *      0x3 - ROTATED_MICRO_TILING
 359                  */
 360                 enum tile_mode_values tile_mode;
 361                 enum tile_mode_values tile_mode_c;
 362                 /* Specifies the number of pipes and how they are
 363                  *      interleaved in the surface.
 364                  * Refer to memory addressing document for complete
 365                  *      details and constraints.
 366                  */
 367                 unsigned int pipe_config;
 368                 /* Specifies the tiling mode of the surface.
 369                  * THIN tiles use an 8x8x1 tile size.
 370                  * THICK tiles use an 8x8x4 tile size.
 371                  * 2D tiling modes rotate banks for successive Z slices
 372                  * 3D tiling modes rotate pipes and banks for Z slices
 373                  * Refer to memory addressing document for complete
 374                  *      details and constraints.
 375                  */
 376                 enum array_mode_values array_mode;
 377         } gfx8;
 378 
 379         struct {
 380                 enum swizzle_mode_values swizzle;
 381                 unsigned int num_pipes;
 382                 unsigned int max_compressed_frags;
 383                 unsigned int pipe_interleave;
 384 
 385                 unsigned int num_banks;
 386                 unsigned int num_shader_engines;
 387                 unsigned int num_rb_per_se;
 388                 bool shaderEnable;
 389 
 390                 bool meta_linear;
 391                 bool rb_aligned;
 392                 bool pipe_aligned;
 393         } gfx9;
 394 };
 395 
 396 /* Rotation angle */
 397 enum dc_rotation_angle {
 398         ROTATION_ANGLE_0 = 0,
 399         ROTATION_ANGLE_90,
 400         ROTATION_ANGLE_180,
 401         ROTATION_ANGLE_270,
 402         ROTATION_ANGLE_COUNT
 403 };
 404 
 405 enum dc_scan_direction {
 406         SCAN_DIRECTION_UNKNOWN = 0,
 407         SCAN_DIRECTION_HORIZONTAL = 1,  /* 0, 180 rotation */
 408         SCAN_DIRECTION_VERTICAL = 2,    /* 90, 270 rotation */
 409 };
 410 
 411 struct dc_cursor_position {
 412         uint32_t x;
 413         uint32_t y;
 414 
 415         uint32_t x_hotspot;
 416         uint32_t y_hotspot;
 417 
 418         /*
 419          * This parameter indicates whether HW cursor should be enabled
 420          */
 421         bool enable;
 422 
 423 };
 424 
 425 struct dc_cursor_mi_param {
 426         unsigned int pixel_clk_khz;
 427         unsigned int ref_clk_khz;
 428         struct rect viewport;
 429         struct fixed31_32 h_scale_ratio;
 430         struct fixed31_32 v_scale_ratio;
 431         enum dc_rotation_angle rotation;
 432         bool mirror;
 433 };
 434 
 435 /* IPP related types */
 436 
 437 enum {
 438         GAMMA_RGB_256_ENTRIES = 256,
 439         GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
 440         GAMMA_CS_TFM_1D_ENTRIES = 4096,
 441         GAMMA_CUSTOM_ENTRIES = 4096,
 442         GAMMA_MAX_ENTRIES = 4096
 443 };
 444 
 445 enum dc_gamma_type {
 446         GAMMA_RGB_256 = 1,
 447         GAMMA_RGB_FLOAT_1024 = 2,
 448         GAMMA_CS_TFM_1D = 3,
 449         GAMMA_CUSTOM = 4,
 450 };
 451 
 452 struct dc_csc_transform {
 453         uint16_t matrix[12];
 454         bool enable_adjustment;
 455 };
 456 
 457 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 458 struct dc_rgb_fixed {
 459         struct fixed31_32 red;
 460         struct fixed31_32 green;
 461         struct fixed31_32 blue;
 462 };
 463 #endif
 464 
 465 struct dc_gamma {
 466         struct kref refcount;
 467         enum dc_gamma_type type;
 468         unsigned int num_entries;
 469 
 470         struct dc_gamma_entries {
 471                 struct fixed31_32 red[GAMMA_MAX_ENTRIES];
 472                 struct fixed31_32 green[GAMMA_MAX_ENTRIES];
 473                 struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
 474         } entries;
 475 
 476         /* private to DC core */
 477         struct dc_context *ctx;
 478 
 479         /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT.
 480          * is_logical_identity indicates the given gamma ramp regardless of type is identity.
 481          */
 482         bool is_identity;
 483 };
 484 
 485 /* Used by both ipp amd opp functions*/
 486 /* TODO: to be consolidated with enum color_space */
 487 
 488 /*
 489  * This enum is for programming CURSOR_MODE register field. What this register
 490  * should be programmed to depends on OS requested cursor shape flags and what
 491  * we stored in the cursor surface.
 492  */
 493 enum dc_cursor_color_format {
 494         CURSOR_MODE_MONO,
 495         CURSOR_MODE_COLOR_1BIT_AND,
 496         CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
 497         CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA,
 498 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 499         CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED,
 500         CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED
 501 #endif
 502 };
 503 
 504 /*
 505  * This is all the parameters required by DAL in order to update the cursor
 506  * attributes, including the new cursor image surface address, size, hotspot
 507  * location, color format, etc.
 508  */
 509 
 510 union dc_cursor_attribute_flags {
 511         struct {
 512                 uint32_t ENABLE_MAGNIFICATION:1;
 513                 uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
 514                 uint32_t HORIZONTAL_MIRROR:1;
 515                 uint32_t VERTICAL_MIRROR:1;
 516                 uint32_t INVERT_PIXEL_DATA:1;
 517                 uint32_t ZERO_EXPANSION:1;
 518                 uint32_t MIN_MAX_INVERT:1;
 519                 uint32_t ENABLE_CURSOR_DEGAMMA:1;
 520                 uint32_t RESERVED:24;
 521         } bits;
 522         uint32_t value;
 523 };
 524 
 525 struct dc_cursor_attributes {
 526         PHYSICAL_ADDRESS_LOC address;
 527         uint32_t pitch;
 528 
 529         /* Width and height should correspond to cursor surface width x heigh */
 530         uint32_t width;
 531         uint32_t height;
 532 
 533         enum dc_cursor_color_format color_format;
 534         uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
 535 
 536         /* In case we support HW Cursor rotation in the future */
 537         enum dc_rotation_angle rotation_angle;
 538 
 539         union dc_cursor_attribute_flags attribute_flags;
 540 };
 541 
 542 struct dpp_cursor_attributes {
 543         int bias;
 544         int scale;
 545 };
 546 
 547 /* OPP */
 548 
 549 enum dc_color_space {
 550         COLOR_SPACE_UNKNOWN,
 551         COLOR_SPACE_SRGB,
 552         COLOR_SPACE_XR_RGB,
 553         COLOR_SPACE_SRGB_LIMITED,
 554         COLOR_SPACE_MSREF_SCRGB,
 555         COLOR_SPACE_YCBCR601,
 556         COLOR_SPACE_YCBCR709,
 557         COLOR_SPACE_XV_YCC_709,
 558         COLOR_SPACE_XV_YCC_601,
 559         COLOR_SPACE_YCBCR601_LIMITED,
 560         COLOR_SPACE_YCBCR709_LIMITED,
 561         COLOR_SPACE_2020_RGB_FULLRANGE,
 562         COLOR_SPACE_2020_RGB_LIMITEDRANGE,
 563         COLOR_SPACE_2020_YCBCR,
 564         COLOR_SPACE_ADOBERGB,
 565         COLOR_SPACE_DCIP3,
 566         COLOR_SPACE_DISPLAYNATIVE,
 567         COLOR_SPACE_DOLBYVISION,
 568         COLOR_SPACE_APPCTRL,
 569         COLOR_SPACE_CUSTOMPOINTS,
 570         COLOR_SPACE_YCBCR709_BLACK,
 571 };
 572 
 573 enum dc_dither_option {
 574         DITHER_OPTION_DEFAULT,
 575         DITHER_OPTION_DISABLE,
 576         DITHER_OPTION_FM6,
 577         DITHER_OPTION_FM8,
 578         DITHER_OPTION_FM10,
 579         DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
 580         DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
 581         DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
 582         DITHER_OPTION_SPATIAL6,
 583         DITHER_OPTION_SPATIAL8,
 584         DITHER_OPTION_SPATIAL10,
 585         DITHER_OPTION_TRUN6,
 586         DITHER_OPTION_TRUN8,
 587         DITHER_OPTION_TRUN10,
 588         DITHER_OPTION_TRUN10_SPATIAL8,
 589         DITHER_OPTION_TRUN10_SPATIAL6,
 590         DITHER_OPTION_TRUN10_FM8,
 591         DITHER_OPTION_TRUN10_FM6,
 592         DITHER_OPTION_TRUN10_SPATIAL8_FM6,
 593         DITHER_OPTION_SPATIAL10_FM8,
 594         DITHER_OPTION_SPATIAL10_FM6,
 595         DITHER_OPTION_TRUN8_SPATIAL6,
 596         DITHER_OPTION_TRUN8_FM6,
 597         DITHER_OPTION_SPATIAL8_FM6,
 598         DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
 599         DITHER_OPTION_INVALID
 600 };
 601 
 602 enum dc_quantization_range {
 603         QUANTIZATION_RANGE_UNKNOWN,
 604         QUANTIZATION_RANGE_FULL,
 605         QUANTIZATION_RANGE_LIMITED
 606 };
 607 
 608 /* XFM */
 609 
 610 /* used in  struct dc_plane_state */
 611 struct scaling_taps {
 612         uint32_t v_taps;
 613         uint32_t h_taps;
 614         uint32_t v_taps_c;
 615         uint32_t h_taps_c;
 616         bool integer_scaling;
 617 };
 618 
 619 enum dc_timing_standard {
 620         DC_TIMING_STANDARD_UNDEFINED,
 621         DC_TIMING_STANDARD_DMT,
 622         DC_TIMING_STANDARD_GTF,
 623         DC_TIMING_STANDARD_CVT,
 624         DC_TIMING_STANDARD_CVT_RB,
 625         DC_TIMING_STANDARD_CEA770,
 626         DC_TIMING_STANDARD_CEA861,
 627         DC_TIMING_STANDARD_HDMI,
 628         DC_TIMING_STANDARD_TV_NTSC,
 629         DC_TIMING_STANDARD_TV_NTSC_J,
 630         DC_TIMING_STANDARD_TV_PAL,
 631         DC_TIMING_STANDARD_TV_PAL_M,
 632         DC_TIMING_STANDARD_TV_PAL_CN,
 633         DC_TIMING_STANDARD_TV_SECAM,
 634         DC_TIMING_STANDARD_EXPLICIT,
 635         /*!< For explicit timings from EDID, VBIOS, etc.*/
 636         DC_TIMING_STANDARD_USER_OVERRIDE,
 637         /*!< For mode timing override by user*/
 638         DC_TIMING_STANDARD_MAX
 639 };
 640 
 641 enum dc_color_depth {
 642         COLOR_DEPTH_UNDEFINED,
 643         COLOR_DEPTH_666,
 644         COLOR_DEPTH_888,
 645         COLOR_DEPTH_101010,
 646         COLOR_DEPTH_121212,
 647         COLOR_DEPTH_141414,
 648         COLOR_DEPTH_161616,
 649 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 650         COLOR_DEPTH_999,
 651         COLOR_DEPTH_111111,
 652 #endif
 653         COLOR_DEPTH_COUNT
 654 };
 655 
 656 enum dc_pixel_encoding {
 657         PIXEL_ENCODING_UNDEFINED,
 658         PIXEL_ENCODING_RGB,
 659         PIXEL_ENCODING_YCBCR422,
 660         PIXEL_ENCODING_YCBCR444,
 661         PIXEL_ENCODING_YCBCR420,
 662         PIXEL_ENCODING_COUNT
 663 };
 664 
 665 enum dc_aspect_ratio {
 666         ASPECT_RATIO_NO_DATA,
 667         ASPECT_RATIO_4_3,
 668         ASPECT_RATIO_16_9,
 669         ASPECT_RATIO_64_27,
 670         ASPECT_RATIO_256_135,
 671         ASPECT_RATIO_FUTURE
 672 };
 673 
 674 enum scanning_type {
 675         SCANNING_TYPE_NODATA = 0,
 676         SCANNING_TYPE_OVERSCAN,
 677         SCANNING_TYPE_UNDERSCAN,
 678         SCANNING_TYPE_FUTURE,
 679         SCANNING_TYPE_UNDEFINED
 680 };
 681 
 682 struct dc_crtc_timing_flags {
 683         uint32_t INTERLACE :1;
 684         uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 685          it is positive polarity --reversed with dal1 or video bios define*/
 686         uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
 687          it is positive polarity --reversed with dal1 or video bios define*/
 688 
 689         uint32_t HORZ_COUNT_BY_TWO:1;
 690 
 691         uint32_t EXCLUSIVE_3D :1; /* if this bit set,
 692          timing can be driven in 3D format only
 693          and there is no corresponding 2D timing*/
 694         uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
 695          (right eye = '1', left eye = '0') */
 696         uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
 697          when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
 698         uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
 699          because corresponding 2D timing also present in the list*/
 700         uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
 701          and we want to match priority of corresponding 3D timing*/
 702         uint32_t Y_ONLY :1;
 703 
 704         uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
 705         uint32_t DTD_COUNTER :5; /* values 1 to 16 */
 706 
 707         uint32_t FORCE_HDR :1;
 708 
 709         /* HDMI 2.0 - Support scrambling for TMDS character
 710          * rates less than or equal to 340Mcsc */
 711         uint32_t LTE_340MCSC_SCRAMBLE:1;
 712 
 713 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 714         uint32_t DSC : 1; /* Use DSC with this timing */
 715 #endif
 716 };
 717 
 718 enum dc_timing_3d_format {
 719         TIMING_3D_FORMAT_NONE,
 720         TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
 721         TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
 722         TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
 723         /* for active DP-HDMI dongle*/
 724         TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
 725         TIMING_3D_FORMAT_HW_FRAME_PACKING,
 726         TIMING_3D_FORMAT_SW_FRAME_PACKING,
 727         TIMING_3D_FORMAT_ROW_INTERLEAVE,
 728         TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
 729         TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
 730         TIMING_3D_FORMAT_SIDE_BY_SIDE,
 731         TIMING_3D_FORMAT_TOP_AND_BOTTOM,
 732         TIMING_3D_FORMAT_SBS_SW_PACKED,
 733         /* Side-by-side, packed by application/driver into 2D frame*/
 734         TIMING_3D_FORMAT_TB_SW_PACKED,
 735         /* Top-and-bottom, packed by application/driver into 2D frame*/
 736 
 737         TIMING_3D_FORMAT_MAX,
 738 };
 739 
 740 enum trigger_delay {
 741         TRIGGER_DELAY_NEXT_PIXEL = 0,
 742         TRIGGER_DELAY_NEXT_LINE,
 743 };
 744 
 745 enum crtc_event {
 746         CRTC_EVENT_VSYNC_RISING = 0,
 747         CRTC_EVENT_VSYNC_FALLING
 748 };
 749 
 750 struct crtc_trigger_info {
 751         bool enabled;
 752         struct dc_stream_state *event_source;
 753         enum crtc_event event;
 754         enum trigger_delay delay;
 755 };
 756 
 757 struct dc_crtc_timing_adjust {
 758         uint32_t v_total_min;
 759         uint32_t v_total_max;
 760         uint32_t v_total_mid;
 761         uint32_t v_total_mid_frame_num;
 762 };
 763 
 764 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 765 struct dc_dsc_config {
 766         uint32_t num_slices_h; /* Number of DSC slices - horizontal */
 767         uint32_t num_slices_v; /* Number of DSC slices - vertical */
 768         uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
 769         bool block_pred_enable; /* DSC block prediction enable */
 770         uint32_t linebuf_depth; /* DSC line buffer depth */
 771         uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
 772         bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
 773         int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
 774 };
 775 #endif
 776 struct dc_crtc_timing {
 777         uint32_t h_total;
 778         uint32_t h_border_left;
 779         uint32_t h_addressable;
 780         uint32_t h_border_right;
 781         uint32_t h_front_porch;
 782         uint32_t h_sync_width;
 783 
 784         uint32_t v_total;
 785         uint32_t v_border_top;
 786         uint32_t v_addressable;
 787         uint32_t v_border_bottom;
 788         uint32_t v_front_porch;
 789         uint32_t v_sync_width;
 790 
 791         uint32_t pix_clk_100hz;
 792 
 793         uint32_t vic;
 794         uint32_t hdmi_vic;
 795         enum dc_timing_3d_format timing_3d_format;
 796         enum dc_color_depth display_color_depth;
 797         enum dc_pixel_encoding pixel_encoding;
 798         enum dc_aspect_ratio aspect_ratio;
 799         enum scanning_type scan_type;
 800 
 801         struct dc_crtc_timing_flags flags;
 802 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 803         struct dc_dsc_config dsc_cfg;
 804 #endif
 805 };
 806 
 807 /* Passed on init */
 808 enum vram_type {
 809         VIDEO_MEMORY_TYPE_GDDR5  = 2,
 810         VIDEO_MEMORY_TYPE_DDR3   = 3,
 811         VIDEO_MEMORY_TYPE_DDR4   = 4,
 812         VIDEO_MEMORY_TYPE_HBM    = 5,
 813         VIDEO_MEMORY_TYPE_GDDR6  = 6,
 814 };
 815 
 816 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 817 enum dwb_cnv_out_bpc {
 818         DWB_CNV_OUT_BPC_8BPC  = 0,
 819         DWB_CNV_OUT_BPC_10BPC = 1,
 820 };
 821 
 822 enum dwb_output_depth {
 823         DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0,
 824         DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1,
 825 };
 826 
 827 enum dwb_capture_rate {
 828         dwb_capture_rate_0 = 0, /* Every frame is captured. */
 829         dwb_capture_rate_1 = 1, /* Every other frame is captured. */
 830         dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */
 831         dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */
 832 };
 833 
 834 enum dwb_scaler_mode {
 835         dwb_scaler_mode_bypass444 = 0,
 836         dwb_scaler_mode_rgb444 = 1,
 837         dwb_scaler_mode_yuv444 = 2,
 838         dwb_scaler_mode_yuv420 = 3
 839 };
 840 
 841 enum dwb_subsample_position {
 842         DWB_INTERSTITIAL_SUBSAMPLING = 0,
 843         DWB_COSITED_SUBSAMPLING      = 1
 844 };
 845 
 846 enum dwb_stereo_eye_select {
 847         DWB_STEREO_EYE_LEFT  = 1,               /* Capture left eye only */
 848         DWB_STEREO_EYE_RIGHT = 2,               /* Capture right eye only */
 849 };
 850 
 851 enum dwb_stereo_type {
 852         DWB_STEREO_TYPE_FRAME_PACKING = 0,              /* Frame packing */
 853         DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3,   /* Frame sequential */
 854 };
 855 
 856 #define MCIF_BUF_COUNT  4
 857 
 858 struct mcif_buf_params {
 859         unsigned long long      luma_address[MCIF_BUF_COUNT];
 860         unsigned long long      chroma_address[MCIF_BUF_COUNT];
 861         unsigned int            luma_pitch;
 862         unsigned int            chroma_pitch;
 863         unsigned int            warmup_pitch;
 864         unsigned int            swlock;
 865 };
 866 
 867 #endif
 868 
 869 #define MAX_TG_COLOR_VALUE 0x3FF
 870 struct tg_color {
 871         /* Maximum 10 bits color value */
 872         uint16_t color_r_cr;
 873         uint16_t color_g_y;
 874         uint16_t color_b_cb;
 875 };
 876 
 877 #endif /* DC_HW_TYPES_H */
 878
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root/drivers/gpu/drm/amd/display/dc/dc_hw_types.h

INCLUDED FROM
