drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
dentist_get_divider_from_did
dce_adjust_dp_ref_freq_for_ss
dce_get_dp_ref_freq_khz
dce12_get_dp_ref_freq_khz
dce_get_max_pixel_clock_for_all_paths
dce_get_required_clocks_state
dce_set_clock
dce_clock_read_integrated_info
dce_clock_read_ss_info
dce_pplib_apply_display_requirements
dce_update_clocks
dce_clk_mgr_construct
   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 
  27 #include "dccg.h"
  28 #include "clk_mgr_internal.h"
  29 #include "dce_clk_mgr.h"
  30 #include "dce110/dce110_clk_mgr.h"
  31 #include "dce112/dce112_clk_mgr.h"
  32 #include "reg_helper.h"
  33 #include "dmcu.h"
  34 #include "core_types.h"
  35 #include "dal_asic_id.h"
  36 
  37 /*
  38  * Currently the register shifts and masks in this file are used for dce100 and dce80
  39  * which has identical definitions.
  40  * TODO: remove this when DPREFCLK_CNTL and dpref DENTIST_DISPCLK_CNTL
  41  * is moved to dccg, where it belongs
  42  */
  43 #include "dce/dce_8_0_d.h"
  44 #include "dce/dce_8_0_sh_mask.h"
  45 
  46 #define REG(reg) \
  47         (clk_mgr->regs->reg)
  48 
  49 #undef FN
  50 #define FN(reg_name, field_name) \
  51         clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
  52 
  53 static const struct clk_mgr_registers disp_clk_regs = {
  54                 CLK_COMMON_REG_LIST_DCE_BASE()
  55 };
  56 
  57 static const struct clk_mgr_shift disp_clk_shift = {
  58                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
  59 };
  60 
  61 static const struct clk_mgr_mask disp_clk_mask = {
  62                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
  63 };
  64 
  65 
  66 /* Max clock values for each state indexed by "enum clocks_state": */
  67 static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
  68 /* ClocksStateInvalid - should not be used */
  69 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
  70 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
  71 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
  72 /* ClocksStateLow */
  73 { .display_clk_khz = 352000, .pixel_clk_khz = 330000},
  74 /* ClocksStateNominal */
  75 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
  76 /* ClocksStatePerformance */
  77 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
  78 
  79 int dentist_get_divider_from_did(int did)
  80 {
  81         if (did < DENTIST_BASE_DID_1)
  82                 did = DENTIST_BASE_DID_1;
  83         if (did > DENTIST_MAX_DID)
  84                 did = DENTIST_MAX_DID;
  85 
  86         if (did < DENTIST_BASE_DID_2) {
  87                 return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
  88                                                         * (did - DENTIST_BASE_DID_1);
  89         } else if (did < DENTIST_BASE_DID_3) {
  90                 return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
  91                                                         * (did - DENTIST_BASE_DID_2);
  92         } else if (did < DENTIST_BASE_DID_4) {
  93                 return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
  94                                                         * (did - DENTIST_BASE_DID_3);
  95         } else {
  96                 return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
  97                                                         * (did - DENTIST_BASE_DID_4);
  98         }
  99 }
 100 
 101 /* SW will adjust DP REF Clock average value for all purposes
 102  * (DP DTO / DP Audio DTO and DP GTC)
 103  if clock is spread for all cases:
 104  -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
 105  calculations for DS_INCR/DS_MODULO (this is planned to be default case)
 106  -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
 107  calculations (not planned to be used, but average clock should still
 108  be valid)
 109  -if SS enabled on DP Ref clock and HW de-spreading disabled
 110  (should not be case with CIK) then SW should program all rates
 111  generated according to average value (case as with previous ASICs)
 112   */
 113 
 114 int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz)
 115 {
 116         if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
 117                 struct fixed31_32 ss_percentage = dc_fixpt_div_int(
 118                                 dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
 119                                                         clk_mgr_dce->dprefclk_ss_divider), 200);
 120                 struct fixed31_32 adj_dp_ref_clk_khz;
 121 
 122                 ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
 123                 adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
 124                 dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
 125         }
 126         return dp_ref_clk_khz;
 127 }
 128 
 129 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
 130 {
 131         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 132         int dprefclk_wdivider;
 133         int dprefclk_src_sel;
 134         int dp_ref_clk_khz = 600000;
 135         int target_div;
 136 
 137         /* ASSERT DP Reference Clock source is from DFS*/
 138         REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
 139         ASSERT(dprefclk_src_sel == 0);
 140 
 141         /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
 142          * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
 143         REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
 144 
 145         /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
 146         target_div = dentist_get_divider_from_did(dprefclk_wdivider);
 147 
 148         /* Calculate the current DFS clock, in kHz.*/
 149         dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
 150                 * clk_mgr->dentist_vco_freq_khz) / target_div;
 151 
 152         return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
 153 }
 154 
 155 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
 156 {
 157         struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 158 
 159         return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
 160 }
 161 
 162 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
 163  * may not be programmed yet
 164  */
 165 uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context)
 166 {
 167         uint32_t max_pix_clk = 0;
 168         int i;
 169 
 170         for (i = 0; i < MAX_PIPES; i++) {
 171                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 172 
 173                 if (pipe_ctx->stream == NULL)
 174                         continue;
 175 
 176                 /* do not check under lay */
 177                 if (pipe_ctx->top_pipe)
 178                         continue;
 179 
 180                 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
 181                         max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
 182 
 183                 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
 184                  * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
 185                  */
 186                 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
 187                                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
 188                         max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
 189         }
 190 
 191         return max_pix_clk;
 192 }
 193 
 194 enum dm_pp_clocks_state dce_get_required_clocks_state(
 195         struct clk_mgr *clk_mgr_base,
 196         struct dc_state *context)
 197 {
 198         struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 199         int i;
 200         enum dm_pp_clocks_state low_req_clk;
 201         int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context);
 202 
 203         /* Iterate from highest supported to lowest valid state, and update
 204          * lowest RequiredState with the lowest state that satisfies
 205          * all required clocks
 206          */
 207         for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
 208                 if (context->bw_ctx.bw.dce.dispclk_khz >
 209                                 clk_mgr_dce->max_clks_by_state[i].display_clk_khz
 210                         || max_pix_clk >
 211                                 clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
 212                         break;
 213 
 214         low_req_clk = i + 1;
 215         if (low_req_clk > clk_mgr_dce->max_clks_state) {
 216                 /* set max clock state for high phyclock, invalid on exceeding display clock */
 217                 if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
 218                                 < context->bw_ctx.bw.dce.dispclk_khz)
 219                         low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
 220                 else
 221                         low_req_clk = clk_mgr_dce->max_clks_state;
 222         }
 223 
 224         return low_req_clk;
 225 }
 226 
 227 
 228 /* TODO: remove use the two broken down functions */
 229 int dce_set_clock(
 230         struct clk_mgr *clk_mgr_base,
 231         int requested_clk_khz)
 232 {
 233         struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 234         struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
 235         struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
 236         int actual_clock = requested_clk_khz;
 237         struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
 238 
 239         /* Make sure requested clock isn't lower than minimum threshold*/
 240         if (requested_clk_khz > 0)
 241                 requested_clk_khz = max(requested_clk_khz,
 242                                 clk_mgr_dce->dentist_vco_freq_khz / 64);
 243 
 244         /* Prepare to program display clock*/
 245         pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
 246         pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
 247 
 248         if (clk_mgr_dce->dfs_bypass_active)
 249                 pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
 250 
 251         bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
 252 
 253         if (clk_mgr_dce->dfs_bypass_active) {
 254                 /* Cache the fixed display clock*/
 255                 clk_mgr_dce->dfs_bypass_disp_clk =
 256                         pxl_clk_params.dfs_bypass_display_clock;
 257                 actual_clock = pxl_clk_params.dfs_bypass_display_clock;
 258         }
 259 
 260         /* from power down, we need mark the clock state as ClocksStateNominal
 261          * from HWReset, so when resume we will call pplib voltage regulator.*/
 262         if (requested_clk_khz == 0)
 263                 clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 264 
 265         if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
 266                 dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
 267 
 268         return actual_clock;
 269 }
 270 
 271 
 272 static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
 273 {
 274         struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
 275         struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
 276         int i;
 277 
 278         if (bp->integrated_info)
 279                 clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
 280         if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
 281                 clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
 282                 if (clk_mgr_dce->dentist_vco_freq_khz == 0)
 283                         clk_mgr_dce->dentist_vco_freq_khz = 3600000;
 284         }
 285 
 286         /*update the maximum display clock for each power state*/
 287         for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
 288                 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
 289 
 290                 switch (i) {
 291                 case 0:
 292                         clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
 293                         break;
 294 
 295                 case 1:
 296                         clk_state = DM_PP_CLOCKS_STATE_LOW;
 297                         break;
 298 
 299                 case 2:
 300                         clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
 301                         break;
 302 
 303                 case 3:
 304                         clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
 305                         break;
 306 
 307                 default:
 308                         clk_state = DM_PP_CLOCKS_STATE_INVALID;
 309                         break;
 310                 }
 311 
 312                 /*Do not allow bad VBIOS/SBIOS to override with invalid values,
 313                  * check for > 100MHz*/
 314                 if (bp->integrated_info)
 315                         if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
 316                                 clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
 317                                         bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
 318         }
 319 
 320         if (!debug->disable_dfs_bypass && bp->integrated_info)
 321                 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
 322                         clk_mgr_dce->dfs_bypass_enabled = true;
 323 }
 324 
 325 void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)
 326 {
 327         struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
 328         int ss_info_num = bp->funcs->get_ss_entry_number(
 329                         bp, AS_SIGNAL_TYPE_GPU_PLL);
 330 
 331         if (ss_info_num) {
 332                 struct spread_spectrum_info info = { { 0 } };
 333                 enum bp_result result = bp->funcs->get_spread_spectrum_info(
 334                                 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
 335 
 336                 /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
 337                  * even if SS not enabled and in that case
 338                  * SSInfo.spreadSpectrumPercentage !=0 would be sign
 339                  * that SS is enabled
 340                  */
 341                 if (result == BP_RESULT_OK &&
 342                                 info.spread_spectrum_percentage != 0) {
 343                         clk_mgr_dce->ss_on_dprefclk = true;
 344                         clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
 345 
 346                         if (info.type.CENTER_MODE == 0) {
 347                                 /* TODO: Currently for DP Reference clock we
 348                                  * need only SS percentage for
 349                                  * downspread */
 350                                 clk_mgr_dce->dprefclk_ss_percentage =
 351                                                 info.spread_spectrum_percentage;
 352                         }
 353 
 354                         return;
 355                 }
 356 
 357                 result = bp->funcs->get_spread_spectrum_info(
 358                                 bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
 359 
 360                 /* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
 361                  * even if SS not enabled and in that case
 362                  * SSInfo.spreadSpectrumPercentage !=0 would be sign
 363                  * that SS is enabled
 364                  */
 365                 if (result == BP_RESULT_OK &&
 366                                 info.spread_spectrum_percentage != 0) {
 367                         clk_mgr_dce->ss_on_dprefclk = true;
 368                         clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
 369 
 370                         if (info.type.CENTER_MODE == 0) {
 371                                 /* Currently for DP Reference clock we
 372                                  * need only SS percentage for
 373                                  * downspread */
 374                                 clk_mgr_dce->dprefclk_ss_percentage =
 375                                                 info.spread_spectrum_percentage;
 376                         }
 377                 }
 378         }
 379 }
 380 
 381 static void dce_pplib_apply_display_requirements(
 382         struct dc *dc,
 383         struct dc_state *context)
 384 {
 385         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
 386 
 387         pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
 388 
 389         dce110_fill_display_configs(context, pp_display_cfg);
 390 
 391         if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
 392                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
 393 }
 394 
 395 static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
 396                         struct dc_state *context,
 397                         bool safe_to_lower)
 398 {
 399         struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 400         struct dm_pp_power_level_change_request level_change_req;
 401         int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
 402 
 403         /*TODO: W/A for dal3 linux, investigate why this works */
 404         if (!clk_mgr_dce->dfs_bypass_active)
 405                 patched_disp_clk = patched_disp_clk * 115 / 100;
 406 
 407         level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
 408         /* get max clock state from PPLIB */
 409         if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
 410                         || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
 411                 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
 412                         clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
 413         }
 414 
 415         if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
 416                 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
 417                 clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
 418         }
 419         dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
 420 }
 421 
 422 
 423 
 424 
 425 
 426 
 427 
 428 
 429 static struct clk_mgr_funcs dce_funcs = {
 430         .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
 431         .update_clocks = dce_update_clocks
 432 };
 433 
 434 void dce_clk_mgr_construct(
 435                 struct dc_context *ctx,
 436                 struct clk_mgr_internal *clk_mgr)
 437 {
 438         struct clk_mgr *base = &clk_mgr->base;
 439         struct dm_pp_static_clock_info static_clk_info = {0};
 440 
 441         memcpy(clk_mgr->max_clks_by_state,
 442                 dce80_max_clks_by_state,
 443                 sizeof(dce80_max_clks_by_state));
 444 
 445         base->ctx = ctx;
 446         base->funcs = &dce_funcs;
 447 
 448         clk_mgr->regs = &disp_clk_regs;
 449         clk_mgr->clk_mgr_shift = &disp_clk_shift;
 450         clk_mgr->clk_mgr_mask = &disp_clk_mask;
 451         clk_mgr->dfs_bypass_disp_clk = 0;
 452 
 453         clk_mgr->dprefclk_ss_percentage = 0;
 454         clk_mgr->dprefclk_ss_divider = 1000;
 455         clk_mgr->ss_on_dprefclk = false;
 456 
 457         if (dm_pp_get_static_clocks(ctx, &static_clk_info))
 458                 clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
 459         else
 460                 clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 461         clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
 462 
 463         dce_clock_read_integrated_info(clk_mgr);
 464         dce_clock_read_ss_info(clk_mgr);
 465 }
 466
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

DEFINITIONS
