root/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

DEFINITIONS

1. rv1_vbios_smu_send_msg_with_param
2. rv1_vbios_smu_set_dispclk
3. rv1_vbios_smu_set_dprefclk

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include "core_types.h"
  27 #include "clk_mgr_internal.h"
  28 #include "reg_helper.h"
  29 
  30 #define MAX_INSTANCE    5
  31 #define MAX_SEGMENT             5
  32 
  33 struct IP_BASE_INSTANCE {
  34         unsigned int segment[MAX_SEGMENT];
  35 };
  36 
  37 struct IP_BASE {
  38         struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
  39 };
  40 
  41 
  42 static const struct IP_BASE MP1_BASE  = { { { { 0x00016000, 0, 0, 0, 0 } },
  43                                                                                          { { 0, 0, 0, 0, 0 } },
  44                                                                                          { { 0, 0, 0, 0, 0 } },
  45                                                                                          { { 0, 0, 0, 0, 0 } },
  46                                                                                          { { 0, 0, 0, 0, 0 } } } };
  47 
  48 #define mmMP1_SMN_C2PMSG_91            0x29B
  49 #define mmMP1_SMN_C2PMSG_83            0x293
  50 #define mmMP1_SMN_C2PMSG_67            0x283
  51 #define mmMP1_SMN_C2PMSG_91_BASE_IDX   0
  52 #define mmMP1_SMN_C2PMSG_83_BASE_IDX   0
  53 #define mmMP1_SMN_C2PMSG_67_BASE_IDX   0
  54 
  55 #define MP1_SMN_C2PMSG_91__CONTENT_MASK                    0xffffffffL
  56 #define MP1_SMN_C2PMSG_83__CONTENT_MASK                    0xffffffffL
  57 #define MP1_SMN_C2PMSG_67__CONTENT_MASK                    0xffffffffL
  58 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                  0x00000000
  59 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                  0x00000000
  60 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                  0x00000000
  61 
  62 #define REG(reg_name) \
  63         (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
  64 
  65 #define FN(reg_name, field) \
  66         FD(reg_name##__##field)
  67 
  68 #define VBIOSSMC_MSG_SetDispclkFreq           0x4
  69 #define VBIOSSMC_MSG_SetDprefclkFreq          0x5
  70 
  71 int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
  72 {
  73         /* First clear response register */
  74         REG_WRITE(MP1_SMN_C2PMSG_91, 0);
  75 
  76         /* Set the parameter register for the SMU message, unit is Mhz */
  77         REG_WRITE(MP1_SMN_C2PMSG_83, param);
  78 
  79         /* Trigger the message transaction by writing the message ID */
  80         REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
  81 
  82         REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000);
  83 
  84         /* Actual dispclk set is returned in the parameter register */
  85         return REG_READ(MP1_SMN_C2PMSG_83);
  86 }
  87 
  88 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
  89 {
  90         int actual_dispclk_set_mhz = -1;
  91         struct dc *core_dc = clk_mgr->base.ctx->dc;
  92         struct dmcu *dmcu = core_dc->res_pool->dmcu;
  93 
  94         /*  Unit of SMU msg parameter is Mhz */
  95         actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
  96                         clk_mgr,
  97                         VBIOSSMC_MSG_SetDispclkFreq,
  98                         requested_dispclk_khz / 1000);
  99 
 100         /* Actual dispclk set is returned in the parameter register */
 101         actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
 102 
 103         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
 104                 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
 105                         if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
 106                                 dmcu->funcs->set_psr_wait_loop(dmcu,
 107                                                 actual_dispclk_set_mhz / 7);
 108                 }
 109         }
 110 
 111         return actual_dispclk_set_mhz * 1000;
 112 }
 113 
 114 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
 115 {
 116         int actual_dprefclk_set_mhz = -1;
 117 
 118         actual_dprefclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
 119                         clk_mgr,
 120                         VBIOSSMC_MSG_SetDprefclkFreq,
 121                         clk_mgr->base.dprefclk_khz / 1000);
 122 
 123         /* TODO: add code for programing DP DTO, currently this is down by command table */
 124 
 125         return actual_dprefclk_set_mhz * 1000;
 126 }