root/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

DEFINITIONS

1. dentist_get_did_from_divider
2. dcn20_update_clocks_update_dpp_dto
3. update_global_dpp_clk
4. update_display_clk
5. request_voltage_and_program_disp_clk
6. request_voltage_and_program_global_dpp_clk
7. dcn2_update_clocks
8. dcn2_update_clocks_fpga
9. dcn2_init_clocks
10. dcn2_enable_pme_wa
11. dcn2_get_clock
12. dcn20_clk_mgr_construct

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include "dccg.h"
  27 #include "clk_mgr_internal.h"
  28 
  29 #include "dce100/dce_clk_mgr.h"
  30 #include "reg_helper.h"
  31 #include "core_types.h"
  32 #include "dm_helpers.h"
  33 
  34 #include "navi10_ip_offset.h"
  35 #include "dcn/dcn_2_0_0_offset.h"
  36 #include "dcn/dcn_2_0_0_sh_mask.h"
  37 #include "clk/clk_11_0_0_offset.h"
  38 #include "clk/clk_11_0_0_sh_mask.h"
  39 
  40 #undef FN
  41 #define FN(reg_name, field_name) \
  42         clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
  43 
  44 #define REG(reg) \
  45         (clk_mgr->regs->reg)
  46 
  47 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
  48 
  49 #define BASE(seg) BASE_INNER(seg)
  50 
  51 #define SR(reg_name)\
  52                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
  53                                         mm ## reg_name
  54 
  55 #define CLK_BASE_INNER(seg) \
  56         CLK_BASE__INST0_SEG ## seg
  57 
  58 
  59 static const struct clk_mgr_registers clk_mgr_regs = {
  60         CLK_REG_LIST_NV10()
  61 };
  62 
  63 static const struct clk_mgr_shift clk_mgr_shift = {
  64         CLK_MASK_SH_LIST_NV10(__SHIFT)
  65 };
  66 
  67 static const struct clk_mgr_mask clk_mgr_mask = {
  68         CLK_MASK_SH_LIST_NV10(_MASK)
  69 };
  70 
  71 uint32_t dentist_get_did_from_divider(int divider)
  72 {
  73         uint32_t divider_id;
  74 
  75         /* we want to floor here to get higher clock than required rather than lower */
  76         if (divider < DENTIST_DIVIDER_RANGE_2_START) {
  77                 if (divider < DENTIST_DIVIDER_RANGE_1_START)
  78                         divider_id = DENTIST_BASE_DID_1;
  79                 else
  80                         divider_id = DENTIST_BASE_DID_1
  81                                 + (divider - DENTIST_DIVIDER_RANGE_1_START)
  82                                         / DENTIST_DIVIDER_RANGE_1_STEP;
  83         } else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
  84                 divider_id = DENTIST_BASE_DID_2
  85                                 + (divider - DENTIST_DIVIDER_RANGE_2_START)
  86                                         / DENTIST_DIVIDER_RANGE_2_STEP;
  87         } else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
  88                 divider_id = DENTIST_BASE_DID_3
  89                                 + (divider - DENTIST_DIVIDER_RANGE_3_START)
  90                                         / DENTIST_DIVIDER_RANGE_3_STEP;
  91         } else {
  92                 divider_id = DENTIST_BASE_DID_4
  93                                 + (divider - DENTIST_DIVIDER_RANGE_4_START)
  94                                         / DENTIST_DIVIDER_RANGE_4_STEP;
  95                 if (divider_id > DENTIST_MAX_DID)
  96                         divider_id = DENTIST_MAX_DID;
  97         }
  98 
  99         return divider_id;
 100 }
 101 
 102 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 103                 struct dc_state *context)
 104 {
 105         int i;
 106 
 107         for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
 108                 int dpp_inst, dppclk_khz;
 109 
 110                 if (!context->res_ctx.pipe_ctx[i].plane_state)
 111                         continue;
 112 
 113                 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
 114                 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
 115                 clk_mgr->dccg->funcs->update_dpp_dto(
 116                                 clk_mgr->dccg, dpp_inst, dppclk_khz, false);
 117         }
 118 }
 119 
 120 static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
 121 {
 122         int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
 123                         * clk_mgr->dentist_vco_freq_khz / khz;
 124 
 125         uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
 126 
 127         REG_UPDATE(DENTIST_DISPCLK_CNTL,
 128                         DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
 129         REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
 130 }
 131 
 132 static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
 133 {
 134         int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
 135                         * clk_mgr->dentist_vco_freq_khz / khz;
 136 
 137         uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
 138 
 139         REG_UPDATE(DENTIST_DISPCLK_CNTL,
 140                         DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
 141 }
 142 
 143 static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
 144 {
 145         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 146         struct dc *dc = clk_mgr_base->ctx->dc;
 147         struct pp_smu_funcs_nv *pp_smu = NULL;
 148         bool going_up = clk_mgr->base.clks.dispclk_khz < khz;
 149 
 150         if (dc->res_pool->pp_smu)
 151                 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
 152 
 153         clk_mgr->base.clks.dispclk_khz = khz;
 154 
 155         if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
 156                 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
 157 
 158         update_display_clk(clk_mgr, khz);
 159 
 160         if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
 161                 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
 162 }
 163 
 164 static void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
 165 {
 166         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 167         struct dc *dc = clk_mgr_base->ctx->dc;
 168         struct pp_smu_funcs_nv *pp_smu = NULL;
 169         bool going_up = clk_mgr->base.clks.dppclk_khz < khz;
 170 
 171         if (dc->res_pool->pp_smu)
 172                 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
 173 
 174         clk_mgr->base.clks.dppclk_khz = khz;
 175         clk_mgr->dccg->ref_dppclk = khz;
 176 
 177         if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
 178                 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
 179 
 180         update_global_dpp_clk(clk_mgr, khz);
 181 
 182         if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
 183                 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
 184 }
 185 
 186 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
 187                         struct dc_state *context,
 188                         bool safe_to_lower)
 189 {
 190         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 191         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 192         struct dc *dc = clk_mgr_base->ctx->dc;
 193         struct pp_smu_funcs_nv *pp_smu = NULL;
 194         int display_count;
 195         bool update_dispclk = false;
 196         bool enter_display_off = false;
 197         struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
 198         bool force_reset = false;
 199         int i;
 200 
 201         if (dc->work_arounds.skip_clock_update)
 202                 return;
 203 
 204         if (clk_mgr_base->clks.dispclk_khz == 0 ||
 205                 dc->debug.force_clock_mode & 0x1) {
 206                 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
 207                 force_reset = true;
 208                 //force_clock_mode 0x1:  force reset the clock even it is the same clock as long as it is in Passive level.
 209         }
 210         display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
 211         if (dc->res_pool->pp_smu)
 212                 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
 213 
 214         if (display_count == 0)
 215                 enter_display_off = true;
 216 
 217         if (enter_display_off == safe_to_lower) {
 218                 if (pp_smu && pp_smu->set_display_count)
 219                         pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
 220         }
 221 
 222         if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
 223                 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
 224                 if (pp_smu && pp_smu->set_voltage_by_freq)
 225                         pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
 226         }
 227 
 228 
 229         if (dc->debug.force_min_dcfclk_mhz > 0)
 230                 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
 231                                 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
 232 
 233         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 234                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 235                 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
 236                         pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);
 237         }
 238 
 239         if (should_set_clock(safe_to_lower,
 240                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 241                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 242                 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
 243                         pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
 244         }
 245 
 246         if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
 247                 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
 248                 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)
 249                         pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
 250         }
 251 
 252         if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
 253                 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
 254 
 255                 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
 256                 if (pp_smu && pp_smu->set_pstate_handshake_support)
 257                         pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
 258         }
 259         clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
 260 
 261         if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
 262                 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
 263                 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
 264                         pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
 265         }
 266 
 267         if (dc->config.forced_clocks == false) {
 268                 // First update display clock
 269                 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz))
 270                         request_voltage_and_program_disp_clk(clk_mgr_base, new_clocks->dispclk_khz);
 271 
 272                 // Updating DPP clock requires some more logic
 273                 if (!safe_to_lower) {
 274                         // For pre-programming, we need to make sure any DPP clock that will go up has to go up
 275 
 276                         // First raise the global reference if needed
 277                         if (new_clocks->dppclk_khz > clk_mgr_base->clks.dppclk_khz)
 278                                 request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
 279 
 280                         // Then raise any dividers that need raising
 281                         for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
 282                                 int dpp_inst, dppclk_khz;
 283 
 284                                 if (!context->res_ctx.pipe_ctx[i].plane_state)
 285                                         continue;
 286 
 287                                 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
 288                                 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
 289 
 290                                 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true);
 291                         }
 292                 } else {
 293                         // For post-programming, we can lower ref clk if needed, and unconditionally set all the DTOs
 294 
 295                         if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz)
 296                                 request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
 297 
 298                         for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
 299                                 int dpp_inst, dppclk_khz;
 300 
 301                                 if (!context->res_ctx.pipe_ctx[i].plane_state)
 302                                         continue;
 303 
 304                                 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
 305                                 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
 306 
 307                                 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false);
 308                         }
 309                 }
 310         }
 311         if (update_dispclk &&
 312                         dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
 313                 /*update dmcu for wait_loop count*/
 314                 dmcu->funcs->set_psr_wait_loop(dmcu,
 315                         clk_mgr_base->clks.dispclk_khz / 1000 / 7);
 316         }
 317 }
 318 
 319 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
 320                 struct dc_state *context,
 321                 bool safe_to_lower)
 322 {
 323         struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
 324 
 325         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 326         /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
 327         int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
 328 
 329         if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
 330                 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
 331         }
 332 
 333         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
 334                 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 335         }
 336 
 337         if (should_set_clock(safe_to_lower,
 338                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
 339                 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 340         }
 341 
 342         if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
 343                 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
 344         }
 345 
 346         if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
 347                 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
 348         }
 349 
 350         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
 351                 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
 352         }
 353 
 354         if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
 355                 clk_mgr->clks.fclk_khz = fclk_adj;
 356         }
 357 
 358         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
 359                 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
 360         }
 361 
 362         /* Both fclk and ref_dppclk run on the same scemi clock.
 363          * So take the higher value since the DPP DTO is typically programmed
 364          * such that max dppclk is 1:1 with ref_dppclk.
 365          */
 366         if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
 367                 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
 368         if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
 369                 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
 370 
 371         // Both fclk and ref_dppclk run on the same scemi clock.
 372         clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
 373 
 374         dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
 375 }
 376 
 377 void dcn2_init_clocks(struct clk_mgr *clk_mgr)
 378 {
 379         memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
 380         // Assumption is that boot state always supports pstate
 381         clk_mgr->clks.p_state_change_support = true;
 382         clk_mgr->clks.prev_p_state_change_support = true;
 383 }
 384 
 385 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 386 {
 387         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 388         struct pp_smu_funcs_nv *pp_smu = NULL;
 389 
 390         if (clk_mgr->pp_smu) {
 391                 pp_smu = &clk_mgr->pp_smu->nv_funcs;
 392 
 393                 if (pp_smu->set_pme_wa_enable)
 394                         pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
 395         }
 396 }
 397 
 398 void dcn2_get_clock(struct clk_mgr *clk_mgr,
 399                 struct dc_state *context,
 400                         enum dc_clock_type clock_type,
 401                         struct dc_clock_config *clock_cfg)
 402 {
 403 
 404         if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
 405                 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
 406                 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
 407                 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
 408                 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
 409         }
 410         if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
 411                 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
 412                 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
 413                 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
 414                 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
 415         }
 416 }
 417 
 418 static struct clk_mgr_funcs dcn2_funcs = {
 419         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 420         .update_clocks = dcn2_update_clocks,
 421         .init_clocks = dcn2_init_clocks,
 422         .enable_pme_wa = dcn2_enable_pme_wa,
 423         .get_clock = dcn2_get_clock,
 424 };
 425 
 426 
 427 void dcn20_clk_mgr_construct(
 428                 struct dc_context *ctx,
 429                 struct clk_mgr_internal *clk_mgr,
 430                 struct pp_smu_funcs *pp_smu,
 431                 struct dccg *dccg)
 432 {
 433         clk_mgr->base.ctx = ctx;
 434         clk_mgr->pp_smu = pp_smu;
 435         clk_mgr->base.funcs = &dcn2_funcs;
 436         clk_mgr->regs = &clk_mgr_regs;
 437         clk_mgr->clk_mgr_shift = &clk_mgr_shift;
 438         clk_mgr->clk_mgr_mask = &clk_mgr_mask;
 439 
 440         clk_mgr->dccg = dccg;
 441         clk_mgr->dfs_bypass_disp_clk = 0;
 442 
 443         clk_mgr->dprefclk_ss_percentage = 0;
 444         clk_mgr->dprefclk_ss_divider = 1000;
 445         clk_mgr->ss_on_dprefclk = false;
 446 
 447         clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
 448 
 449         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
 450                 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
 451                 clk_mgr->dentist_vco_freq_khz = 3850000;
 452 
 453         } else {
 454                 /* DFS Slice 2 should be used for DPREFCLK */
 455                 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
 456                 /* Convert DPREFCLK DFS Slice DID to actual divider*/
 457                 int target_div = dentist_get_divider_from_did(dprefclk_did);
 458 
 459                 /* get FbMult value */
 460                 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
 461                 struct fixed31_32 pll_req;
 462 
 463                 /* set up a fixed-point number
 464                  * this works because the int part is on the right edge of the register
 465                  * and the frac part is on the left edge
 466                  */
 467 
 468                 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
 469                 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
 470 
 471                 /* multiply by REFCLK period */
 472                 pll_req = dc_fixpt_mul_int(pll_req, 100000);
 473 
 474                 /* integer part is now VCO frequency in kHz */
 475                 clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
 476 
 477                 /* in case we don't get a value from the register, use default */
 478                 if (clk_mgr->dentist_vco_freq_khz == 0)
 479                         clk_mgr->dentist_vco_freq_khz = 3850000;
 480 
 481                 /* Calculate the DPREFCLK in kHz.*/
 482                 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
 483                         * clk_mgr->dentist_vco_freq_khz) / target_div;
 484         }
 485         //Integrated_info table does not exist on dGPU projects so should not be referenced
 486         //anywhere in code for dGPUs.
 487         //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
 488         clk_mgr->dfs_bypass_enabled = false;
 489 
 490         dce_clock_read_ss_info(clk_mgr);
 491 }
 492