root/drivers/gpu/drm/amd/display/dc/dc_types.h

INCLUDED FROM

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef DC_TYPES_H_
  26 #define DC_TYPES_H_
  27 
  28 #include "os_types.h"
  29 #include "fixed31_32.h"
  30 #include "irq_types.h"
  31 #include "dc_dp_types.h"
  32 #include "dc_hw_types.h"
  33 #include "dal_types.h"
  34 #include "grph_object_defs.h"
  35 
  36 /* forward declarations */
  37 struct dc_plane_state;
  38 struct dc_stream_state;
  39 struct dc_link;
  40 struct dc_sink;
  41 struct dal;
  42 
  43 /********************************
  44  * Environment definitions
  45  ********************************/
  46 enum dce_environment {
  47         DCE_ENV_PRODUCTION_DRV = 0,
  48         /* Emulation on FPGA, in "Maximus" System.
  49          * This environment enforces that *only* DC registers accessed.
  50          * (access to non-DC registers will hang FPGA) */
  51         DCE_ENV_FPGA_MAXIMUS,
  52         /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
  53          * requirements of Diagnostics team. */
  54         DCE_ENV_DIAG
  55 };
  56 
  57 /* Note: use these macro definitions instead of direct comparison! */
  58 #define IS_FPGA_MAXIMUS_DC(dce_environment) \
  59         (dce_environment == DCE_ENV_FPGA_MAXIMUS)
  60 
  61 #define IS_DIAG_DC(dce_environment) \
  62         (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
  63 
  64 struct hw_asic_id {
  65         uint32_t chip_id;
  66         uint32_t chip_family;
  67         uint32_t pci_revision_id;
  68         uint32_t hw_internal_rev;
  69         uint32_t vram_type;
  70         uint32_t vram_width;
  71         uint32_t feature_flags;
  72         uint32_t fake_paths_num;
  73         void *atombios_base_address;
  74 };
  75 
  76 struct dc_perf_trace {
  77         unsigned long read_count;
  78         unsigned long write_count;
  79         unsigned long last_entry_read;
  80         unsigned long last_entry_write;
  81 };
  82 
  83 struct dc_context {
  84         struct dc *dc;
  85 
  86         void *driver_context; /* e.g. amdgpu_device */
  87         struct dc_perf_trace *perf_trace;
  88         void *cgs_device;
  89 
  90         enum dce_environment dce_environment;
  91         struct hw_asic_id asic_id;
  92 
  93         /* todo: below should probably move to dc.  to facilitate removal
  94          * of AS we will store these here
  95          */
  96         enum dce_version dce_version;
  97         struct dc_bios *dc_bios;
  98         bool created_bios;
  99         struct gpio_service *gpio_service;
 100         uint32_t dc_sink_id_count;
 101         uint32_t dc_stream_id_count;
 102         uint64_t fbc_gpu_addr;
 103 };
 104 
 105 
 106 #define DC_MAX_EDID_BUFFER_SIZE 1024
 107 #define DC_EDID_BLOCK_SIZE 128
 108 #define MAX_SURFACE_NUM 4
 109 #define NUM_PIXEL_FORMATS 10
 110 
 111 #include "dc_ddc_types.h"
 112 
 113 enum tiling_mode {
 114         TILING_MODE_INVALID,
 115         TILING_MODE_LINEAR,
 116         TILING_MODE_TILED,
 117         TILING_MODE_COUNT
 118 };
 119 
 120 enum view_3d_format {
 121         VIEW_3D_FORMAT_NONE = 0,
 122         VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
 123         VIEW_3D_FORMAT_SIDE_BY_SIDE,
 124         VIEW_3D_FORMAT_TOP_AND_BOTTOM,
 125         VIEW_3D_FORMAT_COUNT,
 126         VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
 127 };
 128 
 129 enum plane_stereo_format {
 130         PLANE_STEREO_FORMAT_NONE = 0,
 131         PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
 132         PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
 133         PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
 134         PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
 135         PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
 136         PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
 137 };
 138 
 139 /* TODO: Find way to calculate number of bits
 140  *  Please increase if pixel_format enum increases
 141  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
 142  */
 143 
 144 enum dc_edid_connector_type {
 145         DC_EDID_CONNECTOR_UNKNOWN = 0,
 146         DC_EDID_CONNECTOR_ANALOG = 1,
 147         DC_EDID_CONNECTOR_DIGITAL = 10,
 148         DC_EDID_CONNECTOR_DVI = 11,
 149         DC_EDID_CONNECTOR_HDMIA = 12,
 150         DC_EDID_CONNECTOR_MDDI = 14,
 151         DC_EDID_CONNECTOR_DISPLAYPORT = 15
 152 };
 153 
 154 enum dc_edid_status {
 155         EDID_OK,
 156         EDID_BAD_INPUT,
 157         EDID_NO_RESPONSE,
 158         EDID_BAD_CHECKSUM,
 159         EDID_THE_SAME,
 160 };
 161 
 162 /* audio capability from EDID*/
 163 struct dc_cea_audio_mode {
 164         uint8_t format_code; /* ucData[0] [6:3]*/
 165         uint8_t channel_count; /* ucData[0] [2:0]*/
 166         uint8_t sample_rate; /* ucData[1]*/
 167         union {
 168                 uint8_t sample_size; /* for LPCM*/
 169                 /*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
 170                 uint8_t max_bit_rate;
 171                 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
 172         };
 173 };
 174 
 175 struct dc_edid {
 176         uint32_t length;
 177         uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
 178 };
 179 
 180 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
 181  * is used. In this case we assume speaker location are: front left, front
 182  * right and front center. */
 183 #define DEFAULT_SPEAKER_LOCATION 5
 184 
 185 #define DC_MAX_AUDIO_DESC_COUNT 16
 186 
 187 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
 188 
 189 union display_content_support {
 190         unsigned int raw;
 191         struct {
 192                 unsigned int valid_content_type :1;
 193                 unsigned int game_content :1;
 194                 unsigned int cinema_content :1;
 195                 unsigned int photo_content :1;
 196                 unsigned int graphics_content :1;
 197                 unsigned int reserved :27;
 198         } bits;
 199 };
 200 
 201 struct dc_panel_patch {
 202         unsigned int dppowerup_delay;
 203         unsigned int extra_t12_ms;
 204         unsigned int extra_delay_backlight_off;
 205         unsigned int extra_t7_ms;
 206 };
 207 
 208 struct dc_edid_caps {
 209         /* sink identification */
 210         uint16_t manufacturer_id;
 211         uint16_t product_id;
 212         uint32_t serial_number;
 213         uint8_t manufacture_week;
 214         uint8_t manufacture_year;
 215         uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
 216 
 217         /* audio caps */
 218         uint8_t speaker_flags;
 219         uint32_t audio_mode_count;
 220         struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
 221         uint32_t audio_latency;
 222         uint32_t video_latency;
 223 
 224         union display_content_support content_support;
 225 
 226         uint8_t qs_bit;
 227         uint8_t qy_bit;
 228 
 229         /*HDMI 2.0 caps*/
 230         bool lte_340mcsc_scramble;
 231 
 232         bool edid_hdmi;
 233         bool hdr_supported;
 234 
 235         struct dc_panel_patch panel_patch;
 236 };
 237 
 238 struct view {
 239         uint32_t width;
 240         uint32_t height;
 241 };
 242 
 243 struct dc_mode_flags {
 244         /* note: part of refresh rate flag*/
 245         uint32_t INTERLACE :1;
 246         /* native display timing*/
 247         uint32_t NATIVE :1;
 248         /* preferred is the recommended mode, one per display */
 249         uint32_t PREFERRED :1;
 250         /* true if this mode should use reduced blanking timings
 251          *_not_ related to the Reduced Blanking adjustment*/
 252         uint32_t REDUCED_BLANKING :1;
 253         /* note: part of refreshrate flag*/
 254         uint32_t VIDEO_OPTIMIZED_RATE :1;
 255         /* should be reported to upper layers as mode_flags*/
 256         uint32_t PACKED_PIXEL_FORMAT :1;
 257         /*< preferred view*/
 258         uint32_t PREFERRED_VIEW :1;
 259         /* this timing should be used only in tiled mode*/
 260         uint32_t TILED_MODE :1;
 261         uint32_t DSE_MODE :1;
 262         /* Refresh rate divider when Miracast sink is using a
 263          different rate than the output display device
 264          Must be zero for wired displays and non-zero for
 265          Miracast displays*/
 266         uint32_t MIRACAST_REFRESH_DIVIDER;
 267 };
 268 
 269 
 270 enum dc_timing_source {
 271         TIMING_SOURCE_UNDEFINED,
 272 
 273         /* explicitly specifed by user, most important*/
 274         TIMING_SOURCE_USER_FORCED,
 275         TIMING_SOURCE_USER_OVERRIDE,
 276         TIMING_SOURCE_CUSTOM,
 277         TIMING_SOURCE_EXPLICIT,
 278 
 279         /* explicitly specified by the display device, more important*/
 280         TIMING_SOURCE_EDID_CEA_SVD_3D,
 281         TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
 282         TIMING_SOURCE_EDID_CEA_SVD_420,
 283         TIMING_SOURCE_EDID_DETAILED,
 284         TIMING_SOURCE_EDID_ESTABLISHED,
 285         TIMING_SOURCE_EDID_STANDARD,
 286         TIMING_SOURCE_EDID_CEA_SVD,
 287         TIMING_SOURCE_EDID_CVT_3BYTE,
 288         TIMING_SOURCE_EDID_4BYTE,
 289         TIMING_SOURCE_VBIOS,
 290         TIMING_SOURCE_CV,
 291         TIMING_SOURCE_TV,
 292         TIMING_SOURCE_HDMI_VIC,
 293 
 294         /* implicitly specified by display device, still safe but less important*/
 295         TIMING_SOURCE_DEFAULT,
 296 
 297         /* only used for custom base modes */
 298         TIMING_SOURCE_CUSTOM_BASE,
 299 
 300         /* these timing might not work, least important*/
 301         TIMING_SOURCE_RANGELIMIT,
 302         TIMING_SOURCE_OS_FORCED,
 303         TIMING_SOURCE_IMPLICIT,
 304 
 305         /* only used by default mode list*/
 306         TIMING_SOURCE_BASICMODE,
 307 
 308         TIMING_SOURCE_COUNT
 309 };
 310 
 311 
 312 struct stereo_3d_features {
 313         bool supported                  ;
 314         bool allTimings                 ;
 315         bool cloneMode                  ;
 316         bool scaling                    ;
 317         bool singleFrameSWPacked;
 318 };
 319 
 320 enum dc_timing_support_method {
 321         TIMING_SUPPORT_METHOD_UNDEFINED,
 322         TIMING_SUPPORT_METHOD_EXPLICIT,
 323         TIMING_SUPPORT_METHOD_IMPLICIT,
 324         TIMING_SUPPORT_METHOD_NATIVE
 325 };
 326 
 327 struct dc_mode_info {
 328         uint32_t pixel_width;
 329         uint32_t pixel_height;
 330         uint32_t field_rate;
 331         /* Vertical refresh rate for progressive modes.
 332         * Field rate for interlaced modes.*/
 333 
 334         enum dc_timing_standard timing_standard;
 335         enum dc_timing_source timing_source;
 336         struct dc_mode_flags flags;
 337 };
 338 
 339 enum dc_power_state {
 340         DC_POWER_STATE_ON = 1,
 341         DC_POWER_STATE_STANDBY,
 342         DC_POWER_STATE_SUSPEND,
 343         DC_POWER_STATE_OFF
 344 };
 345 
 346 /* DC PowerStates */
 347 enum dc_video_power_state {
 348         DC_VIDEO_POWER_UNSPECIFIED = 0,
 349         DC_VIDEO_POWER_ON = 1,
 350         DC_VIDEO_POWER_STANDBY,
 351         DC_VIDEO_POWER_SUSPEND,
 352         DC_VIDEO_POWER_OFF,
 353         DC_VIDEO_POWER_HIBERNATE,
 354         DC_VIDEO_POWER_SHUTDOWN,
 355         DC_VIDEO_POWER_ULPS,    /* BACO or Ultra-Light-Power-State */
 356         DC_VIDEO_POWER_AFTER_RESET,
 357         DC_VIDEO_POWER_MAXIMUM
 358 };
 359 
 360 enum dc_acpi_cm_power_state {
 361         DC_ACPI_CM_POWER_STATE_D0 = 1,
 362         DC_ACPI_CM_POWER_STATE_D1 = 2,
 363         DC_ACPI_CM_POWER_STATE_D2 = 4,
 364         DC_ACPI_CM_POWER_STATE_D3 = 8
 365 };
 366 
 367 enum dc_connection_type {
 368         dc_connection_none,
 369         dc_connection_single,
 370         dc_connection_mst_branch,
 371         dc_connection_active_dongle
 372 };
 373 
 374 struct dc_csc_adjustments {
 375         struct fixed31_32 contrast;
 376         struct fixed31_32 saturation;
 377         struct fixed31_32 brightness;
 378         struct fixed31_32 hue;
 379 };
 380 
 381 enum dpcd_downstream_port_max_bpc {
 382         DOWN_STREAM_MAX_8BPC = 0,
 383         DOWN_STREAM_MAX_10BPC,
 384         DOWN_STREAM_MAX_12BPC,
 385         DOWN_STREAM_MAX_16BPC
 386 };
 387 struct dc_dongle_caps {
 388         /* dongle type (DP converter, CV smart dongle) */
 389         enum display_dongle_type dongle_type;
 390         bool extendedCapValid;
 391         /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 392         indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
 393         bool is_dp_hdmi_s3d_converter;
 394         bool is_dp_hdmi_ycbcr422_pass_through;
 395         bool is_dp_hdmi_ycbcr420_pass_through;
 396         bool is_dp_hdmi_ycbcr422_converter;
 397         bool is_dp_hdmi_ycbcr420_converter;
 398         uint32_t dp_hdmi_max_bpc;
 399         uint32_t dp_hdmi_max_pixel_clk_in_khz;
 400 };
 401 /* Scaling format */
 402 enum scaling_transformation {
 403         SCALING_TRANSFORMATION_UNINITIALIZED,
 404         SCALING_TRANSFORMATION_IDENTITY = 0x0001,
 405         SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
 406         SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
 407         SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
 408         SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
 409         SCALING_TRANSFORMATION_INVALID = 0x80000000,
 410 
 411         /* Flag the first and last */
 412         SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
 413         SCALING_TRANSFORMATION_END =
 414                 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
 415 };
 416 
 417 enum display_content_type {
 418         DISPLAY_CONTENT_TYPE_NO_DATA = 0,
 419         DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
 420         DISPLAY_CONTENT_TYPE_PHOTO = 2,
 421         DISPLAY_CONTENT_TYPE_CINEMA = 4,
 422         DISPLAY_CONTENT_TYPE_GAME = 8
 423 };
 424 
 425 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 426 /* writeback */
 427 struct dwb_stereo_params {
 428         bool                            stereo_enabled;         /* false: normal mode, true: 3D stereo */
 429         enum dwb_stereo_type            stereo_type;            /* indicates stereo format */
 430         bool                            stereo_polarity;        /* indicates left eye or right eye comes first in stereo mode */
 431         enum dwb_stereo_eye_select      stereo_eye_select;      /* indicate which eye should be captured */
 432 };
 433 
 434 struct dc_dwb_cnv_params {
 435         unsigned int            src_width;      /* input active width */
 436         unsigned int            src_height;     /* input active height (half-active height in interlaced mode) */
 437         unsigned int            crop_width;     /* cropped window width at cnv output */
 438         bool                    crop_en;        /* window cropping enable in cnv */
 439         unsigned int            crop_height;    /* cropped window height at cnv output */
 440         unsigned int            crop_x;         /* cropped window start x value at cnv output */
 441         unsigned int            crop_y;         /* cropped window start y value at cnv output */
 442         enum dwb_cnv_out_bpc cnv_out_bpc;       /* cnv output pixel depth - 8bpc or 10bpc */
 443 };
 444 
 445 struct dc_dwb_params {
 446         struct dc_dwb_cnv_params        cnv_params;     /* CNV source size and cropping window parameters */
 447         unsigned int                    dest_width;     /* Destination width */
 448         unsigned int                    dest_height;    /* Destination height */
 449         enum dwb_scaler_mode            out_format;     /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
 450         enum dwb_output_depth           output_depth;   /* output pixel depth - 8bpc or 10bpc */
 451         enum dwb_capture_rate           capture_rate;   /* controls the frame capture rate */
 452         struct scaling_taps             scaler_taps;    /* Scaling taps */
 453         enum dwb_subsample_position     subsample_position;
 454         struct dc_transfer_func *out_transfer_func;
 455 };
 456 #endif
 457 
 458 /* audio*/
 459 
 460 union audio_sample_rates {
 461         struct sample_rates {
 462                 uint8_t RATE_32:1;
 463                 uint8_t RATE_44_1:1;
 464                 uint8_t RATE_48:1;
 465                 uint8_t RATE_88_2:1;
 466                 uint8_t RATE_96:1;
 467                 uint8_t RATE_176_4:1;
 468                 uint8_t RATE_192:1;
 469         } rate;
 470 
 471         uint8_t all;
 472 };
 473 
 474 struct audio_speaker_flags {
 475         uint32_t FL_FR:1;
 476         uint32_t LFE:1;
 477         uint32_t FC:1;
 478         uint32_t RL_RR:1;
 479         uint32_t RC:1;
 480         uint32_t FLC_FRC:1;
 481         uint32_t RLC_RRC:1;
 482         uint32_t SUPPORT_AI:1;
 483 };
 484 
 485 struct audio_speaker_info {
 486         uint32_t ALLSPEAKERS:7;
 487         uint32_t SUPPORT_AI:1;
 488 };
 489 
 490 
 491 struct audio_info_flags {
 492 
 493         union {
 494 
 495                 struct audio_speaker_flags speaker_flags;
 496                 struct audio_speaker_info   info;
 497 
 498                 uint8_t all;
 499         };
 500 };
 501 
 502 enum audio_format_code {
 503         AUDIO_FORMAT_CODE_FIRST = 1,
 504         AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
 505 
 506         AUDIO_FORMAT_CODE_AC3,
 507         /*Layers 1 & 2 */
 508         AUDIO_FORMAT_CODE_MPEG1,
 509         /*MPEG1 Layer 3 */
 510         AUDIO_FORMAT_CODE_MP3,
 511         /*multichannel */
 512         AUDIO_FORMAT_CODE_MPEG2,
 513         AUDIO_FORMAT_CODE_AAC,
 514         AUDIO_FORMAT_CODE_DTS,
 515         AUDIO_FORMAT_CODE_ATRAC,
 516         AUDIO_FORMAT_CODE_1BITAUDIO,
 517         AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
 518         AUDIO_FORMAT_CODE_DTS_HD,
 519         AUDIO_FORMAT_CODE_MAT_MLP,
 520         AUDIO_FORMAT_CODE_DST,
 521         AUDIO_FORMAT_CODE_WMAPRO,
 522         AUDIO_FORMAT_CODE_LAST,
 523         AUDIO_FORMAT_CODE_COUNT =
 524                 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
 525 };
 526 
 527 struct audio_mode {
 528          /* ucData[0] [6:3] */
 529         enum audio_format_code format_code;
 530         /* ucData[0] [2:0] */
 531         uint8_t channel_count;
 532         /* ucData[1] */
 533         union audio_sample_rates sample_rates;
 534         union {
 535                 /* for LPCM */
 536                 uint8_t sample_size;
 537                 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
 538                 uint8_t max_bit_rate;
 539                 /* for Audio Formats 9-15 */
 540                 uint8_t vendor_specific;
 541         };
 542 };
 543 
 544 struct audio_info {
 545         struct audio_info_flags flags;
 546         uint32_t video_latency;
 547         uint32_t audio_latency;
 548         uint32_t display_index;
 549         uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
 550         uint32_t manufacture_id;
 551         uint32_t product_id;
 552         /* PortID used for ContainerID when defined */
 553         uint32_t port_id[2];
 554         uint32_t mode_count;
 555         /* this field must be last in this struct */
 556         struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
 557 };
 558 
 559 enum dc_infoframe_type {
 560         DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
 561         DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
 562         DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
 563         DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
 564 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 565         DC_DP_INFOFRAME_TYPE_PPS = 0x10,
 566 #endif
 567 };
 568 
 569 struct dc_info_packet {
 570         bool valid;
 571         uint8_t hb0;
 572         uint8_t hb1;
 573         uint8_t hb2;
 574         uint8_t hb3;
 575         uint8_t sb[32];
 576 };
 577 
 578 struct dc_info_packet_128 {
 579         bool valid;
 580         uint8_t hb0;
 581         uint8_t hb1;
 582         uint8_t hb2;
 583         uint8_t hb3;
 584         uint8_t sb[128];
 585 };
 586 
 587 #define DC_PLANE_UPDATE_TIMES_MAX 10
 588 
 589 struct dc_plane_flip_time {
 590         unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
 591         unsigned int index;
 592         unsigned int prev_update_time_in_us;
 593 };
 594 
 595 struct psr_config {
 596         unsigned char psr_version;
 597         unsigned int psr_rfb_setup_time;
 598         bool psr_exit_link_training_required;
 599         bool psr_frame_capture_indication_req;
 600         unsigned int psr_sdp_transmit_line_num_deadline;
 601         bool allow_smu_optimizations;
 602 };
 603 
 604 union dmcu_psr_level {
 605         struct {
 606                 unsigned int SKIP_CRC:1;
 607                 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
 608                 unsigned int SKIP_PHY_POWER_DOWN:1;
 609                 unsigned int SKIP_AUX_ACK_CHECK:1;
 610                 unsigned int SKIP_CRTC_DISABLE:1;
 611                 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
 612                 unsigned int SKIP_SMU_NOTIFICATION:1;
 613                 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
 614                 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
 615                 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
 616                 unsigned int RESERVED:22;
 617         } bits;
 618         unsigned int u32all;
 619 };
 620 
 621 enum physical_phy_id {
 622         PHYLD_0,
 623         PHYLD_1,
 624         PHYLD_2,
 625         PHYLD_3,
 626         PHYLD_4,
 627         PHYLD_5,
 628         PHYLD_6,
 629         PHYLD_7,
 630         PHYLD_8,
 631         PHYLD_9,
 632         PHYLD_COUNT,
 633         PHYLD_UNKNOWN = (-1L)
 634 };
 635 
 636 enum phy_type {
 637         PHY_TYPE_UNKNOWN  = 1,
 638         PHY_TYPE_PCIE_PHY = 2,
 639         PHY_TYPE_UNIPHY = 3,
 640 };
 641 
 642 struct psr_context {
 643         /* ddc line */
 644         enum channel_id channel;
 645         /* Transmitter id */
 646         enum transmitter transmitterId;
 647         /* Engine Id is used for Dig Be source select */
 648         enum engine_id engineId;
 649         /* Controller Id used for Dig Fe source select */
 650         enum controller_id controllerId;
 651         /* Pcie or Uniphy */
 652         enum phy_type phyType;
 653         /* Physical PHY Id used by SMU interpretation */
 654         enum physical_phy_id smuPhyId;
 655         /* Vertical total pixels from crtc timing.
 656          * This is used for static screen detection.
 657          * ie. If we want to detect half a frame,
 658          * we use this to determine the hyst lines.
 659          */
 660         unsigned int crtcTimingVerticalTotal;
 661         /* PSR supported from panel capabilities and
 662          * current display configuration
 663          */
 664         bool psrSupportedDisplayConfig;
 665         /* Whether fast link training is supported by the panel */
 666         bool psrExitLinkTrainingRequired;
 667         /* If RFB setup time is greater than the total VBLANK time,
 668          * it is not possible for the sink to capture the video frame
 669          * in the same frame the SDP is sent. In this case,
 670          * the frame capture indication bit should be set and an extra
 671          * static frame should be transmitted to the sink.
 672          */
 673         bool psrFrameCaptureIndicationReq;
 674         /* Set the last possible line SDP may be transmitted without violating
 675          * the RFB setup time or entering the active video frame.
 676          */
 677         unsigned int sdpTransmitLineNumDeadline;
 678         /* The VSync rate in Hz used to calculate the
 679          * step size for smooth brightness feature
 680          */
 681         unsigned int vsyncRateHz;
 682         unsigned int skipPsrWaitForPllLock;
 683         unsigned int numberOfControllers;
 684         /* Unused, for future use. To indicate that first changed frame from
 685          * state3 shouldn't result in psr_inactive, but rather to perform
 686          * an automatic single frame rfb_update.
 687          */
 688         bool rfb_update_auto_en;
 689         /* Number of frame before entering static screen */
 690         unsigned int timehyst_frames;
 691         /* Partial frames before entering static screen */
 692         unsigned int hyst_lines;
 693         /* # of repeated AUX transaction attempts to make before
 694          * indicating failure to the driver
 695          */
 696         unsigned int aux_repeats;
 697         /* Controls hw blocks to power down during PSR active state */
 698         union dmcu_psr_level psr_level;
 699         /* Controls additional delay after remote frame capture before
 700          * continuing powerd own
 701          */
 702         unsigned int frame_delay;
 703         bool allow_smu_optimizations;
 704 };
 705 
 706 struct colorspace_transform {
 707         struct fixed31_32 matrix[12];
 708         bool enable_remap;
 709 };
 710 
 711 enum i2c_mot_mode {
 712         I2C_MOT_UNDEF,
 713         I2C_MOT_TRUE,
 714         I2C_MOT_FALSE
 715 };
 716 
 717 struct AsicStateEx {
 718         unsigned int memoryClock;
 719         unsigned int displayClock;
 720         unsigned int engineClock;
 721         unsigned int maxSupportedDppClock;
 722         unsigned int dppClock;
 723         unsigned int socClock;
 724         unsigned int dcfClockDeepSleep;
 725         unsigned int fClock;
 726         unsigned int phyClock;
 727 };
 728 
 729 
 730 enum dc_clock_type {
 731         DC_CLOCK_TYPE_DISPCLK = 0,
 732         DC_CLOCK_TYPE_DPPCLK        = 1,
 733 };
 734 
 735 struct dc_clock_config {
 736         uint32_t max_clock_khz;
 737         uint32_t min_clock_khz;
 738         uint32_t bw_requirequired_clock_khz;
 739         uint32_t current_clock_khz;/*current clock in use*/
 740 };
 741 
 742 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 743 /* DSC DPCD capabilities */
 744 union dsc_slice_caps1 {
 745         struct {
 746                 uint8_t NUM_SLICES_1 : 1;
 747                 uint8_t NUM_SLICES_2 : 1;
 748                 uint8_t RESERVED : 1;
 749                 uint8_t NUM_SLICES_4 : 1;
 750                 uint8_t NUM_SLICES_6 : 1;
 751                 uint8_t NUM_SLICES_8 : 1;
 752                 uint8_t NUM_SLICES_10 : 1;
 753                 uint8_t NUM_SLICES_12 : 1;
 754         } bits;
 755         uint8_t raw;
 756 };
 757 
 758 union dsc_slice_caps2 {
 759         struct {
 760                 uint8_t NUM_SLICES_16 : 1;
 761                 uint8_t NUM_SLICES_20 : 1;
 762                 uint8_t NUM_SLICES_24 : 1;
 763                 uint8_t RESERVED : 5;
 764         } bits;
 765         uint8_t raw;
 766 };
 767 
 768 union dsc_color_formats {
 769         struct {
 770                 uint8_t RGB : 1;
 771                 uint8_t YCBCR_444 : 1;
 772                 uint8_t YCBCR_SIMPLE_422 : 1;
 773                 uint8_t YCBCR_NATIVE_422 : 1;
 774                 uint8_t YCBCR_NATIVE_420 : 1;
 775                 uint8_t RESERVED : 3;
 776         } bits;
 777         uint8_t raw;
 778 };
 779 
 780 union dsc_color_depth {
 781         struct {
 782                 uint8_t RESERVED1 : 1;
 783                 uint8_t COLOR_DEPTH_8_BPC : 1;
 784                 uint8_t COLOR_DEPTH_10_BPC : 1;
 785                 uint8_t COLOR_DEPTH_12_BPC : 1;
 786                 uint8_t RESERVED2 : 3;
 787         } bits;
 788         uint8_t raw;
 789 };
 790 
 791 struct dsc_dec_dpcd_caps {
 792         bool is_dsc_supported;
 793         uint8_t dsc_version;
 794         int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
 795         union dsc_slice_caps1 slice_caps1;
 796         union dsc_slice_caps2 slice_caps2;
 797         int32_t lb_bit_depth;
 798         bool is_block_pred_supported;
 799         int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
 800         union dsc_color_formats color_formats;
 801         union dsc_color_depth color_depth;
 802         int32_t throughput_mode_0_mps; /* In MPs */
 803         int32_t throughput_mode_1_mps; /* In MPs */
 804         int32_t max_slice_width;
 805         uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
 806 
 807         /* Extended DSC caps */
 808         uint32_t branch_overall_throughput_0_mps; /* In MPs */
 809         uint32_t branch_overall_throughput_1_mps; /* In MPs */
 810         uint32_t branch_max_line_width;
 811 };
 812 #endif
 813 #endif /* DC_TYPES_H_ */