This source file includes following definitions.
- dcn21_ipp_create
- dcn21_dpp_create
- dcn21_aux_engine_create
- dcn21_i2c_hw_create
- destruct
- calculate_wm_set_for_vlevel
- dcn21_calculate_wm
- dcn21_validate_bandwidth
- dcn21_destroy_resource_pool
- dcn21_clock_source_create
- dcn21_hubp_create
- dcn21_hubbub_create
- dcn21_opp_create
- dcn21_timing_generator_create
- dcn21_mpc_create
- read_dce_straps
- dcn21_dsc_create
- update_bw_bounding_box
- dummy_set_wm_ranges
- dummy_get_dpm_clock_table
- dcn21_pp_smu_create
- dcn21_pp_smu_destroy
- dcn21_create_audio
- dcn21_stream_encoder_create
- dcn21_hwseq_create
- construct
- dcn21_create_resource_pool
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26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29 #include "dc.h"
30
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dcn20/dcn20_resource.h"
34
35 #include "clk_mgr.h"
36 #include "dcn10/dcn10_hubp.h"
37 #include "dcn10/dcn10_ipp.h"
38 #include "dcn20/dcn20_hubbub.h"
39 #include "dcn20/dcn20_mpc.h"
40 #include "dcn20/dcn20_hubp.h"
41 #include "dcn21_hubp.h"
42 #include "irq/dcn21/irq_service_dcn21.h"
43 #include "dcn20/dcn20_dpp.h"
44 #include "dcn20/dcn20_optc.h"
45 #include "dcn20/dcn20_hwseq.h"
46 #include "dce110/dce110_hw_sequencer.h"
47 #include "dcn20/dcn20_opp.h"
48 #include "dcn20/dcn20_dsc.h"
49 #include "dcn20/dcn20_link_encoder.h"
50 #include "dcn20/dcn20_stream_encoder.h"
51 #include "dce/dce_clock_source.h"
52 #include "dce/dce_audio.h"
53 #include "dce/dce_hwseq.h"
54 #include "virtual/virtual_stream_encoder.h"
55 #include "dce110/dce110_resource.h"
56 #include "dml/display_mode_vba.h"
57 #include "dcn20/dcn20_dccg.h"
58 #include "dcn21_hubbub.h"
59 #include "dcn10/dcn10_resource.h"
60 #include "dce110/dce110_resource.h"
61
62 #include "dcn20/dcn20_dwb.h"
63 #include "dcn20/dcn20_mmhubbub.h"
64
65 #include "renoir_ip_offset.h"
66 #include "dcn/dcn_2_1_0_offset.h"
67 #include "dcn/dcn_2_1_0_sh_mask.h"
68
69 #include "nbio/nbio_7_0_offset.h"
70
71 #include "mmhub/mmhub_2_0_0_offset.h"
72 #include "mmhub/mmhub_2_0_0_sh_mask.h"
73
74 #include "reg_helper.h"
75 #include "dce/dce_abm.h"
76 #include "dce/dce_dmcu.h"
77 #include "dce/dce_aux.h"
78 #include "dce/dce_i2c.h"
79 #include "dcn21_resource.h"
80 #include "vm_helper.h"
81 #include "dcn20/dcn20_vmid.h"
82
83 #define SOC_BOUNDING_BOX_VALID false
84 #define DC_LOGGER_INIT(logger)
85
86
87 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
88 .gpuvm_enable = 0,
89 .hostvm_enable = 0,
90 .gpuvm_max_page_table_levels = 1,
91 .hostvm_max_page_table_levels = 4,
92 .hostvm_cached_page_table_levels = 2,
93 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
94 .num_dsc = 3,
95 #else
96 .num_dsc = 0,
97 #endif
98 .rob_buffer_size_kbytes = 168,
99 .det_buffer_size_kbytes = 164,
100 .dpte_buffer_size_in_pte_reqs_luma = 44,
101 .dpte_buffer_size_in_pte_reqs_chroma = 42,
102 .dpp_output_buffer_pixels = 2560,
103 .opp_output_buffer_lines = 1,
104 .pixel_chunk_size_kbytes = 8,
105 .pte_enable = 1,
106 .max_page_table_levels = 4,
107 .pte_chunk_size_kbytes = 2,
108 .meta_chunk_size_kbytes = 2,
109 .writeback_chunk_size_kbytes = 2,
110 .line_buffer_size_bits = 789504,
111 .is_line_buffer_bpp_fixed = 0,
112 .line_buffer_fixed_bpp = 0,
113 .dcc_supported = true,
114 .max_line_buffer_lines = 12,
115 .writeback_luma_buffer_size_kbytes = 12,
116 .writeback_chroma_buffer_size_kbytes = 8,
117 .writeback_chroma_line_buffer_width_pixels = 4,
118 .writeback_max_hscl_ratio = 1,
119 .writeback_max_vscl_ratio = 1,
120 .writeback_min_hscl_ratio = 1,
121 .writeback_min_vscl_ratio = 1,
122 .writeback_max_hscl_taps = 12,
123 .writeback_max_vscl_taps = 12,
124 .writeback_line_buffer_luma_buffer_size = 0,
125 .writeback_line_buffer_chroma_buffer_size = 14643,
126 .cursor_buffer_size = 8,
127 .cursor_chunk_size = 2,
128 .max_num_otg = 4,
129 .max_num_dpp = 4,
130 .max_num_wb = 1,
131 .max_dchub_pscl_bw_pix_per_clk = 4,
132 .max_pscl_lb_bw_pix_per_clk = 2,
133 .max_lb_vscl_bw_pix_per_clk = 4,
134 .max_vscl_hscl_bw_pix_per_clk = 4,
135 .max_hscl_ratio = 4,
136 .max_vscl_ratio = 4,
137 .hscl_mults = 4,
138 .vscl_mults = 4,
139 .max_hscl_taps = 8,
140 .max_vscl_taps = 8,
141 .dispclk_ramp_margin_percent = 1,
142 .underscan_factor = 1.10,
143 .min_vblank_lines = 32,
144 .dppclk_delay_subtotal = 77,
145 .dppclk_delay_scl_lb_only = 16,
146 .dppclk_delay_scl = 50,
147 .dppclk_delay_cnvc_formatter = 8,
148 .dppclk_delay_cnvc_cursor = 6,
149 .dispclk_delay_subtotal = 87,
150 .dcfclk_cstate_latency = 10,
151 .max_inter_dcn_tile_repeaters = 8,
152
153 .xfc_supported = false,
154 .xfc_fill_bw_overhead_percent = 10.0,
155 .xfc_fill_constant_bytes = 0,
156 .ptoi_supported = 0
157 };
158
159 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
160 .clock_limits = {
161 {
162 .state = 0,
163 .dcfclk_mhz = 304.0,
164 .fabricclk_mhz = 600.0,
165 .dispclk_mhz = 618.0,
166 .dppclk_mhz = 440.0,
167 .phyclk_mhz = 600.0,
168 .socclk_mhz = 278.0,
169 .dscclk_mhz = 205.67,
170 .dram_speed_mts = 1600.0,
171 },
172 {
173 .state = 1,
174 .dcfclk_mhz = 304.0,
175 .fabricclk_mhz = 600.0,
176 .dispclk_mhz = 618.0,
177 .dppclk_mhz = 618.0,
178 .phyclk_mhz = 600.0,
179 .socclk_mhz = 278.0,
180 .dscclk_mhz = 205.67,
181 .dram_speed_mts = 1600.0,
182 },
183 {
184 .state = 2,
185 .dcfclk_mhz = 608.0,
186 .fabricclk_mhz = 1066.0,
187 .dispclk_mhz = 888.0,
188 .dppclk_mhz = 888.0,
189 .phyclk_mhz = 810.0,
190 .socclk_mhz = 278.0,
191 .dscclk_mhz = 287.67,
192 .dram_speed_mts = 2133.0,
193 },
194 {
195 .state = 3,
196 .dcfclk_mhz = 676.0,
197 .fabricclk_mhz = 1600.0,
198 .dispclk_mhz = 1015.0,
199 .dppclk_mhz = 1015.0,
200 .phyclk_mhz = 810.0,
201 .socclk_mhz = 715.0,
202 .dscclk_mhz = 318.334,
203 .dram_speed_mts = 4266.0,
204 },
205 {
206 .state = 4,
207 .dcfclk_mhz = 810.0,
208 .fabricclk_mhz = 1600.0,
209 .dispclk_mhz = 1015.0,
210 .dppclk_mhz = 1015.0,
211 .phyclk_mhz = 810.0,
212 .socclk_mhz = 953.0,
213 .dscclk_mhz = 318.334,
214 .dram_speed_mts = 4266.0,
215 },
216
217 {
218 .state = 5,
219 .dcfclk_mhz = 810.0,
220 .fabricclk_mhz = 1600.0,
221 .dispclk_mhz = 1015.0,
222 .dppclk_mhz = 1015.0,
223 .phyclk_mhz = 810.0,
224 .socclk_mhz = 953.0,
225 .dscclk_mhz = 318.334,
226 .dram_speed_mts = 4266.0,
227 },
228
229 },
230
231 .sr_exit_time_us = 9.0,
232 .sr_enter_plus_exit_time_us = 11.0,
233 .urgent_latency_us = 4.0,
234 .urgent_latency_pixel_data_only_us = 4.0,
235 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
236 .urgent_latency_vm_data_only_us = 4.0,
237 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
238 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
239 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
240 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
241 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
242 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
243 .max_avg_sdp_bw_use_normal_percent = 60.0,
244 .max_avg_dram_bw_use_normal_percent = 100.0,
245 .writeback_latency_us = 12.0,
246 .max_request_size_bytes = 256,
247 .dram_channel_width_bytes = 4,
248 .fabric_datapath_to_dcn_data_return_bytes = 32,
249 .dcn_downspread_percent = 0.5,
250 .downspread_percent = 0.38,
251 .dram_page_open_time_ns = 50.0,
252 .dram_rw_turnaround_time_ns = 17.5,
253 .dram_return_buffer_per_channel_bytes = 8192,
254 .round_trip_ping_latency_dcfclk_cycles = 128,
255 .urgent_out_of_order_return_per_channel_bytes = 4096,
256 .channel_interleave_bytes = 256,
257 .num_banks = 8,
258 .num_chans = 4,
259 .vmm_page_size_bytes = 4096,
260 .dram_clock_change_latency_us = 23.84,
261 .return_bus_width_bytes = 64,
262 .dispclk_dppclk_vco_speed_mhz = 3600,
263 .xfc_bus_transport_time_us = 4,
264 .xfc_xbuf_latency_tolerance_us = 4,
265 .use_urgent_burst_bw = 1,
266 .num_states = 5
267 };
268
269 #ifndef MAX
270 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
271 #endif
272 #ifndef MIN
273 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
274 #endif
275
276
277
278
279
280
281 #undef BASE_INNER
282 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
283
284 #define BASE(seg) BASE_INNER(seg)
285
286 #define SR(reg_name)\
287 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
288 mm ## reg_name
289
290 #define SRI(reg_name, block, id)\
291 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
292 mm ## block ## id ## _ ## reg_name
293
294 #define SRIR(var_name, reg_name, block, id)\
295 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
296 mm ## block ## id ## _ ## reg_name
297
298 #define SRII(reg_name, block, id)\
299 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
300 mm ## block ## id ## _ ## reg_name
301
302 #define DCCG_SRII(reg_name, block, id)\
303 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
304 mm ## block ## id ## _ ## reg_name
305
306
307 #define NBIO_BASE_INNER(seg) \
308 NBIF0_BASE__INST0_SEG ## seg
309
310 #define NBIO_BASE(seg) \
311 NBIO_BASE_INNER(seg)
312
313 #define NBIO_SR(reg_name)\
314 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
315 mm ## reg_name
316
317
318 #define MMHUB_BASE_INNER(seg) \
319 MMHUB_BASE__INST0_SEG ## seg
320
321 #define MMHUB_BASE(seg) \
322 MMHUB_BASE_INNER(seg)
323
324 #define MMHUB_SR(reg_name)\
325 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
326 mmMM ## reg_name
327
328 #define clk_src_regs(index, pllid)\
329 [index] = {\
330 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
331 }
332
333 static const struct dce110_clk_src_regs clk_src_regs[] = {
334 clk_src_regs(0, A),
335 clk_src_regs(1, B),
336 clk_src_regs(2, C),
337 clk_src_regs(3, D),
338 clk_src_regs(4, E),
339 };
340
341 static const struct dce110_clk_src_shift cs_shift = {
342 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
343 };
344
345 static const struct dce110_clk_src_mask cs_mask = {
346 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
347 };
348
349 static const struct bios_registers bios_regs = {
350 NBIO_SR(BIOS_SCRATCH_3),
351 NBIO_SR(BIOS_SCRATCH_6)
352 };
353
354 #ifdef CONFIG_DRM_AMD_DC_DMUB
355 static const struct dcn21_dmcub_registers dmcub_regs = {
356 DMCUB_REG_LIST_DCN()
357 };
358
359 static const struct dcn21_dmcub_shift dmcub_shift = {
360 DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT)
361 };
362
363 static const struct dcn21_dmcub_mask dmcub_mask = {
364 DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK)
365 };
366 #endif
367
368 #define audio_regs(id)\
369 [id] = {\
370 AUD_COMMON_REG_LIST(id)\
371 }
372
373 static const struct dce_audio_registers audio_regs[] = {
374 audio_regs(0),
375 audio_regs(1),
376 audio_regs(2),
377 audio_regs(3),
378 audio_regs(4),
379 audio_regs(5),
380 };
381
382 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
383 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
384 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
385 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
386
387 static const struct dce_audio_shift audio_shift = {
388 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
389 };
390
391 static const struct dce_audio_mask audio_mask = {
392 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
393 };
394
395 static const struct dccg_registers dccg_regs = {
396 DCCG_COMMON_REG_LIST_DCN_BASE()
397 };
398
399 static const struct dccg_shift dccg_shift = {
400 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
401 };
402
403 static const struct dccg_mask dccg_mask = {
404 DCCG_MASK_SH_LIST_DCN2(_MASK)
405 };
406
407 #define opp_regs(id)\
408 [id] = {\
409 OPP_REG_LIST_DCN20(id),\
410 }
411
412 static const struct dcn20_opp_registers opp_regs[] = {
413 opp_regs(0),
414 opp_regs(1),
415 opp_regs(2),
416 opp_regs(3),
417 opp_regs(4),
418 opp_regs(5),
419 };
420
421 static const struct dcn20_opp_shift opp_shift = {
422 OPP_MASK_SH_LIST_DCN20(__SHIFT)
423 };
424
425 static const struct dcn20_opp_mask opp_mask = {
426 OPP_MASK_SH_LIST_DCN20(_MASK)
427 };
428
429 #define tg_regs(id)\
430 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
431
432 static const struct dcn_optc_registers tg_regs[] = {
433 tg_regs(0),
434 tg_regs(1),
435 tg_regs(2),
436 tg_regs(3)
437 };
438
439 static const struct dcn_optc_shift tg_shift = {
440 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
441 };
442
443 static const struct dcn_optc_mask tg_mask = {
444 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
445 };
446
447 static const struct dcn20_mpc_registers mpc_regs = {
448 MPC_REG_LIST_DCN2_0(0),
449 MPC_REG_LIST_DCN2_0(1),
450 MPC_REG_LIST_DCN2_0(2),
451 MPC_REG_LIST_DCN2_0(3),
452 MPC_REG_LIST_DCN2_0(4),
453 MPC_REG_LIST_DCN2_0(5),
454 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
455 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
456 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
457 MPC_OUT_MUX_REG_LIST_DCN2_0(3)
458 };
459
460 static const struct dcn20_mpc_shift mpc_shift = {
461 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
462 };
463
464 static const struct dcn20_mpc_mask mpc_mask = {
465 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
466 };
467
468 #define hubp_regs(id)\
469 [id] = {\
470 HUBP_REG_LIST_DCN21(id)\
471 }
472
473 static const struct dcn_hubp2_registers hubp_regs[] = {
474 hubp_regs(0),
475 hubp_regs(1),
476 hubp_regs(2),
477 hubp_regs(3)
478 };
479
480 static const struct dcn_hubp2_shift hubp_shift = {
481 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
482 };
483
484 static const struct dcn_hubp2_mask hubp_mask = {
485 HUBP_MASK_SH_LIST_DCN21(_MASK)
486 };
487
488 static const struct dcn_hubbub_registers hubbub_reg = {
489 HUBBUB_REG_LIST_DCN21()
490 };
491
492 static const struct dcn_hubbub_shift hubbub_shift = {
493 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
494 };
495
496 static const struct dcn_hubbub_mask hubbub_mask = {
497 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
498 };
499
500
501 #define vmid_regs(id)\
502 [id] = {\
503 DCN20_VMID_REG_LIST(id)\
504 }
505
506 static const struct dcn_vmid_registers vmid_regs[] = {
507 vmid_regs(0),
508 vmid_regs(1),
509 vmid_regs(2),
510 vmid_regs(3),
511 vmid_regs(4),
512 vmid_regs(5),
513 vmid_regs(6),
514 vmid_regs(7),
515 vmid_regs(8),
516 vmid_regs(9),
517 vmid_regs(10),
518 vmid_regs(11),
519 vmid_regs(12),
520 vmid_regs(13),
521 vmid_regs(14),
522 vmid_regs(15)
523 };
524
525 static const struct dcn20_vmid_shift vmid_shifts = {
526 DCN20_VMID_MASK_SH_LIST(__SHIFT)
527 };
528
529 static const struct dcn20_vmid_mask vmid_masks = {
530 DCN20_VMID_MASK_SH_LIST(_MASK)
531 };
532
533 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
534 #define dsc_regsDCN20(id)\
535 [id] = {\
536 DSC_REG_LIST_DCN20(id)\
537 }
538
539 static const struct dcn20_dsc_registers dsc_regs[] = {
540 dsc_regsDCN20(0),
541 dsc_regsDCN20(1),
542 dsc_regsDCN20(2),
543 dsc_regsDCN20(3),
544 dsc_regsDCN20(4),
545 dsc_regsDCN20(5)
546 };
547
548 static const struct dcn20_dsc_shift dsc_shift = {
549 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
550 };
551
552 static const struct dcn20_dsc_mask dsc_mask = {
553 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
554 };
555 #endif
556
557 #define ipp_regs(id)\
558 [id] = {\
559 IPP_REG_LIST_DCN20(id),\
560 }
561
562 static const struct dcn10_ipp_registers ipp_regs[] = {
563 ipp_regs(0),
564 ipp_regs(1),
565 ipp_regs(2),
566 ipp_regs(3),
567 };
568
569 static const struct dcn10_ipp_shift ipp_shift = {
570 IPP_MASK_SH_LIST_DCN20(__SHIFT)
571 };
572
573 static const struct dcn10_ipp_mask ipp_mask = {
574 IPP_MASK_SH_LIST_DCN20(_MASK),
575 };
576
577 #define opp_regs(id)\
578 [id] = {\
579 OPP_REG_LIST_DCN20(id),\
580 }
581
582
583 #define aux_engine_regs(id)\
584 [id] = {\
585 AUX_COMMON_REG_LIST0(id), \
586 .AUXN_IMPCAL = 0, \
587 .AUXP_IMPCAL = 0, \
588 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
589 }
590
591 static const struct dce110_aux_registers aux_engine_regs[] = {
592 aux_engine_regs(0),
593 aux_engine_regs(1),
594 aux_engine_regs(2),
595 aux_engine_regs(3),
596 aux_engine_regs(4),
597 };
598
599 #define tf_regs(id)\
600 [id] = {\
601 TF_REG_LIST_DCN20(id),\
602 }
603
604 static const struct dcn2_dpp_registers tf_regs[] = {
605 tf_regs(0),
606 tf_regs(1),
607 tf_regs(2),
608 tf_regs(3),
609 };
610
611 static const struct dcn2_dpp_shift tf_shift = {
612 TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
613 };
614
615 static const struct dcn2_dpp_mask tf_mask = {
616 TF_REG_LIST_SH_MASK_DCN20(_MASK)
617 };
618
619 #define stream_enc_regs(id)\
620 [id] = {\
621 SE_DCN2_REG_LIST(id)\
622 }
623
624 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
625 stream_enc_regs(0),
626 stream_enc_regs(1),
627 stream_enc_regs(2),
628 stream_enc_regs(3),
629 stream_enc_regs(4),
630 };
631
632 static const struct dcn10_stream_encoder_shift se_shift = {
633 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
634 };
635
636 static const struct dcn10_stream_encoder_mask se_mask = {
637 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
638 };
639
640 static struct input_pixel_processor *dcn21_ipp_create(
641 struct dc_context *ctx, uint32_t inst)
642 {
643 struct dcn10_ipp *ipp =
644 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
645
646 if (!ipp) {
647 BREAK_TO_DEBUGGER();
648 return NULL;
649 }
650
651 dcn20_ipp_construct(ipp, ctx, inst,
652 &ipp_regs[inst], &ipp_shift, &ipp_mask);
653 return &ipp->base;
654 }
655
656 static struct dpp *dcn21_dpp_create(
657 struct dc_context *ctx,
658 uint32_t inst)
659 {
660 struct dcn20_dpp *dpp =
661 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
662
663 if (!dpp)
664 return NULL;
665
666 if (dpp2_construct(dpp, ctx, inst,
667 &tf_regs[inst], &tf_shift, &tf_mask))
668 return &dpp->base;
669
670 BREAK_TO_DEBUGGER();
671 kfree(dpp);
672 return NULL;
673 }
674
675 static struct dce_aux *dcn21_aux_engine_create(
676 struct dc_context *ctx,
677 uint32_t inst)
678 {
679 struct aux_engine_dce110 *aux_engine =
680 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
681
682 if (!aux_engine)
683 return NULL;
684
685 dce110_aux_engine_construct(aux_engine, ctx, inst,
686 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
687 &aux_engine_regs[inst]);
688
689 return &aux_engine->base;
690 }
691
692 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
693
694 static const struct dce_i2c_registers i2c_hw_regs[] = {
695 i2c_inst_regs(1),
696 i2c_inst_regs(2),
697 i2c_inst_regs(3),
698 i2c_inst_regs(4),
699 i2c_inst_regs(5),
700 };
701
702 static const struct dce_i2c_shift i2c_shifts = {
703 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
704 };
705
706 static const struct dce_i2c_mask i2c_masks = {
707 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
708 };
709
710 struct dce_i2c_hw *dcn21_i2c_hw_create(
711 struct dc_context *ctx,
712 uint32_t inst)
713 {
714 struct dce_i2c_hw *dce_i2c_hw =
715 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
716
717 if (!dce_i2c_hw)
718 return NULL;
719
720 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
721 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
722
723 return dce_i2c_hw;
724 }
725
726 static const struct resource_caps res_cap_rn = {
727 .num_timing_generator = 4,
728 .num_opp = 4,
729 .num_video_plane = 4,
730 .num_audio = 6,
731 .num_stream_encoder = 5,
732 .num_pll = 5,
733 .num_dwb = 1,
734 .num_ddc = 5,
735 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
736 .num_dsc = 3,
737 #endif
738 };
739
740 #ifdef DIAGS_BUILD
741 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
742 .num_timing_generator = 4,
743 .num_opp = 4,
744 .num_video_plane = 4,
745 .num_audio = 7,
746 .num_stream_encoder = 4,
747 .num_pll = 4,
748 .num_dwb = 1,
749 .num_ddc = 4,
750 .num_dsc = 0,
751 };
752
753 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
754 .num_timing_generator = 2,
755 .num_opp = 2,
756 .num_video_plane = 2,
757 .num_audio = 7,
758 .num_stream_encoder = 2,
759 .num_pll = 4,
760 .num_dwb = 1,
761 .num_ddc = 4,
762 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
763 .num_dsc = 2,
764 #endif
765 };
766 #endif
767
768 static const struct dc_plane_cap plane_cap = {
769 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
770 .blends_with_above = true,
771 .blends_with_below = true,
772 .per_pixel_alpha = true,
773
774 .pixel_format_support = {
775 .argb8888 = true,
776 .nv12 = true,
777 .fp16 = true
778 },
779
780 .max_upscale_factor = {
781 .argb8888 = 16000,
782 .nv12 = 16000,
783 .fp16 = 16000
784 },
785
786 .max_downscale_factor = {
787 .argb8888 = 250,
788 .nv12 = 250,
789 .fp16 = 250
790 }
791 };
792
793 static const struct dc_debug_options debug_defaults_drv = {
794 .disable_dmcu = true,
795 .force_abm_enable = false,
796 .timing_trace = false,
797 .clock_trace = true,
798 .disable_pplib_clock_request = true,
799 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
800 .force_single_disp_pipe_split = true,
801 .disable_dcc = DCC_ENABLE,
802 .vsr_support = true,
803 .performance_trace = false,
804 .max_downscale_src_width = 5120,
805 .disable_pplib_wm_range = false,
806 .scl_reset_length10 = true,
807 .sanity_checks = true,
808 .disable_48mhz_pwrdwn = true,
809 };
810
811 static const struct dc_debug_options debug_defaults_diags = {
812 .disable_dmcu = true,
813 .force_abm_enable = false,
814 .timing_trace = true,
815 .clock_trace = true,
816 .disable_dpp_power_gate = true,
817 .disable_hubp_power_gate = true,
818 .disable_clock_gate = true,
819 .disable_pplib_clock_request = true,
820 .disable_pplib_wm_range = true,
821 .disable_stutter = true,
822 .disable_48mhz_pwrdwn = true,
823 };
824
825 enum dcn20_clk_src_array_id {
826 DCN20_CLK_SRC_PLL0,
827 DCN20_CLK_SRC_PLL1,
828 DCN20_CLK_SRC_PLL2,
829 DCN20_CLK_SRC_TOTAL_DCN21
830 };
831
832 static void destruct(struct dcn21_resource_pool *pool)
833 {
834 unsigned int i;
835
836 for (i = 0; i < pool->base.stream_enc_count; i++) {
837 if (pool->base.stream_enc[i] != NULL) {
838 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
839 pool->base.stream_enc[i] = NULL;
840 }
841 }
842
843 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
844 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
845 if (pool->base.dscs[i] != NULL)
846 dcn20_dsc_destroy(&pool->base.dscs[i]);
847 }
848 #endif
849
850 if (pool->base.mpc != NULL) {
851 kfree(TO_DCN20_MPC(pool->base.mpc));
852 pool->base.mpc = NULL;
853 }
854 if (pool->base.hubbub != NULL) {
855 kfree(pool->base.hubbub);
856 pool->base.hubbub = NULL;
857 }
858 for (i = 0; i < pool->base.pipe_count; i++) {
859 if (pool->base.dpps[i] != NULL)
860 dcn20_dpp_destroy(&pool->base.dpps[i]);
861
862 if (pool->base.ipps[i] != NULL)
863 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
864
865 if (pool->base.hubps[i] != NULL) {
866 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
867 pool->base.hubps[i] = NULL;
868 }
869
870 if (pool->base.irqs != NULL) {
871 dal_irq_service_destroy(&pool->base.irqs);
872 }
873 }
874
875 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
876 if (pool->base.engines[i] != NULL)
877 dce110_engine_destroy(&pool->base.engines[i]);
878 if (pool->base.hw_i2cs[i] != NULL) {
879 kfree(pool->base.hw_i2cs[i]);
880 pool->base.hw_i2cs[i] = NULL;
881 }
882 if (pool->base.sw_i2cs[i] != NULL) {
883 kfree(pool->base.sw_i2cs[i]);
884 pool->base.sw_i2cs[i] = NULL;
885 }
886 }
887
888 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
889 if (pool->base.opps[i] != NULL)
890 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
891 }
892
893 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
894 if (pool->base.timing_generators[i] != NULL) {
895 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
896 pool->base.timing_generators[i] = NULL;
897 }
898 }
899
900 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
901 if (pool->base.dwbc[i] != NULL) {
902 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
903 pool->base.dwbc[i] = NULL;
904 }
905 if (pool->base.mcif_wb[i] != NULL) {
906 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
907 pool->base.mcif_wb[i] = NULL;
908 }
909 }
910
911 for (i = 0; i < pool->base.audio_count; i++) {
912 if (pool->base.audios[i])
913 dce_aud_destroy(&pool->base.audios[i]);
914 }
915
916 for (i = 0; i < pool->base.clk_src_count; i++) {
917 if (pool->base.clock_sources[i] != NULL) {
918 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
919 pool->base.clock_sources[i] = NULL;
920 }
921 }
922
923 if (pool->base.dp_clock_source != NULL) {
924 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
925 pool->base.dp_clock_source = NULL;
926 }
927
928
929 if (pool->base.abm != NULL)
930 dce_abm_destroy(&pool->base.abm);
931
932 if (pool->base.dmcu != NULL)
933 dce_dmcu_destroy(&pool->base.dmcu);
934
935 #ifdef CONFIG_DRM_AMD_DC_DMUB
936 if (pool->base.dmcub != NULL)
937 dcn21_dmcub_destroy(&pool->base.dmcub);
938 #endif
939
940 if (pool->base.dccg != NULL)
941 dcn_dccg_destroy(&pool->base.dccg);
942
943 if (pool->base.pp_smu != NULL)
944 dcn20_pp_smu_destroy(&pool->base.pp_smu);
945 }
946
947
948 static void calculate_wm_set_for_vlevel(
949 int vlevel,
950 struct wm_range_table_entry *table_entry,
951 struct dcn_watermarks *wm_set,
952 struct display_mode_lib *dml,
953 display_e2e_pipe_params_st *pipes,
954 int pipe_cnt)
955 {
956 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
957
958 ASSERT(vlevel < dml->soc.num_states);
959
960 pipes[0].clks_cfg.voltage = vlevel;
961 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
962 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
963
964 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
965
966 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
967 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
968 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
969 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
970 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
971 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
972 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
973 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
974 #endif
975 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
976
977 }
978
979 void dcn21_calculate_wm(
980 struct dc *dc, struct dc_state *context,
981 display_e2e_pipe_params_st *pipes,
982 int *out_pipe_cnt,
983 int *pipe_split_from,
984 int vlevel_req)
985 {
986 int pipe_cnt, i, pipe_idx;
987 int vlevel, vlevel_max;
988 struct wm_range_table_entry *table_entry;
989 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
990
991 ASSERT(bw_params);
992
993 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
994 if (!context->res_ctx.pipe_ctx[i].stream)
995 continue;
996
997 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
998 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
999
1000 if (pipe_split_from[i] < 0) {
1001 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1002 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1003 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1004 pipes[pipe_cnt].pipe.dest.odm_combine =
1005 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1006 else
1007 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1008 pipe_idx++;
1009 } else {
1010 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1011 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1012 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1013 pipes[pipe_cnt].pipe.dest.odm_combine =
1014 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1015 else
1016 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1017 }
1018 pipe_cnt++;
1019 }
1020
1021 if (pipe_cnt != pipe_idx) {
1022 if (dc->res_pool->funcs->populate_dml_pipes)
1023 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1024 &context->res_ctx, pipes);
1025 else
1026 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
1027 &context->res_ctx, pipes);
1028 }
1029
1030 *out_pipe_cnt = pipe_cnt;
1031
1032 vlevel_max = bw_params->clk_table.num_entries - 1;
1033
1034
1035
1036 table_entry = &bw_params->wm_table.entries[WM_D];
1037 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1038 vlevel = 0;
1039 else
1040 vlevel = vlevel_max;
1041 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1042 &context->bw_ctx.dml, pipes, pipe_cnt);
1043
1044 table_entry = &bw_params->wm_table.entries[WM_C];
1045 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1046 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1047 &context->bw_ctx.dml, pipes, pipe_cnt);
1048
1049 table_entry = &bw_params->wm_table.entries[WM_B];
1050 vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1051 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1052 &context->bw_ctx.dml, pipes, pipe_cnt);
1053
1054
1055 table_entry = &bw_params->wm_table.entries[WM_A];
1056 vlevel = MIN(vlevel_req, vlevel_max);
1057 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1058 &context->bw_ctx.dml, pipes, pipe_cnt);
1059 }
1060
1061
1062 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1063 bool fast_validate)
1064 {
1065 bool out = false;
1066
1067 BW_VAL_TRACE_SETUP();
1068
1069 int vlevel = 0;
1070 int pipe_split_from[MAX_PIPES];
1071 int pipe_cnt = 0;
1072 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1073 DC_LOGGER_INIT(dc->ctx->logger);
1074
1075 BW_VAL_TRACE_COUNT();
1076
1077 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1078
1079 if (pipe_cnt == 0)
1080 goto validate_out;
1081
1082 if (!out)
1083 goto validate_fail;
1084
1085 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1086
1087 if (fast_validate) {
1088 BW_VAL_TRACE_SKIP(fast);
1089 goto validate_out;
1090 }
1091
1092 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1093 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1094
1095 BW_VAL_TRACE_END_WATERMARKS();
1096
1097 goto validate_out;
1098
1099 validate_fail:
1100 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1101 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1102
1103 BW_VAL_TRACE_SKIP(fail);
1104 out = false;
1105
1106 validate_out:
1107 kfree(pipes);
1108
1109 BW_VAL_TRACE_FINISH();
1110
1111 return out;
1112 }
1113 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1114 {
1115 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1116
1117 destruct(dcn21_pool);
1118 kfree(dcn21_pool);
1119 *pool = NULL;
1120 }
1121
1122 static struct clock_source *dcn21_clock_source_create(
1123 struct dc_context *ctx,
1124 struct dc_bios *bios,
1125 enum clock_source_id id,
1126 const struct dce110_clk_src_regs *regs,
1127 bool dp_clk_src)
1128 {
1129 struct dce110_clk_src *clk_src =
1130 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1131
1132 if (!clk_src)
1133 return NULL;
1134
1135 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1136 regs, &cs_shift, &cs_mask)) {
1137 clk_src->base.dp_clk_src = dp_clk_src;
1138 return &clk_src->base;
1139 }
1140
1141 BREAK_TO_DEBUGGER();
1142 return NULL;
1143 }
1144
1145 static struct hubp *dcn21_hubp_create(
1146 struct dc_context *ctx,
1147 uint32_t inst)
1148 {
1149 struct dcn21_hubp *hubp21 =
1150 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1151
1152 if (!hubp21)
1153 return NULL;
1154
1155 if (hubp21_construct(hubp21, ctx, inst,
1156 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1157 return &hubp21->base;
1158
1159 BREAK_TO_DEBUGGER();
1160 kfree(hubp21);
1161 return NULL;
1162 }
1163
1164 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1165 {
1166 int i;
1167
1168 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1169 GFP_KERNEL);
1170
1171 if (!hubbub)
1172 return NULL;
1173
1174 hubbub21_construct(hubbub, ctx,
1175 &hubbub_reg,
1176 &hubbub_shift,
1177 &hubbub_mask);
1178
1179 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1180 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1181
1182 vmid->ctx = ctx;
1183
1184 vmid->regs = &vmid_regs[i];
1185 vmid->shifts = &vmid_shifts;
1186 vmid->masks = &vmid_masks;
1187 }
1188
1189 return &hubbub->base;
1190 }
1191
1192 struct output_pixel_processor *dcn21_opp_create(
1193 struct dc_context *ctx, uint32_t inst)
1194 {
1195 struct dcn20_opp *opp =
1196 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1197
1198 if (!opp) {
1199 BREAK_TO_DEBUGGER();
1200 return NULL;
1201 }
1202
1203 dcn20_opp_construct(opp, ctx, inst,
1204 &opp_regs[inst], &opp_shift, &opp_mask);
1205 return &opp->base;
1206 }
1207
1208 struct timing_generator *dcn21_timing_generator_create(
1209 struct dc_context *ctx,
1210 uint32_t instance)
1211 {
1212 struct optc *tgn10 =
1213 kzalloc(sizeof(struct optc), GFP_KERNEL);
1214
1215 if (!tgn10)
1216 return NULL;
1217
1218 tgn10->base.inst = instance;
1219 tgn10->base.ctx = ctx;
1220
1221 tgn10->tg_regs = &tg_regs[instance];
1222 tgn10->tg_shift = &tg_shift;
1223 tgn10->tg_mask = &tg_mask;
1224
1225 dcn20_timing_generator_init(tgn10);
1226
1227 return &tgn10->base;
1228 }
1229
1230 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1231 {
1232 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1233 GFP_KERNEL);
1234
1235 if (!mpc20)
1236 return NULL;
1237
1238 dcn20_mpc_construct(mpc20, ctx,
1239 &mpc_regs,
1240 &mpc_shift,
1241 &mpc_mask,
1242 6);
1243
1244 return &mpc20->base;
1245 }
1246
1247 static void read_dce_straps(
1248 struct dc_context *ctx,
1249 struct resource_straps *straps)
1250 {
1251 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1252 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1253
1254 }
1255
1256 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1257
1258 struct display_stream_compressor *dcn21_dsc_create(
1259 struct dc_context *ctx, uint32_t inst)
1260 {
1261 struct dcn20_dsc *dsc =
1262 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1263
1264 if (!dsc) {
1265 BREAK_TO_DEBUGGER();
1266 return NULL;
1267 }
1268
1269 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1270 return &dsc->base;
1271 }
1272 #endif
1273
1274 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1275 {
1276 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1277 struct clk_limit_table *clk_table = &bw_params->clk_table;
1278 int i;
1279
1280 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1281 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1282 dcn2_1_soc.num_chans = bw_params->num_channels;
1283 dcn2_1_soc.num_states = 0;
1284
1285 for (i = 0; i < clk_table->num_entries; i++) {
1286
1287 dcn2_1_soc.clock_limits[i].state = i;
1288 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1289 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1290 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1291
1292 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
1293 dcn2_1_soc.num_states++;
1294 }
1295 }
1296
1297
1298 static struct dpm_clocks dummy_clocks = {
1299 .DcfClocks = {
1300 {.Freq = 400, .Vol = 1},
1301 {.Freq = 483, .Vol = 1},
1302 {.Freq = 602, .Vol = 1},
1303 {.Freq = 738, .Vol = 1} },
1304 .SocClocks = {
1305 {.Freq = 300, .Vol = 1},
1306 {.Freq = 400, .Vol = 1},
1307 {.Freq = 400, .Vol = 1},
1308 {.Freq = 400, .Vol = 1} },
1309 .FClocks = {
1310 {.Freq = 400, .Vol = 1},
1311 {.Freq = 800, .Vol = 1},
1312 {.Freq = 1067, .Vol = 1},
1313 {.Freq = 1600, .Vol = 1} },
1314 .MemClocks = {
1315 {.Freq = 800, .Vol = 1},
1316 {.Freq = 1600, .Vol = 1},
1317 {.Freq = 1067, .Vol = 1},
1318 {.Freq = 1600, .Vol = 1} },
1319
1320 };
1321
1322 enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
1323 struct pp_smu_wm_range_sets *ranges)
1324 {
1325 return PP_SMU_RESULT_OK;
1326 }
1327
1328 enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
1329 struct dpm_clocks *clock_table)
1330 {
1331 *clock_table = dummy_clocks;
1332 return PP_SMU_RESULT_OK;
1333 }
1334
1335 struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1336 {
1337 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1338
1339 pp_smu->ctx.ver = PP_SMU_VER_RN;
1340
1341 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1342 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1343
1344 return pp_smu;
1345 }
1346
1347 void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1348 {
1349 if (pp_smu && *pp_smu) {
1350 kfree(*pp_smu);
1351 *pp_smu = NULL;
1352 }
1353 }
1354
1355 static struct audio *dcn21_create_audio(
1356 struct dc_context *ctx, unsigned int inst)
1357 {
1358 return dce_audio_create(ctx, inst,
1359 &audio_regs[inst], &audio_shift, &audio_mask);
1360 }
1361
1362 static struct dc_cap_funcs cap_funcs = {
1363 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1364 };
1365
1366 struct stream_encoder *dcn21_stream_encoder_create(
1367 enum engine_id eng_id,
1368 struct dc_context *ctx)
1369 {
1370 struct dcn10_stream_encoder *enc1 =
1371 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1372
1373 if (!enc1)
1374 return NULL;
1375
1376 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1377 &stream_enc_regs[eng_id],
1378 &se_shift, &se_mask);
1379
1380 return &enc1->base;
1381 }
1382
1383 static const struct dce_hwseq_registers hwseq_reg = {
1384 HWSEQ_DCN21_REG_LIST()
1385 };
1386
1387 static const struct dce_hwseq_shift hwseq_shift = {
1388 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1389 };
1390
1391 static const struct dce_hwseq_mask hwseq_mask = {
1392 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1393 };
1394
1395 static struct dce_hwseq *dcn21_hwseq_create(
1396 struct dc_context *ctx)
1397 {
1398 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1399
1400 if (hws) {
1401 hws->ctx = ctx;
1402 hws->regs = &hwseq_reg;
1403 hws->shifts = &hwseq_shift;
1404 hws->masks = &hwseq_mask;
1405 }
1406 return hws;
1407 }
1408
1409 static const struct resource_create_funcs res_create_funcs = {
1410 .read_dce_straps = read_dce_straps,
1411 .create_audio = dcn21_create_audio,
1412 .create_stream_encoder = dcn21_stream_encoder_create,
1413 .create_hwseq = dcn21_hwseq_create,
1414 };
1415
1416 static const struct resource_create_funcs res_create_maximus_funcs = {
1417 .read_dce_straps = NULL,
1418 .create_audio = NULL,
1419 .create_stream_encoder = NULL,
1420 .create_hwseq = dcn21_hwseq_create,
1421 };
1422
1423 static struct resource_funcs dcn21_res_pool_funcs = {
1424 .destroy = dcn21_destroy_resource_pool,
1425 .link_enc_create = dcn20_link_encoder_create,
1426 .validate_bandwidth = dcn21_validate_bandwidth,
1427 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1428 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1429 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1430 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1431 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
1432 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1433 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1434 .update_bw_bounding_box = update_bw_bounding_box
1435 };
1436
1437 static bool construct(
1438 uint8_t num_virtual_links,
1439 struct dc *dc,
1440 struct dcn21_resource_pool *pool)
1441 {
1442 int i;
1443 struct dc_context *ctx = dc->ctx;
1444 struct irq_service_init_data init_data;
1445
1446 ctx->dc_bios->regs = &bios_regs;
1447
1448 pool->base.res_cap = &res_cap_rn;
1449 #ifdef DIAGS_BUILD
1450 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1451
1452 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1453 #endif
1454
1455 pool->base.funcs = &dcn21_res_pool_funcs;
1456
1457
1458
1459
1460 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1461
1462 pool->base.pipe_count = 4;
1463 dc->caps.max_downscale_ratio = 200;
1464 dc->caps.i2c_speed_in_khz = 100;
1465 dc->caps.max_cursor_size = 256;
1466 dc->caps.dmdata_alloc_size = 2048;
1467 dc->caps.hw_3d_lut = true;
1468
1469 dc->caps.max_slave_planes = 1;
1470 dc->caps.post_blend_color_processing = true;
1471 dc->caps.force_dp_tps4_for_cp2520 = true;
1472
1473 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1474 dc->debug = debug_defaults_drv;
1475 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1476 pool->base.pipe_count = 4;
1477 dc->debug = debug_defaults_diags;
1478 } else
1479 dc->debug = debug_defaults_diags;
1480
1481
1482 if (dc->vm_helper)
1483 vm_helper_init(dc->vm_helper, 16);
1484
1485
1486
1487
1488
1489 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1490 dcn21_clock_source_create(ctx, ctx->dc_bios,
1491 CLOCK_SOURCE_COMBO_PHY_PLL0,
1492 &clk_src_regs[0], false);
1493 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1494 dcn21_clock_source_create(ctx, ctx->dc_bios,
1495 CLOCK_SOURCE_COMBO_PHY_PLL1,
1496 &clk_src_regs[1], false);
1497 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1498 dcn21_clock_source_create(ctx, ctx->dc_bios,
1499 CLOCK_SOURCE_COMBO_PHY_PLL2,
1500 &clk_src_regs[2], false);
1501
1502 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1503
1504
1505 pool->base.dp_clock_source =
1506 dcn21_clock_source_create(ctx, ctx->dc_bios,
1507 CLOCK_SOURCE_ID_DP_DTO,
1508 &clk_src_regs[0], true);
1509
1510 for (i = 0; i < pool->base.clk_src_count; i++) {
1511 if (pool->base.clock_sources[i] == NULL) {
1512 dm_error("DC: failed to create clock sources!\n");
1513 BREAK_TO_DEBUGGER();
1514 goto create_fail;
1515 }
1516 }
1517
1518 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1519 if (pool->base.dccg == NULL) {
1520 dm_error("DC: failed to create dccg!\n");
1521 BREAK_TO_DEBUGGER();
1522 goto create_fail;
1523 }
1524
1525 #ifdef CONFIG_DRM_AMD_DC_DMUB
1526 pool->base.dmcub = dcn21_dmcub_create(ctx,
1527 &dmcub_regs,
1528 &dmcub_shift,
1529 &dmcub_mask);
1530 if (pool->base.dmcub == NULL) {
1531 dm_error("DC: failed to create dmcub!\n");
1532 BREAK_TO_DEBUGGER();
1533 goto create_fail;
1534 }
1535 #endif
1536
1537 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1538
1539 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1540
1541 init_data.ctx = dc->ctx;
1542 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1543 if (!pool->base.irqs)
1544 goto create_fail;
1545
1546
1547 for (i = 0; i < pool->base.pipe_count; i++) {
1548 pool->base.hubps[i] = dcn21_hubp_create(ctx, i);
1549 if (pool->base.hubps[i] == NULL) {
1550 BREAK_TO_DEBUGGER();
1551 dm_error(
1552 "DC: failed to create memory input!\n");
1553 goto create_fail;
1554 }
1555
1556 pool->base.ipps[i] = dcn21_ipp_create(ctx, i);
1557 if (pool->base.ipps[i] == NULL) {
1558 BREAK_TO_DEBUGGER();
1559 dm_error(
1560 "DC: failed to create input pixel processor!\n");
1561 goto create_fail;
1562 }
1563
1564 pool->base.dpps[i] = dcn21_dpp_create(ctx, i);
1565 if (pool->base.dpps[i] == NULL) {
1566 BREAK_TO_DEBUGGER();
1567 dm_error(
1568 "DC: failed to create dpps!\n");
1569 goto create_fail;
1570 }
1571 }
1572
1573 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1574 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1575 if (pool->base.engines[i] == NULL) {
1576 BREAK_TO_DEBUGGER();
1577 dm_error(
1578 "DC:failed to create aux engine!!\n");
1579 goto create_fail;
1580 }
1581 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1582 if (pool->base.hw_i2cs[i] == NULL) {
1583 BREAK_TO_DEBUGGER();
1584 dm_error(
1585 "DC:failed to create hw i2c!!\n");
1586 goto create_fail;
1587 }
1588 pool->base.sw_i2cs[i] = NULL;
1589 }
1590
1591 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1592 pool->base.opps[i] = dcn21_opp_create(ctx, i);
1593 if (pool->base.opps[i] == NULL) {
1594 BREAK_TO_DEBUGGER();
1595 dm_error(
1596 "DC: failed to create output pixel processor!\n");
1597 goto create_fail;
1598 }
1599 }
1600
1601 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1602 pool->base.timing_generators[i] = dcn21_timing_generator_create(
1603 ctx, i);
1604 if (pool->base.timing_generators[i] == NULL) {
1605 BREAK_TO_DEBUGGER();
1606 dm_error("DC: failed to create tg!\n");
1607 goto create_fail;
1608 }
1609 }
1610
1611 pool->base.timing_generator_count = i;
1612
1613 pool->base.mpc = dcn21_mpc_create(ctx);
1614 if (pool->base.mpc == NULL) {
1615 BREAK_TO_DEBUGGER();
1616 dm_error("DC: failed to create mpc!\n");
1617 goto create_fail;
1618 }
1619
1620 pool->base.hubbub = dcn21_hubbub_create(ctx);
1621 if (pool->base.hubbub == NULL) {
1622 BREAK_TO_DEBUGGER();
1623 dm_error("DC: failed to create hubbub!\n");
1624 goto create_fail;
1625 }
1626
1627 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1628 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1629 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1630 if (pool->base.dscs[i] == NULL) {
1631 BREAK_TO_DEBUGGER();
1632 dm_error("DC: failed to create display stream compressor %d!\n", i);
1633 goto create_fail;
1634 }
1635 }
1636 #endif
1637
1638 if (!dcn20_dwbc_create(ctx, &pool->base)) {
1639 BREAK_TO_DEBUGGER();
1640 dm_error("DC: failed to create dwbc!\n");
1641 goto create_fail;
1642 }
1643 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1644 BREAK_TO_DEBUGGER();
1645 dm_error("DC: failed to create mcif_wb!\n");
1646 goto create_fail;
1647 }
1648
1649 if (!resource_construct(num_virtual_links, dc, &pool->base,
1650 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1651 &res_create_funcs : &res_create_maximus_funcs)))
1652 goto create_fail;
1653
1654 dcn20_hw_sequencer_construct(dc);
1655
1656 dc->caps.max_planes = pool->base.pipe_count;
1657
1658 for (i = 0; i < dc->caps.max_planes; ++i)
1659 dc->caps.planes[i] = plane_cap;
1660
1661 dc->cap_funcs = cap_funcs;
1662
1663 return true;
1664
1665 create_fail:
1666
1667 destruct(pool);
1668
1669 return false;
1670 }
1671
1672 struct resource_pool *dcn21_create_resource_pool(
1673 const struct dc_init_data *init_data,
1674 struct dc *dc)
1675 {
1676 struct dcn21_resource_pool *pool =
1677 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
1678
1679 if (!pool)
1680 return NULL;
1681
1682 if (construct(init_data->num_virtual_links, dc, pool))
1683 return &pool->base;
1684
1685 BREAK_TO_DEBUGGER();
1686 kfree(pool);
1687 return NULL;
1688 }