drivers/gpu/drm/amd/display/dc/dcn21/dcn21

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This source file includes following definitions.
apply_DEDCN21_142_wa_for_hostvm_deadline
hubp21_program_deadline
hubp21_program_requestor
hubp21_setup
hubp21_set_vm_system_aperture_settings
hubp21_init
hubp21_construct
   1 /*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dcn21_hubp.h"
  26 
  27 #include "dm_services.h"
  28 #include "reg_helper.h"
  29 
  30 #define REG(reg)\
  31         hubp21->hubp_regs->reg
  32 
  33 #define CTX \
  34         hubp21->base.ctx
  35 
  36 #undef FN
  37 #define FN(reg_name, field_name) \
  38         hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name
  39 
  40 /*
  41  * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL.
  42  * As a result, if S/W updates any of these registers during a mode change,
  43  * the current frame before the mode change will use the new value right away
  44  * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior.
  45  *
  46  * REFCYC_PER_VM_GROUP_FLIP[22:0]
  47  * REFCYC_PER_VM_GROUP_VBLANK[22:0]
  48  * REFCYC_PER_VM_REQ_FLIP[22:0]
  49  * REFCYC_PER_VM_REQ_VBLANK[22:0]
  50  *
  51  * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated
  52  * when flipping to a new surface
  53  *
  54  * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated
  55  * during prefetch  period of a frame. The prefetch starts at a pre-determined
  56  * number of lines before the display active per frame
  57  *
  58  * DCN may underflow due to incorrectly programming these registers
  59  * during VM stage of prefetch/iflip. First lines of display active
  60  * or a sub-region of active using a new surface will be corrupted
  61  * until the VM data returns at flip/mode change transitions
  62  *
  63  * Work around:
  64  * workaround is always opt to use the more aggressive settings.
  65  * On any mode switch, if the new reg values are smaller than the current values,
  66  * then update the regs with the new values.
  67  *
  68  * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142
  69  *
  70  */
  71 void apply_DEDCN21_142_wa_for_hostvm_deadline(
  72                 struct hubp *hubp,
  73                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
  74 {
  75         struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
  76         uint32_t cur_value;
  77 
  78         REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
  79         if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
  80                 REG_SET(VBLANK_PARAMETERS_5, 0,
  81                                 REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank);
  82 
  83         REG_GET(VBLANK_PARAMETERS_6,
  84                         REFCYC_PER_VM_REQ_VBLANK,
  85                         &cur_value);
  86         if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
  87                 REG_SET(VBLANK_PARAMETERS_6, 0,
  88                                 REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank);
  89 
  90         REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
  91         if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
  92                 REG_SET(FLIP_PARAMETERS_3, 0,
  93                                 REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip);
  94 
  95         REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
  96         if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
  97                 REG_SET(FLIP_PARAMETERS_4, 0,
  98                                         REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip);
  99 
 100         REG_SET(FLIP_PARAMETERS_5, 0,
 101                         REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c);
 102         REG_SET(FLIP_PARAMETERS_6, 0,
 103                         REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c);
 104 }
 105 
 106 void hubp21_program_deadline(
 107                 struct hubp *hubp,
 108                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 109                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
 110 {
 111         hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
 112 
 113         apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);
 114 }
 115 
 116 void hubp21_program_requestor(
 117                 struct hubp *hubp,
 118                 struct _vcs_dpi_display_rq_regs_st *rq_regs)
 119 {
 120         struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
 121 
 122         REG_UPDATE(HUBPRET_CONTROL,
 123                         DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
 124         REG_SET_4(DCN_EXPANSION_MODE, 0,
 125                         DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
 126                         PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
 127                         MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
 128                         CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
 129         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
 130                 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
 131                 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
 132                 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
 133                 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
 134                 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
 135                 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
 136                 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
 137                 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
 138         REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0,
 139                 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
 140                 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
 141                 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
 142                 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
 143                 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
 144                 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
 145                 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
 146 }
 147 
 148 static void hubp21_setup(
 149                 struct hubp *hubp,
 150                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 151                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
 152                 struct _vcs_dpi_display_rq_regs_st *rq_regs,
 153                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 154 {
 155         /* otg is locked when this func is called. Register are double buffered.
 156          * disable the requestors is not needed
 157          */
 158 
 159         hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
 160         hubp21_program_requestor(hubp, rq_regs);
 161         hubp21_program_deadline(hubp, dlg_attr, ttu_attr);
 162 
 163 }
 164 
 165 void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
 166                 struct vm_system_aperture_param *apt)
 167 {
 168         struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
 169 
 170         PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
 171         PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
 172         PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
 173 
 174         // The format of default addr is 48:12 of the 48 bit addr
 175         mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
 176 
 177         // The format of high/low are 48:18 of the 48 bit addr
 178         mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
 179         mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
 180 
 181         REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
 182                         MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
 183 
 184         REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
 185                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
 186 
 187         REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
 188                         ENABLE_L1_TLB, 1,
 189                         SYSTEM_ACCESS_MODE, 0x3);
 190 }
 191 
 192 void hubp21_init(struct hubp *hubp)
 193 {
 194         // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
 195         // This is a chicken bit to enable the ECO fix.
 196 
 197         struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
 198         //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
 199         REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
 200 }
 201 static struct hubp_funcs dcn21_hubp_funcs = {
 202         .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
 203         .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
 204         .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
 205         .hubp_program_surface_config = hubp2_program_surface_config,
 206         .hubp_is_flip_pending = hubp1_is_flip_pending,
 207         .hubp_setup = hubp21_setup,
 208         .hubp_setup_interdependent = hubp2_setup_interdependent,
 209         .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
 210         .set_blank = hubp1_set_blank,
 211         .dcc_control = hubp1_dcc_control,
 212         .mem_program_viewport = min_set_viewport,
 213         .set_cursor_attributes  = hubp2_cursor_set_attributes,
 214         .set_cursor_position    = hubp1_cursor_set_position,
 215         .hubp_clk_cntl = hubp1_clk_cntl,
 216         .hubp_vtg_sel = hubp1_vtg_sel,
 217         .dmdata_set_attributes = hubp2_dmdata_set_attributes,
 218         .dmdata_load = hubp2_dmdata_load,
 219         .dmdata_status_done = hubp2_dmdata_status_done,
 220         .hubp_read_state = hubp1_read_state,
 221         .hubp_clear_underflow = hubp1_clear_underflow,
 222         .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
 223         .hubp_init = hubp21_init,
 224 };
 225 
 226 bool hubp21_construct(
 227         struct dcn21_hubp *hubp21,
 228         struct dc_context *ctx,
 229         uint32_t inst,
 230         const struct dcn_hubp2_registers *hubp_regs,
 231         const struct dcn_hubp2_shift *hubp_shift,
 232         const struct dcn_hubp2_mask *hubp_mask)
 233 {
 234         hubp21->base.funcs = &dcn21_hubp_funcs;
 235         hubp21->base.ctx = ctx;
 236         hubp21->hubp_regs = hubp_regs;
 237         hubp21->hubp_shift = hubp_shift;
 238         hubp21->hubp_mask = hubp_mask;
 239         hubp21->base.inst = inst;
 240         hubp21->base.opp_id = OPP_ID_INVALID;
 241         hubp21->base.mpcc_id = 0xf;
 242 
 243         return true;
 244 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c

DEFINITIONS
