root/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

INCLUDED FROM

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DC_LINK_DP_H__
  27 #define __DC_LINK_DP_H__
  28 
  29 #define LINK_TRAINING_ATTEMPTS 4
  30 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
  31 
  32 struct dc_link;
  33 struct dc_stream_state;
  34 struct dc_link_settings;
  35 
  36 bool dp_verify_link_cap(
  37         struct dc_link *link,
  38         struct dc_link_settings *known_limit_link_setting,
  39         int *fail_count);
  40 
  41 bool dp_verify_link_cap_with_retries(
  42         struct dc_link *link,
  43         struct dc_link_settings *known_limit_link_setting,
  44         int attempts);
  45 
  46 bool dp_validate_mode_timing(
  47         struct dc_link *link,
  48         const struct dc_crtc_timing *timing);
  49 
  50 void decide_link_settings(
  51         struct dc_stream_state *stream,
  52         struct dc_link_settings *link_setting);
  53 
  54 bool perform_link_training_with_retries(
  55         struct dc_link *link,
  56         const struct dc_link_settings *link_setting,
  57         bool skip_video_pattern,
  58         int attempts);
  59 
  60 bool is_mst_supported(struct dc_link *link);
  61 
  62 bool detect_dp_sink_caps(struct dc_link *link);
  63 
  64 void detect_edp_sink_caps(struct dc_link *link);
  65 
  66 bool is_dp_active_dongle(const struct dc_link *link);
  67 
  68 void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
  69 
  70 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
  71 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
  72 
  73 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  74 void dp_set_fec_ready(struct dc_link *link, bool ready);
  75 void dp_set_fec_enable(struct dc_link *link, bool enable);
  76 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
  77 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
  78 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
  79 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
  80 #endif
  81 
  82 #endif /* __DC_LINK_DP_H__ */