1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef __DC_CLOCK_SOURCE_H__
27 #define __DC_CLOCK_SOURCE_H__
28
29 #include "dc_types.h"
30 #include "include/grph_object_id.h"
31 #include "include/bios_parser_types.h"
32
33 struct clock_source;
34
35 struct spread_spectrum_data {
36 uint32_t percentage; /*> In unit of 0.01% or 0.001%*/
37 uint32_t percentage_divider; /*> 100 or 1000 */
38 uint32_t freq_range_khz;
39 uint32_t modulation_freq_hz;
40
41 struct spread_spectrum_flags flags;
42 };
43
44 struct delta_sigma_data {
45 uint32_t feedback_amount;
46 uint32_t nfrac_amount;
47 uint32_t ds_frac_size;
48 uint32_t ds_frac_amount;
49 };
50
51 /**
52 * Pixel Clock Parameters structure
53 * These parameters are required as input
54 * when calculating Pixel Clock Dividers for requested Pixel Clock
55 */
56 struct pixel_clk_flags {
57 uint32_t ENABLE_SS:1;
58 uint32_t DISPLAY_BLANKED:1;
59 uint32_t PROGRAM_PIXEL_CLOCK:1;
60 uint32_t PROGRAM_ID_CLOCK:1;
61 uint32_t SUPPORT_YCBCR420:1;
62 };
63
64 /**
65 * Display Port HW De spread of Reference Clock related Parameters structure
66 * Store it once at boot for later usage
67 */
68 struct csdp_ref_clk_ds_params {
69 bool hw_dso_n_dp_ref_clk;
70 /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
71 uint32_t avg_dp_ref_clk_khz;
72 /* Average DP Reference clock (in KHz)*/
73 uint32_t ss_percentage_on_dp_ref_clk;
74 /* DP Reference clock SS percentage
75 * (not to be mixed with DP IDCLK SS from PLL Settings)*/
76 uint32_t ss_percentage_divider;
77 /* DP Reference clock SS percentage divider */
78 };
79
80 struct pixel_clk_params {
81 uint32_t requested_pix_clk_100hz;
82 /*> Requested Pixel Clock
83 * (based on Video Timing standard used for requested mode)*/
84 uint32_t requested_sym_clk; /* in KHz */
85 /*> Requested Sym Clock (relevant only for display port)*/
86 uint32_t dp_ref_clk; /* in KHz */
87 /*> DP reference clock - calculated only for DP signal for specific cases*/
88 struct graphics_object_id encoder_object_id;
89 /*> Encoder object Id - needed by VBIOS Exec table*/
90 enum signal_type signal_type;
91 /*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
92 enum controller_id controller_id;
93 /*> ControllerId - which controller using this PLL*/
94 enum dc_color_depth color_depth;
95 struct csdp_ref_clk_ds_params de_spread_params;
96 /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
97 enum dc_pixel_encoding pixel_encoding;
98 struct pixel_clk_flags flags;
99 };
100
101 /**
102 * Pixel Clock Dividers structure with desired Pixel Clock
103 * (adjusted after VBIOS exec table),
104 * with actually calculated Clock and reference Crystal frequency
105 */
106 struct pll_settings {
107 uint32_t actual_pix_clk_100hz;
108 uint32_t adjusted_pix_clk_100hz;
109 uint32_t calculated_pix_clk_100hz;
110 uint32_t vco_freq;
111 uint32_t reference_freq;
112 uint32_t reference_divider;
113 uint32_t feedback_divider;
114 uint32_t fract_feedback_divider;
115 uint32_t pix_clk_post_divider;
116 uint32_t ss_percentage;
117 bool use_external_clk;
118 };
119
120 struct calc_pll_clock_source_init_data {
121 struct dc_bios *bp;
122 uint32_t min_pix_clk_pll_post_divider;
123 uint32_t max_pix_clk_pll_post_divider;
124 uint32_t min_pll_ref_divider;
125 uint32_t max_pll_ref_divider;
126 uint32_t min_override_input_pxl_clk_pll_freq_khz;
127 /* if not 0, override the firmware info */
128
129 uint32_t max_override_input_pxl_clk_pll_freq_khz;
130 /* if not 0, override the firmware info */
131
132 uint32_t num_fract_fb_divider_decimal_point;
133 /* number of decimal point for fractional feedback divider value */
134
135 uint32_t num_fract_fb_divider_decimal_point_precision;
136 /* number of decimal point to round off for fractional feedback divider value*/
137 struct dc_context *ctx;
138
139 };
140
141 struct calc_pll_clock_source {
142 uint32_t ref_freq_khz;
143 uint32_t min_pix_clock_pll_post_divider;
144 uint32_t max_pix_clock_pll_post_divider;
145 uint32_t min_pll_ref_divider;
146 uint32_t max_pll_ref_divider;
147
148 uint32_t max_vco_khz;
149 uint32_t min_vco_khz;
150 uint32_t min_pll_input_freq_khz;
151 uint32_t max_pll_input_freq_khz;
152
153 uint32_t fract_fb_divider_decimal_points_num;
154 uint32_t fract_fb_divider_factor;
155 uint32_t fract_fb_divider_precision;
156 uint32_t fract_fb_divider_precision_factor;
157 struct dc_context *ctx;
158 };
159
160 struct clock_source_funcs {
161 bool (*cs_power_down)(
162 struct clock_source *);
163 bool (*program_pix_clk)(struct clock_source *,
164 struct pixel_clk_params *, struct pll_settings *);
165 uint32_t (*get_pix_clk_dividers)(
166 struct clock_source *,
167 struct pixel_clk_params *,
168 struct pll_settings *);
169 bool (*get_pixel_clk_frequency_100hz)(
170 const struct clock_source *clock_source,
171 unsigned int inst,
172 unsigned int *pixel_clk_khz);
173 };
174
175 struct clock_source {
176 const struct clock_source_funcs *funcs;
177 struct dc_context *ctx;
178 enum clock_source_id id;
179 bool dp_clk_src;
180 };
181
182 #endif