root/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

/* [<][>][^][v][top][bottom][index][help] */

INCLUDED FROM


   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 
  27 #ifndef __DAL_DPP_H__
  28 #define __DAL_DPP_H__
  29 
  30 #include "transform.h"
  31 
  32 struct dpp {
  33         const struct dpp_funcs *funcs;
  34         struct dc_context *ctx;
  35         int inst;
  36         struct dpp_caps *caps;
  37         struct pwl_params regamma_params;
  38         struct pwl_params degamma_params;
  39 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  40         struct dpp_cursor_attributes cur_attr;
  41 #endif
  42 
  43 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  44         struct pwl_params shaper_params;
  45         bool cm_bypass_mode;
  46 #endif
  47 };
  48 
  49 struct dpp_input_csc_matrix {
  50         enum dc_color_space color_space;
  51         uint16_t regval[12];
  52 };
  53 
  54 struct dpp_grph_csc_adjustment {
  55         struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
  56         enum graphics_gamut_adjust_type gamut_adjust_type;
  57 };
  58 
  59 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
  60 struct cnv_color_keyer_params {
  61         int color_keyer_en;
  62         int color_keyer_mode;
  63         int color_keyer_alpha_low;
  64         int color_keyer_alpha_high;
  65         int color_keyer_red_low;
  66         int color_keyer_red_high;
  67         int color_keyer_green_low;
  68         int color_keyer_green_high;
  69         int color_keyer_blue_low;
  70         int color_keyer_blue_high;
  71 };
  72 
  73 /* new for dcn2: set the 8bit alpha values based on the 2 bit alpha
  74  *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0   default: 0b00000000
  75  *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1   default: 0b01010101
  76  *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2   default: 0b10101010
  77  *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3   default: 0b11111111
  78  */
  79 struct cnv_alpha_2bit_lut {
  80         int lut0;
  81         int lut1;
  82         int lut2;
  83         int lut3;
  84 };
  85 #endif
  86 
  87 struct dcn_dpp_state {
  88         uint32_t is_enabled;
  89         uint32_t igam_lut_mode;
  90         uint32_t igam_input_format;
  91         uint32_t dgam_lut_mode;
  92         uint32_t rgam_lut_mode;
  93         uint32_t gamut_remap_mode;
  94         uint32_t gamut_remap_c11_c12;
  95         uint32_t gamut_remap_c13_c14;
  96         uint32_t gamut_remap_c21_c22;
  97         uint32_t gamut_remap_c23_c24;
  98         uint32_t gamut_remap_c31_c32;
  99         uint32_t gamut_remap_c33_c34;
 100 };
 101 
 102 struct CM_bias_params {
 103         uint32_t cm_bias_cr_r;
 104         uint32_t cm_bias_y_g;
 105         uint32_t cm_bias_cb_b;
 106         uint32_t cm_bias_format;
 107 };
 108 
 109 struct dpp_funcs {
 110 
 111         void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
 112                 uint32_t enable, uint32_t additive_blending);
 113 
 114         void (*dpp_program_cm_bias)(
 115                 struct dpp *dpp_base,
 116                 struct CM_bias_params *bias_params);
 117 
 118         void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
 119 
 120         void (*dpp_reset)(struct dpp *dpp);
 121 
 122         void (*dpp_set_scaler)(struct dpp *dpp,
 123                         const struct scaler_data *scl_data);
 124 
 125         void (*dpp_set_pixel_storage_depth)(
 126                         struct dpp *dpp,
 127                         enum lb_pixel_depth depth,
 128                         const struct bit_depth_reduction_params *bit_depth_params);
 129 
 130         bool (*dpp_get_optimal_number_of_taps)(
 131                         struct dpp *dpp,
 132                         struct scaler_data *scl_data,
 133                         const struct scaling_taps *in_taps);
 134 
 135         void (*dpp_set_gamut_remap)(
 136                         struct dpp *dpp,
 137                         const struct dpp_grph_csc_adjustment *adjust);
 138 
 139         void (*dpp_set_csc_default)(
 140                 struct dpp *dpp,
 141                 enum dc_color_space colorspace);
 142 
 143         void (*dpp_set_csc_adjustment)(
 144                 struct dpp *dpp,
 145                 const uint16_t *regval);
 146 
 147         void (*dpp_power_on_regamma_lut)(
 148                 struct dpp *dpp,
 149                 bool power_on);
 150 
 151         void (*dpp_program_regamma_lut)(
 152                         struct dpp *dpp,
 153                         const struct pwl_result_data *rgb,
 154                         uint32_t num);
 155 
 156         void (*dpp_configure_regamma_lut)(
 157                         struct dpp *dpp,
 158                         bool is_ram_a);
 159 
 160         void (*dpp_program_regamma_lutb_settings)(
 161                         struct dpp *dpp,
 162                         const struct pwl_params *params);
 163 
 164         void (*dpp_program_regamma_luta_settings)(
 165                         struct dpp *dpp,
 166                         const struct pwl_params *params);
 167 
 168         void (*dpp_program_regamma_pwl)(
 169                 struct dpp *dpp,
 170                 const struct pwl_params *params,
 171                 enum opp_regamma mode);
 172 
 173         void (*dpp_program_bias_and_scale)(
 174                         struct dpp *dpp,
 175                         struct dc_bias_and_scale *params);
 176 
 177         void (*dpp_set_degamma)(
 178                         struct dpp *dpp_base,
 179                         enum ipp_degamma_mode mode);
 180 
 181         void (*dpp_program_input_lut)(
 182                         struct dpp *dpp_base,
 183                         const struct dc_gamma *gamma);
 184 
 185         void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
 186                                                                          const struct pwl_params *params);
 187 
 188         void (*dpp_setup)(
 189                         struct dpp *dpp_base,
 190                         enum surface_pixel_format format,
 191                         enum expansion_mode mode,
 192                         struct dc_csc_transform input_csc_color_matrix,
 193 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 194                         enum dc_color_space input_color_space,
 195                         struct cnv_alpha_2bit_lut *alpha_2bit_lut);
 196 #else
 197                         enum dc_color_space input_color_space);
 198 #endif
 199 
 200         void (*dpp_full_bypass)(struct dpp *dpp_base);
 201 
 202         void (*set_cursor_attributes)(
 203                         struct dpp *dpp_base,
 204                         struct dc_cursor_attributes *cursor_attributes);
 205 
 206         void (*set_cursor_position)(
 207                         struct dpp *dpp_base,
 208                         const struct dc_cursor_position *pos,
 209                         const struct dc_cursor_mi_param *param,
 210                         uint32_t width,
 211                         uint32_t height
 212                         );
 213 
 214         void (*dpp_set_hdr_multiplier)(
 215                         struct dpp *dpp_base,
 216                         uint32_t multiplier);
 217 
 218         void (*set_optional_cursor_attributes)(
 219                         struct dpp *dpp_base,
 220                         struct dpp_cursor_attributes *attr);
 221 
 222         void (*dpp_dppclk_control)(
 223                         struct dpp *dpp_base,
 224                         bool dppclk_div,
 225                         bool enable);
 226 
 227 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 228         bool (*dpp_program_blnd_lut)(
 229                         struct dpp *dpp,
 230                         const struct pwl_params *params);
 231         bool (*dpp_program_shaper_lut)(
 232                         struct dpp *dpp,
 233                         const struct pwl_params *params);
 234         bool (*dpp_program_3dlut)(
 235                         struct dpp *dpp,
 236                         struct tetrahedral_params *params);
 237         void (*dpp_cnv_set_alpha_keyer)(
 238                         struct dpp *dpp_base,
 239                         struct cnv_color_keyer_params *color_keyer);
 240 #endif
 241 };
 242 
 243 
 244 
 245 #endif

/* [<][>][^][v][top][bottom][index][help] */