root/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h

INCLUDED FROM

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DAL_HW_SHARED_H__
  27 #define __DAL_HW_SHARED_H__
  28 
  29 #include "os_types.h"
  30 #include "fixed31_32.h"
  31 #include "dc_hw_types.h"
  32 
  33 /******************************************************************************
  34  * Data types shared between different Virtual HW blocks
  35  ******************************************************************************/
  36 
  37 #define MAX_AUDIOS 7
  38 #define MAX_PIPES 6
  39 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  40 #define MAX_DWB_PIPES   1
  41 #endif
  42 
  43 struct gamma_curve {
  44         uint32_t offset;
  45         uint32_t segments_num;
  46 };
  47 
  48 struct curve_points {
  49         struct fixed31_32 x;
  50         struct fixed31_32 y;
  51         struct fixed31_32 offset;
  52         struct fixed31_32 slope;
  53 
  54         uint32_t custom_float_x;
  55         uint32_t custom_float_y;
  56         uint32_t custom_float_offset;
  57         uint32_t custom_float_slope;
  58 };
  59 
  60 struct curve_points3 {
  61         struct curve_points red;
  62         struct curve_points green;
  63         struct curve_points blue;
  64 };
  65 
  66 struct pwl_result_data {
  67         struct fixed31_32 red;
  68         struct fixed31_32 green;
  69         struct fixed31_32 blue;
  70 
  71         struct fixed31_32 delta_red;
  72         struct fixed31_32 delta_green;
  73         struct fixed31_32 delta_blue;
  74 
  75         uint32_t red_reg;
  76         uint32_t green_reg;
  77         uint32_t blue_reg;
  78 
  79         uint32_t delta_red_reg;
  80         uint32_t delta_green_reg;
  81         uint32_t delta_blue_reg;
  82 };
  83 
  84 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  85 struct dc_rgb {
  86         uint32_t red;
  87         uint32_t green;
  88         uint32_t blue;
  89 };
  90 
  91 struct tetrahedral_17x17x17 {
  92         struct dc_rgb lut0[1229];
  93         struct dc_rgb lut1[1228];
  94         struct dc_rgb lut2[1228];
  95         struct dc_rgb lut3[1228];
  96 };
  97 struct tetrahedral_9x9x9 {
  98         struct dc_rgb lut0[183];
  99         struct dc_rgb lut1[182];
 100         struct dc_rgb lut2[182];
 101         struct dc_rgb lut3[182];
 102 };
 103 
 104 struct tetrahedral_params {
 105         union {
 106                 struct tetrahedral_17x17x17 tetrahedral_17;
 107                 struct tetrahedral_9x9x9 tetrahedral_9;
 108         };
 109         bool use_tetrahedral_9;
 110         bool use_12bits;
 111 
 112 };
 113 #endif
 114 
 115 /* arr_curve_points - regamma regions/segments specification
 116  * arr_points - beginning and end point specified separately (only one on DCE)
 117  * corner_points - beginning and end point for all 3 colors (DCN)
 118  * rgb_resulted - final curve
 119  */
 120 struct pwl_params {
 121         struct gamma_curve arr_curve_points[34];
 122         union {
 123                 struct curve_points arr_points[2];
 124                 struct curve_points3 corner_points[2];
 125         };
 126         struct pwl_result_data rgb_resulted[256 + 3];
 127         uint32_t hw_points_num;
 128 };
 129 
 130 /* move to dpp
 131  * while we are moving functionality out of opp to dpp to align
 132  * HW programming to HW IP, we define these struct in hw_shared
 133  * so we can still compile while refactoring
 134  */
 135 
 136 enum lb_pixel_depth {
 137         /* do not change the values because it is used as bit vector */
 138         LB_PIXEL_DEPTH_18BPP = 1,
 139         LB_PIXEL_DEPTH_24BPP = 2,
 140         LB_PIXEL_DEPTH_30BPP = 4,
 141         LB_PIXEL_DEPTH_36BPP = 8
 142 };
 143 
 144 enum graphics_csc_adjust_type {
 145         GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
 146         GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
 147         GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
 148 };
 149 
 150 enum ipp_degamma_mode {
 151         IPP_DEGAMMA_MODE_BYPASS,
 152         IPP_DEGAMMA_MODE_HW_sRGB,
 153         IPP_DEGAMMA_MODE_HW_xvYCC,
 154         IPP_DEGAMMA_MODE_USER_PWL
 155 };
 156 
 157 enum ipp_output_format {
 158         IPP_OUTPUT_FORMAT_12_BIT_FIX,
 159         IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
 160         IPP_OUTPUT_FORMAT_FLOAT
 161 };
 162 
 163 enum expansion_mode {
 164         EXPANSION_MODE_DYNAMIC,
 165         EXPANSION_MODE_ZERO
 166 };
 167 
 168 struct default_adjustment {
 169         enum lb_pixel_depth lb_color_depth;
 170         enum dc_color_space out_color_space;
 171         enum dc_color_space in_color_space;
 172         enum dc_color_depth color_depth;
 173         enum pixel_format surface_pixel_format;
 174         enum graphics_csc_adjust_type csc_adjust_type;
 175         bool force_hw_default;
 176 };
 177 
 178 
 179 struct out_csc_color_matrix {
 180         enum dc_color_space color_space;
 181         uint16_t regval[12];
 182 };
 183 
 184 enum gamut_remap_select {
 185         GAMUT_REMAP_BYPASS = 0,
 186         GAMUT_REMAP_COEFF,
 187         GAMUT_REMAP_COMA_COEFF,
 188         GAMUT_REMAP_COMB_COEFF
 189 };
 190 
 191 enum opp_regamma {
 192         OPP_REGAMMA_BYPASS = 0,
 193         OPP_REGAMMA_SRGB,
 194         OPP_REGAMMA_XVYCC,
 195         OPP_REGAMMA_USER
 196 };
 197 
 198 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 199 enum optc_dsc_mode {
 200         OPTC_DSC_DISABLED = 0,
 201         OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
 202         OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
 203 };
 204 #endif
 205 
 206 struct dc_bias_and_scale {
 207         uint16_t scale_red;
 208         uint16_t bias_red;
 209         uint16_t scale_green;
 210         uint16_t bias_green;
 211         uint16_t scale_blue;
 212         uint16_t bias_blue;
 213 };
 214 
 215 enum test_pattern_dyn_range {
 216         TEST_PATTERN_DYN_RANGE_VESA = 0,
 217         TEST_PATTERN_DYN_RANGE_CEA
 218 };
 219 
 220 enum test_pattern_mode {
 221         TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
 222         TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
 223         TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
 224         TEST_PATTERN_MODE_VERTICALBARS,
 225         TEST_PATTERN_MODE_HORIZONTALBARS,
 226         TEST_PATTERN_MODE_SINGLERAMP_RGB,
 227 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 228         TEST_PATTERN_MODE_DUALRAMP_RGB,
 229         TEST_PATTERN_MODE_XR_BIAS_RGB
 230 #else
 231         TEST_PATTERN_MODE_DUALRAMP_RGB
 232 #endif
 233 };
 234 
 235 enum test_pattern_color_format {
 236         TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
 237         TEST_PATTERN_COLOR_FORMAT_BPC_8,
 238         TEST_PATTERN_COLOR_FORMAT_BPC_10,
 239         TEST_PATTERN_COLOR_FORMAT_BPC_12
 240 };
 241 
 242 enum controller_dp_test_pattern {
 243         CONTROLLER_DP_TEST_PATTERN_D102 = 0,
 244         CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
 245         CONTROLLER_DP_TEST_PATTERN_PRBS7,
 246         CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
 247         CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
 248         CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
 249         CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
 250         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
 251         CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
 252         CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
 253         CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
 254         CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
 255         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
 256 };
 257 
 258 enum dc_lut_mode {
 259         LUT_BYPASS,
 260         LUT_RAM_A,
 261         LUT_RAM_B
 262 };
 263 #endif /* __DAL_HW_SHARED_H__ */