1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
26 #ifndef __DAL_DSC_H__
27 #define __DAL_DSC_H__
28
29 #include "dc_dsc.h"
30 #include "dc_hw_types.h"
31 #include "dc_dp_types.h"
32
33 /* Input parameters for configuring DSC from the outside of DSC */
34 struct dsc_config {
35 uint32_t pic_width;
36 uint32_t pic_height;
37 enum dc_pixel_encoding pixel_encoding;
38 enum dc_color_depth color_depth; /* Bits per component */
39 struct dc_dsc_config dc_dsc_cfg;
40 };
41
42
43 /* Output parameters for configuring DSC-related part of OPTC */
44 struct dsc_optc_config {
45 uint32_t slice_width; /* Slice width in pixels */
46 uint32_t bytes_per_pixel; /* Bytes per pixel in u3.28 format */
47 bool is_pixel_format_444; /* 'true' if pixel format is 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4)' */
48 };
49
50
51 struct dcn_dsc_state {
52 uint32_t dsc_clock_en;
53 uint32_t dsc_slice_width;
54 uint32_t dsc_bytes_per_pixel;
55 };
56
57
58 /* DSC encoder capabilities
59 * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.
60 */
61 union dsc_enc_slice_caps {
62 struct {
63 uint8_t NUM_SLICES_1 : 1;
64 uint8_t NUM_SLICES_2 : 1;
65 uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
66 uint8_t NUM_SLICES_4 : 1;
67 uint8_t NUM_SLICES_8 : 1;
68 } bits;
69 uint8_t raw;
70 };
71
72 struct dsc_enc_caps {
73 uint8_t dsc_version;
74 union dsc_enc_slice_caps slice_caps;
75 int32_t lb_bit_depth;
76 bool is_block_pred_supported;
77 union dsc_color_formats color_formats;
78 union dsc_color_depth color_depth;
79 int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */
80 int32_t max_slice_width;
81 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
82 };
83
84 struct display_stream_compressor {
85 const struct dsc_funcs *funcs;
86 struct dc_context *ctx;
87 int inst;
88 };
89
90 struct dsc_funcs {
91 void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
92 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
93 bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
94 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
95 struct dsc_optc_config *dsc_optc_cfg);
96 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
97 uint8_t *dsc_packed_pps);
98 void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
99 void (*dsc_disable)(struct display_stream_compressor *dsc);
100 };
101
102 #endif
103 #endif