drivers/gpu/drm/amd/display/dc/inc/hw/timing

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   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__
  27 #define __DAL_TIMING_GENERATOR_TYPES_H__
  28 
  29 #include "hw_shared.h"
  30 
  31 struct dc_bios;
  32 
  33 /* Contains CRTC vertical/horizontal pixel counters */
  34 struct crtc_position {
  35         int32_t vertical_count;
  36         int32_t horizontal_count;
  37         int32_t nominal_vcount;
  38 };
  39 
  40 struct dcp_gsl_params {
  41         int gsl_group;
  42         int gsl_master;
  43 };
  44 
  45 struct gsl_params {
  46         int gsl0_en;
  47         int gsl1_en;
  48         int gsl2_en;
  49         int gsl_master_en;
  50         int gsl_master_mode;
  51         int master_update_lock_gsl_en;
  52         int gsl_window_start_x;
  53         int gsl_window_end_x;
  54         int gsl_window_start_y;
  55         int gsl_window_end_y;
  56 };
  57 
  58 /* define the structure of Dynamic Refresh Mode */
  59 struct drr_params {
  60         uint32_t vertical_total_min;
  61         uint32_t vertical_total_max;
  62         uint32_t vertical_total_mid;
  63         uint32_t vertical_total_mid_frame_num;
  64         bool immediate_flip;
  65 };
  66 
  67 #define LEFT_EYE_3D_PRIMARY_SURFACE 1
  68 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0
  69 
  70 enum crtc_state {
  71         CRTC_STATE_VBLANK = 0,
  72         CRTC_STATE_VACTIVE
  73 };
  74 
  75 struct vupdate_keepout_params {
  76         int start_offset;
  77         int end_offset;
  78         int enable;
  79 };
  80 
  81 struct crtc_stereo_flags {
  82         uint8_t PROGRAM_STEREO         : 1;
  83         uint8_t PROGRAM_POLARITY       : 1;
  84         uint8_t RIGHT_EYE_POLARITY     : 1;
  85         uint8_t FRAME_PACKED           : 1;
  86         uint8_t DISABLE_STEREO_DP_SYNC : 1;
  87 };
  88 
  89 enum crc_selection {
  90         /* Order must match values expected by hardware */
  91         UNION_WINDOW_A_B = 0,
  92         UNION_WINDOW_A_NOT_B,
  93         UNION_WINDOW_NOT_A_B,
  94         UNION_WINDOW_NOT_A_NOT_B,
  95         INTERSECT_WINDOW_A_B,
  96         INTERSECT_WINDOW_A_NOT_B,
  97         INTERSECT_WINDOW_NOT_A_B,
  98         INTERSECT_WINDOW_NOT_A_NOT_B,
  99 };
 100 
 101 enum h_timing_div_mode {
 102         H_TIMING_NO_DIV,
 103         H_TIMING_DIV_BY2,
 104 };
 105 
 106 struct crc_params {
 107         /* Regions used to calculate CRC*/
 108         uint16_t windowa_x_start;
 109         uint16_t windowa_x_end;
 110         uint16_t windowa_y_start;
 111         uint16_t windowa_y_end;
 112 
 113         uint16_t windowb_x_start;
 114         uint16_t windowb_x_end;
 115         uint16_t windowb_y_start;
 116         uint16_t windowb_y_end;
 117 
 118         enum crc_selection selection;
 119 
 120         bool continuous_mode;
 121         bool enable;
 122 };
 123 
 124 struct timing_generator {
 125         const struct timing_generator_funcs *funcs;
 126         struct dc_bios *bp;
 127         struct dc_context *ctx;
 128         int inst;
 129 };
 130 
 131 struct dc_crtc_timing;
 132 
 133 struct drr_params;
 134 
 135 
 136 struct timing_generator_funcs {
 137         bool (*validate_timing)(struct timing_generator *tg,
 138                                                         const struct dc_crtc_timing *timing);
 139         void (*program_timing)(struct timing_generator *tg,
 140                                                         const struct dc_crtc_timing *timing,
 141                                                         int vready_offset,
 142                                                         int vstartup_start,
 143                                                         int vupdate_offset,
 144                                                         int vupdate_width,
 145                                                         const enum signal_type signal,
 146                                                         bool use_vbios
 147         );
 148         void (*setup_vertical_interrupt0)(
 149                         struct timing_generator *optc,
 150                         uint32_t start_line,
 151                         uint32_t end_line);
 152         void (*setup_vertical_interrupt1)(
 153                         struct timing_generator *optc,
 154                         uint32_t start_line);
 155         void (*setup_vertical_interrupt2)(
 156                         struct timing_generator *optc,
 157                         uint32_t start_line);
 158 
 159         bool (*enable_crtc)(struct timing_generator *tg);
 160         bool (*disable_crtc)(struct timing_generator *tg);
 161         bool (*is_counter_moving)(struct timing_generator *tg);
 162         void (*get_position)(struct timing_generator *tg,
 163                                 struct crtc_position *position);
 164 
 165         uint32_t (*get_frame_count)(struct timing_generator *tg);
 166         void (*get_scanoutpos)(
 167                 struct timing_generator *tg,
 168                 uint32_t *v_blank_start,
 169                 uint32_t *v_blank_end,
 170                 uint32_t *h_position,
 171                 uint32_t *v_position);
 172         bool (*get_otg_active_size)(struct timing_generator *optc,
 173                         uint32_t *otg_active_width,
 174                         uint32_t *otg_active_height);
 175         bool (*is_matching_timing)(struct timing_generator *tg,
 176                         const struct dc_crtc_timing *otg_timing);
 177         void (*set_early_control)(struct timing_generator *tg,
 178                                                            uint32_t early_cntl);
 179         void (*wait_for_state)(struct timing_generator *tg,
 180                                                         enum crtc_state state);
 181         void (*set_blank)(struct timing_generator *tg,
 182                                         bool enable_blanking);
 183         bool (*is_blanked)(struct timing_generator *tg);
 184         void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
 185         void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
 186         void (*set_colors)(struct timing_generator *tg,
 187                                                 const struct tg_color *blank_color,
 188                                                 const struct tg_color *overscan_color);
 189 
 190         void (*disable_vga)(struct timing_generator *tg);
 191         bool (*did_triggered_reset_occur)(struct timing_generator *tg);
 192         void (*setup_global_swap_lock)(struct timing_generator *tg,
 193                                                         const struct dcp_gsl_params *gsl_params);
 194         void (*unlock)(struct timing_generator *tg);
 195         void (*lock)(struct timing_generator *tg);
 196         void (*lock_doublebuffer_disable)(struct timing_generator *tg);
 197         void (*lock_doublebuffer_enable)(struct timing_generator *tg);
 198 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 199         void(*triplebuffer_unlock)(struct timing_generator *tg);
 200         void(*triplebuffer_lock)(struct timing_generator *tg);
 201 #endif
 202         void (*enable_reset_trigger)(struct timing_generator *tg,
 203                                      int source_tg_inst);
 204         void (*enable_crtc_reset)(struct timing_generator *tg,
 205                                   int source_tg_inst,
 206                                   struct crtc_trigger_info *crtc_tp);
 207         void (*disable_reset_trigger)(struct timing_generator *tg);
 208         void (*tear_down_global_swap_lock)(struct timing_generator *tg);
 209         void (*enable_advanced_request)(struct timing_generator *tg,
 210                                         bool enable, const struct dc_crtc_timing *timing);
 211         void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
 212         void (*set_static_screen_control)(struct timing_generator *tg,
 213                                                         uint32_t value);
 214         void (*set_test_pattern)(
 215                 struct timing_generator *tg,
 216                 enum controller_dp_test_pattern test_pattern,
 217                 enum dc_color_depth color_depth);
 218 
 219         bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
 220 
 221         void (*program_global_sync)(struct timing_generator *tg,
 222                         int vready_offset,
 223                         int vstartup_start,
 224                         int vupdate_offset,
 225                         int vupdate_width);
 226         void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
 227         void (*program_stereo)(struct timing_generator *tg,
 228                 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
 229         bool (*is_stereo_left_eye)(struct timing_generator *tg);
 230 
 231         void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
 232 
 233         void (*tg_init)(struct timing_generator *tg);
 234         bool (*is_tg_enabled)(struct timing_generator *tg);
 235         bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
 236         void (*clear_optc_underflow)(struct timing_generator *tg);
 237 
 238 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 239         void (*set_dwb_source)(struct timing_generator *optc,
 240                 uint32_t dwb_pipe_inst);
 241 
 242         void (*get_optc_source)(struct timing_generator *optc,
 243                         uint32_t *num_of_input_segments,
 244                         uint32_t *seg0_src_sel,
 245                         uint32_t *seg1_src_sel);
 246 #endif
 247 
 248         /**
 249          * Configure CRCs for the given timing generator. Return false if TG is
 250          * not on.
 251          */
 252         bool (*configure_crc)(struct timing_generator *tg,
 253                                const struct crc_params *params);
 254 
 255         /**
 256          * Get CRCs for the given timing generator. Return false if CRCs are
 257          * not enabled (via configure_crc).
 258          */
 259         bool (*get_crc)(struct timing_generator *tg,
 260                         uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
 261 
 262         void (*program_manual_trigger)(struct timing_generator *optc);
 263         void (*setup_manual_trigger)(struct timing_generator *optc);
 264 
 265         void (*set_vtg_params)(struct timing_generator *optc,
 266                         const struct dc_crtc_timing *dc_crtc_timing);
 267 
 268 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 269 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 270         void (*set_dsc_config)(struct timing_generator *optc,
 271                                enum optc_dsc_mode dsc_mode,
 272                                uint32_t dsc_bytes_per_pixel,
 273                                uint32_t dsc_slice_width);
 274 #endif
 275         void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
 276         void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
 277                         struct dc_crtc_timing *timing);
 278         void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
 279         void (*set_gsl_source_select)(struct timing_generator *optc,
 280                         int group_idx,
 281                         uint32_t gsl_ready_signal);
 282 #endif
 283 };
 284 
 285 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

INCLUDED FROM
