1 /* Copyright 2012-17 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25 #ifndef __DC_DWBC_H__
26 #define __DC_DWBC_H__
27
28 #include "dc_hw_types.h"
29
30
31 #define DWB_SW_V2 1
32 #define DWB_MCIF_BUF_COUNT 4
33
34 /* forward declaration of mcif_wb struct */
35 struct mcif_wb;
36
37 enum dce_version;
38
39 enum dwb_sw_version {
40 dwb_ver_1_0 = 1,
41 dwb_ver_2_0 = 2,
42 };
43
44 enum dwb_source {
45 dwb_src_scl = 0, /* for DCE7x/9x, DCN won't support. */
46 dwb_src_blnd, /* for DCE7x/9x */
47 dwb_src_fmt, /* for DCE7x/9x */
48 dwb_src_otg0 = 0x100, /* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */
49 dwb_src_otg1, /* for DCN1.x/DCN2.x */
50 dwb_src_otg2, /* for DCN1.x/DCN2.x */
51 dwb_src_otg3, /* for DCN1.x/DCN2.x */
52 };
53
54 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
55 /* DCN1.x, DCN2.x support 2 pipes */
56 #else
57 /* DCN1.x supports 2 pipes */
58 #endif
59 enum dwb_pipe {
60 dwb_pipe0 = 0,
61 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
62 dwb_pipe1,
63 #endif
64 dwb_pipe_max_num,
65 };
66
67 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
68 enum dwb_frame_capture_enable {
69 DWB_FRAME_CAPTURE_DISABLE = 0,
70 DWB_FRAME_CAPTURE_ENABLE = 1,
71 };
72
73 enum wbscl_coef_filter_type_sel {
74 WBSCL_COEF_LUMA_VERT_FILTER = 0,
75 WBSCL_COEF_CHROMA_VERT_FILTER = 1,
76 WBSCL_COEF_LUMA_HORZ_FILTER = 2,
77 WBSCL_COEF_CHROMA_HORZ_FILTER = 3
78 };
79
80 #endif
81
82 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
83 struct dwb_warmup_params {
84 bool warmup_en; /* false: normal mode, true: enable pattern generator */
85 bool warmup_mode; /* false: 420, true: 444 */
86 bool warmup_depth; /* false: 8bit, true: 10bit */
87 int warmup_data; /* Data to be sent by pattern generator (same for each pixel component) */
88 int warmup_width; /* Pattern width (pixels) */
89 int warmup_height; /* Pattern height (lines) */
90 };
91 #endif
92
93 struct dwb_caps {
94 enum dce_version hw_version; /* DCN engine version. */
95 enum dwb_sw_version sw_version; /* DWB sw implementation version. */
96 unsigned int reserved[6]; /* Reserved for future use, MUST BE 0. */
97 unsigned int adapter_id;
98 unsigned int num_pipes; /* number of DWB pipes */
99 struct {
100 unsigned int support_dwb :1;
101 unsigned int support_ogam :1;
102 unsigned int support_wbscl :1;
103 unsigned int support_ocsc :1;
104 unsigned int support_stereo :1;
105 } caps;
106 unsigned int reserved2[9]; /* Reserved for future use, MUST BE 0. */
107 };
108
109 struct dwbc {
110 const struct dwbc_funcs *funcs;
111 struct dc_context *ctx;
112 int inst;
113 struct mcif_wb *mcif;
114 bool status;
115 int inputSrcSelect;
116 bool dwb_output_black;
117 enum dc_transfer_func_predefined tf;
118 enum dc_color_space output_color_space;
119 bool dwb_is_efc_transition;
120 bool dwb_is_drc;
121 int wb_src_plane_inst;/*hubp, mpcc, inst*/
122 bool update_privacymask;
123 uint32_t mask_id;
124
125 };
126
127 struct dwbc_funcs {
128 bool (*get_caps)(
129 struct dwbc *dwbc,
130 struct dwb_caps *caps);
131
132 bool (*enable)(
133 struct dwbc *dwbc,
134 struct dc_dwb_params *params);
135
136 bool (*disable)(struct dwbc *dwbc);
137
138 bool (*update)(
139 struct dwbc *dwbc,
140 struct dc_dwb_params *params);
141
142 bool (*is_enabled)(
143 struct dwbc *dwbc);
144
145 void (*set_stereo)(
146 struct dwbc *dwbc,
147 struct dwb_stereo_params *stereo_params);
148
149 void (*set_new_content)(
150 struct dwbc *dwbc,
151 bool is_new_content);
152
153 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
154
155 void (*set_warmup)(
156 struct dwbc *dwbc,
157 struct dwb_warmup_params *warmup_params);
158
159 #endif
160
161 bool (*get_dwb_status)(
162 struct dwbc *dwbc);
163 void (*dwb_set_scaler)(
164 struct dwbc *dwbc,
165 struct dc_dwb_params *params);
166 };
167
168 #endif