root/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h

INCLUDED FROM

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DAL_DCHUBBUB_H__
  27 #define __DAL_DCHUBBUB_H__
  28 
  29 
  30 enum dcc_control {
  31         dcc_control__256_256_xxx,
  32         dcc_control__128_128_xxx,
  33         dcc_control__256_64_64,
  34 };
  35 
  36 enum segment_order {
  37         segment_order__na,
  38         segment_order__contiguous,
  39         segment_order__non_contiguous,
  40 };
  41 
  42 struct dcn_hubbub_wm_set {
  43         uint32_t wm_set;
  44         uint32_t data_urgent;
  45         uint32_t pte_meta_urgent;
  46         uint32_t sr_enter;
  47         uint32_t sr_exit;
  48         uint32_t dram_clk_chanage;
  49 };
  50 
  51 struct dcn_hubbub_wm {
  52         struct dcn_hubbub_wm_set sets[4];
  53 };
  54 
  55 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
  56 enum dcn_hubbub_page_table_depth {
  57         DCN_PAGE_TABLE_DEPTH_1_LEVEL,
  58         DCN_PAGE_TABLE_DEPTH_2_LEVEL,
  59         DCN_PAGE_TABLE_DEPTH_3_LEVEL,
  60         DCN_PAGE_TABLE_DEPTH_4_LEVEL
  61 };
  62 
  63 enum dcn_hubbub_page_table_block_size {
  64         DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0,
  65         DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4,
  66 };
  67 
  68 struct dcn_hubbub_phys_addr_config {
  69         struct {
  70                 uint64_t fb_top;
  71                 uint64_t fb_offset;
  72                 uint64_t fb_base;
  73                 uint64_t agp_top;
  74                 uint64_t agp_bot;
  75                 uint64_t agp_base;
  76         } system_aperture;
  77 
  78         struct {
  79                 uint64_t page_table_start_addr;
  80                 uint64_t page_table_end_addr;
  81                 uint64_t page_table_base_addr;
  82         } gart_config;
  83 
  84         uint64_t page_table_default_page_addr;
  85 };
  86 
  87 struct dcn_hubbub_virt_addr_config {
  88         uint64_t                                page_table_start_addr;
  89         uint64_t                                page_table_end_addr;
  90         enum dcn_hubbub_page_table_block_size   page_table_block_size;
  91         enum dcn_hubbub_page_table_depth        page_table_depth;
  92         uint64_t                                page_table_base_addr;
  93 };
  94 
  95 struct hubbub_addr_config {
  96         struct dcn_hubbub_phys_addr_config pa_config;
  97         struct dcn_hubbub_virt_addr_config va_config;
  98         struct {
  99                 uint64_t aperture_check_fault;
 100                 uint64_t generic_fault;
 101         } default_addrs;
 102 };
 103 
 104 #endif
 105 struct hubbub_funcs {
 106         void (*update_dchub)(
 107                         struct hubbub *hubbub,
 108                         struct dchub_init_data *dh_data);
 109 
 110 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 111         int (*init_dchub_sys_ctx)(
 112                         struct hubbub *hubbub,
 113                         struct dcn_hubbub_phys_addr_config *pa_config);
 114         void (*init_vm_ctx)(
 115                         struct hubbub *hubbub,
 116                         struct dcn_hubbub_virt_addr_config *va_config,
 117                         int vmid);
 118 
 119 #endif
 120         bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
 121                         const struct dc_dcc_surface_param *input,
 122                         struct dc_surface_dcc_cap *output);
 123 
 124         bool (*dcc_support_swizzle)(
 125                         enum swizzle_mode_values swizzle,
 126                         unsigned int bytes_per_element,
 127                         enum segment_order *segment_order_horz,
 128                         enum segment_order *segment_order_vert);
 129 
 130         bool (*dcc_support_pixel_format)(
 131                         enum surface_pixel_format format,
 132                         unsigned int *bytes_per_element);
 133 
 134         void (*wm_read_state)(struct hubbub *hubbub,
 135                         struct dcn_hubbub_wm *wm);
 136 
 137         void (*get_dchub_ref_freq)(struct hubbub *hubbub,
 138                         unsigned int dccg_ref_freq_inKhz,
 139                         unsigned int *dchub_ref_freq_inKhz);
 140 
 141         void (*program_watermarks)(
 142                         struct hubbub *hubbub,
 143                         struct dcn_watermark_set *watermarks,
 144                         unsigned int refclk_mhz,
 145                         bool safe_to_lower);
 146 
 147         bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
 148         void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
 149 
 150 };
 151 
 152 struct hubbub {
 153         const struct hubbub_funcs *funcs;
 154         struct dc_context *ctx;
 155 };
 156 
 157 #endif