root/drivers/gpu/drm/amd/display/dc/dc_stream.h

INCLUDED FROM

   1 /*
   2  * Copyright 2012-14 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef DC_STREAM_H_
  27 #define DC_STREAM_H_
  28 
  29 #include "dc_types.h"
  30 #include "grph_object_defs.h"
  31 
  32 /*******************************************************************************
  33  * Stream Interfaces
  34  ******************************************************************************/
  35 struct timing_sync_info {
  36         int group_id;
  37         int group_size;
  38         bool master;
  39 };
  40 
  41 struct dc_stream_status {
  42         int primary_otg_inst;
  43         int stream_enc_inst;
  44         int plane_count;
  45         int audio_inst;
  46         struct timing_sync_info timing_sync_info;
  47         struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
  48 };
  49 
  50 // TODO: References to this needs to be removed..
  51 struct freesync_context {
  52         bool dummy;
  53 };
  54 
  55 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  56 enum hubp_dmdata_mode {
  57         DMDATA_SW_MODE,
  58         DMDATA_HW_MODE
  59 };
  60 
  61 struct dc_dmdata_attributes {
  62         /* Specifies whether dynamic meta data will be updated by software
  63          * or has to be fetched by hardware (DMA mode)
  64          */
  65         enum hubp_dmdata_mode dmdata_mode;
  66         /* Specifies if current dynamic meta data is to be used only for the current frame */
  67         bool dmdata_repeat;
  68         /* Specifies the size of Dynamic Metadata surface in byte.  Size of 0 means no Dynamic metadata is fetched */
  69         uint32_t dmdata_size;
  70         /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */
  71         bool dmdata_updated;
  72         /* If hardware mode is used, the base address where DMDATA surface is located */
  73         PHYSICAL_ADDRESS_LOC address;
  74         /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */
  75         bool dmdata_qos_mode;
  76         /* If qos_mode = 1, this is the QOS value to be used: */
  77         uint32_t dmdata_qos_level;
  78         /* Specifies the value in unit of REFCLK cycles to be added to the
  79          * current time to produce the Amortized deadline for Dynamic Metadata chunk request
  80          */
  81         uint32_t dmdata_dl_delta;
  82         /* An unbounded array of uint32s, represents software dmdata to be loaded */
  83         uint32_t *dmdata_sw_data;
  84 };
  85 #endif
  86 
  87 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  88 struct dc_writeback_info {
  89         bool wb_enabled;
  90         int dwb_pipe_inst;
  91         struct dc_dwb_params dwb_params;
  92         struct mcif_buf_params mcif_buf_params;
  93 };
  94 
  95 struct dc_writeback_update {
  96         unsigned int num_wb_info;
  97         struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
  98 };
  99 #endif
 100 
 101 enum vertical_interrupt_ref_point {
 102         START_V_UPDATE = 0,
 103         START_V_SYNC,
 104         INVALID_POINT
 105 
 106         //For now, only v_update interrupt is used.
 107         //START_V_BLANK,
 108         //START_V_ACTIVE
 109 };
 110 
 111 struct periodic_interrupt_config {
 112         enum vertical_interrupt_ref_point ref_point;
 113         int lines_offset;
 114 };
 115 
 116 
 117 struct dc_stream_state {
 118         // sink is deprecated, new code should not reference
 119         // this pointer
 120         struct dc_sink *sink;
 121 
 122         struct dc_link *link;
 123         struct dc_panel_patch sink_patches;
 124         union display_content_support content_support;
 125         struct dc_crtc_timing timing;
 126         struct dc_crtc_timing_adjust adjust;
 127         struct dc_info_packet vrr_infopacket;
 128         struct dc_info_packet vsc_infopacket;
 129         struct dc_info_packet vsp_infopacket;
 130 
 131         struct rect src; /* composition area */
 132         struct rect dst; /* stream addressable area */
 133 
 134         // TODO: References to this needs to be removed..
 135         struct freesync_context freesync_ctx;
 136 
 137         struct audio_info audio_info;
 138 
 139         struct dc_info_packet hdr_static_metadata;
 140         PHYSICAL_ADDRESS_LOC dmdata_address;
 141         bool   use_dynamic_meta;
 142 
 143         struct dc_transfer_func *out_transfer_func;
 144         struct colorspace_transform gamut_remap_matrix;
 145         struct dc_csc_transform csc_color_matrix;
 146 
 147         enum dc_color_space output_color_space;
 148         enum dc_dither_option dither_option;
 149 
 150         enum view_3d_format view_format;
 151 
 152         bool ignore_msa_timing_param;
 153         bool converter_disable_audio;
 154         uint8_t qs_bit;
 155         uint8_t qy_bit;
 156 
 157         /* TODO: custom INFO packets */
 158         /* TODO: ABM info (DMCU) */
 159         /* PSR info */
 160         unsigned char psr_version;
 161         /* TODO: CEA VIC */
 162 
 163         /* DMCU info */
 164         unsigned int abm_level;
 165 
 166         struct periodic_interrupt_config periodic_interrupt0;
 167         struct periodic_interrupt_config periodic_interrupt1;
 168 
 169         /* from core_stream struct */
 170         struct dc_context *ctx;
 171 
 172         /* used by DCP and FMT */
 173         struct bit_depth_reduction_params bit_depth_params;
 174         struct clamping_and_pixel_encoding_params clamping;
 175 
 176         int phy_pix_clk;
 177         enum signal_type signal;
 178         bool dpms_off;
 179 
 180         void *dm_stream_context;
 181 
 182         struct dc_cursor_attributes cursor_attributes;
 183         struct dc_cursor_position cursor_position;
 184         uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
 185 
 186         /* from stream struct */
 187         struct kref refcount;
 188 
 189         struct crtc_trigger_info triggered_crtc_reset;
 190 
 191 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 192         /* writeback */
 193         unsigned int num_wb_info;
 194         struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
 195 #endif
 196         /* Computed state bits */
 197         bool mode_changed : 1;
 198 
 199         /* Output from DC when stream state is committed or altered
 200          * DC may only access these values during:
 201          * dc_commit_state, dc_commit_state_no_check, dc_commit_streams
 202          * values may not change outside of those calls
 203          */
 204         struct {
 205                 // For interrupt management, some hardware instance
 206                 // offsets need to be exposed to DM
 207                 uint8_t otg_offset;
 208         } out;
 209 
 210         bool apply_edp_fast_boot_optimization;
 211         bool apply_seamless_boot_optimization;
 212 
 213         uint32_t stream_id;
 214 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 215         bool is_dsc_enabled;
 216 #endif
 217 };
 218 
 219 struct dc_stream_update {
 220         struct rect src;
 221         struct rect dst;
 222         struct dc_transfer_func *out_transfer_func;
 223         struct dc_info_packet *hdr_static_metadata;
 224         unsigned int *abm_level;
 225 
 226         struct periodic_interrupt_config *periodic_interrupt0;
 227         struct periodic_interrupt_config *periodic_interrupt1;
 228 
 229         struct dc_info_packet *vrr_infopacket;
 230         struct dc_info_packet *vsc_infopacket;
 231         struct dc_info_packet *vsp_infopacket;
 232 
 233         bool *dpms_off;
 234 
 235         struct colorspace_transform *gamut_remap;
 236         enum dc_color_space *output_color_space;
 237         enum dc_dither_option *dither_option;
 238 
 239         struct dc_csc_transform *output_csc_transform;
 240 
 241 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 242         struct dc_writeback_update *wb_update;
 243 #endif
 244 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
 245         struct dc_dsc_config *dsc_config;
 246 #endif
 247 };
 248 
 249 bool dc_is_stream_unchanged(
 250         struct dc_stream_state *old_stream, struct dc_stream_state *stream);
 251 bool dc_is_stream_scaling_unchanged(
 252         struct dc_stream_state *old_stream, struct dc_stream_state *stream);
 253 
 254 /*
 255  * Set up surface attributes and associate to a stream
 256  * The surfaces parameter is an absolute set of all surface active for the stream.
 257  * If no surfaces are provided, the stream will be blanked; no memory read.
 258  * Any flip related attribute changes must be done through this interface.
 259  *
 260  * After this call:
 261  *   Surfaces attributes are programmed and configured to be composed into stream.
 262  *   This does not trigger a flip.  No surface address is programmed.
 263  */
 264 
 265 void dc_commit_updates_for_stream(struct dc *dc,
 266                 struct dc_surface_update *srf_updates,
 267                 int surface_count,
 268                 struct dc_stream_state *stream,
 269                 struct dc_stream_update *stream_update,
 270                 struct dc_state *state);
 271 /*
 272  * Log the current stream state.
 273  */
 274 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
 275 
 276 uint8_t dc_get_current_stream_count(struct dc *dc);
 277 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
 278 
 279 /*
 280  * Return the current frame counter.
 281  */
 282 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
 283 
 284 /*
 285  * Send dp sdp message.
 286  */
 287 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
 288                 const uint8_t *custom_sdp_message,
 289                 unsigned int sdp_message_size);
 290 
 291 /* TODO: Return parsed values rather than direct register read
 292  * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos)
 293  * being refactored properly to be dce-specific
 294  */
 295 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
 296                                   uint32_t *v_blank_start,
 297                                   uint32_t *v_blank_end,
 298                                   uint32_t *h_position,
 299                                   uint32_t *v_position);
 300 
 301 enum dc_status dc_add_stream_to_ctx(
 302                         struct dc *dc,
 303                 struct dc_state *new_ctx,
 304                 struct dc_stream_state *stream);
 305 
 306 enum dc_status dc_remove_stream_from_ctx(
 307                 struct dc *dc,
 308                         struct dc_state *new_ctx,
 309                         struct dc_stream_state *stream);
 310 
 311 
 312 bool dc_add_plane_to_context(
 313                 const struct dc *dc,
 314                 struct dc_stream_state *stream,
 315                 struct dc_plane_state *plane_state,
 316                 struct dc_state *context);
 317 
 318 bool dc_remove_plane_from_context(
 319                 const struct dc *dc,
 320                 struct dc_stream_state *stream,
 321                 struct dc_plane_state *plane_state,
 322                 struct dc_state *context);
 323 
 324 bool dc_rem_all_planes_for_stream(
 325                 const struct dc *dc,
 326                 struct dc_stream_state *stream,
 327                 struct dc_state *context);
 328 
 329 bool dc_add_all_planes_for_stream(
 330                 const struct dc *dc,
 331                 struct dc_stream_state *stream,
 332                 struct dc_plane_state * const *plane_states,
 333                 int plane_count,
 334                 struct dc_state *context);
 335 
 336 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 337 bool dc_stream_add_writeback(struct dc *dc,
 338                 struct dc_stream_state *stream,
 339                 struct dc_writeback_info *wb_info);
 340 bool dc_stream_remove_writeback(struct dc *dc,
 341                 struct dc_stream_state *stream,
 342                 uint32_t dwb_pipe_inst);
 343 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
 344 bool dc_stream_set_dynamic_metadata(struct dc *dc,
 345                 struct dc_stream_state *stream,
 346                 struct dc_dmdata_attributes *dmdata_attr);
 347 #endif
 348 
 349 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
 350 
 351 /*
 352  * Set up streams and links associated to drive sinks
 353  * The streams parameter is an absolute set of all active streams.
 354  *
 355  * After this call:
 356  *   Phy, Encoder, Timing Generator are programmed and enabled.
 357  *   New streams are enabled with blank stream; no memory read.
 358  */
 359 /*
 360  * Enable stereo when commit_streams is not required,
 361  * for example, frame alternate.
 362  */
 363 bool dc_enable_stereo(
 364         struct dc *dc,
 365         struct dc_state *context,
 366         struct dc_stream_state *streams[],
 367         uint8_t stream_count);
 368 
 369 
 370 enum surface_update_type dc_check_update_surfaces_for_stream(
 371                 struct dc *dc,
 372                 struct dc_surface_update *updates,
 373                 int surface_count,
 374                 struct dc_stream_update *stream_update,
 375                 const struct dc_stream_status *stream_status);
 376 
 377 /**
 378  * Create a new default stream for the requested sink
 379  */
 380 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
 381 
 382 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream);
 383 
 384 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);
 385 
 386 void dc_stream_retain(struct dc_stream_state *dc_stream);
 387 void dc_stream_release(struct dc_stream_state *dc_stream);
 388 
 389 struct dc_stream_status *dc_stream_get_status_from_state(
 390         struct dc_state *state,
 391         struct dc_stream_state *stream);
 392 struct dc_stream_status *dc_stream_get_status(
 393         struct dc_stream_state *dc_stream);
 394 
 395 /*******************************************************************************
 396  * Cursor interfaces - To manages the cursor within a stream
 397  ******************************************************************************/
 398 /* TODO: Deprecated once we switch to dc_set_cursor_position */
 399 bool dc_stream_set_cursor_attributes(
 400         struct dc_stream_state *stream,
 401         const struct dc_cursor_attributes *attributes);
 402 
 403 bool dc_stream_set_cursor_position(
 404         struct dc_stream_state *stream,
 405         const struct dc_cursor_position *position);
 406 
 407 
 408 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 409                                 struct dc_stream_state *stream,
 410                                 struct dc_crtc_timing_adjust *adjust);
 411 
 412 bool dc_stream_get_crtc_position(struct dc *dc,
 413                                  struct dc_stream_state **stream,
 414                                  int num_streams,
 415                                  unsigned int *v_pos,
 416                                  unsigned int *nom_v_pos);
 417 
 418 bool dc_stream_configure_crc(struct dc *dc,
 419                              struct dc_stream_state *stream,
 420                              bool enable,
 421                              bool continuous);
 422 
 423 bool dc_stream_get_crc(struct dc *dc,
 424                        struct dc_stream_state *stream,
 425                        uint32_t *r_cr,
 426                        uint32_t *g_y,
 427                        uint32_t *b_cb);
 428 
 429 void dc_stream_set_static_screen_events(struct dc *dc,
 430                                         struct dc_stream_state **stream,
 431                                         int num_streams,
 432                                         const struct dc_static_screen_events *events);
 433 
 434 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 435                                  enum dc_dither_option option);
 436 
 437 bool dc_stream_set_gamut_remap(struct dc *dc,
 438                                const struct dc_stream_state *stream);
 439 
 440 bool dc_stream_program_csc_matrix(struct dc *dc,
 441                                   struct dc_stream_state *stream);
 442 
 443 bool dc_stream_get_crtc_position(struct dc *dc,
 444                                  struct dc_stream_state **stream,
 445                                  int num_streams,
 446                                  unsigned int *v_pos,
 447                                  unsigned int *nom_v_pos);
 448 
 449 #endif /* DC_STREAM_H_ */