drivers/gpu/drm/amd/display/dc/dc_dp

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   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef DC_DP_TYPES_H
  27 #define DC_DP_TYPES_H
  28 
  29 #include "os_types.h"
  30 
  31 enum dc_lane_count {
  32         LANE_COUNT_UNKNOWN = 0,
  33         LANE_COUNT_ONE = 1,
  34         LANE_COUNT_TWO = 2,
  35         LANE_COUNT_FOUR = 4,
  36         LANE_COUNT_EIGHT = 8,
  37         LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
  38 };
  39 
  40 /* This is actually a reference clock (27MHz) multiplier
  41  * 162MBps bandwidth for 1.62GHz like rate,
  42  * 270MBps for 2.70GHz,
  43  * 324MBps for 3.24Ghz,
  44  * 540MBps for 5.40GHz
  45  * 810MBps for 8.10GHz
  46  */
  47 enum dc_link_rate {
  48         LINK_RATE_UNKNOWN = 0,
  49         LINK_RATE_LOW = 0x06,           // Rate_1 (RBR) - 1.62 Gbps/Lane
  50         LINK_RATE_RATE_2 = 0x08,        // Rate_2               - 2.16 Gbps/Lane
  51         LINK_RATE_RATE_3 = 0x09,        // Rate_3               - 2.43 Gbps/Lane
  52         LINK_RATE_HIGH = 0x0A,          // Rate_4 (HBR) - 2.70 Gbps/Lane
  53         LINK_RATE_RBR2 = 0x0C,          // Rate_5 (RBR2)- 3.24 Gbps/Lane
  54         LINK_RATE_RATE_6 = 0x10,        // Rate_6               - 4.32 Gbps/Lane
  55         LINK_RATE_HIGH2 = 0x14,         // Rate_7 (HBR2)- 5.40 Gbps/Lane
  56         LINK_RATE_HIGH3 = 0x1E          // Rate_8 (HBR3)- 8.10 Gbps/Lane
  57 };
  58 
  59 enum dc_link_spread {
  60         LINK_SPREAD_DISABLED = 0x00,
  61         /* 0.5 % downspread 30 kHz */
  62         LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
  63         /* 0.5 % downspread 33 kHz */
  64         LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
  65 };
  66 
  67 enum dc_voltage_swing {
  68         VOLTAGE_SWING_LEVEL0 = 0,       /* direct HW translation! */
  69         VOLTAGE_SWING_LEVEL1,
  70         VOLTAGE_SWING_LEVEL2,
  71         VOLTAGE_SWING_LEVEL3,
  72         VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
  73 };
  74 
  75 enum dc_pre_emphasis {
  76         PRE_EMPHASIS_DISABLED = 0,      /* direct HW translation! */
  77         PRE_EMPHASIS_LEVEL1,
  78         PRE_EMPHASIS_LEVEL2,
  79         PRE_EMPHASIS_LEVEL3,
  80         PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
  81 };
  82 /* Post Cursor 2 is optional for transmitter
  83  * and it applies only to the main link operating at HBR2
  84  */
  85 enum dc_post_cursor2 {
  86         POST_CURSOR2_DISABLED = 0,      /* direct HW translation! */
  87         POST_CURSOR2_LEVEL1,
  88         POST_CURSOR2_LEVEL2,
  89         POST_CURSOR2_LEVEL3,
  90         POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
  91 };
  92 
  93 enum dc_dp_training_pattern {
  94         DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
  95         DP_TRAINING_PATTERN_SEQUENCE_2,
  96         DP_TRAINING_PATTERN_SEQUENCE_3,
  97         DP_TRAINING_PATTERN_SEQUENCE_4,
  98 };
  99 
 100 struct dc_link_settings {
 101         enum dc_lane_count lane_count;
 102         enum dc_link_rate link_rate;
 103         enum dc_link_spread link_spread;
 104         bool use_link_rate_set;
 105         uint8_t link_rate_set;
 106 };
 107 
 108 struct dc_lane_settings {
 109         enum dc_voltage_swing VOLTAGE_SWING;
 110         enum dc_pre_emphasis PRE_EMPHASIS;
 111         enum dc_post_cursor2 POST_CURSOR2;
 112 };
 113 
 114 struct dc_link_training_settings {
 115         struct dc_link_settings link;
 116         struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
 117 };
 118 
 119 struct dc_link_training_overrides {
 120         enum dc_voltage_swing *voltage_swing;
 121         enum dc_pre_emphasis *pre_emphasis;
 122         enum dc_post_cursor2 *post_cursor2;
 123 
 124         uint16_t *cr_pattern_time;
 125         uint16_t *eq_pattern_time;
 126         enum dc_dp_training_pattern *pattern_for_eq;
 127 
 128         enum dc_link_spread *downspread;
 129         bool *alternate_scrambler_reset;
 130         bool *enhanced_framing;
 131         bool *mst_enable;
 132 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 133         bool *fec_enable;
 134 #endif
 135 };
 136 
 137 union dpcd_rev {
 138         struct {
 139                 uint8_t MINOR:4;
 140                 uint8_t MAJOR:4;
 141         } bits;
 142         uint8_t raw;
 143 };
 144 
 145 union max_lane_count {
 146         struct {
 147                 uint8_t MAX_LANE_COUNT:5;
 148                 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
 149                 uint8_t TPS3_SUPPORTED:1;
 150                 uint8_t ENHANCED_FRAME_CAP:1;
 151         } bits;
 152         uint8_t raw;
 153 };
 154 
 155 union max_down_spread {
 156         struct {
 157                 uint8_t MAX_DOWN_SPREAD:1;
 158                 uint8_t RESERVED:5;
 159                 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
 160                 uint8_t TPS4_SUPPORTED:1;
 161         } bits;
 162         uint8_t raw;
 163 };
 164 
 165 union mstm_cap {
 166         struct {
 167                 uint8_t MST_CAP:1;
 168                 uint8_t RESERVED:7;
 169         } bits;
 170         uint8_t raw;
 171 };
 172 
 173 union lane_count_set {
 174         struct {
 175                 uint8_t LANE_COUNT_SET:5;
 176                 uint8_t POST_LT_ADJ_REQ_GRANTED:1;
 177                 uint8_t RESERVED:1;
 178                 uint8_t ENHANCED_FRAMING:1;
 179         } bits;
 180         uint8_t raw;
 181 };
 182 
 183 union lane_status {
 184         struct {
 185                 uint8_t CR_DONE_0:1;
 186                 uint8_t CHANNEL_EQ_DONE_0:1;
 187                 uint8_t SYMBOL_LOCKED_0:1;
 188                 uint8_t RESERVED0:1;
 189                 uint8_t CR_DONE_1:1;
 190                 uint8_t CHANNEL_EQ_DONE_1:1;
 191                 uint8_t SYMBOL_LOCKED_1:1;
 192                 uint8_t RESERVED_1:1;
 193         } bits;
 194         uint8_t raw;
 195 };
 196 
 197 union device_service_irq {
 198         struct {
 199                 uint8_t REMOTE_CONTROL_CMD_PENDING:1;
 200                 uint8_t AUTOMATED_TEST:1;
 201                 uint8_t CP_IRQ:1;
 202                 uint8_t MCCS_IRQ:1;
 203                 uint8_t DOWN_REP_MSG_RDY:1;
 204                 uint8_t UP_REQ_MSG_RDY:1;
 205                 uint8_t SINK_SPECIFIC:1;
 206                 uint8_t reserved:1;
 207         } bits;
 208         uint8_t raw;
 209 };
 210 
 211 union sink_count {
 212         struct {
 213                 uint8_t SINK_COUNT:6;
 214                 uint8_t CPREADY:1;
 215                 uint8_t RESERVED:1;
 216         } bits;
 217         uint8_t raw;
 218 };
 219 
 220 union lane_align_status_updated {
 221         struct {
 222                 uint8_t INTERLANE_ALIGN_DONE:1;
 223                 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
 224                 uint8_t RESERVED:4;
 225                 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
 226                 uint8_t LINK_STATUS_UPDATED:1;
 227         } bits;
 228         uint8_t raw;
 229 };
 230 
 231 union lane_adjust {
 232         struct {
 233                 uint8_t VOLTAGE_SWING_LANE:2;
 234                 uint8_t PRE_EMPHASIS_LANE:2;
 235                 uint8_t RESERVED:4;
 236         } bits;
 237         uint8_t raw;
 238 };
 239 
 240 union dpcd_training_pattern {
 241         struct {
 242                 uint8_t TRAINING_PATTERN_SET:4;
 243                 uint8_t RECOVERED_CLOCK_OUT_EN:1;
 244                 uint8_t SCRAMBLING_DISABLE:1;
 245                 uint8_t SYMBOL_ERROR_COUNT_SEL:2;
 246         } v1_4;
 247         struct {
 248                 uint8_t TRAINING_PATTERN_SET:2;
 249                 uint8_t LINK_QUAL_PATTERN_SET:2;
 250                 uint8_t RESERVED:4;
 251         } v1_3;
 252         uint8_t raw;
 253 };
 254 
 255 /* Training Lane is used to configure downstream DP device's voltage swing
 256 and pre-emphasis levels*/
 257 /* The DPCD addresses are from 0x103 to 0x106*/
 258 union dpcd_training_lane {
 259         struct {
 260                 uint8_t VOLTAGE_SWING_SET:2;
 261                 uint8_t MAX_SWING_REACHED:1;
 262                 uint8_t PRE_EMPHASIS_SET:2;
 263                 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
 264                 uint8_t RESERVED:2;
 265         } bits;
 266         uint8_t raw;
 267 };
 268 
 269 /* TMDS-converter related */
 270 union dwnstream_port_caps_byte0 {
 271         struct {
 272                 uint8_t DWN_STRM_PORTX_TYPE:3;
 273                 uint8_t DWN_STRM_PORTX_HPD:1;
 274                 uint8_t RESERVERD:4;
 275         } bits;
 276         uint8_t raw;
 277 };
 278 
 279 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
 280 enum dpcd_downstream_port_detailed_type {
 281         DOWN_STREAM_DETAILED_DP = 0,
 282         DOWN_STREAM_DETAILED_VGA,
 283         DOWN_STREAM_DETAILED_DVI,
 284         DOWN_STREAM_DETAILED_HDMI,
 285         DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
 286         DOWN_STREAM_DETAILED_DP_PLUS_PLUS
 287 };
 288 
 289 union dwnstream_port_caps_byte2 {
 290         struct {
 291                 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
 292                 uint8_t RESERVED:6;
 293         } bits;
 294         uint8_t raw;
 295 };
 296 
 297 union dp_downstream_port_present {
 298         uint8_t byte;
 299         struct {
 300                 uint8_t PORT_PRESENT:1;
 301                 uint8_t PORT_TYPE:2;
 302                 uint8_t FMT_CONVERSION:1;
 303                 uint8_t DETAILED_CAPS:1;
 304                 uint8_t RESERVED:3;
 305         } fields;
 306 };
 307 
 308 union dwnstream_port_caps_byte3_dvi {
 309         struct {
 310                 uint8_t RESERVED1:1;
 311                 uint8_t DUAL_LINK:1;
 312                 uint8_t HIGH_COLOR_DEPTH:1;
 313                 uint8_t RESERVED2:5;
 314         } bits;
 315         uint8_t raw;
 316 };
 317 
 318 union dwnstream_port_caps_byte3_hdmi {
 319         struct {
 320                 uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
 321                 uint8_t YCrCr422_PASS_THROUGH:1;
 322                 uint8_t YCrCr420_PASS_THROUGH:1;
 323                 uint8_t YCrCr422_CONVERSION:1;
 324                 uint8_t YCrCr420_CONVERSION:1;
 325                 uint8_t RESERVED:3;
 326         } bits;
 327         uint8_t raw;
 328 };
 329 
 330 /*4-byte structure for detailed capabilities of a down-stream port
 331 (DP-to-TMDS converter).*/
 332 union dwnstream_portxcaps {
 333         struct {
 334                 union dwnstream_port_caps_byte0 byte0;
 335                 unsigned char max_TMDS_clock;   //byte1
 336                 union dwnstream_port_caps_byte2 byte2;
 337 
 338                 union {
 339                         union dwnstream_port_caps_byte3_dvi byteDVI;
 340                         union dwnstream_port_caps_byte3_hdmi byteHDMI;
 341                 } byte3;
 342         } bytes;
 343 
 344         unsigned char raw[4];
 345 };
 346 
 347 union downstream_port {
 348         struct {
 349                 unsigned char   present:1;
 350                 unsigned char   type:2;
 351                 unsigned char   format_conv:1;
 352                 unsigned char   detailed_caps:1;
 353                 unsigned char   reserved:3;
 354         } bits;
 355         unsigned char raw;
 356 };
 357 
 358 
 359 union sink_status {
 360         struct {
 361                 uint8_t RX_PORT0_STATUS:1;
 362                 uint8_t RX_PORT1_STATUS:1;
 363                 uint8_t RESERVED:6;
 364         } bits;
 365         uint8_t raw;
 366 };
 367 
 368 /*6-byte structure corresponding to 6 registers (200h-205h)
 369 read during handling of HPD-IRQ*/
 370 union hpd_irq_data {
 371         struct {
 372                 union sink_count sink_cnt;/* 200h */
 373                 union device_service_irq device_service_irq;/* 201h */
 374                 union lane_status lane01_status;/* 202h */
 375                 union lane_status lane23_status;/* 203h */
 376                 union lane_align_status_updated lane_status_updated;/* 204h */
 377                 union sink_status sink_status;
 378         } bytes;
 379         uint8_t raw[6];
 380 };
 381 
 382 union down_stream_port_count {
 383         struct {
 384                 uint8_t DOWN_STR_PORT_COUNT:4;
 385                 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
 386                 /*Bit 6 = MSA_TIMING_PAR_IGNORED
 387                 0 = Sink device requires the MSA timing parameters
 388                 1 = Sink device is capable of rendering incoming video
 389                  stream without MSA timing parameters*/
 390                 uint8_t IGNORE_MSA_TIMING_PARAM:1;
 391                 /*Bit 7 = OUI Support
 392                 0 = OUI not supported
 393                 1 = OUI supported
 394                 (OUI and Device Identification mandatory for DP 1.2)*/
 395                 uint8_t OUI_SUPPORT:1;
 396         } bits;
 397         uint8_t raw;
 398 };
 399 
 400 union down_spread_ctrl {
 401         struct {
 402                 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
 403         /* Bits 4 = SPREAD_AMP. Spreading amplitude
 404         0 = Main link signal is not downspread
 405         1 = Main link signal is downspread <= 0.5%
 406         with frequency in the range of 30kHz ~ 33kHz*/
 407                 uint8_t SPREAD_AMP:1;
 408                 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
 409         /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
 410         0 = Source device will send valid data for the MSA Timing Params
 411         1 = Source device may send invalid data for these MSA Timing Params*/
 412                 uint8_t IGNORE_MSA_TIMING_PARAM:1;
 413         } bits;
 414         uint8_t raw;
 415 };
 416 
 417 union dpcd_edp_config {
 418         struct {
 419                 uint8_t PANEL_MODE_EDP:1;
 420                 uint8_t FRAMING_CHANGE_ENABLE:1;
 421                 uint8_t RESERVED:5;
 422                 uint8_t PANEL_SELF_TEST_ENABLE:1;
 423         } bits;
 424         uint8_t raw;
 425 };
 426 
 427 struct dp_device_vendor_id {
 428         uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
 429         uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
 430 };
 431 
 432 struct dp_sink_hw_fw_revision {
 433         uint8_t ieee_hw_rev;
 434         uint8_t ieee_fw_rev[2];
 435 };
 436 
 437 /*DPCD register of DP receiver capability field bits-*/
 438 union edp_configuration_cap {
 439         struct {
 440                 uint8_t ALT_SCRAMBLER_RESET:1;
 441                 uint8_t FRAMING_CHANGE:1;
 442                 uint8_t RESERVED:1;
 443                 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
 444                 uint8_t RESERVED2:4;
 445         } bits;
 446         uint8_t raw;
 447 };
 448 
 449 union dprx_feature {
 450         struct {
 451                 uint8_t GTC_CAP:1;                             // bit 0: DP 1.3+
 452                 uint8_t SST_SPLIT_SDP_CAP:1;                   // bit 1: DP 1.4
 453                 uint8_t AV_SYNC_CAP:1;                         // bit 2: DP 1.3+
 454                 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1;       // bit 3: DP 1.3+
 455                 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1;          // bit 4: DP 1.4
 456                 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4
 457                 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1;           // bit 6: DP 1.4
 458                 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1;  // bit 7: DP 1.4
 459         } bits;
 460         uint8_t raw;
 461 };
 462 
 463 union training_aux_rd_interval {
 464         struct {
 465                 uint8_t TRAINIG_AUX_RD_INTERVAL:7;
 466                 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
 467         } bits;
 468         uint8_t raw;
 469 };
 470 
 471 /* Automated test structures */
 472 union test_request {
 473         struct {
 474         uint8_t LINK_TRAINING         :1;
 475         uint8_t LINK_TEST_PATTRN      :1;
 476         uint8_t EDID_READ             :1;
 477         uint8_t PHY_TEST_PATTERN      :1;
 478         uint8_t AUDIO_TEST_PATTERN    :1;
 479         uint8_t RESERVED              :1;
 480         uint8_t TEST_STEREO_3D        :1;
 481         } bits;
 482         uint8_t raw;
 483 };
 484 
 485 union test_response {
 486         struct {
 487                 uint8_t ACK         :1;
 488                 uint8_t NO_ACK      :1;
 489                 uint8_t EDID_CHECKSUM_WRITE:1;
 490                 uint8_t RESERVED    :5;
 491         } bits;
 492         uint8_t raw;
 493 };
 494 
 495 union phy_test_pattern {
 496         struct {
 497                 /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
 498                  * and 3 bits for DP1.2.
 499                  */
 500                 uint8_t PATTERN     :3;
 501                 /* BY speci, bit7:2 is 0 for DP1.1. */
 502                 uint8_t RESERVED    :5;
 503         } bits;
 504         uint8_t raw;
 505 };
 506 
 507 /* States of Compliance Test Specification (CTS DP1.2). */
 508 union compliance_test_state {
 509         struct {
 510                 unsigned char STEREO_3D_RUNNING        : 1;
 511                 unsigned char RESERVED                 : 7;
 512         } bits;
 513         unsigned char raw;
 514 };
 515 
 516 union link_test_pattern {
 517         struct {
 518                 /* dpcd_link_test_patterns */
 519                 unsigned char PATTERN :2;
 520                 unsigned char RESERVED:6;
 521         } bits;
 522         unsigned char raw;
 523 };
 524 
 525 union test_misc {
 526         struct dpcd_test_misc_bits {
 527                 unsigned char SYNC_CLOCK :1;
 528                 /* dpcd_test_color_format */
 529                 unsigned char CLR_FORMAT :2;
 530                 /* dpcd_test_dyn_range */
 531                 unsigned char DYN_RANGE  :1;
 532                 unsigned char YCBCR      :1;
 533                 /* dpcd_test_bit_depth */
 534                 unsigned char BPC        :3;
 535         } bits;
 536         unsigned char raw;
 537 };
 538 
 539 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 540 /* FEC capability DPCD register field bits-*/
 541 union dpcd_fec_capability {
 542         struct {
 543                 uint8_t FEC_CAPABLE:1;
 544                 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
 545                 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
 546                 uint8_t BIT_ERROR_COUNT_CAPABLE:1;
 547                 uint8_t RESERVED:4;
 548         } bits;
 549         uint8_t raw;
 550 };
 551 
 552 /* DSC capability DPCD register field bits-*/
 553 struct dpcd_dsc_support {
 554         uint8_t DSC_SUPPORT             :1;
 555         uint8_t DSC_PASSTHROUGH_SUPPORT :1;
 556         uint8_t RESERVED                :6;
 557 };
 558 
 559 struct dpcd_dsc_algorithm_revision {
 560         uint8_t DSC_VERSION_MAJOR       :4;
 561         uint8_t DSC_VERSION_MINOR       :4;
 562 };
 563 
 564 struct dpcd_dsc_rc_buffer_block_size {
 565         uint8_t RC_BLOCK_BUFFER_SIZE    :2;
 566         uint8_t RESERVED                :6;
 567 };
 568 
 569 struct dpcd_dsc_slice_capability1 {
 570         uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE        :1;
 571         uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 572         uint8_t RESERVED                                :1;
 573         uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE      :1;
 574         uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 575         uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE     :1;
 576         uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 577         uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE    :1;
 578 };
 579 
 580 struct dpcd_dsc_line_buffer_bit_depth {
 581         uint8_t LINE_BUFFER_BIT_DEPTH   :4;
 582         uint8_t RESERVED                :4;
 583 };
 584 
 585 struct dpcd_dsc_block_prediction_support {
 586         uint8_t BLOCK_PREDICTION_SUPPORT:1;
 587         uint8_t RESERVED                :7;
 588 };
 589 
 590 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor {
 591         uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW        :7;
 592         uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH       :7;
 593         uint8_t RESERVED                                                        :2;
 594 };
 595 
 596 struct dpcd_dsc_decoder_color_format_capabilities {
 597         uint8_t RGB_SUPPORT                     :1;
 598         uint8_t Y_CB_CR_444_SUPPORT             :1;
 599         uint8_t Y_CB_CR_SIMPLE_422_SUPPORT      :1;
 600         uint8_t Y_CB_CR_NATIVE_422_SUPPORT      :1;
 601         uint8_t Y_CB_CR_NATIVE_420_SUPPORT      :1;
 602         uint8_t RESERVED                        :3;
 603 };
 604 
 605 struct dpcd_dsc_decoder_color_depth_capabilities {
 606         uint8_t RESERVED0                       :1;
 607         uint8_t EIGHT_BITS_PER_COLOR_SUPPORT    :1;
 608         uint8_t TEN_BITS_PER_COLOR_SUPPORT      :1;
 609         uint8_t TWELVE_BITS_PER_COLOR_SUPPORT   :1;
 610         uint8_t RESERVED1                       :4;
 611 };
 612 
 613 struct dpcd_peak_dsc_throughput_dsc_sink {
 614         uint8_t THROUGHPUT_MODE_0:4;
 615         uint8_t THROUGHPUT_MODE_1:4;
 616 };
 617 
 618 struct dpcd_dsc_slice_capabilities_2 {
 619         uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE      :1;
 620         uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE       :1;
 621         uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE   :1;
 622         uint8_t RESERVED                                :5;
 623 };
 624 
 625 struct dpcd_bits_per_pixel_increment{
 626         uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED   :3;
 627         uint8_t RESERVED                                :5;
 628 };
 629 union dpcd_dsc_basic_capabilities {
 630         struct {
 631                 struct dpcd_dsc_support dsc_support;
 632                 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision;
 633                 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size;
 634                 uint8_t dsc_rc_buffer_size;
 635                 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1;
 636                 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth;
 637                 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support;
 638                 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor;
 639                 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities;
 640                 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities;
 641                 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink;
 642                 uint8_t dsc_maximum_slice_width;
 643                 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2;
 644                 uint8_t reserved;
 645                 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment;
 646         } fields;
 647         uint8_t raw[16];
 648 };
 649 
 650 union dpcd_dsc_ext_capabilities {
 651         struct {
 652                 uint8_t BRANCH_OVERALL_THROUGHPUT_0;
 653                 uint8_t BRANCH_OVERALL_THROUGHPUT_1;
 654                 uint8_t BRANCH_MAX_LINE_WIDTH;
 655         } fields;
 656         uint8_t raw[3];
 657 };
 658 
 659 struct dpcd_dsc_capabilities {
 660         union dpcd_dsc_basic_capabilities dsc_basic_caps;
 661         union dpcd_dsc_ext_capabilities dsc_ext_caps;
 662 };
 663 
 664 #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
 665 
 666 #endif /* DC_DP_TYPES_H */
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root/drivers/gpu/drm/amd/display/dc/dc_dp_types.h

INCLUDED FROM
