drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service

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This source file includes following definitions.
to_dal_irq_source_dcn10
hpd_ack
construct
dal_irq_service_dcn10_create
   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include <linux/slab.h>
  27 
  28 #include "dm_services.h"
  29 
  30 #include "include/logger_interface.h"
  31 
  32 #include "../dce110/irq_service_dce110.h"
  33 
  34 #include "dcn/dcn_1_0_offset.h"
  35 #include "dcn/dcn_1_0_sh_mask.h"
  36 #include "soc15_hw_ip.h"
  37 #include "vega10_ip_offset.h"
  38 
  39 #include "irq_service_dcn10.h"
  40 
  41 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  42 
  43 enum dc_irq_source to_dal_irq_source_dcn10(
  44                 struct irq_service *irq_service,
  45                 uint32_t src_id,
  46                 uint32_t ext_id)
  47 {
  48         switch (src_id) {
  49         case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
  50                 return DC_IRQ_SOURCE_VBLANK1;
  51         case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
  52                 return DC_IRQ_SOURCE_VBLANK2;
  53         case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
  54                 return DC_IRQ_SOURCE_VBLANK3;
  55         case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
  56                 return DC_IRQ_SOURCE_VBLANK4;
  57         case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
  58                 return DC_IRQ_SOURCE_VBLANK5;
  59         case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
  60                 return DC_IRQ_SOURCE_VBLANK6;
  61         case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  62                 return DC_IRQ_SOURCE_VUPDATE1;
  63         case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  64                 return DC_IRQ_SOURCE_VUPDATE2;
  65         case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  66                 return DC_IRQ_SOURCE_VUPDATE3;
  67         case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  68                 return DC_IRQ_SOURCE_VUPDATE4;
  69         case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  70                 return DC_IRQ_SOURCE_VUPDATE5;
  71         case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  72                 return DC_IRQ_SOURCE_VUPDATE6;
  73         case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
  74                 return DC_IRQ_SOURCE_PFLIP1;
  75         case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
  76                 return DC_IRQ_SOURCE_PFLIP2;
  77         case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
  78                 return DC_IRQ_SOURCE_PFLIP3;
  79         case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
  80                 return DC_IRQ_SOURCE_PFLIP4;
  81         case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
  82                 return DC_IRQ_SOURCE_PFLIP5;
  83         case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
  84                 return DC_IRQ_SOURCE_PFLIP6;
  85 
  86         case DCN_1_0__SRCID__DC_HPD1_INT:
  87                 /* generic src_id for all HPD and HPDRX interrupts */
  88                 switch (ext_id) {
  89                 case DCN_1_0__CTXID__DC_HPD1_INT:
  90                         return DC_IRQ_SOURCE_HPD1;
  91                 case DCN_1_0__CTXID__DC_HPD2_INT:
  92                         return DC_IRQ_SOURCE_HPD2;
  93                 case DCN_1_0__CTXID__DC_HPD3_INT:
  94                         return DC_IRQ_SOURCE_HPD3;
  95                 case DCN_1_0__CTXID__DC_HPD4_INT:
  96                         return DC_IRQ_SOURCE_HPD4;
  97                 case DCN_1_0__CTXID__DC_HPD5_INT:
  98                         return DC_IRQ_SOURCE_HPD5;
  99                 case DCN_1_0__CTXID__DC_HPD6_INT:
 100                         return DC_IRQ_SOURCE_HPD6;
 101                 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
 102                         return DC_IRQ_SOURCE_HPD1RX;
 103                 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
 104                         return DC_IRQ_SOURCE_HPD2RX;
 105                 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
 106                         return DC_IRQ_SOURCE_HPD3RX;
 107                 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
 108                         return DC_IRQ_SOURCE_HPD4RX;
 109                 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
 110                         return DC_IRQ_SOURCE_HPD5RX;
 111                 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
 112                         return DC_IRQ_SOURCE_HPD6RX;
 113                 default:
 114                         return DC_IRQ_SOURCE_INVALID;
 115                 }
 116                 break;
 117 
 118         default:
 119                 return DC_IRQ_SOURCE_INVALID;
 120         }
 121 }
 122 
 123 static bool hpd_ack(
 124         struct irq_service *irq_service,
 125         const struct irq_source_info *info)
 126 {
 127         uint32_t addr = info->status_reg;
 128         uint32_t value = dm_read_reg(irq_service->ctx, addr);
 129         uint32_t current_status =
 130                 get_reg_field_value(
 131                         value,
 132                         HPD0_DC_HPD_INT_STATUS,
 133                         DC_HPD_SENSE_DELAYED);
 134 
 135         dal_irq_service_ack_generic(irq_service, info);
 136 
 137         value = dm_read_reg(irq_service->ctx, info->enable_reg);
 138 
 139         set_reg_field_value(
 140                 value,
 141                 current_status ? 0 : 1,
 142                 HPD0_DC_HPD_INT_CONTROL,
 143                 DC_HPD_INT_POLARITY);
 144 
 145         dm_write_reg(irq_service->ctx, info->enable_reg, value);
 146 
 147         return true;
 148 }
 149 
 150 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
 151         .set = NULL,
 152         .ack = hpd_ack
 153 };
 154 
 155 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 156         .set = NULL,
 157         .ack = NULL
 158 };
 159 
 160 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
 161         .set = NULL,
 162         .ack = NULL
 163 };
 164 
 165 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 166         .set = NULL,
 167         .ack = NULL
 168 };
 169 
 170 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
 171         .set = NULL,
 172         .ack = NULL
 173 };
 174 
 175 #define BASE_INNER(seg) \
 176         DCE_BASE__INST0_SEG ## seg
 177 
 178 #define BASE(seg) \
 179         BASE_INNER(seg)
 180 
 181 #define SRI(reg_name, block, id)\
 182         BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 183                         mm ## block ## id ## _ ## reg_name
 184 
 185 
 186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
 187         .enable_reg = SRI(reg1, block, reg_num),\
 188         .enable_mask = \
 189                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 190         .enable_value = {\
 191                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 192                 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
 193         },\
 194         .ack_reg = SRI(reg2, block, reg_num),\
 195         .ack_mask = \
 196                 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
 197         .ack_value = \
 198                 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
 199 
 200 #define hpd_int_entry(reg_num)\
 201         [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
 202                 IRQ_REG_ENTRY(HPD, reg_num,\
 203                         DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
 204                         DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
 205                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 206                 .funcs = &hpd_irq_info_funcs\
 207         }
 208 
 209 #define hpd_rx_int_entry(reg_num)\
 210         [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
 211                 IRQ_REG_ENTRY(HPD, reg_num,\
 212                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
 213                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
 214                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 215                 .funcs = &hpd_rx_irq_info_funcs\
 216         }
 217 #define pflip_int_entry(reg_num)\
 218         [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
 219                 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
 220                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
 221                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
 222                 .funcs = &pflip_irq_info_funcs\
 223         }
 224 
 225 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
 226  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
 227  */
 228 #define vupdate_no_lock_int_entry(reg_num)\
 229         [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
 230                 IRQ_REG_ENTRY(OTG, reg_num,\
 231                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
 232                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
 233                 .funcs = &vupdate_no_lock_irq_info_funcs\
 234         }
 235 
 236 #define vblank_int_entry(reg_num)\
 237         [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
 238                 IRQ_REG_ENTRY(OTG, reg_num,\
 239                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
 240                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
 241                 .funcs = &vblank_irq_info_funcs\
 242         }
 243 
 244 #define dummy_irq_entry() \
 245         {\
 246                 .funcs = &dummy_irq_info_funcs\
 247         }
 248 
 249 #define i2c_int_entry(reg_num) \
 250         [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
 251 
 252 #define dp_sink_int_entry(reg_num) \
 253         [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
 254 
 255 #define gpio_pad_int_entry(reg_num) \
 256         [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
 257 
 258 #define dc_underflow_int_entry(reg_num) \
 259         [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
 260 
 261 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
 262         .set = dal_irq_service_dummy_set,
 263         .ack = dal_irq_service_dummy_ack
 264 };
 265 
 266 static const struct irq_source_info
 267 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
 268         [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
 269         hpd_int_entry(0),
 270         hpd_int_entry(1),
 271         hpd_int_entry(2),
 272         hpd_int_entry(3),
 273         hpd_int_entry(4),
 274         hpd_int_entry(5),
 275         hpd_rx_int_entry(0),
 276         hpd_rx_int_entry(1),
 277         hpd_rx_int_entry(2),
 278         hpd_rx_int_entry(3),
 279         hpd_rx_int_entry(4),
 280         hpd_rx_int_entry(5),
 281         i2c_int_entry(1),
 282         i2c_int_entry(2),
 283         i2c_int_entry(3),
 284         i2c_int_entry(4),
 285         i2c_int_entry(5),
 286         i2c_int_entry(6),
 287         dp_sink_int_entry(1),
 288         dp_sink_int_entry(2),
 289         dp_sink_int_entry(3),
 290         dp_sink_int_entry(4),
 291         dp_sink_int_entry(5),
 292         dp_sink_int_entry(6),
 293         [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
 294         pflip_int_entry(0),
 295         pflip_int_entry(1),
 296         pflip_int_entry(2),
 297         pflip_int_entry(3),
 298         [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
 299         [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
 300         [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
 301         gpio_pad_int_entry(0),
 302         gpio_pad_int_entry(1),
 303         gpio_pad_int_entry(2),
 304         gpio_pad_int_entry(3),
 305         gpio_pad_int_entry(4),
 306         gpio_pad_int_entry(5),
 307         gpio_pad_int_entry(6),
 308         gpio_pad_int_entry(7),
 309         gpio_pad_int_entry(8),
 310         gpio_pad_int_entry(9),
 311         gpio_pad_int_entry(10),
 312         gpio_pad_int_entry(11),
 313         gpio_pad_int_entry(12),
 314         gpio_pad_int_entry(13),
 315         gpio_pad_int_entry(14),
 316         gpio_pad_int_entry(15),
 317         gpio_pad_int_entry(16),
 318         gpio_pad_int_entry(17),
 319         gpio_pad_int_entry(18),
 320         gpio_pad_int_entry(19),
 321         gpio_pad_int_entry(20),
 322         gpio_pad_int_entry(21),
 323         gpio_pad_int_entry(22),
 324         gpio_pad_int_entry(23),
 325         gpio_pad_int_entry(24),
 326         gpio_pad_int_entry(25),
 327         gpio_pad_int_entry(26),
 328         gpio_pad_int_entry(27),
 329         gpio_pad_int_entry(28),
 330         gpio_pad_int_entry(29),
 331         gpio_pad_int_entry(30),
 332         dc_underflow_int_entry(1),
 333         dc_underflow_int_entry(2),
 334         dc_underflow_int_entry(3),
 335         dc_underflow_int_entry(4),
 336         dc_underflow_int_entry(5),
 337         dc_underflow_int_entry(6),
 338         [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
 339         [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
 340         vupdate_no_lock_int_entry(0),
 341         vupdate_no_lock_int_entry(1),
 342         vupdate_no_lock_int_entry(2),
 343         vupdate_no_lock_int_entry(3),
 344         vupdate_no_lock_int_entry(4),
 345         vupdate_no_lock_int_entry(5),
 346         vblank_int_entry(0),
 347         vblank_int_entry(1),
 348         vblank_int_entry(2),
 349         vblank_int_entry(3),
 350         vblank_int_entry(4),
 351         vblank_int_entry(5),
 352 };
 353 
 354 static const struct irq_service_funcs irq_service_funcs_dcn10 = {
 355                 .to_dal_irq_source = to_dal_irq_source_dcn10
 356 };
 357 
 358 static void construct(
 359         struct irq_service *irq_service,
 360         struct irq_service_init_data *init_data)
 361 {
 362         dal_irq_service_construct(irq_service, init_data);
 363 
 364         irq_service->info = irq_source_info_dcn10;
 365         irq_service->funcs = &irq_service_funcs_dcn10;
 366 }
 367 
 368 struct irq_service *dal_irq_service_dcn10_create(
 369         struct irq_service_init_data *init_data)
 370 {
 371         struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
 372                                                   GFP_KERNEL);
 373 
 374         if (!irq_service)
 375                 return NULL;
 376 
 377         construct(irq_service, init_data);
 378         return irq_service;
 379 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

DEFINITIONS
