drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory

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This source file includes following definitions.
define_generic_registers
define_ddc_registers
define_hpd_registers
dal_hw_factory_dcn21_init
   1 /*
   2  * Copyright 2013-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  26 #include "dm_services.h"
  27 #include "include/gpio_types.h"
  28 #include "../hw_factory.h"
  29 
  30 
  31 #include "../hw_gpio.h"
  32 #include "../hw_ddc.h"
  33 #include "../hw_hpd.h"
  34 #include "../hw_generic.h"
  35 
  36 #include "hw_factory_dcn21.h"
  37 
  38 #include "dcn/dcn_2_1_0_offset.h"
  39 #include "dcn/dcn_2_1_0_sh_mask.h"
  40 #include "renoir_ip_offset.h"
  41 
  42 #include "reg_helper.h"
  43 #include "../hpd_regs.h"
  44 /* begin *********************
  45  * macros to expend register list macro defined in HW object header file */
  46 
  47 /* DCN */
  48 #define block HPD
  49 #define reg_num 0
  50 
  51 #undef BASE_INNER
  52 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
  53 
  54 #define BASE(seg) BASE_INNER(seg)
  55 
  56 
  57 
  58 #define REG(reg_name)\
  59                 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
  60 
  61 #define SF_HPD(reg_name, field_name, post_fix)\
  62         .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
  63 
  64 #define REGI(reg_name, block, id)\
  65         BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
  66                                 mm ## block ## id ## _ ## reg_name
  67 
  68 #define SF(reg_name, field_name, post_fix)\
  69         .field_name = reg_name ## __ ## field_name ## post_fix
  70 
  71 /* macros to expend register list macro defined in HW object header file
  72  * end *********************/
  73 
  74 
  75 
  76 #define hpd_regs(id) \
  77 {\
  78         HPD_REG_LIST(id)\
  79 }
  80 
  81 static const struct hpd_registers hpd_regs[] = {
  82         hpd_regs(0),
  83         hpd_regs(1),
  84         hpd_regs(2),
  85         hpd_regs(3),
  86         hpd_regs(4),
  87 };
  88 
  89 static const struct hpd_sh_mask hpd_shift = {
  90                 HPD_MASK_SH_LIST(__SHIFT)
  91 };
  92 
  93 static const struct hpd_sh_mask hpd_mask = {
  94                 HPD_MASK_SH_LIST(_MASK)
  95 };
  96 
  97 #include "../ddc_regs.h"
  98 
  99  /* set field name */
 100 #define SF_DDC(reg_name, field_name, post_fix)\
 101         .field_name = reg_name ## __ ## field_name ## post_fix
 102 
 103 static const struct ddc_registers ddc_data_regs_dcn[] = {
 104         ddc_data_regs_dcn2(1),
 105         ddc_data_regs_dcn2(2),
 106         ddc_data_regs_dcn2(3),
 107         ddc_data_regs_dcn2(4),
 108         ddc_data_regs_dcn2(5),
 109 };
 110 
 111 static const struct ddc_registers ddc_clk_regs_dcn[] = {
 112         ddc_clk_regs_dcn2(1),
 113         ddc_clk_regs_dcn2(2),
 114         ddc_clk_regs_dcn2(3),
 115         ddc_clk_regs_dcn2(4),
 116         ddc_clk_regs_dcn2(5),
 117 };
 118 
 119 static const struct ddc_sh_mask ddc_shift[] = {
 120         DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
 121         DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
 122         DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
 123         DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
 124         DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
 125         DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
 126 };
 127 
 128 static const struct ddc_sh_mask ddc_mask[] = {
 129         DDC_MASK_SH_LIST_DCN2(_MASK, 1),
 130         DDC_MASK_SH_LIST_DCN2(_MASK, 2),
 131         DDC_MASK_SH_LIST_DCN2(_MASK, 3),
 132         DDC_MASK_SH_LIST_DCN2(_MASK, 4),
 133         DDC_MASK_SH_LIST_DCN2(_MASK, 5),
 134         DDC_MASK_SH_LIST_DCN2(_MASK, 6)
 135 };
 136 
 137 #include "../generic_regs.h"
 138 
 139 /* set field name */
 140 #define SF_GENERIC(reg_name, field_name, post_fix)\
 141         .field_name = reg_name ## __ ## field_name ## post_fix
 142 
 143 #define generic_regs(id) \
 144 {\
 145         GENERIC_REG_LIST(id)\
 146 }
 147 
 148 static const struct generic_registers generic_regs[] = {
 149         generic_regs(A),
 150 };
 151 
 152 static const struct generic_sh_mask generic_shift[] = {
 153         GENERIC_MASK_SH_LIST(__SHIFT, A),
 154 };
 155 
 156 static const struct generic_sh_mask generic_mask[] = {
 157         GENERIC_MASK_SH_LIST(_MASK, A),
 158 };
 159 
 160 static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
 161 {
 162         struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
 163 
 164         generic->regs = &generic_regs[en];
 165         generic->shifts = &generic_shift[en];
 166         generic->masks = &generic_mask[en];
 167         generic->base.regs = &generic_regs[en].gpio;
 168 }
 169 
 170 static void define_ddc_registers(
 171                 struct hw_gpio_pin *pin,
 172                 uint32_t en)
 173 {
 174         struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
 175 
 176         switch (pin->id) {
 177         case GPIO_ID_DDC_DATA:
 178                 ddc->regs = &ddc_data_regs_dcn[en];
 179                 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
 180                 break;
 181         case GPIO_ID_DDC_CLOCK:
 182                 ddc->regs = &ddc_clk_regs_dcn[en];
 183                 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
 184                 break;
 185         default:
 186                 ASSERT_CRITICAL(false);
 187                 return;
 188         }
 189 
 190         ddc->shifts = &ddc_shift[en];
 191         ddc->masks = &ddc_mask[en];
 192 
 193 }
 194 
 195 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
 196 {
 197         struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
 198 
 199         hpd->regs = &hpd_regs[en];
 200         hpd->shifts = &hpd_shift;
 201         hpd->masks = &hpd_mask;
 202         hpd->base.regs = &hpd_regs[en].gpio;
 203 }
 204 
 205 
 206 /* fucntion table */
 207 static const struct hw_factory_funcs funcs = {
 208         .init_ddc_data = dal_hw_ddc_init,
 209         .init_generic = dal_hw_generic_init,
 210         .init_hpd = dal_hw_hpd_init,
 211         .get_ddc_pin = dal_hw_ddc_get_pin,
 212         .get_hpd_pin = dal_hw_hpd_get_pin,
 213         .get_generic_pin = dal_hw_generic_get_pin,
 214         .define_hpd_registers = define_hpd_registers,
 215         .define_ddc_registers = define_ddc_registers,
 216         .define_generic_registers = define_generic_registers
 217 };
 218 /*
 219  * dal_hw_factory_dcn10_init
 220  *
 221  * @brief
 222  * Initialize HW factory function pointers and pin info
 223  *
 224  * @param
 225  * struct hw_factory *factory - [out] struct of function pointers
 226  */
 227 void dal_hw_factory_dcn21_init(struct hw_factory *factory)
 228 {
 229         /*TODO check ASIC CAPs*/
 230         factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
 231         factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
 232         factory->number_of_pins[GPIO_ID_GENERIC] = 4;
 233         factory->number_of_pins[GPIO_ID_HPD] = 6;
 234         factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
 235         factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
 236         factory->number_of_pins[GPIO_ID_SYNC] = 0;
 237         factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
 238 
 239         factory->funcs = &funcs;
 240 }
 241 
 242 #endif
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root/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

DEFINITIONS
