root/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

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DEFINITIONS

This source file includes following definitions.
  1. offset_to_id
  2. id_to_offset
  3. dal_hw_translate_dcn21_init
   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 /*
  27  * Pre-requisites: headers required by header of this unit
  28  */
  29 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  30 #include "hw_translate_dcn21.h"
  31 
  32 #include "dm_services.h"
  33 #include "include/gpio_types.h"
  34 #include "../hw_translate.h"
  35 
  36 #include "dcn/dcn_2_1_0_offset.h"
  37 #include "dcn/dcn_2_1_0_sh_mask.h"
  38 #include "renoir_ip_offset.h"
  39 
  40 
  41 
  42 
  43 /* begin *********************
  44  * macros to expend register list macro defined in HW object header file */
  45 
  46 /* DCN */
  47 #define block HPD
  48 #define reg_num 0
  49 
  50 #undef BASE_INNER
  51 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
  52 
  53 #define BASE(seg) BASE_INNER(seg)
  54 
  55 #undef REG
  56 #define REG(reg_name)\
  57                 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
  58 #define SF_HPD(reg_name, field_name, post_fix)\
  59         .field_name = reg_name ## __ ## field_name ## post_fix
  60 
  61 /* macros to expend register list macro defined in HW object header file
  62  * end *********************/
  63 
  64 
  65 static bool offset_to_id(
  66         uint32_t offset,
  67         uint32_t mask,
  68         enum gpio_id *id,
  69         uint32_t *en)
  70 {
  71         switch (offset) {
  72         /* GENERIC */
  73         case REG(DC_GPIO_GENERIC_A):
  74                 *id = GPIO_ID_GENERIC;
  75                 switch (mask) {
  76                 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
  77                         *en = GPIO_GENERIC_A;
  78                         return true;
  79                 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
  80                         *en = GPIO_GENERIC_B;
  81                         return true;
  82                 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
  83                         *en = GPIO_GENERIC_C;
  84                         return true;
  85                 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
  86                         *en = GPIO_GENERIC_D;
  87                         return true;
  88                 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
  89                         *en = GPIO_GENERIC_E;
  90                         return true;
  91                 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
  92                         *en = GPIO_GENERIC_F;
  93                         return true;
  94                 case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
  95                         *en = GPIO_GENERIC_G;
  96                         return true;
  97                 default:
  98                         ASSERT_CRITICAL(false);
  99 #ifdef PALLADIUM_SUPPORTED
 100                 *en = GPIO_DDC_LINE_DDC1;
 101                 return true;
 102 #endif
 103                         return false;
 104                 }
 105         break;
 106         /* HPD */
 107         case REG(DC_GPIO_HPD_A):
 108                 *id = GPIO_ID_HPD;
 109                 switch (mask) {
 110                 case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
 111                         *en = GPIO_HPD_1;
 112                         return true;
 113                 case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
 114                         *en = GPIO_HPD_2;
 115                         return true;
 116                 case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
 117                         *en = GPIO_HPD_3;
 118                         return true;
 119                 case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
 120                         *en = GPIO_HPD_4;
 121                         return true;
 122                 case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
 123                         *en = GPIO_HPD_5;
 124                         return true;
 125                 case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
 126                         *en = GPIO_HPD_6;
 127                         return true;
 128                 default:
 129                         ASSERT_CRITICAL(false);
 130                         return false;
 131                 }
 132         break;
 133         /* REG(DC_GPIO_GENLK_MASK */
 134         case REG(DC_GPIO_GENLK_A):
 135                 *id = GPIO_ID_GSL;
 136                 switch (mask) {
 137                 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
 138                         *en = GPIO_GSL_GENLOCK_CLOCK;
 139                         return true;
 140                 case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
 141                         *en = GPIO_GSL_GENLOCK_VSYNC;
 142                         return true;
 143                 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
 144                         *en = GPIO_GSL_SWAPLOCK_A;
 145                         return true;
 146                 case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
 147                         *en = GPIO_GSL_SWAPLOCK_B;
 148                         return true;
 149                 default:
 150                         ASSERT_CRITICAL(false);
 151                         return false;
 152                 }
 153         break;
 154         /* DDC */
 155         /* we don't care about the GPIO_ID for DDC
 156          * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
 157          * directly in the create method */
 158         case REG(DC_GPIO_DDC1_A):
 159                 *en = GPIO_DDC_LINE_DDC1;
 160                 return true;
 161         case REG(DC_GPIO_DDC2_A):
 162                 *en = GPIO_DDC_LINE_DDC2;
 163                 return true;
 164         case REG(DC_GPIO_DDC3_A):
 165                 *en = GPIO_DDC_LINE_DDC3;
 166                 return true;
 167         case REG(DC_GPIO_DDC4_A):
 168                 *en = GPIO_DDC_LINE_DDC4;
 169                 return true;
 170         case REG(DC_GPIO_DDC5_A):
 171                 *en = GPIO_DDC_LINE_DDC5;
 172                 return true;
 173         case REG(DC_GPIO_DDCVGA_A):
 174                 *en = GPIO_DDC_LINE_DDC_VGA;
 175                 return true;
 176 
 177 //      case REG(DC_GPIO_I2CPAD_A): not exit
 178 //      case REG(DC_GPIO_PWRSEQ_A):
 179 //      case REG(DC_GPIO_PAD_STRENGTH_1):
 180 //      case REG(DC_GPIO_PAD_STRENGTH_2):
 181 //      case REG(DC_GPIO_DEBUG):
 182         /* UNEXPECTED */
 183         default:
 184 //      case REG(DC_GPIO_SYNCA_A): not exist
 185 #ifdef PALLADIUM_SUPPORTED
 186                 *id = GPIO_ID_HPD;
 187                 *en = GPIO_DDC_LINE_DDC1;
 188                 return true;
 189 #endif
 190                 ASSERT_CRITICAL(false);
 191                 return false;
 192         }
 193 }
 194 
 195 static bool id_to_offset(
 196         enum gpio_id id,
 197         uint32_t en,
 198         struct gpio_pin_info *info)
 199 {
 200         bool result = true;
 201 
 202         switch (id) {
 203         case GPIO_ID_DDC_DATA:
 204                 info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK;
 205                 switch (en) {
 206                 case GPIO_DDC_LINE_DDC1:
 207                         info->offset = REG(DC_GPIO_DDC1_A);
 208                 break;
 209                 case GPIO_DDC_LINE_DDC2:
 210                         info->offset = REG(DC_GPIO_DDC2_A);
 211                 break;
 212                 case GPIO_DDC_LINE_DDC3:
 213                         info->offset = REG(DC_GPIO_DDC3_A);
 214                 break;
 215                 case GPIO_DDC_LINE_DDC4:
 216                         info->offset = REG(DC_GPIO_DDC4_A);
 217                 break;
 218                 case GPIO_DDC_LINE_DDC5:
 219                         info->offset = REG(DC_GPIO_DDC5_A);
 220                 break;
 221                 case GPIO_DDC_LINE_DDC_VGA:
 222                         info->offset = REG(DC_GPIO_DDCVGA_A);
 223                 break;
 224                 case GPIO_DDC_LINE_I2C_PAD:
 225                 default:
 226                         ASSERT_CRITICAL(false);
 227                         result = false;
 228                 }
 229         break;
 230         case GPIO_ID_DDC_CLOCK:
 231                 info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK;
 232                 switch (en) {
 233                 case GPIO_DDC_LINE_DDC1:
 234                         info->offset = REG(DC_GPIO_DDC1_A);
 235                 break;
 236                 case GPIO_DDC_LINE_DDC2:
 237                         info->offset = REG(DC_GPIO_DDC2_A);
 238                 break;
 239                 case GPIO_DDC_LINE_DDC3:
 240                         info->offset = REG(DC_GPIO_DDC3_A);
 241                 break;
 242                 case GPIO_DDC_LINE_DDC4:
 243                         info->offset = REG(DC_GPIO_DDC4_A);
 244                 break;
 245                 case GPIO_DDC_LINE_DDC5:
 246                         info->offset = REG(DC_GPIO_DDC5_A);
 247                 break;
 248                 case GPIO_DDC_LINE_DDC_VGA:
 249                         info->offset = REG(DC_GPIO_DDCVGA_A);
 250                 break;
 251                 case GPIO_DDC_LINE_I2C_PAD:
 252                 default:
 253                         ASSERT_CRITICAL(false);
 254                         result = false;
 255                 }
 256         break;
 257         case GPIO_ID_GENERIC:
 258                 info->offset = REG(DC_GPIO_GENERIC_A);
 259                 switch (en) {
 260                 case GPIO_GENERIC_A:
 261                         info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
 262                 break;
 263                 case GPIO_GENERIC_B:
 264                         info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
 265                 break;
 266                 case GPIO_GENERIC_C:
 267                         info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
 268                 break;
 269                 case GPIO_GENERIC_D:
 270                         info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
 271                 break;
 272                 case GPIO_GENERIC_E:
 273                         info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
 274                 break;
 275                 case GPIO_GENERIC_F:
 276                         info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
 277                 break;
 278                 case GPIO_GENERIC_G:
 279                         info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
 280                 break;
 281                 default:
 282                         ASSERT_CRITICAL(false);
 283                         result = false;
 284                 }
 285         break;
 286         case GPIO_ID_HPD:
 287                 info->offset = REG(DC_GPIO_HPD_A);
 288                 switch (en) {
 289                 case GPIO_HPD_1:
 290                         info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
 291                 break;
 292                 case GPIO_HPD_2:
 293                         info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
 294                 break;
 295                 case GPIO_HPD_3:
 296                         info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
 297                 break;
 298                 case GPIO_HPD_4:
 299                         info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
 300                 break;
 301                 case GPIO_HPD_5:
 302                         info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
 303                 break;
 304                 case GPIO_HPD_6:
 305                         info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
 306                 break;
 307                 default:
 308                         ASSERT_CRITICAL(false);
 309 #ifdef PALLADIUM_SUPPORTED
 310                         info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
 311                         result = true;
 312 #endif
 313                         result = false;
 314                 }
 315         break;
 316         case GPIO_ID_GSL:
 317                 switch (en) {
 318                 case GPIO_GSL_GENLOCK_CLOCK:
 319                                 /*not implmented*/
 320                         ASSERT_CRITICAL(false);
 321                         result = false;
 322                 break;
 323                 case GPIO_GSL_GENLOCK_VSYNC:
 324                         /*not implmented*/
 325                         ASSERT_CRITICAL(false);
 326                         result = false;
 327                 break;
 328                 case GPIO_GSL_SWAPLOCK_A:
 329                         /*not implmented*/
 330                         ASSERT_CRITICAL(false);
 331                         result = false;
 332                 break;
 333                 case GPIO_GSL_SWAPLOCK_B:
 334                         /*not implmented*/
 335                         ASSERT_CRITICAL(false);
 336                         result = false;
 337 
 338                 break;
 339                 default:
 340                         ASSERT_CRITICAL(false);
 341                         result = false;
 342                 }
 343         break;
 344         case GPIO_ID_SYNC:
 345         case GPIO_ID_VIP_PAD:
 346         default:
 347                 ASSERT_CRITICAL(false);
 348                 result = false;
 349         }
 350 
 351         if (result) {
 352                 info->offset_y = info->offset + 2;
 353                 info->offset_en = info->offset + 1;
 354                 info->offset_mask = info->offset - 1;
 355 
 356                 info->mask_y = info->mask;
 357                 info->mask_en = info->mask;
 358                 info->mask_mask = info->mask;
 359         }
 360 
 361         return result;
 362 }
 363 
 364 /* function table */
 365 static const struct hw_translate_funcs funcs = {
 366         .offset_to_id = offset_to_id,
 367         .id_to_offset = id_to_offset,
 368 };
 369 
 370 /*
 371  * dal_hw_translate_dcn10_init
 372  *
 373  * @brief
 374  * Initialize Hw translate function pointers.
 375  *
 376  * @param
 377  * struct hw_translate *tr - [out] struct of function pointers
 378  *
 379  */
 380 void dal_hw_translate_dcn21_init(struct hw_translate *tr)
 381 {
 382         tr->funcs = &funcs;
 383 }
 384 
 385 #endif
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