drivers/gpu/drm/amd/display/dc/gpio/hw

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This source file includes following definitions.
destruct
destroy
set_config
construct
dal_hw_ddc_init
dal_hw_ddc_get_pin
   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 
  29 #include "dm_services.h"
  30 
  31 #include "include/gpio_interface.h"
  32 #include "include/gpio_types.h"
  33 #include "hw_gpio.h"
  34 #include "hw_ddc.h"
  35 
  36 #include "reg_helper.h"
  37 #include "gpio_regs.h"
  38 
  39 
  40 #undef FN
  41 #define FN(reg_name, field_name) \
  42         ddc->shifts->field_name, ddc->masks->field_name
  43 
  44 #define CTX \
  45         ddc->base.base.ctx
  46 #define REG(reg)\
  47         (ddc->regs->reg)
  48 
  49 struct gpio;
  50 
  51 static void destruct(
  52         struct hw_ddc *pin)
  53 {
  54         dal_hw_gpio_destruct(&pin->base);
  55 }
  56 
  57 static void destroy(
  58         struct hw_gpio_pin **ptr)
  59 {
  60         struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr);
  61 
  62         destruct(pin);
  63 
  64         kfree(pin);
  65 
  66         *ptr = NULL;
  67 }
  68 
  69 static enum gpio_result set_config(
  70         struct hw_gpio_pin *ptr,
  71         const struct gpio_config_data *config_data)
  72 {
  73         struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr);
  74         struct hw_gpio *hw_gpio = NULL;
  75         uint32_t regval;
  76         uint32_t ddc_data_pd_en = 0;
  77         uint32_t ddc_clk_pd_en = 0;
  78         uint32_t aux_pad_mode = 0;
  79 
  80         hw_gpio = &ddc->base;
  81 
  82         if (hw_gpio == NULL) {
  83                 ASSERT_CRITICAL(false);
  84                 return GPIO_RESULT_NULL_HANDLE;
  85         }
  86 
  87         regval = REG_GET_3(gpio.MASK_reg,
  88                         DC_GPIO_DDC1DATA_PD_EN, &ddc_data_pd_en,
  89                         DC_GPIO_DDC1CLK_PD_EN, &ddc_clk_pd_en,
  90                         AUX_PAD1_MODE, &aux_pad_mode);
  91 
  92         switch (config_data->config.ddc.type) {
  93         case GPIO_DDC_CONFIG_TYPE_MODE_I2C:
  94                 /* On plug-in, there is a transient level on the pad
  95                  * which must be discharged through the internal pull-down.
  96                  * Enable internal pull-down, 2.5msec discharge time
  97                  * is required for detection of AUX mode */
  98                 if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {
  99                         if (!ddc_data_pd_en || !ddc_clk_pd_en) {
 100 
 101                                 REG_SET_2(gpio.MASK_reg, regval,
 102                                                 DC_GPIO_DDC1DATA_PD_EN, 1,
 103                                                 DC_GPIO_DDC1CLK_PD_EN, 1);
 104 
 105                                 if (config_data->type ==
 106                                                 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
 107                                         msleep(3);
 108                         }
 109                 } else {
 110                         uint32_t reg2;
 111                         uint32_t sda_pd_dis = 0;
 112                         uint32_t scl_pd_dis = 0;
 113 
 114                         reg2 = REG_GET_2(gpio.MASK_reg,
 115                                         DC_GPIO_SDA_PD_DIS, &sda_pd_dis,
 116                                         DC_GPIO_SCL_PD_DIS, &scl_pd_dis);
 117 
 118                         if (sda_pd_dis) {
 119                                 REG_SET(gpio.MASK_reg, regval,
 120                                                 DC_GPIO_SDA_PD_DIS, 0);
 121 
 122                                 if (config_data->type ==
 123                                                 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
 124                                         msleep(3);
 125                         }
 126 
 127                         if (!scl_pd_dis) {
 128                                 REG_SET(gpio.MASK_reg, regval,
 129                                                 DC_GPIO_SCL_PD_DIS, 1);
 130 
 131                                 if (config_data->type ==
 132                                                 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
 133                                         msleep(3);
 134                         }
 135                 }
 136 
 137                 if (aux_pad_mode) {
 138                         /* let pins to get de-asserted
 139                          * before setting pad to I2C mode */
 140                         if (config_data->config.ddc.data_en_bit_present ||
 141                                 config_data->config.ddc.clock_en_bit_present)
 142                                 /* [anaumov] in DAL2, there was
 143                                  * dc_service_delay_in_microseconds(2000); */
 144                                 msleep(2);
 145 
 146                         /* set the I2C pad mode */
 147                         /* read the register again,
 148                          * some bits may have been changed */
 149                         REG_UPDATE(gpio.MASK_reg,
 150                                         AUX_PAD1_MODE, 0);
 151                 }
 152 
 153 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 154                 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {
 155                                 REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1);
 156                 }
 157                 //set  DC_IO_aux_rxsel = 2'b01
 158                 if (ddc->regs->phy_aux_cntl != 0) {
 159                                 REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1);
 160                 }
 161 #endif
 162                 return GPIO_RESULT_OK;
 163         case GPIO_DDC_CONFIG_TYPE_MODE_AUX:
 164                 /* set the AUX pad mode */
 165                 if (!aux_pad_mode) {
 166                         REG_SET(gpio.MASK_reg, regval,
 167                                         AUX_PAD1_MODE, 1);
 168                 }
 169 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 170                 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {
 171                         REG_UPDATE(dc_gpio_aux_ctrl_5,
 172                                         DDC_PAD_I2CMODE, 0);
 173                 }
 174 #endif
 175 
 176                 return GPIO_RESULT_OK;
 177         case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
 178                 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
 179                         (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
 180                         REG_UPDATE_3(ddc_setup,
 181                                 DC_I2C_DDC1_ENABLE, 1,
 182                                 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
 183                                 DC_I2C_DDC1_EDID_DETECT_MODE, 0);
 184                         return GPIO_RESULT_OK;
 185                 }
 186         break;
 187         case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT:
 188                 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
 189                         (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
 190                         REG_UPDATE_3(ddc_setup,
 191                                 DC_I2C_DDC1_ENABLE, 1,
 192                                 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
 193                                 DC_I2C_DDC1_EDID_DETECT_MODE, 1);
 194                         return GPIO_RESULT_OK;
 195                 }
 196         break;
 197         case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING:
 198                 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
 199                         (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
 200                         REG_UPDATE_2(ddc_setup,
 201                                 DC_I2C_DDC1_ENABLE, 0,
 202                                 DC_I2C_DDC1_EDID_DETECT_ENABLE, 0);
 203                         return GPIO_RESULT_OK;
 204                 }
 205         break;
 206         }
 207 
 208         BREAK_TO_DEBUGGER();
 209 
 210         return GPIO_RESULT_NON_SPECIFIC_ERROR;
 211 }
 212 
 213 static const struct hw_gpio_pin_funcs funcs = {
 214         .destroy = destroy,
 215         .open = dal_hw_gpio_open,
 216         .get_value = dal_hw_gpio_get_value,
 217         .set_value = dal_hw_gpio_set_value,
 218         .set_config = set_config,
 219         .change_mode = dal_hw_gpio_change_mode,
 220         .close = dal_hw_gpio_close,
 221 };
 222 
 223 static void construct(
 224         struct hw_ddc *ddc,
 225         enum gpio_id id,
 226         uint32_t en,
 227         struct dc_context *ctx)
 228 {
 229         dal_hw_gpio_construct(&ddc->base, id, en, ctx);
 230         ddc->base.base.funcs = &funcs;
 231 }
 232 
 233 void dal_hw_ddc_init(
 234         struct hw_ddc **hw_ddc,
 235         struct dc_context *ctx,
 236         enum gpio_id id,
 237         uint32_t en)
 238 {
 239         if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
 240                 ASSERT_CRITICAL(false);
 241                 *hw_ddc = NULL;
 242         }
 243 
 244         *hw_ddc = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL);
 245         if (!*hw_ddc) {
 246                 ASSERT_CRITICAL(false);
 247                 return;
 248         }
 249 
 250         construct(*hw_ddc, id, en, ctx);
 251 }
 252 
 253 struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio)
 254 {
 255         struct hw_ddc *hw_ddc = dal_gpio_get_ddc(gpio);
 256 
 257         return &hw_ddc->base.base;
 258 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

DEFINITIONS
