drivers/gpu/drm/amd/display/dc/core/dc

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This source file includes following definitions.
destruct
get_hpd_gpio
program_hpd_filter
dc_link_detect_sink
get_ddc_transaction_type
get_basic_signal_type
dc_link_is_dp_sink_present
link_detect_sink
decide_signal_from_strap_and_dongle_type
dp_passive_dongle_detection
link_disconnect_sink
link_disconnect_remap
read_edp_current_link_settings_on_detect
detect_dp
is_same_edid
wait_for_alt_mode
dc_link_detect
dc_link_get_hpd_state
get_hpd_line
get_ddc_line
translate_encoder_to_transmitter
construct
link_create
link_destroy
enable_stream_features
enable_link_dp
enable_link_edp
enable_link_dp_mst
get_ext_hdmi_settings
i2c_write
write_i2c_retimer_setting
write_i2c_default_retimer_setting
write_i2c_redriver_setting
enable_link_hdmi
enable_link_lvds
enable_link
disable_link
get_timing_pixel_clock_100hz
dp_active_dongle_validate_timing
dc_link_validate_mode_timing
dc_link_get_backlight_level
dc_link_set_backlight_level
dc_link_set_abm_disable
dc_link_set_psr_enable
dc_link_get_status
core_link_resume
get_pbn_per_slot
get_color_depth
get_pbn_from_timing
update_mst_stream_alloc_table
allocate_mst_payload
deallocate_mst_payload
core_link_enable_stream
core_link_disable_stream
core_link_set_avmute
dc_link_enable_hpd_filter
dc_bandwidth_in_kbps_from_timing
dc_link_set_drive_settings
dc_link_perform_link_training
dc_link_set_preferred_link_settings
dc_link_set_preferred_training_settings
dc_link_enable_hpd
dc_link_disable_hpd
dc_link_set_test_pattern
dc_link_bandwidth_kbps
dc_link_get_link_cap
   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include <linux/slab.h>
  27 
  28 #include "dm_services.h"
  29 #include "atom.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39 
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 
  49 #define DC_LOGGER_INIT(logger)
  50 
  51 
  52 #define LINK_INFO(...) \
  53         DC_LOG_HW_HOTPLUG(  \
  54                 __VA_ARGS__)
  55 
  56 #define RETIMER_REDRIVER_INFO(...) \
  57         DC_LOG_RETIMER_REDRIVER(  \
  58                 __VA_ARGS__)
  59 /*******************************************************************************
  60  * Private structures
  61  ******************************************************************************/
  62 
  63 enum {
  64         PEAK_FACTOR_X1000 = 1006,
  65         /*
  66         * Some receivers fail to train on first try and are good
  67         * on subsequent tries. 2 retries should be plenty. If we
  68         * don't have a successful training then we don't expect to
  69         * ever get one.
  70         */
  71         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  72 };
  73 
  74 /*******************************************************************************
  75  * Private functions
  76  ******************************************************************************/
  77 static void destruct(struct dc_link *link)
  78 {
  79         int i;
  80 
  81         if (link->hpd_gpio != NULL) {
  82                 dal_gpio_close(link->hpd_gpio);
  83                 dal_gpio_destroy_irq(&link->hpd_gpio);
  84                 link->hpd_gpio = NULL;
  85         }
  86 
  87         if (link->ddc)
  88                 dal_ddc_service_destroy(&link->ddc);
  89 
  90         if(link->link_enc)
  91                 link->link_enc->funcs->destroy(&link->link_enc);
  92 
  93         if (link->local_sink)
  94                 dc_sink_release(link->local_sink);
  95 
  96         for (i = 0; i < link->sink_count; ++i)
  97                 dc_sink_release(link->remote_sinks[i]);
  98 }
  99 
 100 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 101                 struct graphics_object_id link_id,
 102                 struct gpio_service *gpio_service)
 103 {
 104         enum bp_result bp_result;
 105         struct graphics_object_hpd_info hpd_info;
 106         struct gpio_pin_info pin_info;
 107 
 108         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 109                 return NULL;
 110 
 111         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 112                 hpd_info.hpd_int_gpio_uid, &pin_info);
 113 
 114         if (bp_result != BP_RESULT_OK) {
 115                 ASSERT(bp_result == BP_RESULT_NORECORD);
 116                 return NULL;
 117         }
 118 
 119         return dal_gpio_service_create_irq(
 120                 gpio_service,
 121                 pin_info.offset,
 122                 pin_info.mask);
 123 }
 124 
 125 /*
 126  *  Function: program_hpd_filter
 127  *
 128  *  @brief
 129  *     Programs HPD filter on associated HPD line
 130  *
 131  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 132  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 133  *
 134  *  @return
 135  *     true on success, false otherwise
 136  */
 137 static bool program_hpd_filter(
 138         const struct dc_link *link)
 139 {
 140         bool result = false;
 141 
 142         struct gpio *hpd;
 143 
 144         int delay_on_connect_in_ms = 0;
 145         int delay_on_disconnect_in_ms = 0;
 146 
 147         if (link->is_hpd_filter_disabled)
 148                 return false;
 149         /* Verify feature is supported */
 150         switch (link->connector_signal) {
 151         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 152         case SIGNAL_TYPE_DVI_DUAL_LINK:
 153         case SIGNAL_TYPE_HDMI_TYPE_A:
 154                 /* Program hpd filter */
 155                 delay_on_connect_in_ms = 500;
 156                 delay_on_disconnect_in_ms = 100;
 157                 break;
 158         case SIGNAL_TYPE_DISPLAY_PORT:
 159         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 160                 /* Program hpd filter to allow DP signal to settle */
 161                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 162                  *      only 100ms on DELL U2413
 163                  * 0:   some passive dongle still show aux mode instead of i2c
 164                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 165                  *      also see intermittent i2c read issues.
 166                  */
 167                 delay_on_connect_in_ms = 80;
 168                 delay_on_disconnect_in_ms = 0;
 169                 break;
 170         case SIGNAL_TYPE_LVDS:
 171         case SIGNAL_TYPE_EDP:
 172         default:
 173                 /* Don't program hpd filter */
 174                 return false;
 175         }
 176 
 177         /* Obtain HPD handle */
 178         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 179 
 180         if (!hpd)
 181                 return result;
 182 
 183         /* Setup HPD filtering */
 184         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 185                 struct gpio_hpd_config config;
 186 
 187                 config.delay_on_connect = delay_on_connect_in_ms;
 188                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 189 
 190                 dal_irq_setup_hpd_filter(hpd, &config);
 191 
 192                 dal_gpio_close(hpd);
 193 
 194                 result = true;
 195         } else {
 196                 ASSERT_CRITICAL(false);
 197         }
 198 
 199         /* Release HPD handle */
 200         dal_gpio_destroy_irq(&hpd);
 201 
 202         return result;
 203 }
 204 
 205 /**
 206  * dc_link_detect_sink() - Determine if there is a sink connected
 207  *
 208  * @type: Returned connection type
 209  * Does not detect downstream devices, such as MST sinks
 210  * or display connected through active dongles
 211  */
 212 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 213 {
 214         uint32_t is_hpd_high = 0;
 215         struct gpio *hpd_pin;
 216 
 217         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 218                 *type = dc_connection_single;
 219                 return true;
 220         }
 221 
 222         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 223                 /*in case it is not on*/
 224                 link->dc->hwss.edp_power_control(link, true);
 225                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 226         }
 227 
 228         /* todo: may need to lock gpio access */
 229         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 230         if (hpd_pin == NULL)
 231                 goto hpd_gpio_failure;
 232 
 233         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 234         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 235         dal_gpio_close(hpd_pin);
 236         dal_gpio_destroy_irq(&hpd_pin);
 237 
 238         if (is_hpd_high) {
 239                 *type = dc_connection_single;
 240                 /* TODO: need to do the actual detection */
 241         } else {
 242                 *type = dc_connection_none;
 243         }
 244 
 245         return true;
 246 
 247 hpd_gpio_failure:
 248         return false;
 249 }
 250 
 251 static enum ddc_transaction_type get_ddc_transaction_type(
 252                 enum signal_type sink_signal)
 253 {
 254         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 255 
 256         switch (sink_signal) {
 257         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 258         case SIGNAL_TYPE_DVI_DUAL_LINK:
 259         case SIGNAL_TYPE_HDMI_TYPE_A:
 260         case SIGNAL_TYPE_LVDS:
 261         case SIGNAL_TYPE_RGB:
 262                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 263                 break;
 264 
 265         case SIGNAL_TYPE_DISPLAY_PORT:
 266         case SIGNAL_TYPE_EDP:
 267                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 268                 break;
 269 
 270         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 271                 /* MST does not use I2COverAux, but there is the
 272                  * SPECIAL use case for "immediate dwnstrm device
 273                  * access" (EPR#370830). */
 274                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 275                 break;
 276 
 277         default:
 278                 break;
 279         }
 280 
 281         return transaction_type;
 282 }
 283 
 284 static enum signal_type get_basic_signal_type(
 285         struct graphics_object_id encoder,
 286         struct graphics_object_id downstream)
 287 {
 288         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 289                 switch (downstream.id) {
 290                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 291                         switch (encoder.id) {
 292                         case ENCODER_ID_INTERNAL_DAC1:
 293                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 294                         case ENCODER_ID_INTERNAL_DAC2:
 295                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 296                                 return SIGNAL_TYPE_RGB;
 297                         default:
 298                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 299                         }
 300                 break;
 301                 case CONNECTOR_ID_DUAL_LINK_DVII:
 302                 {
 303                         switch (encoder.id) {
 304                         case ENCODER_ID_INTERNAL_DAC1:
 305                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 306                         case ENCODER_ID_INTERNAL_DAC2:
 307                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 308                                 return SIGNAL_TYPE_RGB;
 309                         default:
 310                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 311                         }
 312                 }
 313                 break;
 314                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 315                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 316                 case CONNECTOR_ID_DUAL_LINK_DVID:
 317                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 318                 case CONNECTOR_ID_VGA:
 319                         return SIGNAL_TYPE_RGB;
 320                 case CONNECTOR_ID_HDMI_TYPE_A:
 321                         return SIGNAL_TYPE_HDMI_TYPE_A;
 322                 case CONNECTOR_ID_LVDS:
 323                         return SIGNAL_TYPE_LVDS;
 324                 case CONNECTOR_ID_DISPLAY_PORT:
 325                         return SIGNAL_TYPE_DISPLAY_PORT;
 326                 case CONNECTOR_ID_EDP:
 327                         return SIGNAL_TYPE_EDP;
 328                 default:
 329                         return SIGNAL_TYPE_NONE;
 330                 }
 331         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 332                 switch (downstream.id) {
 333                 case ENCODER_ID_EXTERNAL_NUTMEG:
 334                 case ENCODER_ID_EXTERNAL_TRAVIS:
 335                         return SIGNAL_TYPE_DISPLAY_PORT;
 336                 default:
 337                         return SIGNAL_TYPE_NONE;
 338                 }
 339         }
 340 
 341         return SIGNAL_TYPE_NONE;
 342 }
 343 
 344 /**
 345  * dc_link_is_dp_sink_present() - Check if there is a native DP
 346  * or passive DP-HDMI dongle connected
 347  */
 348 bool dc_link_is_dp_sink_present(struct dc_link *link)
 349 {
 350         enum gpio_result gpio_result;
 351         uint32_t clock_pin = 0;
 352         uint8_t retry = 0;
 353         struct ddc *ddc;
 354 
 355         enum connector_id connector_id =
 356                 dal_graphics_object_id_get_connector_id(link->link_id);
 357 
 358         bool present =
 359                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 360                 (connector_id == CONNECTOR_ID_EDP));
 361 
 362         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 363 
 364         if (!ddc) {
 365                 BREAK_TO_DEBUGGER();
 366                 return present;
 367         }
 368 
 369         /* Open GPIO and set it to I2C mode */
 370         /* Note: this GpioMode_Input will be converted
 371          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 372          * which indicates we need additional delay */
 373 
 374         if (GPIO_RESULT_OK != dal_ddc_open(
 375                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 376                 dal_ddc_close(ddc);
 377 
 378                 return present;
 379         }
 380 
 381         /*
 382          * Read GPIO: DP sink is present if both clock and data pins are zero
 383          *
 384          * [W/A] plug-unplug DP cable, sometimes customer board has
 385          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 386          * then monitor can't br light up. Add retry 3 times
 387          * But in real passive dongle, it need additional 3ms to detect
 388          */
 389         do {
 390                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 391                 ASSERT(gpio_result == GPIO_RESULT_OK);
 392                 if (clock_pin)
 393                         udelay(1000);
 394                 else
 395                         break;
 396         } while (retry++ < 3);
 397 
 398         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 399 
 400         dal_ddc_close(ddc);
 401 
 402         return present;
 403 }
 404 
 405 /*
 406  * @brief
 407  * Detect output sink type
 408  */
 409 static enum signal_type link_detect_sink(
 410         struct dc_link *link,
 411         enum dc_detect_reason reason)
 412 {
 413         enum signal_type result = get_basic_signal_type(
 414                 link->link_enc->id, link->link_id);
 415 
 416         /* Internal digital encoder will detect only dongles
 417          * that require digital signal */
 418 
 419         /* Detection mechanism is different
 420          * for different native connectors.
 421          * LVDS connector supports only LVDS signal;
 422          * PCIE is a bus slot, the actual connector needs to be detected first;
 423          * eDP connector supports only eDP signal;
 424          * HDMI should check straps for audio */
 425 
 426         /* PCIE detects the actual connector on add-on board */
 427 
 428         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 429                 /* ZAZTODO implement PCIE add-on card detection */
 430         }
 431 
 432         switch (link->link_id.id) {
 433         case CONNECTOR_ID_HDMI_TYPE_A: {
 434                 /* check audio support:
 435                  * if native HDMI is not supported, switch to DVI */
 436                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 437 
 438                 if (!aud_support->hdmi_audio_native)
 439                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 440                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 441         }
 442         break;
 443         case CONNECTOR_ID_DISPLAY_PORT: {
 444                 /* DP HPD short pulse. Passive DP dongle will not
 445                  * have short pulse
 446                  */
 447                 if (reason != DETECT_REASON_HPDRX) {
 448                         /* Check whether DP signal detected: if not -
 449                          * we assume signal is DVI; it could be corrected
 450                          * to HDMI after dongle detection
 451                          */
 452                         if (!dm_helpers_is_dp_sink_present(link))
 453                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 454                 }
 455         }
 456         break;
 457         default:
 458         break;
 459         }
 460 
 461         return result;
 462 }
 463 
 464 static enum signal_type decide_signal_from_strap_and_dongle_type(
 465                 enum display_dongle_type dongle_type,
 466                 struct audio_support *audio_support)
 467 {
 468         enum signal_type signal = SIGNAL_TYPE_NONE;
 469 
 470         switch (dongle_type) {
 471         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 472                 if (audio_support->hdmi_audio_on_dongle)
 473                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 474                 else
 475                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 476                 break;
 477         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 478                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 479                 break;
 480         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 481                 if (audio_support->hdmi_audio_native)
 482                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 483                 else
 484                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 485                 break;
 486         default:
 487                 signal = SIGNAL_TYPE_NONE;
 488                 break;
 489         }
 490 
 491         return signal;
 492 }
 493 
 494 static enum signal_type dp_passive_dongle_detection(
 495                 struct ddc_service *ddc,
 496                 struct display_sink_capability *sink_cap,
 497                 struct audio_support *audio_support)
 498 {
 499         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 500                                                 ddc, sink_cap);
 501         return decide_signal_from_strap_and_dongle_type(
 502                         sink_cap->dongle_type,
 503                         audio_support);
 504 }
 505 
 506 static void link_disconnect_sink(struct dc_link *link)
 507 {
 508         if (link->local_sink) {
 509                 dc_sink_release(link->local_sink);
 510                 link->local_sink = NULL;
 511         }
 512 
 513         link->dpcd_sink_count = 0;
 514 }
 515 
 516 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 517 {
 518         dc_sink_release(link->local_sink);
 519         link->local_sink = prev_sink;
 520 }
 521 
 522 
 523 static void read_edp_current_link_settings_on_detect(struct dc_link *link)
 524 {
 525         union lane_count_set lane_count_set = { {0} };
 526         uint8_t link_bw_set;
 527         uint8_t link_rate_set;
 528         uint32_t read_dpcd_retry_cnt = 10;
 529         enum dc_status status = DC_ERROR_UNEXPECTED;
 530         int i;
 531         union max_down_spread max_down_spread = { {0} };
 532 
 533         // Read DPCD 00101h to find out the number of lanes currently set
 534         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 535                 status = core_link_read_dpcd(
 536                                 link,
 537                                 DP_LANE_COUNT_SET,
 538                                 &lane_count_set.raw,
 539                                 sizeof(lane_count_set));
 540                 /* First DPCD read after VDD ON can fail if the particular board
 541                  * does not have HPD pin wired correctly. So if DPCD read fails,
 542                  * which it should never happen, retry a few times. Target worst
 543                  * case scenario of 80 ms.
 544                  */
 545                 if (status == DC_OK) {
 546                         link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET;
 547                         break;
 548                 }
 549 
 550                 msleep(8);
 551         }
 552 
 553         // Read DPCD 00100h to find if standard link rates are set
 554         core_link_read_dpcd(link, DP_LINK_BW_SET,
 555                         &link_bw_set, sizeof(link_bw_set));
 556 
 557         if (link_bw_set == 0) {
 558                 /* If standard link rates are not being used,
 559                  * Read DPCD 00115h to find the link rate set used
 560                  */
 561                 core_link_read_dpcd(link, DP_LINK_RATE_SET,
 562                                 &link_rate_set, sizeof(link_rate_set));
 563 
 564                 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 565                         link->cur_link_settings.link_rate =
 566                                 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 567                         link->cur_link_settings.link_rate_set = link_rate_set;
 568                         link->cur_link_settings.use_link_rate_set = true;
 569                 }
 570         } else {
 571                 link->cur_link_settings.link_rate = link_bw_set;
 572                 link->cur_link_settings.use_link_rate_set = false;
 573         }
 574         // Read DPCD 00003h to find the max down spread.
 575         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 576                         &max_down_spread.raw, sizeof(max_down_spread));
 577         link->cur_link_settings.link_spread =
 578                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 579                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 580 }
 581 
 582 static bool detect_dp(
 583         struct dc_link *link,
 584         struct display_sink_capability *sink_caps,
 585         bool *converter_disable_audio,
 586         struct audio_support *audio_support,
 587         enum dc_detect_reason reason)
 588 {
 589         bool boot = false;
 590         sink_caps->signal = link_detect_sink(link, reason);
 591         sink_caps->transaction_type =
 592                 get_ddc_transaction_type(sink_caps->signal);
 593 
 594         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 595                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 596                 if (!detect_dp_sink_caps(link))
 597                         return false;
 598 
 599                 if (is_mst_supported(link)) {
 600                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 601                         link->type = dc_connection_mst_branch;
 602 
 603                         dal_ddc_service_set_transaction_type(
 604                                                         link->ddc,
 605                                                         sink_caps->transaction_type);
 606 
 607                         /*
 608                          * This call will initiate MST topology discovery. Which
 609                          * will detect MST ports and add new DRM connector DRM
 610                          * framework. Then read EDID via remote i2c over aux. In
 611                          * the end, will notify DRM detect result and save EDID
 612                          * into DRM framework.
 613                          *
 614                          * .detect is called by .fill_modes.
 615                          * .fill_modes is called by user mode ioctl
 616                          * DRM_IOCTL_MODE_GETCONNECTOR.
 617                          *
 618                          * .get_modes is called by .fill_modes.
 619                          *
 620                          * call .get_modes, AMDGPU DM implementation will create
 621                          * new dc_sink and add to dc_link. For long HPD plug
 622                          * in/out, MST has its own handle.
 623                          *
 624                          * Therefore, just after dc_create, link->sink is not
 625                          * created for MST until user mode app calls
 626                          * DRM_IOCTL_MODE_GETCONNECTOR.
 627                          *
 628                          * Need check ->sink usages in case ->sink = NULL
 629                          * TODO: s3 resume check
 630                          */
 631                         if (reason == DETECT_REASON_BOOT)
 632                                 boot = true;
 633 
 634                         dm_helpers_dp_update_branch_info(
 635                                 link->ctx,
 636                                 link);
 637 
 638                         if (!dm_helpers_dp_mst_start_top_mgr(
 639                                 link->ctx,
 640                                 link, boot)) {
 641                                 /* MST not supported */
 642                                 link->type = dc_connection_single;
 643                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 644                         }
 645                 }
 646 
 647                 if (link->type != dc_connection_mst_branch &&
 648                         is_dp_active_dongle(link)) {
 649                         /* DP active dongles */
 650                         link->type = dc_connection_active_dongle;
 651                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 652                                 /*
 653                                  * active dongle unplug processing for short irq
 654                                  */
 655                                 link_disconnect_sink(link);
 656                                 return true;
 657                         }
 658 
 659                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 660                                 *converter_disable_audio = true;
 661                 }
 662         } else {
 663                 /* DP passive dongles */
 664                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 665                                 sink_caps,
 666                                 audio_support);
 667         }
 668 
 669         return true;
 670 }
 671 
 672 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 673 {
 674         if (old_edid->length != new_edid->length)
 675                 return false;
 676 
 677         if (new_edid->length == 0)
 678                 return false;
 679 
 680         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 681 }
 682 
 683 bool wait_for_alt_mode(struct dc_link *link)
 684 {
 685 
 686         /**
 687          * something is terribly wrong if time out is > 200ms. (5Hz)
 688          * 500 microseconds * 400 tries us 200 ms
 689          **/
 690         unsigned int sleep_time_in_microseconds = 500;
 691         unsigned int tries_allowed = 400;
 692         bool is_in_alt_mode;
 693         unsigned long long enter_timestamp;
 694         unsigned long long finish_timestamp;
 695         unsigned long long time_taken_in_ns;
 696         int tries_taken;
 697 
 698         DC_LOGGER_INIT(link->ctx->logger);
 699 
 700         if (link->link_enc->funcs->is_in_alt_mode == NULL)
 701                 return true;
 702 
 703         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 704         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 705 
 706         if (is_in_alt_mode)
 707                 return true;
 708 
 709         enter_timestamp = dm_get_timestamp(link->ctx);
 710 
 711         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 712                 udelay(sleep_time_in_microseconds);
 713                 /* ask the link if alt mode is enabled, if so return ok */
 714                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 715 
 716                         finish_timestamp = dm_get_timestamp(link->ctx);
 717                         time_taken_in_ns = dm_get_elapse_time_in_ns(
 718                                 link->ctx, finish_timestamp, enter_timestamp);
 719                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 720                                        div_u64(time_taken_in_ns, 1000000));
 721                         return true;
 722                 }
 723 
 724         }
 725         finish_timestamp = dm_get_timestamp(link->ctx);
 726         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 727                                                     enter_timestamp);
 728         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 729                         div_u64(time_taken_in_ns, 1000000));
 730         return false;
 731 }
 732 
 733 /**
 734  * dc_link_detect() - Detect if a sink is attached to a given link
 735  *
 736  * link->local_sink is created or destroyed as needed.
 737  *
 738  * This does not create remote sinks but will trigger DM
 739  * to start MST detection if a branch is detected.
 740  */
 741 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 742 {
 743         struct dc_sink_init_data sink_init_data = { 0 };
 744         struct display_sink_capability sink_caps = { 0 };
 745         uint8_t i;
 746         bool converter_disable_audio = false;
 747         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 748         bool same_edid = false;
 749         enum dc_edid_status edid_status;
 750         struct dc_context *dc_ctx = link->ctx;
 751         struct dc_sink *sink = NULL;
 752         struct dc_sink *prev_sink = NULL;
 753         struct dpcd_caps prev_dpcd_caps;
 754         bool same_dpcd = true;
 755         enum dc_connection_type new_connection_type = dc_connection_none;
 756         DC_LOGGER_INIT(link->ctx->logger);
 757 
 758         if (dc_is_virtual_signal(link->connector_signal))
 759                 return false;
 760 
 761         if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
 762                         link->connector_signal == SIGNAL_TYPE_EDP) &&
 763                         link->local_sink)
 764                 return true;
 765 
 766         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 767                 BREAK_TO_DEBUGGER();
 768                 return false;
 769         }
 770 
 771         prev_sink = link->local_sink;
 772         if (prev_sink != NULL) {
 773                 dc_sink_retain(prev_sink);
 774                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 775         }
 776         link_disconnect_sink(link);
 777 
 778         if (new_connection_type != dc_connection_none) {
 779                 link->type = new_connection_type;
 780                 link->link_state_valid = false;
 781 
 782                 /* From Disconnected-to-Connected. */
 783                 switch (link->connector_signal) {
 784                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 785                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 786                         if (aud_support->hdmi_audio_native)
 787                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 788                         else
 789                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 790                         break;
 791                 }
 792 
 793                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 794                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 795                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 796                         break;
 797                 }
 798 
 799                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 800                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 801                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 802                         break;
 803                 }
 804 
 805                 case SIGNAL_TYPE_LVDS: {
 806                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 807                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 808                         break;
 809                 }
 810 
 811                 case SIGNAL_TYPE_EDP: {
 812                         detect_edp_sink_caps(link);
 813                         read_edp_current_link_settings_on_detect(link);
 814                         sink_caps.transaction_type =
 815                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 816                         sink_caps.signal = SIGNAL_TYPE_EDP;
 817                         break;
 818                 }
 819 
 820                 case SIGNAL_TYPE_DISPLAY_PORT: {
 821                         /* wa HPD high coming too early*/
 822                         if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 823 
 824                                 /* if alt mode times out, return false */
 825                                 if (wait_for_alt_mode(link) == false) {
 826                                         return false;
 827                                 }
 828                         }
 829 
 830                         if (!detect_dp(
 831                                 link,
 832                                 &sink_caps,
 833                                 &converter_disable_audio,
 834                                 aud_support, reason)) {
 835                                 if (prev_sink != NULL)
 836                                         dc_sink_release(prev_sink);
 837                                 return false;
 838                         }
 839 
 840                         // Check if dpcp block is the same
 841                         if (prev_sink != NULL) {
 842                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 843                                         same_dpcd = false;
 844                         }
 845                         /* Active dongle plug in without display or downstream unplug*/
 846                         if (link->type == dc_connection_active_dongle &&
 847                                 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 848                                 if (prev_sink != NULL) {
 849                                         /* Downstream unplug */
 850                                         dc_sink_release(prev_sink);
 851                                 } else {
 852                                         /* Empty dongle plug in */
 853                                         dp_verify_link_cap_with_retries(link,
 854                                                         &link->reported_link_cap,
 855                                                         LINK_TRAINING_MAX_VERIFY_RETRY);
 856                                 }
 857                                 return true;
 858                         }
 859 
 860                         if (link->type == dc_connection_mst_branch) {
 861                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 862                                         link->link_index);
 863                                 /* Need to setup mst link_cap struct here
 864                                  * otherwise dc_link_detect() will leave mst link_cap
 865                                  * empty which leads to allocate_mst_payload() has "0"
 866                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 867                                  */
 868                                 link->verified_link_cap = link->reported_link_cap;
 869                                 if (prev_sink != NULL)
 870                                         dc_sink_release(prev_sink);
 871                                 return false;
 872                         }
 873 
 874                         break;
 875                 }
 876 
 877                 default:
 878                         DC_ERROR("Invalid connector type! signal:%d\n",
 879                                 link->connector_signal);
 880                         if (prev_sink != NULL)
 881                                 dc_sink_release(prev_sink);
 882                         return false;
 883                 } /* switch() */
 884 
 885                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 886                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 887                                         bits.SINK_COUNT;
 888                 else
 889                         link->dpcd_sink_count = 1;
 890 
 891                 dal_ddc_service_set_transaction_type(
 892                                                 link->ddc,
 893                                                 sink_caps.transaction_type);
 894 
 895                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 896                                 link->ddc);
 897 
 898                 sink_init_data.link = link;
 899                 sink_init_data.sink_signal = sink_caps.signal;
 900 
 901                 sink = dc_sink_create(&sink_init_data);
 902                 if (!sink) {
 903                         DC_ERROR("Failed to create sink!\n");
 904                         if (prev_sink != NULL)
 905                                 dc_sink_release(prev_sink);
 906                         return false;
 907                 }
 908 
 909                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 910                 sink->converter_disable_audio = converter_disable_audio;
 911 
 912                 /* dc_sink_create returns a new reference */
 913                 link->local_sink = sink;
 914 
 915                 edid_status = dm_helpers_read_local_edid(
 916                                 link->ctx,
 917                                 link,
 918                                 sink);
 919 
 920                 switch (edid_status) {
 921                 case EDID_BAD_CHECKSUM:
 922                         DC_LOG_ERROR("EDID checksum invalid.\n");
 923                         break;
 924                 case EDID_NO_RESPONSE:
 925                         DC_LOG_ERROR("No EDID read.\n");
 926 
 927                         /*
 928                          * Abort detection for non-DP connectors if we have
 929                          * no EDID
 930                          *
 931                          * DP needs to report as connected if HDP is high
 932                          * even if we have no EDID in order to go to
 933                          * fail-safe mode
 934                          */
 935                         if (dc_is_hdmi_signal(link->connector_signal) ||
 936                             dc_is_dvi_signal(link->connector_signal)) {
 937                                 if (prev_sink != NULL)
 938                                         dc_sink_release(prev_sink);
 939 
 940                                 return false;
 941                         }
 942                 default:
 943                         break;
 944                 }
 945 
 946                 // Check if edid is the same
 947                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 948                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 949 
 950                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 951                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 952                         /*
 953                          * TODO debug why Dell 2413 doesn't like
 954                          *  two link trainings
 955                          */
 956 
 957                         /* deal with non-mst cases */
 958                         dp_verify_link_cap_with_retries(link,
 959                                         &link->reported_link_cap,
 960                                         LINK_TRAINING_MAX_VERIFY_RETRY);
 961                 } else {
 962                         // If edid is the same, then discard new sink and revert back to original sink
 963                         if (same_edid) {
 964                                 link_disconnect_remap(prev_sink, link);
 965                                 sink = prev_sink;
 966                                 prev_sink = NULL;
 967 
 968                         }
 969                 }
 970 
 971                 /* HDMI-DVI Dongle */
 972                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 973                                 !sink->edid_caps.edid_hdmi)
 974                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 975 
 976                 /* Connectivity log: detection */
 977                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
 978                         CONN_DATA_DETECT(link,
 979                                         &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
 980                                         DC_EDID_BLOCK_SIZE,
 981                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 982                 }
 983 
 984                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 985                         "manufacturer_id = %X, "
 986                         "product_id = %X, "
 987                         "serial_number = %X, "
 988                         "manufacture_week = %d, "
 989                         "manufacture_year = %d, "
 990                         "display_name = %s, "
 991                         "speaker_flag = %d, "
 992                         "audio_mode_count = %d\n",
 993                         __func__,
 994                         sink->edid_caps.manufacturer_id,
 995                         sink->edid_caps.product_id,
 996                         sink->edid_caps.serial_number,
 997                         sink->edid_caps.manufacture_week,
 998                         sink->edid_caps.manufacture_year,
 999                         sink->edid_caps.display_name,
1000                         sink->edid_caps.speaker_flags,
1001                         sink->edid_caps.audio_mode_count);
1002 
1003                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1004                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1005                                 "format_code = %d, "
1006                                 "channel_count = %d, "
1007                                 "sample_rate = %d, "
1008                                 "sample_size = %d\n",
1009                                 __func__,
1010                                 i,
1011                                 sink->edid_caps.audio_modes[i].format_code,
1012                                 sink->edid_caps.audio_modes[i].channel_count,
1013                                 sink->edid_caps.audio_modes[i].sample_rate,
1014                                 sink->edid_caps.audio_modes[i].sample_size);
1015                 }
1016 
1017         } else {
1018                 /* From Connected-to-Disconnected. */
1019                 if (link->type == dc_connection_mst_branch) {
1020                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1021                                 link->link_index);
1022 
1023                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1024 
1025                         link->mst_stream_alloc_table.stream_count = 0;
1026                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
1027                 }
1028 
1029                 link->type = dc_connection_none;
1030                 sink_caps.signal = SIGNAL_TYPE_NONE;
1031                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1032                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1033                  *  the dongle is still there and limits the number of modes we can emulate.
1034                  *  Clear dongle_max_pix_clk on disconnect to fix this
1035                  */
1036                 link->dongle_max_pix_clk = 0;
1037         }
1038 
1039         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1040                 link->link_index, sink,
1041                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
1042                         "Disconnected":"Connected"), prev_sink,
1043                         same_dpcd, same_edid);
1044 
1045         if (prev_sink != NULL)
1046                 dc_sink_release(prev_sink);
1047 
1048         return true;
1049 }
1050 
1051 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1052 {
1053         uint32_t state;
1054 
1055         dal_gpio_lock_pin(dc_link->hpd_gpio);
1056         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1057         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1058 
1059         return state;
1060 }
1061 
1062 static enum hpd_source_id get_hpd_line(
1063                 struct dc_link *link)
1064 {
1065         struct gpio *hpd;
1066         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1067 
1068         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1069 
1070         if (hpd) {
1071                 switch (dal_irq_get_source(hpd)) {
1072                 case DC_IRQ_SOURCE_HPD1:
1073                         hpd_id = HPD_SOURCEID1;
1074                 break;
1075                 case DC_IRQ_SOURCE_HPD2:
1076                         hpd_id = HPD_SOURCEID2;
1077                 break;
1078                 case DC_IRQ_SOURCE_HPD3:
1079                         hpd_id = HPD_SOURCEID3;
1080                 break;
1081                 case DC_IRQ_SOURCE_HPD4:
1082                         hpd_id = HPD_SOURCEID4;
1083                 break;
1084                 case DC_IRQ_SOURCE_HPD5:
1085                         hpd_id = HPD_SOURCEID5;
1086                 break;
1087                 case DC_IRQ_SOURCE_HPD6:
1088                         hpd_id = HPD_SOURCEID6;
1089                 break;
1090                 default:
1091                         BREAK_TO_DEBUGGER();
1092                 break;
1093                 }
1094 
1095                 dal_gpio_destroy_irq(&hpd);
1096         }
1097 
1098         return hpd_id;
1099 }
1100 
1101 static enum channel_id get_ddc_line(struct dc_link *link)
1102 {
1103         struct ddc *ddc;
1104         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1105 
1106         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1107 
1108         if (ddc) {
1109                 switch (dal_ddc_get_line(ddc)) {
1110                 case GPIO_DDC_LINE_DDC1:
1111                         channel = CHANNEL_ID_DDC1;
1112                         break;
1113                 case GPIO_DDC_LINE_DDC2:
1114                         channel = CHANNEL_ID_DDC2;
1115                         break;
1116                 case GPIO_DDC_LINE_DDC3:
1117                         channel = CHANNEL_ID_DDC3;
1118                         break;
1119                 case GPIO_DDC_LINE_DDC4:
1120                         channel = CHANNEL_ID_DDC4;
1121                         break;
1122                 case GPIO_DDC_LINE_DDC5:
1123                         channel = CHANNEL_ID_DDC5;
1124                         break;
1125                 case GPIO_DDC_LINE_DDC6:
1126                         channel = CHANNEL_ID_DDC6;
1127                         break;
1128                 case GPIO_DDC_LINE_DDC_VGA:
1129                         channel = CHANNEL_ID_DDC_VGA;
1130                         break;
1131                 case GPIO_DDC_LINE_I2C_PAD:
1132                         channel = CHANNEL_ID_I2C_PAD;
1133                         break;
1134                 default:
1135                         BREAK_TO_DEBUGGER();
1136                         break;
1137                 }
1138         }
1139 
1140         return channel;
1141 }
1142 
1143 static enum transmitter translate_encoder_to_transmitter(
1144         struct graphics_object_id encoder)
1145 {
1146         switch (encoder.id) {
1147         case ENCODER_ID_INTERNAL_UNIPHY:
1148                 switch (encoder.enum_id) {
1149                 case ENUM_ID_1:
1150                         return TRANSMITTER_UNIPHY_A;
1151                 case ENUM_ID_2:
1152                         return TRANSMITTER_UNIPHY_B;
1153                 default:
1154                         return TRANSMITTER_UNKNOWN;
1155                 }
1156         break;
1157         case ENCODER_ID_INTERNAL_UNIPHY1:
1158                 switch (encoder.enum_id) {
1159                 case ENUM_ID_1:
1160                         return TRANSMITTER_UNIPHY_C;
1161                 case ENUM_ID_2:
1162                         return TRANSMITTER_UNIPHY_D;
1163                 default:
1164                         return TRANSMITTER_UNKNOWN;
1165                 }
1166         break;
1167         case ENCODER_ID_INTERNAL_UNIPHY2:
1168                 switch (encoder.enum_id) {
1169                 case ENUM_ID_1:
1170                         return TRANSMITTER_UNIPHY_E;
1171                 case ENUM_ID_2:
1172                         return TRANSMITTER_UNIPHY_F;
1173                 default:
1174                         return TRANSMITTER_UNKNOWN;
1175                 }
1176         break;
1177         case ENCODER_ID_INTERNAL_UNIPHY3:
1178                 switch (encoder.enum_id) {
1179                 case ENUM_ID_1:
1180                         return TRANSMITTER_UNIPHY_G;
1181                 default:
1182                         return TRANSMITTER_UNKNOWN;
1183                 }
1184         break;
1185         case ENCODER_ID_EXTERNAL_NUTMEG:
1186                 switch (encoder.enum_id) {
1187                 case ENUM_ID_1:
1188                         return TRANSMITTER_NUTMEG_CRT;
1189                 default:
1190                         return TRANSMITTER_UNKNOWN;
1191                 }
1192         break;
1193         case ENCODER_ID_EXTERNAL_TRAVIS:
1194                 switch (encoder.enum_id) {
1195                 case ENUM_ID_1:
1196                         return TRANSMITTER_TRAVIS_CRT;
1197                 case ENUM_ID_2:
1198                         return TRANSMITTER_TRAVIS_LCD;
1199                 default:
1200                         return TRANSMITTER_UNKNOWN;
1201                 }
1202         break;
1203         default:
1204                 return TRANSMITTER_UNKNOWN;
1205         }
1206 }
1207 
1208 static bool construct(
1209         struct dc_link *link,
1210         const struct link_init_data *init_params)
1211 {
1212         uint8_t i;
1213         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1214         struct dc_context *dc_ctx = init_params->ctx;
1215         struct encoder_init_data enc_init_data = { 0 };
1216         struct integrated_info info = {{{ 0 }}};
1217         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1218         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1219         DC_LOGGER_INIT(dc_ctx->logger);
1220 
1221         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1222         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1223 
1224         link->link_status.dpcd_caps = &link->dpcd_caps;
1225 
1226         link->dc = init_params->dc;
1227         link->ctx = dc_ctx;
1228         link->link_index = init_params->link_index;
1229 
1230         memset(&link->preferred_training_settings, 0, sizeof(struct dc_link_training_overrides));
1231         memset(&link->preferred_link_setting, 0, sizeof(struct dc_link_settings));
1232 
1233         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1234 
1235         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1236                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1237                          __func__, init_params->connector_index,
1238                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1239                 goto create_fail;
1240         }
1241 
1242         if (link->dc->res_pool->funcs->link_init)
1243                 link->dc->res_pool->funcs->link_init(link);
1244 
1245         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1246         if (link->hpd_gpio != NULL) {
1247                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1248                 dal_gpio_unlock_pin(link->hpd_gpio);
1249                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1250         }
1251 
1252         switch (link->link_id.id) {
1253         case CONNECTOR_ID_HDMI_TYPE_A:
1254                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1255 
1256                 break;
1257         case CONNECTOR_ID_SINGLE_LINK_DVID:
1258         case CONNECTOR_ID_SINGLE_LINK_DVII:
1259                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1260                 break;
1261         case CONNECTOR_ID_DUAL_LINK_DVID:
1262         case CONNECTOR_ID_DUAL_LINK_DVII:
1263                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1264                 break;
1265         case CONNECTOR_ID_DISPLAY_PORT:
1266                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1267 
1268                 if (link->hpd_gpio != NULL)
1269                         link->irq_source_hpd_rx =
1270                                         dal_irq_get_rx_source(link->hpd_gpio);
1271 
1272                 break;
1273         case CONNECTOR_ID_EDP:
1274                 link->connector_signal = SIGNAL_TYPE_EDP;
1275 
1276                 if (link->hpd_gpio != NULL) {
1277                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1278                         link->irq_source_hpd_rx =
1279                                         dal_irq_get_rx_source(link->hpd_gpio);
1280                 }
1281                 break;
1282         case CONNECTOR_ID_LVDS:
1283                 link->connector_signal = SIGNAL_TYPE_LVDS;
1284                 break;
1285         default:
1286                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1287                 goto create_fail;
1288         }
1289 
1290         /* TODO: #DAL3 Implement id to str function.*/
1291         LINK_INFO("Connector[%d] description:"
1292                         "signal %d\n",
1293                         init_params->connector_index,
1294                         link->connector_signal);
1295 
1296         ddc_service_init_data.ctx = link->ctx;
1297         ddc_service_init_data.id = link->link_id;
1298         ddc_service_init_data.link = link;
1299         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1300 
1301         if (link->ddc == NULL) {
1302                 DC_ERROR("Failed to create ddc_service!\n");
1303                 goto ddc_create_fail;
1304         }
1305 
1306         link->ddc_hw_inst =
1307                 dal_ddc_get_line(
1308                         dal_ddc_service_get_ddc_pin(link->ddc));
1309 
1310         enc_init_data.ctx = dc_ctx;
1311         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1312         enc_init_data.connector = link->link_id;
1313         enc_init_data.channel = get_ddc_line(link);
1314         enc_init_data.hpd_source = get_hpd_line(link);
1315 
1316         link->hpd_src = enc_init_data.hpd_source;
1317 
1318         enc_init_data.transmitter =
1319                         translate_encoder_to_transmitter(enc_init_data.encoder);
1320         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1321                                                                 &enc_init_data);
1322 
1323         if (link->link_enc == NULL) {
1324                 DC_ERROR("Failed to create link encoder!\n");
1325                 goto link_enc_create_fail;
1326         }
1327 
1328         link->link_enc_hw_inst = link->link_enc->transmitter;
1329 
1330         for (i = 0; i < 4; i++) {
1331                 if (BP_RESULT_OK !=
1332                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1333                         DC_ERROR("Failed to find device tag!\n");
1334                         goto device_tag_fail;
1335                 }
1336 
1337                 /* Look for device tag that matches connector signal,
1338                  * CRT for rgb, LCD for other supported signal tyes
1339                  */
1340                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1341                         continue;
1342                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1343                         && link->connector_signal != SIGNAL_TYPE_RGB)
1344                         continue;
1345                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1346                         && link->connector_signal == SIGNAL_TYPE_RGB)
1347                         continue;
1348                 break;
1349         }
1350 
1351         if (bios->integrated_info)
1352                 info = *bios->integrated_info;
1353 
1354         /* Look for channel mapping corresponding to connector and device tag */
1355         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1356                 struct external_display_path *path =
1357                         &info.ext_disp_conn_info.path[i];
1358                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1359                         && path->device_connector_id.id == link->link_id.id
1360                         && path->device_connector_id.type == link->link_id.type) {
1361 
1362                         if (link->device_tag.acpi_device != 0
1363                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1364                                 link->ddi_channel_mapping = path->channel_mapping;
1365                                 link->chip_caps = path->caps;
1366                         } else if (path->device_tag ==
1367                                         link->device_tag.dev_id.raw_device_tag) {
1368                                 link->ddi_channel_mapping = path->channel_mapping;
1369                                 link->chip_caps = path->caps;
1370                         }
1371                         break;
1372                 }
1373         }
1374 
1375         /*
1376          * TODO check if GPIO programmed correctly
1377          *
1378          * If GPIO isn't programmed correctly HPD might not rise or drain
1379          * fast enough, leading to bounces.
1380          */
1381         program_hpd_filter(link);
1382 
1383         return true;
1384 device_tag_fail:
1385         link->link_enc->funcs->destroy(&link->link_enc);
1386 link_enc_create_fail:
1387         dal_ddc_service_destroy(&link->ddc);
1388 ddc_create_fail:
1389 create_fail:
1390 
1391         if (link->hpd_gpio != NULL) {
1392                 dal_gpio_destroy_irq(&link->hpd_gpio);
1393                 link->hpd_gpio = NULL;
1394         }
1395 
1396         return false;
1397 }
1398 
1399 /*******************************************************************************
1400  * Public functions
1401  ******************************************************************************/
1402 struct dc_link *link_create(const struct link_init_data *init_params)
1403 {
1404         struct dc_link *link =
1405                         kzalloc(sizeof(*link), GFP_KERNEL);
1406 
1407         if (NULL == link)
1408                 goto alloc_fail;
1409 
1410         if (false == construct(link, init_params))
1411                 goto construct_fail;
1412 
1413         return link;
1414 
1415 construct_fail:
1416         kfree(link);
1417 
1418 alloc_fail:
1419         return NULL;
1420 }
1421 
1422 void link_destroy(struct dc_link **link)
1423 {
1424         destruct(*link);
1425         kfree(*link);
1426         *link = NULL;
1427 }
1428 
1429 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1430 {
1431         struct dc_stream_state *stream = pipe_ctx->stream;
1432         struct dc_link *link = stream->link;
1433         union down_spread_ctrl old_downspread;
1434         union down_spread_ctrl new_downspread;
1435 
1436         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1437                         &old_downspread.raw, sizeof(old_downspread));
1438 
1439         new_downspread.raw = old_downspread.raw;
1440 
1441         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1442                         (stream->ignore_msa_timing_param) ? 1 : 0;
1443 
1444         if (new_downspread.raw != old_downspread.raw) {
1445                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1446                         &new_downspread.raw, sizeof(new_downspread));
1447         }
1448 }
1449 
1450 static enum dc_status enable_link_dp(
1451                 struct dc_state *state,
1452                 struct pipe_ctx *pipe_ctx)
1453 {
1454         struct dc_stream_state *stream = pipe_ctx->stream;
1455         enum dc_status status;
1456         bool skip_video_pattern;
1457         struct dc_link *link = stream->link;
1458         struct dc_link_settings link_settings = {0};
1459         enum dp_panel_mode panel_mode;
1460 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1461         bool fec_enable;
1462 #endif
1463         int i;
1464         bool apply_seamless_boot_optimization = false;
1465 
1466         // check for seamless boot
1467         for (i = 0; i < state->stream_count; i++) {
1468                 if (state->streams[i]->apply_seamless_boot_optimization) {
1469                         apply_seamless_boot_optimization = true;
1470                         break;
1471                 }
1472         }
1473 
1474         /* get link settings for video mode timing */
1475         decide_link_settings(stream, &link_settings);
1476 
1477         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1478                 /* If link settings are different than current and link already enabled
1479                  * then need to disable before programming to new rate.
1480                  */
1481                 if (link->link_status.link_active &&
1482                         (link->cur_link_settings.lane_count != link_settings.lane_count ||
1483                          link->cur_link_settings.link_rate != link_settings.link_rate)) {
1484                         dp_disable_link_phy(link, pipe_ctx->stream->signal);
1485                 }
1486 
1487                 /*in case it is not on*/
1488                 link->dc->hwss.edp_power_control(link, true);
1489                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1490         }
1491 
1492         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1493                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1494         if (!apply_seamless_boot_optimization)
1495                 state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
1496 
1497         dp_enable_link_phy(
1498                 link,
1499                 pipe_ctx->stream->signal,
1500                 pipe_ctx->clock_source->id,
1501                 &link_settings);
1502 
1503         if (stream->sink_patches.dppowerup_delay > 0) {
1504                 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1505 
1506                 msleep(delay_dp_power_up_in_ms);
1507         }
1508 
1509         panel_mode = dp_get_panel_mode(link);
1510         dp_set_panel_mode(link, panel_mode);
1511 
1512         skip_video_pattern = true;
1513 
1514         if (link_settings.link_rate == LINK_RATE_LOW)
1515                         skip_video_pattern = false;
1516 
1517         if (link->aux_access_disabled) {
1518                 dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
1519 
1520                 link->cur_link_settings = link_settings;
1521                 status = DC_OK;
1522         } else if (perform_link_training_with_retries(
1523                         link,
1524                         &link_settings,
1525                         skip_video_pattern,
1526                         LINK_TRAINING_ATTEMPTS)) {
1527                 link->cur_link_settings = link_settings;
1528                 status = DC_OK;
1529         }
1530         else
1531                 status = DC_FAIL_DP_LINK_TRAINING;
1532 
1533 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1534         if (link->preferred_training_settings.fec_enable != NULL)
1535                 fec_enable = *link->preferred_training_settings.fec_enable;
1536         else
1537                 fec_enable = true;
1538 
1539         dp_set_fec_enable(link, fec_enable);
1540 #endif
1541         return status;
1542 }
1543 
1544 static enum dc_status enable_link_edp(
1545                 struct dc_state *state,
1546                 struct pipe_ctx *pipe_ctx)
1547 {
1548         enum dc_status status;
1549 
1550         status = enable_link_dp(state, pipe_ctx);
1551 
1552         return status;
1553 }
1554 
1555 static enum dc_status enable_link_dp_mst(
1556                 struct dc_state *state,
1557                 struct pipe_ctx *pipe_ctx)
1558 {
1559         struct dc_link *link = pipe_ctx->stream->link;
1560 
1561         /* sink signal type after MST branch is MST. Multiple MST sinks
1562          * share one link. Link DP PHY is enable or training only once.
1563          */
1564         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1565                 return DC_OK;
1566 
1567         /* clear payload table */
1568         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1569 
1570         /* to make sure the pending down rep can be processed
1571          * before enabling the link
1572          */
1573         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1574 
1575         /* set the sink to MST mode before enabling the link */
1576         dp_enable_mst_on_sink(link, true);
1577 
1578         return enable_link_dp(state, pipe_ctx);
1579 }
1580 
1581 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1582                 enum engine_id eng_id,
1583                 struct ext_hdmi_settings *settings)
1584 {
1585         bool result = false;
1586         int i = 0;
1587         struct integrated_info *integrated_info =
1588                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1589 
1590         if (integrated_info == NULL)
1591                 return false;
1592 
1593         /*
1594          * Get retimer settings from sbios for passing SI eye test for DCE11
1595          * The setting values are varied based on board revision and port id
1596          * Therefore the setting values of each ports is passed by sbios.
1597          */
1598 
1599         // Check if current bios contains ext Hdmi settings
1600         if (integrated_info->gpu_cap_info & 0x20) {
1601                 switch (eng_id) {
1602                 case ENGINE_ID_DIGA:
1603                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1604                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1605                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1606                         memmove(settings->reg_settings,
1607                                         integrated_info->dp0_ext_hdmi_reg_settings,
1608                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1609                         memmove(settings->reg_settings_6g,
1610                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1611                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1612                         result = true;
1613                         break;
1614                 case ENGINE_ID_DIGB:
1615                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1616                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1617                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1618                         memmove(settings->reg_settings,
1619                                         integrated_info->dp1_ext_hdmi_reg_settings,
1620                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1621                         memmove(settings->reg_settings_6g,
1622                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1623                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1624                         result = true;
1625                         break;
1626                 case ENGINE_ID_DIGC:
1627                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1628                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1629                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1630                         memmove(settings->reg_settings,
1631                                         integrated_info->dp2_ext_hdmi_reg_settings,
1632                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1633                         memmove(settings->reg_settings_6g,
1634                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1635                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1636                         result = true;
1637                         break;
1638                 case ENGINE_ID_DIGD:
1639                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1640                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1641                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1642                         memmove(settings->reg_settings,
1643                                         integrated_info->dp3_ext_hdmi_reg_settings,
1644                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1645                         memmove(settings->reg_settings_6g,
1646                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1647                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1648                         result = true;
1649                         break;
1650                 default:
1651                         break;
1652                 }
1653 
1654                 if (result == true) {
1655                         // Validate settings from bios integrated info table
1656                         if (settings->slv_addr == 0)
1657                                 return false;
1658                         if (settings->reg_num > 9)
1659                                 return false;
1660                         if (settings->reg_num_6g > 3)
1661                                 return false;
1662 
1663                         for (i = 0; i < settings->reg_num; i++) {
1664                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1665                                         return false;
1666                         }
1667 
1668                         for (i = 0; i < settings->reg_num_6g; i++) {
1669                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1670                                         return false;
1671                         }
1672                 }
1673         }
1674 
1675         return result;
1676 }
1677 
1678 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1679                 uint8_t address, uint8_t *buffer, uint32_t length)
1680 {
1681         struct i2c_command cmd = {0};
1682         struct i2c_payload payload = {0};
1683 
1684         memset(&payload, 0, sizeof(payload));
1685         memset(&cmd, 0, sizeof(cmd));
1686 
1687         cmd.number_of_payloads = 1;
1688         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1689         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1690 
1691         payload.address = address;
1692         payload.data = buffer;
1693         payload.length = length;
1694         payload.write = true;
1695         cmd.payloads = &payload;
1696 
1697         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1698                         pipe_ctx->stream->link, &cmd))
1699                 return true;
1700 
1701         return false;
1702 }
1703 
1704 static void write_i2c_retimer_setting(
1705                 struct pipe_ctx *pipe_ctx,
1706                 bool is_vga_mode,
1707                 bool is_over_340mhz,
1708                 struct ext_hdmi_settings *settings)
1709 {
1710         uint8_t slave_address = (settings->slv_addr >> 1);
1711         uint8_t buffer[2];
1712         const uint8_t apply_rx_tx_change = 0x4;
1713         uint8_t offset = 0xA;
1714         uint8_t value = 0;
1715         int i = 0;
1716         bool i2c_success = false;
1717         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1718 
1719         memset(&buffer, 0, sizeof(buffer));
1720 
1721         /* Start Ext-Hdmi programming*/
1722 
1723         for (i = 0; i < settings->reg_num; i++) {
1724                 /* Apply 3G settings */
1725                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1726 
1727                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1728                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1729                         i2c_success = i2c_write(pipe_ctx, slave_address,
1730                                                 buffer, sizeof(buffer));
1731                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1732                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1733                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1734 
1735                         if (!i2c_success)
1736                                 /* Write failure */
1737                                 ASSERT(i2c_success);
1738 
1739                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1740                          * needs to be set to 1 on every 0xA-0xC write.
1741                          */
1742                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1743                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1744                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1745 
1746                                 /* Query current value from offset 0xA */
1747                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1748                                         value = settings->reg_settings[i].i2c_reg_val;
1749                                 else {
1750                                         i2c_success =
1751                                                 dal_ddc_service_query_ddc_data(
1752                                                 pipe_ctx->stream->link->ddc,
1753                                                 slave_address, &offset, 1, &value, 1);
1754                                         if (!i2c_success)
1755                                                 /* Write failure */
1756                                                 ASSERT(i2c_success);
1757                                 }
1758 
1759                                 buffer[0] = offset;
1760                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1761                                 buffer[1] = value | apply_rx_tx_change;
1762                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1763                                                 buffer, sizeof(buffer));
1764                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1765                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1766                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1767                                 if (!i2c_success)
1768                                         /* Write failure */
1769                                         ASSERT(i2c_success);
1770                         }
1771                 }
1772         }
1773 
1774         /* Apply 3G settings */
1775         if (is_over_340mhz) {
1776                 for (i = 0; i < settings->reg_num_6g; i++) {
1777                         /* Apply 3G settings */
1778                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1779 
1780                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1781                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1782                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1783                                                         buffer, sizeof(buffer));
1784                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1785                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1786                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1787 
1788                                 if (!i2c_success)
1789                                         /* Write failure */
1790                                         ASSERT(i2c_success);
1791 
1792                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1793                                  * needs to be set to 1 on every 0xA-0xC write.
1794                                  */
1795                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1796                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1797                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1798 
1799                                         /* Query current value from offset 0xA */
1800                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1801                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1802                                         else {
1803                                                 i2c_success =
1804                                                                 dal_ddc_service_query_ddc_data(
1805                                                                 pipe_ctx->stream->link->ddc,
1806                                                                 slave_address, &offset, 1, &value, 1);
1807                                                 if (!i2c_success)
1808                                                         /* Write failure */
1809                                                         ASSERT(i2c_success);
1810                                         }
1811 
1812                                         buffer[0] = offset;
1813                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1814                                         buffer[1] = value | apply_rx_tx_change;
1815                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1816                                                         buffer, sizeof(buffer));
1817                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1818                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1819                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1820                                         if (!i2c_success)
1821                                                 /* Write failure */
1822                                                 ASSERT(i2c_success);
1823                                 }
1824                         }
1825                 }
1826         }
1827 
1828         if (is_vga_mode) {
1829                 /* Program additional settings if using 640x480 resolution */
1830 
1831                 /* Write offset 0xFF to 0x01 */
1832                 buffer[0] = 0xff;
1833                 buffer[1] = 0x01;
1834                 i2c_success = i2c_write(pipe_ctx, slave_address,
1835                                 buffer, sizeof(buffer));
1836                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1837                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1838                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1839                 if (!i2c_success)
1840                         /* Write failure */
1841                         ASSERT(i2c_success);
1842 
1843                 /* Write offset 0x00 to 0x23 */
1844                 buffer[0] = 0x00;
1845                 buffer[1] = 0x23;
1846                 i2c_success = i2c_write(pipe_ctx, slave_address,
1847                                 buffer, sizeof(buffer));
1848                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1849                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1850                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1851                 if (!i2c_success)
1852                         /* Write failure */
1853                         ASSERT(i2c_success);
1854 
1855                 /* Write offset 0xff to 0x00 */
1856                 buffer[0] = 0xff;
1857                 buffer[1] = 0x00;
1858                 i2c_success = i2c_write(pipe_ctx, slave_address,
1859                                 buffer, sizeof(buffer));
1860                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1861                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1862                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1863                 if (!i2c_success)
1864                         /* Write failure */
1865                         ASSERT(i2c_success);
1866 
1867         }
1868 }
1869 
1870 static void write_i2c_default_retimer_setting(
1871                 struct pipe_ctx *pipe_ctx,
1872                 bool is_vga_mode,
1873                 bool is_over_340mhz)
1874 {
1875         uint8_t slave_address = (0xBA >> 1);
1876         uint8_t buffer[2];
1877         bool i2c_success = false;
1878         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1879 
1880         memset(&buffer, 0, sizeof(buffer));
1881 
1882         /* Program Slave Address for tuning single integrity */
1883         /* Write offset 0x0A to 0x13 */
1884         buffer[0] = 0x0A;
1885         buffer[1] = 0x13;
1886         i2c_success = i2c_write(pipe_ctx, slave_address,
1887                         buffer, sizeof(buffer));
1888         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1889                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1890                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1891         if (!i2c_success)
1892                 /* Write failure */
1893                 ASSERT(i2c_success);
1894 
1895         /* Write offset 0x0A to 0x17 */
1896         buffer[0] = 0x0A;
1897         buffer[1] = 0x17;
1898         i2c_success = i2c_write(pipe_ctx, slave_address,
1899                         buffer, sizeof(buffer));
1900         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1901                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1902                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1903         if (!i2c_success)
1904                 /* Write failure */
1905                 ASSERT(i2c_success);
1906 
1907         /* Write offset 0x0B to 0xDA or 0xD8 */
1908         buffer[0] = 0x0B;
1909         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1910         i2c_success = i2c_write(pipe_ctx, slave_address,
1911                         buffer, sizeof(buffer));
1912         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1913                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1914                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1915         if (!i2c_success)
1916                 /* Write failure */
1917                 ASSERT(i2c_success);
1918 
1919         /* Write offset 0x0A to 0x17 */
1920         buffer[0] = 0x0A;
1921         buffer[1] = 0x17;
1922         i2c_success = i2c_write(pipe_ctx, slave_address,
1923                         buffer, sizeof(buffer));
1924         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1925                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1926                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1927         if (!i2c_success)
1928                 /* Write failure */
1929                 ASSERT(i2c_success);
1930 
1931         /* Write offset 0x0C to 0x1D or 0x91 */
1932         buffer[0] = 0x0C;
1933         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1934         i2c_success = i2c_write(pipe_ctx, slave_address,
1935                         buffer, sizeof(buffer));
1936         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1937                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1938                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1939         if (!i2c_success)
1940                 /* Write failure */
1941                 ASSERT(i2c_success);
1942 
1943         /* Write offset 0x0A to 0x17 */
1944         buffer[0] = 0x0A;
1945         buffer[1] = 0x17;
1946         i2c_success = i2c_write(pipe_ctx, slave_address,
1947                         buffer, sizeof(buffer));
1948         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1949                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1950                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1951         if (!i2c_success)
1952                 /* Write failure */
1953                 ASSERT(i2c_success);
1954 
1955 
1956         if (is_vga_mode) {
1957                 /* Program additional settings if using 640x480 resolution */
1958 
1959                 /* Write offset 0xFF to 0x01 */
1960                 buffer[0] = 0xff;
1961                 buffer[1] = 0x01;
1962                 i2c_success = i2c_write(pipe_ctx, slave_address,
1963                                 buffer, sizeof(buffer));
1964                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1965                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1966                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1967                 if (!i2c_success)
1968                         /* Write failure */
1969                         ASSERT(i2c_success);
1970 
1971                 /* Write offset 0x00 to 0x23 */
1972                 buffer[0] = 0x00;
1973                 buffer[1] = 0x23;
1974                 i2c_success = i2c_write(pipe_ctx, slave_address,
1975                                 buffer, sizeof(buffer));
1976                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1977                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1978                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1979                 if (!i2c_success)
1980                         /* Write failure */
1981                         ASSERT(i2c_success);
1982 
1983                 /* Write offset 0xff to 0x00 */
1984                 buffer[0] = 0xff;
1985                 buffer[1] = 0x00;
1986                 i2c_success = i2c_write(pipe_ctx, slave_address,
1987                                 buffer, sizeof(buffer));
1988                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
1989                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
1990                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1991                 if (!i2c_success)
1992                         /* Write failure */
1993                         ASSERT(i2c_success);
1994         }
1995 }
1996 
1997 static void write_i2c_redriver_setting(
1998                 struct pipe_ctx *pipe_ctx,
1999                 bool is_over_340mhz)
2000 {
2001         uint8_t slave_address = (0xF0 >> 1);
2002         uint8_t buffer[16];
2003         bool i2c_success = false;
2004         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2005 
2006         memset(&buffer, 0, sizeof(buffer));
2007 
2008         // Program Slave Address for tuning single integrity
2009         buffer[3] = 0x4E;
2010         buffer[4] = 0x4E;
2011         buffer[5] = 0x4E;
2012         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2013 
2014         i2c_success = i2c_write(pipe_ctx, slave_address,
2015                                         buffer, sizeof(buffer));
2016         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2017                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2018                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2019                 i2c_success = %d\n",
2020                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2021 
2022         if (!i2c_success)
2023                 /* Write failure */
2024                 ASSERT(i2c_success);
2025 }
2026 
2027 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2028 {
2029         struct dc_stream_state *stream = pipe_ctx->stream;
2030         struct dc_link *link = stream->link;
2031         enum dc_color_depth display_color_depth;
2032         enum engine_id eng_id;
2033         struct ext_hdmi_settings settings = {0};
2034         bool is_over_340mhz = false;
2035         bool is_vga_mode = (stream->timing.h_addressable == 640)
2036                         && (stream->timing.v_addressable == 480);
2037 
2038         if (stream->phy_pix_clk == 0)
2039                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2040         if (stream->phy_pix_clk > 340000)
2041                 is_over_340mhz = true;
2042 
2043         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2044                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2045                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2046                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2047                         /* DP159, Retimer settings */
2048                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2049 
2050                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2051                                 write_i2c_retimer_setting(pipe_ctx,
2052                                                 is_vga_mode, is_over_340mhz, &settings);
2053                         } else {
2054                                 write_i2c_default_retimer_setting(pipe_ctx,
2055                                                 is_vga_mode, is_over_340mhz);
2056                         }
2057                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2058                         /* PI3EQX1204, Redriver settings */
2059                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2060                 }
2061         }
2062 
2063         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2064                 dal_ddc_service_write_scdc_data(
2065                         stream->link->ddc,
2066                         stream->phy_pix_clk,
2067                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2068 
2069         memset(&stream->link->cur_link_settings, 0,
2070                         sizeof(struct dc_link_settings));
2071 
2072         display_color_depth = stream->timing.display_color_depth;
2073         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2074                 display_color_depth = COLOR_DEPTH_888;
2075 
2076         link->link_enc->funcs->enable_tmds_output(
2077                         link->link_enc,
2078                         pipe_ctx->clock_source->id,
2079                         display_color_depth,
2080                         pipe_ctx->stream->signal,
2081                         stream->phy_pix_clk);
2082 
2083         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2084                 dal_ddc_service_read_scdc_data(link->ddc);
2085 }
2086 
2087 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2088 {
2089         struct dc_stream_state *stream = pipe_ctx->stream;
2090         struct dc_link *link = stream->link;
2091 
2092         if (stream->phy_pix_clk == 0)
2093                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2094 
2095         memset(&stream->link->cur_link_settings, 0,
2096                         sizeof(struct dc_link_settings));
2097 
2098         link->link_enc->funcs->enable_lvds_output(
2099                         link->link_enc,
2100                         pipe_ctx->clock_source->id,
2101                         stream->phy_pix_clk);
2102 
2103 }
2104 
2105 /****************************enable_link***********************************/
2106 static enum dc_status enable_link(
2107                 struct dc_state *state,
2108                 struct pipe_ctx *pipe_ctx)
2109 {
2110         enum dc_status status = DC_ERROR_UNEXPECTED;
2111         switch (pipe_ctx->stream->signal) {
2112         case SIGNAL_TYPE_DISPLAY_PORT:
2113                 status = enable_link_dp(state, pipe_ctx);
2114                 break;
2115         case SIGNAL_TYPE_EDP:
2116                 status = enable_link_edp(state, pipe_ctx);
2117                 break;
2118         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2119                 status = enable_link_dp_mst(state, pipe_ctx);
2120                 msleep(200);
2121                 break;
2122         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2123         case SIGNAL_TYPE_DVI_DUAL_LINK:
2124         case SIGNAL_TYPE_HDMI_TYPE_A:
2125                 enable_link_hdmi(pipe_ctx);
2126                 status = DC_OK;
2127                 break;
2128         case SIGNAL_TYPE_LVDS:
2129                 enable_link_lvds(pipe_ctx);
2130                 status = DC_OK;
2131                 break;
2132         case SIGNAL_TYPE_VIRTUAL:
2133                 status = DC_OK;
2134                 break;
2135         default:
2136                 break;
2137         }
2138 
2139         if (status == DC_OK)
2140                 pipe_ctx->stream->link->link_status.link_active = true;
2141 
2142         return status;
2143 }
2144 
2145 static void disable_link(struct dc_link *link, enum signal_type signal)
2146 {
2147         /*
2148          * TODO: implement call for dp_set_hw_test_pattern
2149          * it is needed for compliance testing
2150          */
2151 
2152         /* here we need to specify that encoder output settings
2153          * need to be calculated as for the set mode,
2154          * it will lead to querying dynamic link capabilities
2155          * which should be done before enable output */
2156 
2157         if (dc_is_dp_signal(signal)) {
2158                 /* SST DP, eDP */
2159                 if (dc_is_dp_sst_signal(signal))
2160                         dp_disable_link_phy(link, signal);
2161                 else
2162                         dp_disable_link_phy_mst(link, signal);
2163 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2164 
2165                 if (dc_is_dp_sst_signal(signal) ||
2166                                 link->mst_stream_alloc_table.stream_count == 0) {
2167                         dp_set_fec_enable(link, false);
2168                         dp_set_fec_ready(link, false);
2169                 }
2170 #endif
2171         } else {
2172                 if (signal != SIGNAL_TYPE_VIRTUAL)
2173                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2174         }
2175 
2176         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2177                 /* MST disable link only when no stream use the link */
2178                 if (link->mst_stream_alloc_table.stream_count <= 0)
2179                         link->link_status.link_active = false;
2180         } else {
2181                 link->link_status.link_active = false;
2182         }
2183 }
2184 
2185 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2186 {
2187 
2188         uint32_t pxl_clk = timing->pix_clk_100hz;
2189 
2190         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2191                 pxl_clk /= 2;
2192         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2193                 pxl_clk = pxl_clk * 2 / 3;
2194 
2195         if (timing->display_color_depth == COLOR_DEPTH_101010)
2196                 pxl_clk = pxl_clk * 10 / 8;
2197         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2198                 pxl_clk = pxl_clk * 12 / 8;
2199 
2200         return pxl_clk;
2201 }
2202 
2203 static bool dp_active_dongle_validate_timing(
2204                 const struct dc_crtc_timing *timing,
2205                 const struct dpcd_caps *dpcd_caps)
2206 {
2207         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2208 
2209         switch (dpcd_caps->dongle_type) {
2210         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2211         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2212         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2213                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2214                         return true;
2215                 else
2216                         return false;
2217         default:
2218                 break;
2219         }
2220 
2221         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2222                 dongle_caps->extendedCapValid == false)
2223                 return true;
2224 
2225         /* Check Pixel Encoding */
2226         switch (timing->pixel_encoding) {
2227         case PIXEL_ENCODING_RGB:
2228         case PIXEL_ENCODING_YCBCR444:
2229                 break;
2230         case PIXEL_ENCODING_YCBCR422:
2231                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2232                         return false;
2233                 break;
2234         case PIXEL_ENCODING_YCBCR420:
2235                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2236                         return false;
2237                 break;
2238         default:
2239                 /* Invalid Pixel Encoding*/
2240                 return false;
2241         }
2242 
2243         switch (timing->display_color_depth) {
2244         case COLOR_DEPTH_666:
2245         case COLOR_DEPTH_888:
2246                 /*888 and 666 should always be supported*/
2247                 break;
2248         case COLOR_DEPTH_101010:
2249                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2250                         return false;
2251                 break;
2252         case COLOR_DEPTH_121212:
2253                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2254                         return false;
2255                 break;
2256         case COLOR_DEPTH_141414:
2257         case COLOR_DEPTH_161616:
2258         default:
2259                 /* These color depths are currently not supported */
2260                 return false;
2261         }
2262 
2263         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2264                 return false;
2265 
2266         return true;
2267 }
2268 
2269 enum dc_status dc_link_validate_mode_timing(
2270                 const struct dc_stream_state *stream,
2271                 struct dc_link *link,
2272                 const struct dc_crtc_timing *timing)
2273 {
2274         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2275         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2276 
2277         /* A hack to avoid failing any modes for EDID override feature on
2278          * topology change such as lower quality cable for DP or different dongle
2279          */
2280         if (link->remote_sinks[0])
2281                 return DC_OK;
2282 
2283         /* Passive Dongle */
2284         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2285                 return DC_EXCEED_DONGLE_CAP;
2286 
2287         /* Active Dongle*/
2288         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2289                 return DC_EXCEED_DONGLE_CAP;
2290 
2291         switch (stream->signal) {
2292         case SIGNAL_TYPE_EDP:
2293         case SIGNAL_TYPE_DISPLAY_PORT:
2294                 if (!dp_validate_mode_timing(
2295                                 link,
2296                                 timing))
2297                         return DC_NO_DP_LINK_BANDWIDTH;
2298                 break;
2299 
2300         default:
2301                 break;
2302         }
2303 
2304         return DC_OK;
2305 }
2306 
2307 int dc_link_get_backlight_level(const struct dc_link *link)
2308 {
2309         struct abm *abm = link->ctx->dc->res_pool->abm;
2310 
2311         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2312                 return DC_ERROR_UNEXPECTED;
2313 
2314         return (int) abm->funcs->get_current_backlight(abm);
2315 }
2316 
2317 bool dc_link_set_backlight_level(const struct dc_link *link,
2318                 uint32_t backlight_pwm_u16_16,
2319                 uint32_t frame_ramp)
2320 {
2321         struct dc  *core_dc = link->ctx->dc;
2322         struct abm *abm = core_dc->res_pool->abm;
2323         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2324         unsigned int controller_id = 0;
2325         bool use_smooth_brightness = true;
2326         int i;
2327         DC_LOGGER_INIT(link->ctx->logger);
2328 
2329         if ((dmcu == NULL) ||
2330                 (abm == NULL) ||
2331                 (abm->funcs->set_backlight_level_pwm == NULL))
2332                 return false;
2333 
2334         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2335 
2336         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2337                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2338 
2339         if (dc_is_embedded_signal(link->connector_signal)) {
2340                 for (i = 0; i < MAX_PIPES; i++) {
2341                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
2342                                 if (core_dc->current_state->res_ctx.
2343                                                 pipe_ctx[i].stream->link
2344                                                 == link) {
2345                                         /* DMCU -1 for all controller id values,
2346                                          * therefore +1 here
2347                                          */
2348                                         controller_id =
2349                                                 core_dc->current_state->
2350                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2351                                                 1;
2352 
2353                                         /* Disable brightness ramping when the display is blanked
2354                                          * as it can hang the DMCU
2355                                          */
2356                                         if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
2357                                                 frame_ramp = 0;
2358                                 }
2359                         }
2360                 }
2361                 abm->funcs->set_backlight_level_pwm(
2362                                 abm,
2363                                 backlight_pwm_u16_16,
2364                                 frame_ramp,
2365                                 controller_id,
2366                                 use_smooth_brightness);
2367         }
2368 
2369         return true;
2370 }
2371 
2372 bool dc_link_set_abm_disable(const struct dc_link *link)
2373 {
2374         struct dc  *core_dc = link->ctx->dc;
2375         struct abm *abm = core_dc->res_pool->abm;
2376 
2377         if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2378                 return false;
2379 
2380         abm->funcs->set_abm_immediate_disable(abm);
2381 
2382         return true;
2383 }
2384 
2385 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2386 {
2387         struct dc  *core_dc = link->ctx->dc;
2388         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2389 
2390         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
2391                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2392 
2393         return true;
2394 }
2395 
2396 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2397 {
2398         return &link->link_status;
2399 }
2400 
2401 void core_link_resume(struct dc_link *link)
2402 {
2403         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2404                 program_hpd_filter(link);
2405 }
2406 
2407 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2408 {
2409         struct fixed31_32 mbytes_per_sec;
2410         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2411                         &stream->link->cur_link_settings);
2412         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2413 
2414         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2415 
2416         return dc_fixpt_div_int(mbytes_per_sec, 54);
2417 }
2418 
2419 static int get_color_depth(enum dc_color_depth color_depth)
2420 {
2421         switch (color_depth) {
2422         case COLOR_DEPTH_666: return 6;
2423         case COLOR_DEPTH_888: return 8;
2424         case COLOR_DEPTH_101010: return 10;
2425         case COLOR_DEPTH_121212: return 12;
2426         case COLOR_DEPTH_141414: return 14;
2427         case COLOR_DEPTH_161616: return 16;
2428         default: return 0;
2429         }
2430 }
2431 
2432 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2433 {
2434         uint32_t bpc;
2435         uint64_t kbps;
2436         struct fixed31_32 peak_kbps;
2437         uint32_t numerator;
2438         uint32_t denominator;
2439 
2440         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2441         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2442 
2443         /*
2444          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2445          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2446          * common multiplier to render an integer PBN for all link rate/lane
2447          * counts combinations
2448          * calculate
2449          * peak_kbps *= (1006/1000)
2450          * peak_kbps *= (64/54)
2451          * peak_kbps *= 8    convert to bytes
2452          */
2453 
2454         numerator = 64 * PEAK_FACTOR_X1000;
2455         denominator = 54 * 8 * 1000 * 1000;
2456         kbps *= numerator;
2457         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2458 
2459         return peak_kbps;
2460 }
2461 
2462 static void update_mst_stream_alloc_table(
2463         struct dc_link *link,
2464         struct stream_encoder *stream_enc,
2465         const struct dp_mst_stream_allocation_table *proposed_table)
2466 {
2467         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2468                         { 0 } };
2469         struct link_mst_stream_allocation *dc_alloc;
2470 
2471         int i;
2472         int j;
2473 
2474         /* if DRM proposed_table has more than one new payload */
2475         ASSERT(proposed_table->stream_count -
2476                         link->mst_stream_alloc_table.stream_count < 2);
2477 
2478         /* copy proposed_table to link, add stream encoder */
2479         for (i = 0; i < proposed_table->stream_count; i++) {
2480 
2481                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2482                         dc_alloc =
2483                         &link->mst_stream_alloc_table.stream_allocations[j];
2484 
2485                         if (dc_alloc->vcp_id ==
2486                                 proposed_table->stream_allocations[i].vcp_id) {
2487 
2488                                 work_table[i] = *dc_alloc;
2489                                 break; /* exit j loop */
2490                         }
2491                 }
2492 
2493                 /* new vcp_id */
2494                 if (j == link->mst_stream_alloc_table.stream_count) {
2495                         work_table[i].vcp_id =
2496                                 proposed_table->stream_allocations[i].vcp_id;
2497                         work_table[i].slot_count =
2498                                 proposed_table->stream_allocations[i].slot_count;
2499                         work_table[i].stream_enc = stream_enc;
2500                 }
2501         }
2502 
2503         /* update link->mst_stream_alloc_table with work_table */
2504         link->mst_stream_alloc_table.stream_count =
2505                         proposed_table->stream_count;
2506         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2507                 link->mst_stream_alloc_table.stream_allocations[i] =
2508                                 work_table[i];
2509 }
2510 
2511 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2512  * because stream_encoder is not exposed to dm
2513  */
2514 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2515 {
2516         struct dc_stream_state *stream = pipe_ctx->stream;
2517         struct dc_link *link = stream->link;
2518         struct link_encoder *link_encoder = link->link_enc;
2519         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2520         struct dp_mst_stream_allocation_table proposed_table = {0};
2521         struct fixed31_32 avg_time_slots_per_mtp;
2522         struct fixed31_32 pbn;
2523         struct fixed31_32 pbn_per_slot;
2524         uint8_t i;
2525         DC_LOGGER_INIT(link->ctx->logger);
2526 
2527         /* enable_link_dp_mst already check link->enabled_stream_count
2528          * and stream is in link->stream[]. This is called during set mode,
2529          * stream_enc is available.
2530          */
2531 
2532         /* get calculate VC payload for stream: stream_alloc */
2533         if (dm_helpers_dp_mst_write_payload_allocation_table(
2534                 stream->ctx,
2535                 stream,
2536                 &proposed_table,
2537                 true)) {
2538                 update_mst_stream_alloc_table(
2539                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2540         }
2541         else
2542                 DC_LOG_WARNING("Failed to update"
2543                                 "MST allocation table for"
2544                                 "pipe idx:%d\n",
2545                                 pipe_ctx->pipe_idx);
2546 
2547         DC_LOG_MST("%s  "
2548                         "stream_count: %d: \n ",
2549                         __func__,
2550                         link->mst_stream_alloc_table.stream_count);
2551 
2552         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2553                 DC_LOG_MST("stream_enc[%d]: %p      "
2554                 "stream[%d].vcp_id: %d      "
2555                 "stream[%d].slot_count: %d\n",
2556                 i,
2557                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2558                 i,
2559                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2560                 i,
2561                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2562         }
2563 
2564         ASSERT(proposed_table.stream_count > 0);
2565 
2566         /* program DP source TX for payload */
2567         link_encoder->funcs->update_mst_stream_allocation_table(
2568                 link_encoder,
2569                 &link->mst_stream_alloc_table);
2570 
2571         /* send down message */
2572         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2573                         stream->ctx,
2574                         stream);
2575 
2576         dm_helpers_dp_mst_send_payload_allocation(
2577                         stream->ctx,
2578                         stream,
2579                         true);
2580 
2581         /* slot X.Y for only current stream */
2582         pbn_per_slot = get_pbn_per_slot(stream);
2583         pbn = get_pbn_from_timing(pipe_ctx);
2584         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2585 
2586         stream_encoder->funcs->set_mst_bandwidth(
2587                 stream_encoder,
2588                 avg_time_slots_per_mtp);
2589 
2590         return DC_OK;
2591 
2592 }
2593 
2594 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2595 {
2596         struct dc_stream_state *stream = pipe_ctx->stream;
2597         struct dc_link *link = stream->link;
2598         struct link_encoder *link_encoder = link->link_enc;
2599         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2600         struct dp_mst_stream_allocation_table proposed_table = {0};
2601         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2602         uint8_t i;
2603         bool mst_mode = (link->type == dc_connection_mst_branch);
2604         DC_LOGGER_INIT(link->ctx->logger);
2605 
2606         /* deallocate_mst_payload is called before disable link. When mode or
2607          * disable/enable monitor, new stream is created which is not in link
2608          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2609          * should not done. For new mode set, map_resources will get engine
2610          * for new stream, so stream_enc->id should be validated until here.
2611          */
2612 
2613         /* slot X.Y */
2614         stream_encoder->funcs->set_mst_bandwidth(
2615                 stream_encoder,
2616                 avg_time_slots_per_mtp);
2617 
2618         /* TODO: which component is responsible for remove payload table? */
2619         if (mst_mode) {
2620                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2621                                 stream->ctx,
2622                                 stream,
2623                                 &proposed_table,
2624                                 false)) {
2625 
2626                         update_mst_stream_alloc_table(
2627                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2628                 }
2629                 else {
2630                                 DC_LOG_WARNING("Failed to update"
2631                                                 "MST allocation table for"
2632                                                 "pipe idx:%d\n",
2633                                                 pipe_ctx->pipe_idx);
2634                 }
2635         }
2636 
2637         DC_LOG_MST("%s"
2638                         "stream_count: %d: ",
2639                         __func__,
2640                         link->mst_stream_alloc_table.stream_count);
2641 
2642         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2643                 DC_LOG_MST("stream_enc[%d]: %p      "
2644                 "stream[%d].vcp_id: %d      "
2645                 "stream[%d].slot_count: %d\n",
2646                 i,
2647                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2648                 i,
2649                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2650                 i,
2651                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2652         }
2653 
2654         link_encoder->funcs->update_mst_stream_allocation_table(
2655                 link_encoder,
2656                 &link->mst_stream_alloc_table);
2657 
2658         if (mst_mode) {
2659                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2660                         stream->ctx,
2661                         stream);
2662 
2663                 dm_helpers_dp_mst_send_payload_allocation(
2664                         stream->ctx,
2665                         stream,
2666                         false);
2667         }
2668 
2669         return DC_OK;
2670 }
2671 
2672 void core_link_enable_stream(
2673                 struct dc_state *state,
2674                 struct pipe_ctx *pipe_ctx)
2675 {
2676         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2677         struct dc_stream_state *stream = pipe_ctx->stream;
2678         enum dc_status status;
2679         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2680 
2681         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
2682                 stream->link->link_enc->funcs->setup(
2683                         stream->link->link_enc,
2684                         pipe_ctx->stream->signal);
2685                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2686                         pipe_ctx->stream_res.stream_enc,
2687                         pipe_ctx->stream_res.tg->inst,
2688                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2689         }
2690 
2691         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2692                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2693                         pipe_ctx->stream_res.stream_enc,
2694                         &stream->timing,
2695                         stream->output_color_space,
2696                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
2697 
2698         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
2699                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2700                         pipe_ctx->stream_res.stream_enc,
2701                         &stream->timing,
2702                         stream->phy_pix_clk,
2703                         pipe_ctx->stream_res.audio != NULL);
2704 
2705         pipe_ctx->stream->link->link_state_valid = true;
2706 
2707         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2708                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2709                         pipe_ctx->stream_res.stream_enc,
2710                         &stream->timing,
2711                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2712                         true : false);
2713 
2714         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2715                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2716                         pipe_ctx->stream_res.stream_enc,
2717                         &stream->timing);
2718 
2719         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2720                 bool apply_edp_fast_boot_optimization =
2721                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
2722 
2723                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2724 
2725                 resource_build_info_frame(pipe_ctx);
2726                 core_dc->hwss.update_info_frame(pipe_ctx);
2727 
2728                 /* Do not touch link on seamless boot optimization. */
2729                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
2730                         pipe_ctx->stream->dpms_off = false;
2731                         return;
2732                 }
2733 
2734                 /* eDP lit up by bios already, no need to enable again. */
2735                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2736                                         apply_edp_fast_boot_optimization) {
2737                         pipe_ctx->stream->dpms_off = false;
2738                         return;
2739                 }
2740 
2741                 if (pipe_ctx->stream->dpms_off)
2742                         return;
2743 
2744                 status = enable_link(state, pipe_ctx);
2745 
2746                 if (status != DC_OK) {
2747                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2748                         pipe_ctx->stream->link->link_index,
2749                         status);
2750 
2751                         /* Abort stream enable *unless* the failure was due to
2752                          * DP link training - some DP monitors will recover and
2753                          * show the stream anyway. But MST displays can't proceed
2754                          * without link training.
2755                          */
2756                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2757                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2758                                 BREAK_TO_DEBUGGER();
2759                                 return;
2760                         }
2761                 }
2762 
2763                 core_dc->hwss.enable_audio_stream(pipe_ctx);
2764 
2765                 /* turn off otg test pattern if enable */
2766                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2767                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2768                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2769                                         COLOR_DEPTH_UNDEFINED);
2770 
2771 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2772                 if (pipe_ctx->stream->timing.flags.DSC) {
2773                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2774                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2775                                 dp_set_dsc_enable(pipe_ctx, true);
2776                 }
2777 #endif
2778                 core_dc->hwss.enable_stream(pipe_ctx);
2779 
2780 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2781                 /* Set DPS PPS SDP (AKA "info frames") */
2782                 if (pipe_ctx->stream->timing.flags.DSC) {
2783                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2784                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2785                                 dp_set_dsc_pps_sdp(pipe_ctx, true);
2786                 }
2787 #endif
2788 
2789                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2790                         allocate_mst_payload(pipe_ctx);
2791 
2792                 core_dc->hwss.unblank_stream(pipe_ctx,
2793                         &pipe_ctx->stream->link->cur_link_settings);
2794 
2795                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2796                         enable_stream_features(pipe_ctx);
2797         }
2798 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2799         else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
2800                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2801                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
2802                         dp_set_dsc_enable(pipe_ctx, true);
2803 
2804         }
2805 #endif
2806 }
2807 
2808 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
2809 {
2810         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2811         struct dc_stream_state *stream = pipe_ctx->stream;
2812         struct dc_link *link = stream->sink->link;
2813 
2814         core_dc->hwss.blank_stream(pipe_ctx);
2815 
2816         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2817                 deallocate_mst_payload(pipe_ctx);
2818 
2819         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2820                 struct ext_hdmi_settings settings = {0};
2821                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
2822 
2823                 unsigned short masked_chip_caps = link->chip_caps &
2824                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2825                 //Need to inform that sink is going to use legacy HDMI mode.
2826                 dal_ddc_service_write_scdc_data(
2827                         link->ddc,
2828                         165000,//vbios only handles 165Mhz.
2829                         false);
2830                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2831                         /* DP159, Retimer settings */
2832                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
2833                                 write_i2c_retimer_setting(pipe_ctx,
2834                                                 false, false, &settings);
2835                         else
2836                                 write_i2c_default_retimer_setting(pipe_ctx,
2837                                                 false, false);
2838                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2839                         /* PI3EQX1204, Redriver settings */
2840                         write_i2c_redriver_setting(pipe_ctx, false);
2841                 }
2842         }
2843         core_dc->hwss.disable_stream(pipe_ctx);
2844 
2845         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
2846 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2847         if (pipe_ctx->stream->timing.flags.DSC) {
2848                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2849                         dp_set_dsc_enable(pipe_ctx, false);
2850         }
2851 #endif
2852 }
2853 
2854 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2855 {
2856         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2857 
2858         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
2859                 return;
2860 
2861         core_dc->hwss.set_avmute(pipe_ctx, enable);
2862 }
2863 
2864 /**
2865  *****************************************************************************
2866  *  Function: dc_link_enable_hpd_filter
2867  *
2868  *  @brief
2869  *     If enable is true, programs HPD filter on associated HPD line using
2870  *     delay_on_disconnect/delay_on_connect values dependent on
2871  *     link->connector_signal
2872  *
2873  *     If enable is false, programs HPD filter on associated HPD line with no
2874  *     delays on connect or disconnect
2875  *
2876  *  @param [in] link: pointer to the dc link
2877  *  @param [in] enable: boolean specifying whether to enable hbd
2878  *****************************************************************************
2879  */
2880 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2881 {
2882         struct gpio *hpd;
2883 
2884         if (enable) {
2885                 link->is_hpd_filter_disabled = false;
2886                 program_hpd_filter(link);
2887         } else {
2888                 link->is_hpd_filter_disabled = true;
2889                 /* Obtain HPD handle */
2890                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2891 
2892                 if (!hpd)
2893                         return;
2894 
2895                 /* Setup HPD filtering */
2896                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2897                         struct gpio_hpd_config config;
2898 
2899                         config.delay_on_connect = 0;
2900                         config.delay_on_disconnect = 0;
2901 
2902                         dal_irq_setup_hpd_filter(hpd, &config);
2903 
2904                         dal_gpio_close(hpd);
2905                 } else {
2906                         ASSERT_CRITICAL(false);
2907                 }
2908                 /* Release HPD handle */
2909                 dal_gpio_destroy_irq(&hpd);
2910         }
2911 }
2912 
2913 uint32_t dc_bandwidth_in_kbps_from_timing(
2914         const struct dc_crtc_timing *timing)
2915 {
2916         uint32_t bits_per_channel = 0;
2917         uint32_t kbps;
2918 
2919 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2920         if (timing->flags.DSC) {
2921                 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
2922                 kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
2923                 return kbps;
2924         }
2925 #endif
2926 
2927         switch (timing->display_color_depth) {
2928         case COLOR_DEPTH_666:
2929                 bits_per_channel = 6;
2930                 break;
2931         case COLOR_DEPTH_888:
2932                 bits_per_channel = 8;
2933                 break;
2934         case COLOR_DEPTH_101010:
2935                 bits_per_channel = 10;
2936                 break;
2937         case COLOR_DEPTH_121212:
2938                 bits_per_channel = 12;
2939                 break;
2940         case COLOR_DEPTH_141414:
2941                 bits_per_channel = 14;
2942                 break;
2943         case COLOR_DEPTH_161616:
2944                 bits_per_channel = 16;
2945                 break;
2946         default:
2947                 break;
2948         }
2949 
2950         ASSERT(bits_per_channel != 0);
2951 
2952         kbps = timing->pix_clk_100hz / 10;
2953         kbps *= bits_per_channel;
2954 
2955         if (timing->flags.Y_ONLY != 1) {
2956                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
2957                 kbps *= 3;
2958                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2959                         kbps /= 2;
2960                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2961                         kbps = kbps * 2 / 3;
2962         }
2963 
2964         return kbps;
2965 
2966 }
2967 
2968 void dc_link_set_drive_settings(struct dc *dc,
2969                                 struct link_training_settings *lt_settings,
2970                                 const struct dc_link *link)
2971 {
2972 
2973         int i;
2974 
2975         for (i = 0; i < dc->link_count; i++) {
2976                 if (dc->links[i] == link)
2977                         break;
2978         }
2979 
2980         if (i >= dc->link_count)
2981                 ASSERT_CRITICAL(false);
2982 
2983         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
2984 }
2985 
2986 void dc_link_perform_link_training(struct dc *dc,
2987                                    struct dc_link_settings *link_setting,
2988                                    bool skip_video_pattern)
2989 {
2990         int i;
2991 
2992         for (i = 0; i < dc->link_count; i++)
2993                 dc_link_dp_perform_link_training(
2994                         dc->links[i],
2995                         link_setting,
2996                         skip_video_pattern);
2997 }
2998 
2999 void dc_link_set_preferred_link_settings(struct dc *dc,
3000                                          struct dc_link_settings *link_setting,
3001                                          struct dc_link *link)
3002 {
3003         int i;
3004         struct pipe_ctx *pipe;
3005         struct dc_stream_state *link_stream;
3006         struct dc_link_settings store_settings = *link_setting;
3007 
3008         link->preferred_link_setting = store_settings;
3009 
3010         /* Retrain with preferred link settings only relevant for
3011          * DP signal type
3012          * Check for non-DP signal or if passive dongle present
3013          */
3014         if (!dc_is_dp_signal(link->connector_signal) ||
3015                 link->dongle_max_pix_clk > 0)
3016                 return;
3017 
3018         for (i = 0; i < MAX_PIPES; i++) {
3019                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3020                 if (pipe->stream && pipe->stream->link) {
3021                         if (pipe->stream->link == link) {
3022                                 link_stream = pipe->stream;
3023                                 break;
3024                         }
3025                 }
3026         }
3027 
3028         /* Stream not found */
3029         if (i == MAX_PIPES)
3030                 return;
3031 
3032         /* Cannot retrain link if backend is off */
3033         if (link_stream->dpms_off)
3034                 return;
3035 
3036         decide_link_settings(link_stream, &store_settings);
3037 
3038         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3039                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3040                 dp_retrain_link_dp_test(link, &store_settings, false);
3041 }
3042 
3043 void dc_link_set_preferred_training_settings(struct dc *dc,
3044                                                  struct dc_link_settings *link_setting,
3045                                                  struct dc_link_training_overrides *lt_overrides,
3046                                                  struct dc_link *link,
3047                                                  bool skip_immediate_retrain)
3048 {
3049         if (lt_overrides != NULL)
3050                 link->preferred_training_settings = *lt_overrides;
3051         else
3052                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3053 
3054         if (link_setting != NULL) {
3055                 link->preferred_link_setting = *link_setting;
3056         } else {
3057                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3058                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3059         }
3060 
3061         /* Retrain now, or wait until next stream update to apply */
3062         if (skip_immediate_retrain == false)
3063                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3064 }
3065 
3066 void dc_link_enable_hpd(const struct dc_link *link)
3067 {
3068         dc_link_dp_enable_hpd(link);
3069 }
3070 
3071 void dc_link_disable_hpd(const struct dc_link *link)
3072 {
3073         dc_link_dp_disable_hpd(link);
3074 }
3075 
3076 void dc_link_set_test_pattern(struct dc_link *link,
3077                               enum dp_test_pattern test_pattern,
3078                               const struct link_training_settings *p_link_settings,
3079                               const unsigned char *p_custom_pattern,
3080                               unsigned int cust_pattern_size)
3081 {
3082         if (link != NULL)
3083                 dc_link_dp_set_test_pattern(
3084                         link,
3085                         test_pattern,
3086                         p_link_settings,
3087                         p_custom_pattern,
3088                         cust_pattern_size);
3089 }
3090 
3091 uint32_t dc_link_bandwidth_kbps(
3092         const struct dc_link *link,
3093         const struct dc_link_settings *link_setting)
3094 {
3095         uint32_t link_bw_kbps =
3096                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3097 
3098         link_bw_kbps *= 8;   /* 8 bits per byte*/
3099         link_bw_kbps *= link_setting->lane_count;
3100 
3101 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3102         if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
3103                 /* Account for FEC overhead.
3104                  * We have to do it based on caps,
3105                  * and not based on FEC being set ready,
3106                  * because FEC is set ready too late in
3107                  * the process to correctly be picked up
3108                  * by mode enumeration.
3109                  *
3110                  * There's enough zeros at the end of 'kbps'
3111                  * that make the below operation 100% precise
3112                  * for our purposes.
3113                  * 'long long' makes it work even for HDMI 2.1
3114                  * max bandwidth (and much, much bigger bandwidths
3115                  * than that, actually).
3116                  *
3117                  * NOTE: Reducing link BW by 3% may not be precise
3118                  * because it may be a stream BT that increases by 3%, and so
3119                  * 1/1.03 = 0.970873 factor should have been used instead,
3120                  * but the difference is minimal and is in a safe direction,
3121                  * which all works well around potential ambiguity of DP 1.4a spec.
3122                  */
3123                 link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
3124                                                link_bw_kbps, 32);
3125         }
3126 #endif
3127 
3128         return link_bw_kbps;
3129 
3130 }
3131 
3132 const struct dc_link_settings *dc_link_get_link_cap(
3133                 const struct dc_link *link)
3134 {
3135         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3136                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3137                 return &link->preferred_link_setting;
3138         return &link->verified_link_cap;
3139 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/core/dc_link.c

DEFINITIONS
