drivers/gpu/drm/amd/display/dc/dcn10/dcn10

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   1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19  * OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * Authors: AMD
  22  *
  23  */
  24 
  25 #ifndef __DC_MEM_INPUT_DCN10_H__
  26 #define __DC_MEM_INPUT_DCN10_H__
  27 
  28 #include "hubp.h"
  29 
  30 #define TO_DCN10_HUBP(hubp)\
  31         container_of(hubp, struct dcn10_hubp, base)
  32 
  33 /* Register address initialization macro for all ASICs (including those with reduced functionality) */
  34 #define HUBP_REG_LIST_DCN(id)\
  35         SRI(DCHUBP_CNTL, HUBP, id),\
  36         SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
  37         SRI(HUBPREQ_DEBUG, HUBP, id),\
  38         SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
  39         SRI(DCSURF_TILING_CONFIG, HUBP, id),\
  40         SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
  41         SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
  42         SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
  43         SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
  44         SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
  45         SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
  46         SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
  47         SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
  48         SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
  49         SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
  50         SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
  51         SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
  52         SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
  53         SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
  54         SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
  55         SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
  56         SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
  57         SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
  58         SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
  59         SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
  60         SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
  61         SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
  62         SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
  63         SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
  64         SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
  65         SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
  66         SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
  67         SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
  68         SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
  69         SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
  70         SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
  71         SRI(HUBPRET_CONTROL, HUBPRET, id),\
  72         SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
  73         SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
  74         SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
  75         SRI(BLANK_OFFSET_0, HUBPREQ, id),\
  76         SRI(BLANK_OFFSET_1, HUBPREQ, id),\
  77         SRI(DST_DIMENSIONS, HUBPREQ, id),\
  78         SRI(DST_AFTER_SCALER, HUBPREQ, id),\
  79         SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
  80         SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
  81         SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
  82         SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
  83         SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
  84         SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
  85         SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
  86         SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
  87         SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
  88         SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
  89         SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
  90         SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
  91         SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
  92         SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
  93         SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
  94         SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
  95         SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
  96         SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
  97         SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
  98         SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
  99         SRI(HUBP_CLK_CNTL, HUBP, id)
 100 
 101 /* Register address initialization macro for ASICs with VM */
 102 #define HUBP_REG_LIST_DCN_VM(id)\
 103         SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
 104         SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
 105         SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
 106         SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
 107         SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
 108 
 109 #define HUBP_REG_LIST_DCN10(id)\
 110         HUBP_REG_LIST_DCN(id),\
 111         HUBP_REG_LIST_DCN_VM(id),\
 112         SRI(PREFETCH_SETTINS, HUBPREQ, id),\
 113         SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
 114         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
 115         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
 116         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
 117         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
 118         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
 119         SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
 120         SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
 121         SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
 122         SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
 123         SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
 124         SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
 125         SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
 126         SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
 127         SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
 128         SRI(CURSOR_SETTINS, HUBPREQ, id), \
 129         SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
 130         SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
 131         SRI(CURSOR_SIZE, CURSOR, id), \
 132         SRI(CURSOR_CONTROL, CURSOR, id), \
 133         SRI(CURSOR_POSITION, CURSOR, id), \
 134         SRI(CURSOR_HOT_SPOT, CURSOR, id), \
 135         SRI(CURSOR_DST_OFFSET, CURSOR, id)
 136 
 137 #define HUBP_COMMON_REG_VARIABLE_LIST \
 138         uint32_t DCHUBP_CNTL; \
 139         uint32_t HUBPREQ_DEBUG_DB; \
 140         uint32_t HUBPREQ_DEBUG; \
 141         uint32_t DCSURF_ADDR_CONFIG; \
 142         uint32_t DCSURF_TILING_CONFIG; \
 143         uint32_t DCSURF_SURFACE_PITCH; \
 144         uint32_t DCSURF_SURFACE_PITCH_C; \
 145         uint32_t DCSURF_SURFACE_CONFIG; \
 146         uint32_t DCSURF_FLIP_CONTROL; \
 147         uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \
 148         uint32_t DCSURF_PRI_VIEWPORT_START; \
 149         uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \
 150         uint32_t DCSURF_SEC_VIEWPORT_START; \
 151         uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \
 152         uint32_t DCSURF_PRI_VIEWPORT_START_C; \
 153         uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \
 154         uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \
 155         uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \
 156         uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \
 157         uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \
 158         uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \
 159         uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \
 160         uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \
 161         uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \
 162         uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \
 163         uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \
 164         uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \
 165         uint32_t DCSURF_SURFACE_INUSE; \
 166         uint32_t DCSURF_SURFACE_INUSE_HIGH; \
 167         uint32_t DCSURF_SURFACE_INUSE_C; \
 168         uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \
 169         uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \
 170         uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \
 171         uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \
 172         uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \
 173         uint32_t DCSURF_SURFACE_CONTROL; \
 174         uint32_t HUBPRET_CONTROL; \
 175         uint32_t DCN_EXPANSION_MODE; \
 176         uint32_t DCHUBP_REQ_SIZE_CONFIG; \
 177         uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \
 178         uint32_t BLANK_OFFSET_0; \
 179         uint32_t BLANK_OFFSET_1; \
 180         uint32_t DST_DIMENSIONS; \
 181         uint32_t DST_AFTER_SCALER; \
 182         uint32_t PREFETCH_SETTINS; \
 183         uint32_t PREFETCH_SETTINGS; \
 184         uint32_t VBLANK_PARAMETERS_0; \
 185         uint32_t REF_FREQ_TO_PIX_FREQ; \
 186         uint32_t VBLANK_PARAMETERS_1; \
 187         uint32_t VBLANK_PARAMETERS_3; \
 188         uint32_t NOM_PARAMETERS_0; \
 189         uint32_t NOM_PARAMETERS_1; \
 190         uint32_t NOM_PARAMETERS_4; \
 191         uint32_t NOM_PARAMETERS_5; \
 192         uint32_t PER_LINE_DELIVERY_PRE; \
 193         uint32_t PER_LINE_DELIVERY; \
 194         uint32_t PREFETCH_SETTINS_C; \
 195         uint32_t PREFETCH_SETTINGS_C; \
 196         uint32_t VBLANK_PARAMETERS_2; \
 197         uint32_t VBLANK_PARAMETERS_4; \
 198         uint32_t NOM_PARAMETERS_2; \
 199         uint32_t NOM_PARAMETERS_3; \
 200         uint32_t NOM_PARAMETERS_6; \
 201         uint32_t NOM_PARAMETERS_7; \
 202         uint32_t DCN_TTU_QOS_WM; \
 203         uint32_t DCN_GLOBAL_TTU_CNTL; \
 204         uint32_t DCN_SURF0_TTU_CNTL0; \
 205         uint32_t DCN_SURF0_TTU_CNTL1; \
 206         uint32_t DCN_SURF1_TTU_CNTL0; \
 207         uint32_t DCN_SURF1_TTU_CNTL1; \
 208         uint32_t DCN_CUR0_TTU_CNTL0; \
 209         uint32_t DCN_CUR0_TTU_CNTL1; \
 210         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \
 211         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \
 212         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
 213         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \
 214         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \
 215         uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \
 216         uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \
 217         uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \
 218         uint32_t DCN_VM_MX_L1_TLB_CNTL; \
 219         uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \
 220         uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \
 221         uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \
 222         uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \
 223         uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \
 224         uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \
 225         uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \
 226         uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \
 227         uint32_t CURSOR_SETTINS; \
 228         uint32_t CURSOR_SETTINGS; \
 229         uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \
 230         uint32_t CURSOR_SURFACE_ADDRESS; \
 231         uint32_t CURSOR_SIZE; \
 232         uint32_t CURSOR_CONTROL; \
 233         uint32_t CURSOR_POSITION; \
 234         uint32_t CURSOR_HOT_SPOT; \
 235         uint32_t CURSOR_DST_OFFSET; \
 236         uint32_t HUBP_CLK_CNTL
 237 
 238 #define HUBP_SF(reg_name, field_name, post_fix)\
 239         .field_name = reg_name ## __ ## field_name ## post_fix
 240 
 241 /* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
 242 /*1.x, 2.x, and 3.x*/
 243 #define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\
 244         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
 245         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
 246         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
 247         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
 248         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
 249         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
 250         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
 251         HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
 252         HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
 253         HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
 254         HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
 255         HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
 256         HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
 257         HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
 258         HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
 259         HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
 260         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
 261         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
 262         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
 263         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
 264         HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
 265         HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
 266         HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
 267         HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
 268         HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
 269         HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
 270         HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
 271         HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
 272         HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
 273         HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
 274         HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
 275         HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
 276         HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
 277         HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
 278         HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
 279         HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
 280         HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
 281         HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
 282         HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
 283         HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
 284         HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
 285         HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
 286         HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
 287         HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
 288         HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
 289         HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
 290         HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
 291         HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
 292         HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
 293         HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
 294         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
 295         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
 296         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
 297         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
 298         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
 299         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
 300         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
 301         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
 302         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
 303         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
 304         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
 305         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
 306         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
 307         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
 308         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
 309         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
 310         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
 311         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
 312         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
 313         HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
 314         HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
 315         HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
 316         HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
 317         HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
 318         HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
 319         HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
 320         HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
 321         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
 322         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
 323         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
 324         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
 325         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
 326         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
 327         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
 328         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
 329         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
 330         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
 331         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
 332         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
 333         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
 334         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
 335         HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
 336         HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
 337         HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
 338         HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
 339         HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
 340         HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
 341         HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
 342         HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
 343         HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
 344         HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
 345         HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
 346         HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
 347         HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
 348         HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
 349         HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
 350         HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
 351         HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
 352         HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
 353         HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
 354         HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
 355         HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
 356         HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
 357         HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
 358         HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
 359         HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
 360         HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
 361         HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
 362         HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
 363         HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
 364         HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
 365 /*2.x and 1.x only*/
 366 #define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\
 367         HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
 368         HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
 369         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
 370         HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
 371 
 372 /*2.x and 1.x only*/
 373 #define HUBP_MASK_SH_LIST_DCN(mask_sh)\
 374         HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)
 375 
 376 /* Mask/shift struct generation macro for ASICs with VM */
 377 #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
 378         HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
 379         HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
 380         HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
 381         HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
 382         HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
 383         HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
 384         HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
 385         HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
 386         HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
 387         HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)
 388 
 389 #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
 390         HUBP_MASK_SH_LIST_DCN(mask_sh),\
 391         HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
 392         HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
 393         HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
 394         HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
 395         HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
 396         HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
 397         HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
 398         HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
 399         HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
 400         HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
 401         HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
 402         HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
 403         HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
 404         HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\
 405         HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
 406         HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
 407         HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
 408         HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
 409         HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
 410         HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
 411         HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
 412         HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
 413         HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
 414         HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
 415         HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
 416         HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
 417         HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
 418         HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
 419         HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
 420         HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
 421         HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
 422         HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
 423         HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
 424         HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
 425         HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
 426         HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
 427         HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
 428         HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
 429 
 430 #define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
 431         type HUBP_BLANK_EN;\
 432         type HUBP_DISABLE;\
 433         type HUBP_TTU_DISABLE;\
 434         type HUBP_NO_OUTSTANDING_REQ;\
 435         type HUBP_VTG_SEL;\
 436         type HUBP_UNDERFLOW_STATUS;\
 437         type HUBP_UNDERFLOW_CLEAR;\
 438         type NUM_PIPES;\
 439         type NUM_BANKS;\
 440         type PIPE_INTERLEAVE;\
 441         type NUM_SE;\
 442         type NUM_RB_PER_SE;\
 443         type MAX_COMPRESSED_FRAGS;\
 444         type SW_MODE;\
 445         type META_LINEAR;\
 446         type RB_ALIGNED;\
 447         type PIPE_ALIGNED;\
 448         type PITCH;\
 449         type META_PITCH;\
 450         type PITCH_C;\
 451         type META_PITCH_C;\
 452         type ROTATION_ANGLE;\
 453         type H_MIRROR_EN;\
 454         type SURFACE_PIXEL_FORMAT;\
 455         type SURFACE_FLIP_TYPE;\
 456         type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\
 457         type SURFACE_FLIP_IN_STEREOSYNC;\
 458         type SURFACE_UPDATE_LOCK;\
 459         type SURFACE_FLIP_PENDING;\
 460         type PRI_VIEWPORT_WIDTH; \
 461         type PRI_VIEWPORT_HEIGHT; \
 462         type PRI_VIEWPORT_X_START; \
 463         type PRI_VIEWPORT_Y_START; \
 464         type SEC_VIEWPORT_WIDTH; \
 465         type SEC_VIEWPORT_HEIGHT; \
 466         type SEC_VIEWPORT_X_START; \
 467         type SEC_VIEWPORT_Y_START; \
 468         type PRI_VIEWPORT_WIDTH_C; \
 469         type PRI_VIEWPORT_HEIGHT_C; \
 470         type PRI_VIEWPORT_X_START_C; \
 471         type PRI_VIEWPORT_Y_START_C; \
 472         type PRIMARY_SURFACE_ADDRESS_HIGH;\
 473         type PRIMARY_SURFACE_ADDRESS;\
 474         type SECONDARY_SURFACE_ADDRESS_HIGH;\
 475         type SECONDARY_SURFACE_ADDRESS;\
 476         type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
 477         type PRIMARY_META_SURFACE_ADDRESS;\
 478         type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
 479         type SECONDARY_META_SURFACE_ADDRESS;\
 480         type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
 481         type PRIMARY_SURFACE_ADDRESS_C;\
 482         type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
 483         type PRIMARY_META_SURFACE_ADDRESS_C;\
 484         type SURFACE_INUSE_ADDRESS;\
 485         type SURFACE_INUSE_ADDRESS_HIGH;\
 486         type SURFACE_INUSE_ADDRESS_C;\
 487         type SURFACE_INUSE_ADDRESS_HIGH_C;\
 488         type SURFACE_EARLIEST_INUSE_ADDRESS;\
 489         type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\
 490         type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
 491         type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
 492         type PRIMARY_SURFACE_TMZ;\
 493         type PRIMARY_SURFACE_TMZ_C;\
 494         type SECONDARY_SURFACE_TMZ;\
 495         type SECONDARY_SURFACE_TMZ_C;\
 496         type PRIMARY_META_SURFACE_TMZ;\
 497         type PRIMARY_META_SURFACE_TMZ_C;\
 498         type SECONDARY_META_SURFACE_TMZ;\
 499         type SECONDARY_META_SURFACE_TMZ_C;\
 500         type PRIMARY_SURFACE_DCC_EN;\
 501         type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
 502         type SECONDARY_SURFACE_DCC_EN;\
 503         type SECONDARY_SURFACE_DCC_IND_64B_BLK;\
 504         type DET_BUF_PLANE1_BASE_ADDRESS;\
 505         type CROSSBAR_SRC_CB_B;\
 506         type CROSSBAR_SRC_CR_R;\
 507         type DRQ_EXPANSION_MODE;\
 508         type PRQ_EXPANSION_MODE;\
 509         type MRQ_EXPANSION_MODE;\
 510         type CRQ_EXPANSION_MODE;\
 511         type CHUNK_SIZE;\
 512         type MIN_CHUNK_SIZE;\
 513         type META_CHUNK_SIZE;\
 514         type MIN_META_CHUNK_SIZE;\
 515         type DPTE_GROUP_SIZE;\
 516         type MPTE_GROUP_SIZE;\
 517         type SWATH_HEIGHT;\
 518         type PTE_ROW_HEIGHT_LINEAR;\
 519         type CHUNK_SIZE_C;\
 520         type MIN_CHUNK_SIZE_C;\
 521         type META_CHUNK_SIZE_C;\
 522         type MIN_META_CHUNK_SIZE_C;\
 523         type DPTE_GROUP_SIZE_C;\
 524         type MPTE_GROUP_SIZE_C;\
 525         type SWATH_HEIGHT_C;\
 526         type PTE_ROW_HEIGHT_LINEAR_C;\
 527         type REFCYC_H_BLANK_END;\
 528         type DLG_V_BLANK_END;\
 529         type MIN_DST_Y_NEXT_START;\
 530         type REFCYC_PER_HTOTAL;\
 531         type REFCYC_X_AFTER_SCALER;\
 532         type DST_Y_AFTER_SCALER;\
 533         type DST_Y_PREFETCH;\
 534         type VRATIO_PREFETCH;\
 535         type DST_Y_PER_VM_VBLANK;\
 536         type DST_Y_PER_ROW_VBLANK;\
 537         type REF_FREQ_TO_PIX_FREQ;\
 538         type REFCYC_PER_PTE_GROUP_VBLANK_L;\
 539         type REFCYC_PER_META_CHUNK_VBLANK_L;\
 540         type DST_Y_PER_PTE_ROW_NOM_L;\
 541         type REFCYC_PER_PTE_GROUP_NOM_L;\
 542         type DST_Y_PER_META_ROW_NOM_L;\
 543         type REFCYC_PER_META_CHUNK_NOM_L;\
 544         type REFCYC_PER_LINE_DELIVERY_PRE_L;\
 545         type REFCYC_PER_LINE_DELIVERY_PRE_C;\
 546         type REFCYC_PER_LINE_DELIVERY_L;\
 547         type REFCYC_PER_LINE_DELIVERY_C;\
 548         type VRATIO_PREFETCH_C;\
 549         type REFCYC_PER_PTE_GROUP_VBLANK_C;\
 550         type REFCYC_PER_META_CHUNK_VBLANK_C;\
 551         type DST_Y_PER_PTE_ROW_NOM_C;\
 552         type REFCYC_PER_PTE_GROUP_NOM_C;\
 553         type DST_Y_PER_META_ROW_NOM_C;\
 554         type REFCYC_PER_META_CHUNK_NOM_C;\
 555         type QoS_LEVEL_LOW_WM;\
 556         type QoS_LEVEL_HIGH_WM;\
 557         type MIN_TTU_VBLANK;\
 558         type QoS_LEVEL_FLIP;\
 559         type REFCYC_PER_REQ_DELIVERY;\
 560         type QoS_LEVEL_FIXED;\
 561         type QoS_RAMP_DISABLE;\
 562         type REFCYC_PER_REQ_DELIVERY_PRE;\
 563         type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
 564         type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
 565         type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
 566         type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
 567         type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
 568         type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
 569         type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
 570         type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\
 571         type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
 572         type ENABLE_L1_TLB;\
 573         type SYSTEM_ACCESS_MODE;\
 574         type HUBP_CLOCK_ENABLE;\
 575         type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
 576         type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
 577         type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
 578         type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
 579         type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
 580         type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
 581         type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
 582         type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
 583         type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
 584         type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
 585         type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
 586         type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
 587         /* todo:  get these from GVM instead of reading registers ourselves */\
 588         type PAGE_DIRECTORY_ENTRY_HI32;\
 589         type PAGE_DIRECTORY_ENTRY_LO32;\
 590         type LOGICAL_PAGE_NUMBER_HI4;\
 591         type LOGICAL_PAGE_NUMBER_LO32;\
 592         type PHYSICAL_PAGE_ADDR_HI4;\
 593         type PHYSICAL_PAGE_ADDR_LO32;\
 594         type PHYSICAL_PAGE_NUMBER_MSB;\
 595         type PHYSICAL_PAGE_NUMBER_LSB;\
 596         type LOGICAL_ADDR;\
 597         type CURSOR0_DST_Y_OFFSET; \
 598         type CURSOR0_CHUNK_HDL_ADJUST; \
 599         type CURSOR_SURFACE_ADDRESS_HIGH; \
 600         type CURSOR_SURFACE_ADDRESS; \
 601         type CURSOR_WIDTH; \
 602         type CURSOR_HEIGHT; \
 603         type CURSOR_MODE; \
 604         type CURSOR_2X_MAGNIFY; \
 605         type CURSOR_PITCH; \
 606         type CURSOR_LINES_PER_CHUNK; \
 607         type CURSOR_ENABLE; \
 608         type CURSOR_X_POSITION; \
 609         type CURSOR_Y_POSITION; \
 610         type CURSOR_HOT_SPOT_X; \
 611         type CURSOR_HOT_SPOT_Y; \
 612         type CURSOR_DST_X_OFFSET; \
 613         type OUTPUT_FP
 614 
 615 #define DCN_HUBP_REG_FIELD_LIST(type) \
 616         DCN_HUBP_REG_FIELD_BASE_LIST(type);\
 617         type ALPHA_PLANE_EN
 618 
 619 struct dcn_mi_registers {
 620         HUBP_COMMON_REG_VARIABLE_LIST;
 621 };
 622 
 623 struct dcn_mi_shift {
 624         DCN_HUBP_REG_FIELD_LIST(uint8_t);
 625 };
 626 
 627 struct dcn_mi_mask {
 628         DCN_HUBP_REG_FIELD_LIST(uint32_t);
 629 };
 630 
 631 struct dcn_hubp_state {
 632         struct _vcs_dpi_display_dlg_regs_st dlg_attr;
 633         struct _vcs_dpi_display_ttu_regs_st ttu_attr;
 634         struct _vcs_dpi_display_rq_regs_st rq_regs;
 635         uint32_t pixel_format;
 636         uint32_t inuse_addr_hi;
 637         uint32_t inuse_addr_lo;
 638         uint32_t viewport_width;
 639         uint32_t viewport_height;
 640         uint32_t rotation_angle;
 641         uint32_t h_mirror_en;
 642         uint32_t sw_mode;
 643         uint32_t dcc_en;
 644         uint32_t blank_en;
 645         uint32_t underflow_status;
 646         uint32_t ttu_disable;
 647         uint32_t min_ttu_vblank;
 648         uint32_t qos_level_low_wm;
 649         uint32_t qos_level_high_wm;
 650 };
 651 
 652 struct dcn10_hubp {
 653         struct hubp base;
 654         struct dcn_hubp_state state;
 655         const struct dcn_mi_registers *hubp_regs;
 656         const struct dcn_mi_shift *hubp_shift;
 657         const struct dcn_mi_mask *hubp_mask;
 658 };
 659 
 660 void hubp1_program_surface_config(
 661         struct hubp *hubp,
 662         enum surface_pixel_format format,
 663         union dc_tiling_info *tiling_info,
 664         struct plane_size *plane_size,
 665         enum dc_rotation_angle rotation,
 666         struct dc_plane_dcc_param *dcc,
 667         bool horizontal_mirror,
 668         unsigned int compat_level);
 669 
 670 void hubp1_program_deadline(
 671                 struct hubp *hubp,
 672                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 673                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
 674 
 675 void hubp1_program_requestor(
 676                 struct hubp *hubp,
 677                 struct _vcs_dpi_display_rq_regs_st *rq_regs);
 678 
 679 void hubp1_program_pixel_format(
 680         struct hubp *hubp,
 681         enum surface_pixel_format format);
 682 
 683 void hubp1_program_size(
 684         struct hubp *hubp,
 685         enum surface_pixel_format format,
 686         const struct plane_size *plane_size,
 687         struct dc_plane_dcc_param *dcc);
 688 
 689 void hubp1_program_rotation(
 690         struct hubp *hubp,
 691         enum dc_rotation_angle rotation,
 692         bool horizontal_mirror);
 693 
 694 void hubp1_program_tiling(
 695         struct hubp *hubp,
 696         const union dc_tiling_info *info,
 697         const enum surface_pixel_format pixel_format);
 698 
 699 void hubp1_dcc_control(struct hubp *hubp,
 700                 bool enable,
 701                 enum hubp_ind_block_size independent_64b_blks);
 702 
 703 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 704 bool hubp1_program_surface_flip_and_addr(
 705         struct hubp *hubp,
 706         const struct dc_plane_address *address,
 707         bool flip_immediate);
 708 
 709 #endif
 710 bool hubp1_is_flip_pending(struct hubp *hubp);
 711 
 712 void hubp1_cursor_set_attributes(
 713                 struct hubp *hubp,
 714                 const struct dc_cursor_attributes *attr);
 715 
 716 void hubp1_cursor_set_position(
 717                 struct hubp *hubp,
 718                 const struct dc_cursor_position *pos,
 719                 const struct dc_cursor_mi_param *param);
 720 
 721 void hubp1_set_blank(struct hubp *hubp, bool blank);
 722 
 723 void min_set_viewport(struct hubp *hubp,
 724                 const struct rect *viewport,
 725                 const struct rect *viewport_c);
 726 
 727 void hubp1_clk_cntl(struct hubp *hubp, bool enable);
 728 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
 729 
 730 void dcn10_hubp_construct(
 731         struct dcn10_hubp *hubp1,
 732         struct dc_context *ctx,
 733         uint32_t inst,
 734         const struct dcn_mi_registers *hubp_regs,
 735         const struct dcn_mi_shift *hubp_shift,
 736         const struct dcn_mi_mask *hubp_mask);
 737 
 738 void hubp1_read_state(struct hubp *hubp);
 739 void hubp1_clear_underflow(struct hubp *hubp);
 740 
 741 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
 742 
 743 void hubp1_vready_workaround(struct hubp *hubp,
 744                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
 745 
 746 void hubp1_init(struct hubp *hubp);
 747 void hubp1_read_state_common(struct hubp *hubp);
 748 
 749 #endif
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root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h

INCLUDED FROM
