drivers/gpu/drm/amd/display/dc/dcn10/dcn10

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   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef _DCN10_IPP_H_
  27 #define _DCN10_IPP_H_
  28 
  29 #include "ipp.h"
  30 
  31 #define TO_DCN10_IPP(ipp)\
  32         container_of(ipp, struct dcn10_ipp, base)
  33 
  34 #define IPP_REG_LIST_DCN(id) \
  35         SRI(FORMAT_CONTROL, CNVC_CFG, id), \
  36         SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
  37         SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
  38         SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
  39         SRI(CURSOR0_COLOR1, CNVC_CUR, id)
  40 
  41 #define IPP_REG_LIST_DCN10(id) \
  42         IPP_REG_LIST_DCN(id), \
  43         SRI(CURSOR_SETTINS, HUBPREQ, id), \
  44         SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
  45         SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
  46         SRI(CURSOR_SIZE, CURSOR, id), \
  47         SRI(CURSOR_CONTROL, CURSOR, id), \
  48         SRI(CURSOR_POSITION, CURSOR, id), \
  49         SRI(CURSOR_HOT_SPOT, CURSOR, id), \
  50         SRI(CURSOR_DST_OFFSET, CURSOR, id)
  51 
  52 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  53 #define IPP_REG_LIST_DCN20(id) \
  54         IPP_REG_LIST_DCN(id), \
  55         SRI(CURSOR_SETTINGS, HUBPREQ, id), \
  56         SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
  57         SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
  58         SRI(CURSOR_SIZE, CURSOR0_, id), \
  59         SRI(CURSOR_CONTROL, CURSOR0_, id), \
  60         SRI(CURSOR_POSITION, CURSOR0_, id), \
  61         SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
  62         SRI(CURSOR_DST_OFFSET, CURSOR0_, id)
  63 #endif
  64 
  65 #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT        0x4
  66 #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK          0x00000010L
  67 #define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT        0x4
  68 #define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK          0x00000010L
  69 #define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT        0x4
  70 #define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK          0x00000010L
  71 #define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT        0x4
  72 #define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK          0x00000010L
  73 
  74 #define IPP_SF(reg_name, field_name, post_fix)\
  75         .field_name = reg_name ## __ ## field_name ## post_fix
  76 
  77 #define IPP_MASK_SH_LIST_DCN(mask_sh) \
  78         IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
  79         IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
  80         IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \
  81         IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
  82         IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
  83         IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
  84         IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
  85         IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
  86         IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh)
  87 
  88 #define IPP_MASK_SH_LIST_DCN10(mask_sh) \
  89         IPP_MASK_SH_LIST_DCN(mask_sh),\
  90         IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
  91         IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
  92         IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
  93         IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
  94         IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
  95         IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
  96         IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
  97         IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
  98         IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
  99         IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
 100         IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
 101         IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
 102         IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
 103         IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
 104         IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
 105         IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
 106         IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
 107 
 108 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 109 #define IPP_MASK_SH_LIST_DCN20(mask_sh) \
 110         IPP_MASK_SH_LIST_DCN(mask_sh), \
 111         IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
 112         IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
 113         IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
 114         IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
 115         IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
 116         IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
 117         IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
 118         IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
 119         IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
 120         IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
 121         IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
 122         IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
 123         IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
 124         IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
 125         IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
 126         IPP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
 127 #endif
 128 
 129 #define IPP_DCN10_REG_FIELD_LIST(type) \
 130         type CNVC_SURFACE_PIXEL_FORMAT; \
 131         type CNVC_BYPASS; \
 132         type ALPHA_EN; \
 133         type FORMAT_EXPANSION_MODE; \
 134         type CURSOR0_DST_Y_OFFSET; \
 135         type CURSOR0_CHUNK_HDL_ADJUST; \
 136         type CUR0_MODE; \
 137         type CUR0_COLOR0; \
 138         type CUR0_COLOR1; \
 139         type CUR0_EXPANSION_MODE; \
 140         type CURSOR_SURFACE_ADDRESS_HIGH; \
 141         type CURSOR_SURFACE_ADDRESS; \
 142         type CURSOR_WIDTH; \
 143         type CURSOR_HEIGHT; \
 144         type CURSOR_MODE; \
 145         type CURSOR_2X_MAGNIFY; \
 146         type CURSOR_PITCH; \
 147         type CURSOR_LINES_PER_CHUNK; \
 148         type CURSOR_ENABLE; \
 149         type CUR0_ENABLE; \
 150         type CURSOR_X_POSITION; \
 151         type CURSOR_Y_POSITION; \
 152         type CURSOR_HOT_SPOT_X; \
 153         type CURSOR_HOT_SPOT_Y; \
 154         type CURSOR_DST_X_OFFSET; \
 155         type OUTPUT_FP
 156 
 157 struct dcn10_ipp_shift {
 158         IPP_DCN10_REG_FIELD_LIST(uint8_t);
 159 };
 160 
 161 struct dcn10_ipp_mask {
 162         IPP_DCN10_REG_FIELD_LIST(uint32_t);
 163 };
 164 
 165 struct dcn10_ipp_registers {
 166         uint32_t CURSOR_SETTINS;
 167         uint32_t CURSOR_SETTINGS;
 168         uint32_t CNVC_SURFACE_PIXEL_FORMAT;
 169         uint32_t CURSOR0_CONTROL;
 170         uint32_t CURSOR0_COLOR0;
 171         uint32_t CURSOR0_COLOR1;
 172         uint32_t FORMAT_CONTROL;
 173         uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
 174         uint32_t CURSOR_SURFACE_ADDRESS;
 175         uint32_t CURSOR_SIZE;
 176         uint32_t CURSOR_CONTROL;
 177         uint32_t CURSOR_POSITION;
 178         uint32_t CURSOR_HOT_SPOT;
 179         uint32_t CURSOR_DST_OFFSET;
 180 };
 181 
 182 struct dcn10_ipp {
 183         struct input_pixel_processor base;
 184 
 185         const struct dcn10_ipp_registers *regs;
 186         const struct dcn10_ipp_shift *ipp_shift;
 187         const struct dcn10_ipp_mask *ipp_mask;
 188 
 189         struct dc_cursor_attributes curs_attr;
 190 };
 191 
 192 void dcn10_ipp_construct(struct dcn10_ipp *ippn10,
 193         struct dc_context *ctx,
 194         int inst,
 195         const struct dcn10_ipp_registers *regs,
 196         const struct dcn10_ipp_shift *ipp_shift,
 197         const struct dcn10_ipp_mask *ipp_mask);
 198 
 199 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 200 void dcn20_ipp_construct(struct dcn10_ipp *ippn10,
 201         struct dc_context *ctx,
 202         int inst,
 203         const struct dcn10_ipp_registers *regs,
 204         const struct dcn10_ipp_shift *ipp_shift,
 205         const struct dcn10_ipp_mask *ipp_mask);
 206 #endif
 207 
 208 #endif /* _DCN10_IPP_H_ */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h

INCLUDED FROM
