This source file includes following definitions.
- link_transmitter_control
- enable_phy_bypass_mode
- disable_prbs_symbols
- disable_prbs_mode
- program_pattern_symbols
- set_dp_phy_pattern_d102
- set_link_training_complete
- dcn10_link_encoder_set_dp_phy_pattern_training_pattern
- setup_panel_mode
- set_dp_phy_pattern_symbol_error
- set_dp_phy_pattern_prbs7
- set_dp_phy_pattern_80bit_custom
- set_dp_phy_pattern_hbr2_compliance_cp2520_2
- set_dp_phy_pattern_passthrough_mode
- get_frontend_source
- dcn10_get_dig_frontend
- enc1_configure_encoder
- dcn10_psr_program_dp_dphy_fast_training
- dcn10_psr_program_secondary_packet
- dcn10_is_dig_enabled
- link_encoder_disable
- hpd_initialize
- dcn10_link_encoder_validate_dvi_output
- dcn10_link_encoder_validate_hdmi_output
- dcn10_link_encoder_validate_dp_output
- dcn10_link_encoder_construct
- dcn10_link_encoder_validate_output_with_stream
- dcn10_link_encoder_hw_init
- dcn10_link_encoder_destroy
- dcn10_link_encoder_setup
- dcn10_link_encoder_enable_tmds_output
- dcn10_link_encoder_enable_dp_output
- dcn10_link_encoder_enable_dp_mst_output
- dcn10_link_encoder_disable_output
- dcn10_link_encoder_dp_set_lane_settings
- dcn10_link_encoder_dp_set_phy_pattern
- fill_stream_allocation_row_info
- dcn10_link_encoder_update_mst_stream_allocation_table
- dcn10_link_encoder_connect_dig_be_to_fe
- dcn10_link_encoder_enable_hpd
- dcn10_link_encoder_disable_hpd
- dcn10_aux_initialize
- dcn10_get_dig_mode
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26 #include <linux/delay.h>
27 #include <linux/slab.h>
28
29 #include "reg_helper.h"
30
31 #include "core_types.h"
32 #include "link_encoder.h"
33 #include "dcn10_link_encoder.h"
34 #include "stream_encoder.h"
35 #include "i2caux_interface.h"
36 #include "dc_bios_types.h"
37
38 #include "gpio_service_interface.h"
39
40 #define CTX \
41 enc10->base.ctx
42 #define DC_LOGGER \
43 enc10->base.ctx->logger
44
45 #define REG(reg)\
46 (enc10->link_regs->reg)
47
48 #undef FN
49 #define FN(reg_name, field_name) \
50 enc10->link_shift->field_name, enc10->link_mask->field_name
51
52
53
54
55
56
57
58 #define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
59 #define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
60 #define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
61 #define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
62 #define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
63 #define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
64 #define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
65 #define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
66
67 enum {
68 DP_MST_UPDATE_MAX_RETRY = 50
69 };
70
71 static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
72 .validate_output_with_stream =
73 dcn10_link_encoder_validate_output_with_stream,
74 .hw_init = dcn10_link_encoder_hw_init,
75 .setup = dcn10_link_encoder_setup,
76 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
77 .enable_dp_output = dcn10_link_encoder_enable_dp_output,
78 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
79 .disable_output = dcn10_link_encoder_disable_output,
80 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
81 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
82 .update_mst_stream_allocation_table =
83 dcn10_link_encoder_update_mst_stream_allocation_table,
84 .psr_program_dp_dphy_fast_training =
85 dcn10_psr_program_dp_dphy_fast_training,
86 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
87 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
88 .enable_hpd = dcn10_link_encoder_enable_hpd,
89 .disable_hpd = dcn10_link_encoder_disable_hpd,
90 .is_dig_enabled = dcn10_is_dig_enabled,
91 .get_dig_frontend = dcn10_get_dig_frontend,
92 .get_dig_mode = dcn10_get_dig_mode,
93 .destroy = dcn10_link_encoder_destroy
94 };
95
96 static enum bp_result link_transmitter_control(
97 struct dcn10_link_encoder *enc10,
98 struct bp_transmitter_control *cntl)
99 {
100 enum bp_result result;
101 struct dc_bios *bp = enc10->base.ctx->dc_bios;
102
103 result = bp->funcs->transmitter_control(bp, cntl);
104
105 return result;
106 }
107
108 static void enable_phy_bypass_mode(
109 struct dcn10_link_encoder *enc10,
110 bool enable)
111 {
112
113
114
115 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
116
117 }
118
119 static void disable_prbs_symbols(
120 struct dcn10_link_encoder *enc10,
121 bool disable)
122 {
123
124
125
126 REG_UPDATE_4(DP_DPHY_CNTL,
127 DPHY_ATEST_SEL_LANE0, disable,
128 DPHY_ATEST_SEL_LANE1, disable,
129 DPHY_ATEST_SEL_LANE2, disable,
130 DPHY_ATEST_SEL_LANE3, disable);
131 }
132
133 static void disable_prbs_mode(
134 struct dcn10_link_encoder *enc10)
135 {
136 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
137 }
138
139 static void program_pattern_symbols(
140 struct dcn10_link_encoder *enc10,
141 uint16_t pattern_symbols[8])
142 {
143
144
145
146 REG_SET_3(DP_DPHY_SYM0, 0,
147 DPHY_SYM1, pattern_symbols[0],
148 DPHY_SYM2, pattern_symbols[1],
149 DPHY_SYM3, pattern_symbols[2]);
150
151
152
153
154 REG_SET_3(DP_DPHY_SYM1, 0,
155 DPHY_SYM4, pattern_symbols[3],
156 DPHY_SYM5, pattern_symbols[4],
157 DPHY_SYM6, pattern_symbols[5]);
158
159
160
161
162 REG_SET_2(DP_DPHY_SYM2, 0,
163 DPHY_SYM7, pattern_symbols[6],
164 DPHY_SYM8, pattern_symbols[7]);
165 }
166
167 static void set_dp_phy_pattern_d102(
168 struct dcn10_link_encoder *enc10)
169 {
170
171 enable_phy_bypass_mode(enc10, false);
172
173
174
175
176
177
178 disable_prbs_symbols(enc10, true);
179
180
181 disable_prbs_mode(enc10);
182
183
184 {
185 uint16_t pattern_symbols[8] = {
186 0x2AA, 0x2AA, 0x2AA, 0x2AA,
187 0x2AA, 0x2AA, 0x2AA, 0x2AA
188 };
189
190 program_pattern_symbols(enc10, pattern_symbols);
191 }
192
193
194
195 enable_phy_bypass_mode(enc10, true);
196 }
197
198 static void set_link_training_complete(
199 struct dcn10_link_encoder *enc10,
200 bool complete)
201 {
202
203
204
205 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
206
207 }
208
209 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
210 struct link_encoder *enc,
211 uint32_t index)
212 {
213 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
214
215
216 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
217
218
219
220 set_link_training_complete(enc10, false);
221
222
223
224 enable_phy_bypass_mode(enc10, false);
225
226
227 disable_prbs_mode(enc10);
228 }
229
230 static void setup_panel_mode(
231 struct dcn10_link_encoder *enc10,
232 enum dp_panel_mode panel_mode)
233 {
234 uint32_t value;
235
236 if (!REG(DP_DPHY_INTERNAL_CTRL))
237 return;
238
239 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
240
241 switch (panel_mode) {
242 case DP_PANEL_MODE_EDP:
243 value = 0x1;
244 break;
245 case DP_PANEL_MODE_SPECIAL:
246 value = 0x11;
247 break;
248 default:
249 value = 0x0;
250 break;
251 }
252
253 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
254 }
255
256 static void set_dp_phy_pattern_symbol_error(
257 struct dcn10_link_encoder *enc10)
258 {
259
260 enable_phy_bypass_mode(enc10, false);
261
262
263 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
264
265
266
267
268 disable_prbs_symbols(enc10, false);
269
270
271 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
272 DPHY_PRBS_SEL, 1,
273 DPHY_PRBS_EN, 1);
274
275
276 enable_phy_bypass_mode(enc10, true);
277 }
278
279 static void set_dp_phy_pattern_prbs7(
280 struct dcn10_link_encoder *enc10)
281 {
282
283 enable_phy_bypass_mode(enc10, false);
284
285
286
287
288 disable_prbs_symbols(enc10, false);
289
290
291 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
292 DPHY_PRBS_SEL, 0,
293 DPHY_PRBS_EN, 1);
294
295
296 enable_phy_bypass_mode(enc10, true);
297 }
298
299 static void set_dp_phy_pattern_80bit_custom(
300 struct dcn10_link_encoder *enc10,
301 const uint8_t *pattern)
302 {
303
304 enable_phy_bypass_mode(enc10, false);
305
306
307
308 disable_prbs_symbols(enc10, true);
309
310
311
312
313 enable_phy_bypass_mode(enc10, true);
314
315
316 {
317 uint16_t pattern_symbols[8];
318
319 pattern_symbols[0] =
320 ((pattern[1] & 0x03) << 8) | pattern[0];
321 pattern_symbols[1] =
322 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
323 pattern_symbols[2] =
324 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
325 pattern_symbols[3] =
326 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
327 pattern_symbols[4] =
328 ((pattern[6] & 0x03) << 8) | pattern[5];
329 pattern_symbols[5] =
330 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
331 pattern_symbols[6] =
332 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
333 pattern_symbols[7] =
334 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
335
336 program_pattern_symbols(enc10, pattern_symbols);
337 }
338
339
340
341 enable_phy_bypass_mode(enc10, true);
342 }
343
344 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
345 struct dcn10_link_encoder *enc10,
346 unsigned int cp2520_pattern)
347 {
348
349
350
351
352
353
354
355
356
357
358
359
360 enable_phy_bypass_mode(enc10, false);
361
362
363 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
364
365
366 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
367
368
369
370
371
372 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
373 DP_IDLE_BS_INTERVAL, 0xFC,
374 DP_VBID_DISABLE, 1,
375 DP_VID_ENHANCED_FRAME_MODE, 1);
376
377
378 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
379
380
381 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
382 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
383 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
384 else
385
386 ASSERT(cp2520_pattern == 2);
387
388
389 set_link_training_complete(enc10, true);
390
391
392 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
393
394
395 enable_phy_bypass_mode(enc10, false);
396 }
397
398 static void set_dp_phy_pattern_passthrough_mode(
399 struct dcn10_link_encoder *enc10,
400 enum dp_panel_mode panel_mode)
401 {
402
403 setup_panel_mode(enc10, panel_mode);
404
405
406
407
408 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
409 DP_IDLE_BS_INTERVAL, 0x2000,
410 DP_VBID_DISABLE, 0,
411 DP_VID_ENHANCED_FRAME_MODE, 1);
412
413 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
414
415
416 set_link_training_complete(enc10, true);
417
418
419 enable_phy_bypass_mode(enc10, false);
420
421
422 disable_prbs_mode(enc10);
423 }
424
425
426 static uint8_t get_frontend_source(
427 enum engine_id engine)
428 {
429 switch (engine) {
430 case ENGINE_ID_DIGA:
431 return DCN10_DIG_FE_SOURCE_SELECT_DIGA;
432 case ENGINE_ID_DIGB:
433 return DCN10_DIG_FE_SOURCE_SELECT_DIGB;
434 case ENGINE_ID_DIGC:
435 return DCN10_DIG_FE_SOURCE_SELECT_DIGC;
436 case ENGINE_ID_DIGD:
437 return DCN10_DIG_FE_SOURCE_SELECT_DIGD;
438 case ENGINE_ID_DIGE:
439 return DCN10_DIG_FE_SOURCE_SELECT_DIGE;
440 case ENGINE_ID_DIGF:
441 return DCN10_DIG_FE_SOURCE_SELECT_DIGF;
442 case ENGINE_ID_DIGG:
443 return DCN10_DIG_FE_SOURCE_SELECT_DIGG;
444 default:
445 ASSERT_CRITICAL(false);
446 return DCN10_DIG_FE_SOURCE_SELECT_INVALID;
447 }
448 }
449
450 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
451 {
452 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
453 int32_t value;
454 enum engine_id result;
455
456 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
457
458 switch (value) {
459 case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
460 result = ENGINE_ID_DIGA;
461 break;
462 case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
463 result = ENGINE_ID_DIGB;
464 break;
465 case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
466 result = ENGINE_ID_DIGC;
467 break;
468 case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
469 result = ENGINE_ID_DIGD;
470 break;
471 case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
472 result = ENGINE_ID_DIGE;
473 break;
474 case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
475 result = ENGINE_ID_DIGF;
476 break;
477 case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
478 result = ENGINE_ID_DIGG;
479 break;
480 default:
481
482 ASSERT(false);
483 result = ENGINE_ID_UNKNOWN;
484 }
485
486 return result;
487
488 }
489
490 void enc1_configure_encoder(
491 struct dcn10_link_encoder *enc10,
492 const struct dc_link_settings *link_settings)
493 {
494
495 REG_SET(DP_CONFIG, 0,
496 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
497
498
499 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
500 }
501
502 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
503 bool exit_link_training_required)
504 {
505 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
506
507 if (exit_link_training_required)
508 REG_UPDATE(DP_DPHY_FAST_TRAINING,
509 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
510 else {
511 REG_UPDATE(DP_DPHY_FAST_TRAINING,
512 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
513
514
515
516
517
518
519
520
521
522 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
523 }
524 }
525
526 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
527 unsigned int sdp_transmit_line_num_deadline)
528 {
529 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
530
531 REG_UPDATE_2(DP_SEC_CNTL1,
532 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
533 DP_SEC_GSP0_PRIORITY, 1);
534 }
535
536 bool dcn10_is_dig_enabled(struct link_encoder *enc)
537 {
538 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
539 uint32_t value;
540
541 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
542 return value;
543 }
544
545 static void link_encoder_disable(struct dcn10_link_encoder *enc10)
546 {
547
548 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
549 DPHY_TRAINING_PATTERN_SEL, 0);
550
551
552 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
553
554
555 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
556 }
557
558 static void hpd_initialize(
559 struct dcn10_link_encoder *enc10)
560 {
561
562 enum hpd_source_id hpd_source = enc10->base.hpd_source;
563
564 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
565 }
566
567 bool dcn10_link_encoder_validate_dvi_output(
568 const struct dcn10_link_encoder *enc10,
569 enum signal_type connector_signal,
570 enum signal_type signal,
571 const struct dc_crtc_timing *crtc_timing)
572 {
573 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
574
575 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
576 max_pixel_clock *= 2;
577
578
579
580
581 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
582 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
583 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
584
585
586 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
587 return false;
588
589
590 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
591 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
592 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
593 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
594 return false;
595 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
596 return false;
597
598 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
599 return false;
600
601
602 switch (crtc_timing->display_color_depth) {
603 case COLOR_DEPTH_666:
604 case COLOR_DEPTH_888:
605 break;
606 case COLOR_DEPTH_101010:
607 case COLOR_DEPTH_161616:
608 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
609 return false;
610 break;
611 default:
612 return false;
613 }
614
615 return true;
616 }
617
618 static bool dcn10_link_encoder_validate_hdmi_output(
619 const struct dcn10_link_encoder *enc10,
620 const struct dc_crtc_timing *crtc_timing,
621 int adjusted_pix_clk_100hz)
622 {
623 enum dc_color_depth max_deep_color =
624 enc10->base.features.max_hdmi_deep_color;
625
626 if (max_deep_color < crtc_timing->display_color_depth)
627 return false;
628
629 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
630 return false;
631 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
632 return false;
633
634 if ((adjusted_pix_clk_100hz == 0) ||
635 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
636 return false;
637
638
639 if (!enc10->base.features.hdmi_ycbcr420_supported &&
640 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
641 return false;
642
643 if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
644 adjusted_pix_clk_100hz >= 3000000)
645 return false;
646 if (enc10->base.ctx->dc->debug.hdmi20_disable &&
647 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
648 return false;
649 return true;
650 }
651
652 bool dcn10_link_encoder_validate_dp_output(
653 const struct dcn10_link_encoder *enc10,
654 const struct dc_crtc_timing *crtc_timing)
655 {
656 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
657 if (!enc10->base.features.dp_ycbcr420_supported)
658 return false;
659 }
660
661 return true;
662 }
663
664 void dcn10_link_encoder_construct(
665 struct dcn10_link_encoder *enc10,
666 const struct encoder_init_data *init_data,
667 const struct encoder_feature_support *enc_features,
668 const struct dcn10_link_enc_registers *link_regs,
669 const struct dcn10_link_enc_aux_registers *aux_regs,
670 const struct dcn10_link_enc_hpd_registers *hpd_regs,
671 const struct dcn10_link_enc_shift *link_shift,
672 const struct dcn10_link_enc_mask *link_mask)
673 {
674 struct bp_encoder_cap_info bp_cap_info = {0};
675 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
676 enum bp_result result = BP_RESULT_OK;
677
678 enc10->base.funcs = &dcn10_lnk_enc_funcs;
679 enc10->base.ctx = init_data->ctx;
680 enc10->base.id = init_data->encoder;
681
682 enc10->base.hpd_source = init_data->hpd_source;
683 enc10->base.connector = init_data->connector;
684
685 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
686
687 enc10->base.features = *enc_features;
688
689 enc10->base.transmitter = init_data->transmitter;
690
691
692
693
694
695
696
697
698
699
700 enc10->base.output_signals =
701 SIGNAL_TYPE_DVI_SINGLE_LINK |
702 SIGNAL_TYPE_DVI_DUAL_LINK |
703 SIGNAL_TYPE_LVDS |
704 SIGNAL_TYPE_DISPLAY_PORT |
705 SIGNAL_TYPE_DISPLAY_PORT_MST |
706 SIGNAL_TYPE_EDP |
707 SIGNAL_TYPE_HDMI_TYPE_A;
708
709
710
711
712
713
714
715
716
717
718
719
720 enc10->link_regs = link_regs;
721 enc10->aux_regs = aux_regs;
722 enc10->hpd_regs = hpd_regs;
723 enc10->link_shift = link_shift;
724 enc10->link_mask = link_mask;
725
726 switch (enc10->base.transmitter) {
727 case TRANSMITTER_UNIPHY_A:
728 enc10->base.preferred_engine = ENGINE_ID_DIGA;
729 break;
730 case TRANSMITTER_UNIPHY_B:
731 enc10->base.preferred_engine = ENGINE_ID_DIGB;
732 break;
733 case TRANSMITTER_UNIPHY_C:
734 enc10->base.preferred_engine = ENGINE_ID_DIGC;
735 break;
736 case TRANSMITTER_UNIPHY_D:
737 enc10->base.preferred_engine = ENGINE_ID_DIGD;
738 break;
739 case TRANSMITTER_UNIPHY_E:
740 enc10->base.preferred_engine = ENGINE_ID_DIGE;
741 break;
742 case TRANSMITTER_UNIPHY_F:
743 enc10->base.preferred_engine = ENGINE_ID_DIGF;
744 break;
745 case TRANSMITTER_UNIPHY_G:
746 enc10->base.preferred_engine = ENGINE_ID_DIGG;
747 break;
748 default:
749 ASSERT_CRITICAL(false);
750 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
751 }
752
753
754 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
755
756 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
757 enc10->base.id, &bp_cap_info);
758
759
760 if (result == BP_RESULT_OK) {
761 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
762 bp_cap_info.DP_HBR2_EN;
763 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
764 bp_cap_info.DP_HBR3_EN;
765 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
766 enc10->base.features.flags.bits.DP_IS_USB_C =
767 bp_cap_info.DP_IS_USB_C;
768 } else {
769 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
770 __func__,
771 result);
772 }
773 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
774 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
775 }
776 }
777
778 bool dcn10_link_encoder_validate_output_with_stream(
779 struct link_encoder *enc,
780 const struct dc_stream_state *stream)
781 {
782 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
783 bool is_valid;
784
785 switch (stream->signal) {
786 case SIGNAL_TYPE_DVI_SINGLE_LINK:
787 case SIGNAL_TYPE_DVI_DUAL_LINK:
788 is_valid = dcn10_link_encoder_validate_dvi_output(
789 enc10,
790 stream->link->connector_signal,
791 stream->signal,
792 &stream->timing);
793 break;
794 case SIGNAL_TYPE_HDMI_TYPE_A:
795 is_valid = dcn10_link_encoder_validate_hdmi_output(
796 enc10,
797 &stream->timing,
798 stream->phy_pix_clk * 10);
799 break;
800 case SIGNAL_TYPE_DISPLAY_PORT:
801 case SIGNAL_TYPE_DISPLAY_PORT_MST:
802 is_valid = dcn10_link_encoder_validate_dp_output(
803 enc10, &stream->timing);
804 break;
805 case SIGNAL_TYPE_EDP:
806 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
807 break;
808 case SIGNAL_TYPE_VIRTUAL:
809 is_valid = true;
810 break;
811 default:
812 is_valid = false;
813 break;
814 }
815
816 return is_valid;
817 }
818
819 void dcn10_link_encoder_hw_init(
820 struct link_encoder *enc)
821 {
822 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
823 struct bp_transmitter_control cntl = { 0 };
824 enum bp_result result;
825
826 cntl.action = TRANSMITTER_CONTROL_INIT;
827 cntl.engine_id = ENGINE_ID_UNKNOWN;
828 cntl.transmitter = enc10->base.transmitter;
829 cntl.connector_obj_id = enc10->base.connector;
830 cntl.lanes_number = LANE_COUNT_FOUR;
831 cntl.coherent = false;
832 cntl.hpd_sel = enc10->base.hpd_source;
833
834 if (enc10->base.connector.id == CONNECTOR_ID_EDP)
835 cntl.signal = SIGNAL_TYPE_EDP;
836
837 result = link_transmitter_control(enc10, &cntl);
838
839 if (result != BP_RESULT_OK) {
840 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
841 __func__);
842 BREAK_TO_DEBUGGER();
843 return;
844 }
845
846 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
847 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
848
849 result = link_transmitter_control(enc10, &cntl);
850
851 ASSERT(result == BP_RESULT_OK);
852
853 }
854 dcn10_aux_initialize(enc10);
855
856
857
858
859
860
861
862 hpd_initialize(enc10);
863 }
864
865 void dcn10_link_encoder_destroy(struct link_encoder **enc)
866 {
867 kfree(TO_DCN10_LINK_ENC(*enc));
868 *enc = NULL;
869 }
870
871 void dcn10_link_encoder_setup(
872 struct link_encoder *enc,
873 enum signal_type signal)
874 {
875 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
876
877 switch (signal) {
878 case SIGNAL_TYPE_EDP:
879 case SIGNAL_TYPE_DISPLAY_PORT:
880
881 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
882 break;
883 case SIGNAL_TYPE_LVDS:
884
885 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
886 break;
887 case SIGNAL_TYPE_DVI_SINGLE_LINK:
888 case SIGNAL_TYPE_DVI_DUAL_LINK:
889
890 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
891 break;
892 case SIGNAL_TYPE_HDMI_TYPE_A:
893
894 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
895 break;
896 case SIGNAL_TYPE_DISPLAY_PORT_MST:
897
898 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
899 break;
900 default:
901 ASSERT_CRITICAL(false);
902
903 break;
904 }
905
906 }
907
908
909 void dcn10_link_encoder_enable_tmds_output(
910 struct link_encoder *enc,
911 enum clock_source_id clock_source,
912 enum dc_color_depth color_depth,
913 enum signal_type signal,
914 uint32_t pixel_clock)
915 {
916 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
917 struct bp_transmitter_control cntl = { 0 };
918 enum bp_result result;
919
920
921
922 cntl.action = TRANSMITTER_CONTROL_ENABLE;
923 cntl.engine_id = enc->preferred_engine;
924 cntl.transmitter = enc10->base.transmitter;
925 cntl.pll_id = clock_source;
926 cntl.signal = signal;
927 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
928 cntl.lanes_number = 8;
929 else
930 cntl.lanes_number = 4;
931
932 cntl.hpd_sel = enc10->base.hpd_source;
933
934 cntl.pixel_clock = pixel_clock;
935 cntl.color_depth = color_depth;
936
937 result = link_transmitter_control(enc10, &cntl);
938
939 if (result != BP_RESULT_OK) {
940 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
941 __func__);
942 BREAK_TO_DEBUGGER();
943 }
944 }
945
946
947 void dcn10_link_encoder_enable_dp_output(
948 struct link_encoder *enc,
949 const struct dc_link_settings *link_settings,
950 enum clock_source_id clock_source)
951 {
952 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
953 struct bp_transmitter_control cntl = { 0 };
954 enum bp_result result;
955
956
957
958
959
960
961
962 enc1_configure_encoder(enc10, link_settings);
963
964 cntl.action = TRANSMITTER_CONTROL_ENABLE;
965 cntl.engine_id = enc->preferred_engine;
966 cntl.transmitter = enc10->base.transmitter;
967 cntl.pll_id = clock_source;
968 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
969 cntl.lanes_number = link_settings->lane_count;
970 cntl.hpd_sel = enc10->base.hpd_source;
971 cntl.pixel_clock = link_settings->link_rate
972 * LINK_RATE_REF_FREQ_IN_KHZ;
973
974 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
975
976 result = link_transmitter_control(enc10, &cntl);
977
978 if (result != BP_RESULT_OK) {
979 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
980 __func__);
981 BREAK_TO_DEBUGGER();
982 }
983 }
984
985
986 void dcn10_link_encoder_enable_dp_mst_output(
987 struct link_encoder *enc,
988 const struct dc_link_settings *link_settings,
989 enum clock_source_id clock_source)
990 {
991 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
992 struct bp_transmitter_control cntl = { 0 };
993 enum bp_result result;
994
995
996
997
998
999
1000
1001 enc1_configure_encoder(enc10, link_settings);
1002
1003 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1004 cntl.engine_id = ENGINE_ID_UNKNOWN;
1005 cntl.transmitter = enc10->base.transmitter;
1006 cntl.pll_id = clock_source;
1007 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1008 cntl.lanes_number = link_settings->lane_count;
1009 cntl.hpd_sel = enc10->base.hpd_source;
1010 cntl.pixel_clock = link_settings->link_rate
1011 * LINK_RATE_REF_FREQ_IN_KHZ;
1012
1013 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1014
1015 result = link_transmitter_control(enc10, &cntl);
1016
1017 if (result != BP_RESULT_OK) {
1018 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1019 __func__);
1020 BREAK_TO_DEBUGGER();
1021 }
1022 }
1023
1024
1025
1026
1027 void dcn10_link_encoder_disable_output(
1028 struct link_encoder *enc,
1029 enum signal_type signal)
1030 {
1031 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1032 struct bp_transmitter_control cntl = { 0 };
1033 enum bp_result result;
1034
1035 if (!dcn10_is_dig_enabled(enc)) {
1036
1037
1038
1039 return;
1040 }
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1055 cntl.transmitter = enc10->base.transmitter;
1056 cntl.hpd_sel = enc10->base.hpd_source;
1057 cntl.signal = signal;
1058 cntl.connector_obj_id = enc10->base.connector;
1059
1060 result = link_transmitter_control(enc10, &cntl);
1061
1062 if (result != BP_RESULT_OK) {
1063 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1064 __func__);
1065 BREAK_TO_DEBUGGER();
1066 return;
1067 }
1068
1069
1070 if (dc_is_dp_signal(signal))
1071 link_encoder_disable(enc10);
1072 }
1073
1074 void dcn10_link_encoder_dp_set_lane_settings(
1075 struct link_encoder *enc,
1076 const struct link_training_settings *link_settings)
1077 {
1078 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1079 union dpcd_training_lane_set training_lane_set = { { 0 } };
1080 int32_t lane = 0;
1081 struct bp_transmitter_control cntl = { 0 };
1082
1083 if (!link_settings) {
1084 BREAK_TO_DEBUGGER();
1085 return;
1086 }
1087
1088 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1089 cntl.transmitter = enc10->base.transmitter;
1090 cntl.connector_obj_id = enc10->base.connector;
1091 cntl.lanes_number = link_settings->link_settings.lane_count;
1092 cntl.hpd_sel = enc10->base.hpd_source;
1093 cntl.pixel_clock = link_settings->link_settings.link_rate *
1094 LINK_RATE_REF_FREQ_IN_KHZ;
1095
1096 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1097
1098
1099 training_lane_set.bits.VOLTAGE_SWING_SET =
1100 link_settings->lane_settings[lane].VOLTAGE_SWING;
1101 training_lane_set.bits.PRE_EMPHASIS_SET =
1102 link_settings->lane_settings[lane].PRE_EMPHASIS;
1103
1104
1105 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1106
1107
1108
1109 training_lane_set.bits.POST_CURSOR2_SET =
1110 link_settings->lane_settings[lane].POST_CURSOR2;
1111 }
1112
1113 cntl.lane_select = lane;
1114 cntl.lane_settings = training_lane_set.raw;
1115
1116
1117 link_transmitter_control(enc10, &cntl);
1118 }
1119 }
1120
1121
1122 void dcn10_link_encoder_dp_set_phy_pattern(
1123 struct link_encoder *enc,
1124 const struct encoder_set_dp_phy_pattern_param *param)
1125 {
1126 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1127
1128 switch (param->dp_phy_pattern) {
1129 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1130 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1131 break;
1132 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1133 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1134 break;
1135 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1136 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1137 break;
1138 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1139 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1140 break;
1141 case DP_TEST_PATTERN_D102:
1142 set_dp_phy_pattern_d102(enc10);
1143 break;
1144 case DP_TEST_PATTERN_SYMBOL_ERROR:
1145 set_dp_phy_pattern_symbol_error(enc10);
1146 break;
1147 case DP_TEST_PATTERN_PRBS7:
1148 set_dp_phy_pattern_prbs7(enc10);
1149 break;
1150 case DP_TEST_PATTERN_80BIT_CUSTOM:
1151 set_dp_phy_pattern_80bit_custom(
1152 enc10, param->custom_pattern);
1153 break;
1154 case DP_TEST_PATTERN_CP2520_1:
1155 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1);
1156 break;
1157 case DP_TEST_PATTERN_CP2520_2:
1158 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2);
1159 break;
1160 case DP_TEST_PATTERN_CP2520_3:
1161 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3);
1162 break;
1163 case DP_TEST_PATTERN_VIDEO_MODE: {
1164 set_dp_phy_pattern_passthrough_mode(
1165 enc10, param->dp_panel_mode);
1166 break;
1167 }
1168
1169 default:
1170
1171 ASSERT_CRITICAL(false);
1172 break;
1173 }
1174 }
1175
1176 static void fill_stream_allocation_row_info(
1177 const struct link_mst_stream_allocation *stream_allocation,
1178 uint32_t *src,
1179 uint32_t *slots)
1180 {
1181 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1182
1183 if (stream_enc) {
1184 *src = stream_enc->id;
1185 *slots = stream_allocation->slot_count;
1186 } else {
1187 *src = 0;
1188 *slots = 0;
1189 }
1190 }
1191
1192
1193 void dcn10_link_encoder_update_mst_stream_allocation_table(
1194 struct link_encoder *enc,
1195 const struct link_mst_stream_allocation_table *table)
1196 {
1197 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1198 uint32_t value0 = 0;
1199 uint32_t value1 = 0;
1200 uint32_t value2 = 0;
1201 uint32_t slots = 0;
1202 uint32_t src = 0;
1203 uint32_t retries = 0;
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215 if (table->stream_count >= 1) {
1216 fill_stream_allocation_row_info(
1217 &table->stream_allocations[0],
1218 &src,
1219 &slots);
1220 } else {
1221 src = 0;
1222 slots = 0;
1223 }
1224
1225 REG_UPDATE_2(DP_MSE_SAT0,
1226 DP_MSE_SAT_SRC0, src,
1227 DP_MSE_SAT_SLOT_COUNT0, slots);
1228
1229 if (table->stream_count >= 2) {
1230 fill_stream_allocation_row_info(
1231 &table->stream_allocations[1],
1232 &src,
1233 &slots);
1234 } else {
1235 src = 0;
1236 slots = 0;
1237 }
1238
1239 REG_UPDATE_2(DP_MSE_SAT0,
1240 DP_MSE_SAT_SRC1, src,
1241 DP_MSE_SAT_SLOT_COUNT1, slots);
1242
1243 if (table->stream_count >= 3) {
1244 fill_stream_allocation_row_info(
1245 &table->stream_allocations[2],
1246 &src,
1247 &slots);
1248 } else {
1249 src = 0;
1250 slots = 0;
1251 }
1252
1253 REG_UPDATE_2(DP_MSE_SAT1,
1254 DP_MSE_SAT_SRC2, src,
1255 DP_MSE_SAT_SLOT_COUNT2, slots);
1256
1257 if (table->stream_count >= 4) {
1258 fill_stream_allocation_row_info(
1259 &table->stream_allocations[3],
1260 &src,
1261 &slots);
1262 } else {
1263 src = 0;
1264 slots = 0;
1265 }
1266
1267 REG_UPDATE_2(DP_MSE_SAT1,
1268 DP_MSE_SAT_SRC3, src,
1269 DP_MSE_SAT_SLOT_COUNT3, slots);
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284 REG_UPDATE(DP_MSE_SAT_UPDATE,
1285 DP_MSE_SAT_UPDATE, 1);
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297 do {
1298 udelay(10);
1299
1300 value0 = REG_READ(DP_MSE_SAT_UPDATE);
1301
1302 REG_GET(DP_MSE_SAT_UPDATE,
1303 DP_MSE_SAT_UPDATE, &value1);
1304
1305 REG_GET(DP_MSE_SAT_UPDATE,
1306 DP_MSE_16_MTP_KEEPOUT, &value2);
1307
1308
1309 if (!value1 && !value2)
1310 break;
1311 ++retries;
1312 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1313 }
1314
1315 void dcn10_link_encoder_connect_dig_be_to_fe(
1316 struct link_encoder *enc,
1317 enum engine_id engine,
1318 bool connect)
1319 {
1320 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1321 uint32_t field;
1322
1323 if (engine != ENGINE_ID_UNKNOWN) {
1324
1325 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1326
1327 if (connect)
1328 field |= get_frontend_source(engine);
1329 else
1330 field &= ~get_frontend_source(engine);
1331
1332 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1333 }
1334 }
1335
1336
1337 #define HPD_REG(reg)\
1338 (enc10->hpd_regs->reg)
1339
1340 #define HPD_REG_READ(reg_name) \
1341 dm_read_reg(CTX, HPD_REG(reg_name))
1342
1343 #define HPD_REG_UPDATE_N(reg_name, n, ...) \
1344 generic_reg_update_ex(CTX, \
1345 HPD_REG(reg_name), \
1346 n, __VA_ARGS__)
1347
1348 #define HPD_REG_UPDATE(reg_name, field, val) \
1349 HPD_REG_UPDATE_N(reg_name, 1, \
1350 FN(reg_name, field), val)
1351
1352 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
1353 {
1354 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1355
1356 HPD_REG_UPDATE(DC_HPD_CONTROL,
1357 DC_HPD_EN, 1);
1358 }
1359
1360 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
1361 {
1362 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1363
1364 HPD_REG_UPDATE(DC_HPD_CONTROL,
1365 DC_HPD_EN, 0);
1366 }
1367
1368
1369 #define AUX_REG(reg)\
1370 (enc10->aux_regs->reg)
1371
1372 #define AUX_REG_READ(reg_name) \
1373 dm_read_reg(CTX, AUX_REG(reg_name))
1374
1375 #define AUX_REG_UPDATE_N(reg_name, n, ...) \
1376 generic_reg_update_ex(CTX, \
1377 AUX_REG(reg_name), \
1378 n, __VA_ARGS__)
1379
1380 #define AUX_REG_UPDATE(reg_name, field, val) \
1381 AUX_REG_UPDATE_N(reg_name, 1, \
1382 FN(reg_name, field), val)
1383
1384 #define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \
1385 AUX_REG_UPDATE_N(reg, 2,\
1386 FN(reg, f1), v1,\
1387 FN(reg, f2), v2)
1388
1389 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
1390 {
1391 enum hpd_source_id hpd_source = enc10->base.hpd_source;
1392
1393 AUX_REG_UPDATE_2(AUX_CONTROL,
1394 AUX_HPD_SEL, hpd_source,
1395 AUX_LS_READ_EN, 0);
1396
1397
1398 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
1399 AUX_RX_RECEIVE_WINDOW, 0);
1400 }
1401
1402 enum signal_type dcn10_get_dig_mode(
1403 struct link_encoder *enc)
1404 {
1405 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1406 uint32_t value;
1407 REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
1408 switch (value) {
1409 case 1:
1410 return SIGNAL_TYPE_DISPLAY_PORT;
1411 case 2:
1412 return SIGNAL_TYPE_DVI_SINGLE_LINK;
1413 case 3:
1414 return SIGNAL_TYPE_HDMI_TYPE_A;
1415 case 5:
1416 return SIGNAL_TYPE_DISPLAY_PORT_MST;
1417 default:
1418 return SIGNAL_TYPE_NONE;
1419 }
1420 return SIGNAL_TYPE_NONE;
1421 }
1422