root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h

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   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DC_HUBBUB_DCN10_H__
  27 #define __DC_HUBBUB_DCN10_H__
  28 
  29 #include "core_types.h"
  30 #include "dchubbub.h"
  31 
  32 #define TO_DCN10_HUBBUB(hubbub)\
  33         container_of(hubbub, struct dcn10_hubbub, base)
  34 
  35 #define HUBBUB_REG_LIST_DCN_COMMON()\
  36         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
  37         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
  38         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
  39         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
  40         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
  41         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
  42         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
  43         SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
  44         SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
  45         SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
  46         SR(DCHUBBUB_ARB_SAT_LEVEL),\
  47         SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
  48         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
  49         SR(DCHUBBUB_TEST_DEBUG_INDEX), \
  50         SR(DCHUBBUB_TEST_DEBUG_DATA),\
  51         SR(DCHUBBUB_SOFT_RESET)
  52 
  53 #define HUBBUB_VM_REG_LIST() \
  54         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
  55         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
  56         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
  57         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)
  58 
  59 #define HUBBUB_SR_WATERMARK_REG_LIST()\
  60         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
  61         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
  62         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
  63         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
  64         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
  65         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
  66         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
  67         SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
  68 
  69 #define HUBBUB_REG_LIST_DCN10(id)\
  70         HUBBUB_REG_LIST_DCN_COMMON(), \
  71         HUBBUB_VM_REG_LIST(), \
  72         HUBBUB_SR_WATERMARK_REG_LIST(), \
  73         SR(DCHUBBUB_SDPIF_FB_TOP),\
  74         SR(DCHUBBUB_SDPIF_FB_BASE),\
  75         SR(DCHUBBUB_SDPIF_FB_OFFSET),\
  76         SR(DCHUBBUB_SDPIF_AGP_BASE),\
  77         SR(DCHUBBUB_SDPIF_AGP_BOT),\
  78         SR(DCHUBBUB_SDPIF_AGP_TOP)
  79 
  80 struct dcn_hubbub_registers {
  81         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
  82         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
  83         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
  84         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
  85         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
  86         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
  87         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
  88         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
  89         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
  90         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
  91         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
  92         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
  93         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
  94         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
  95         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
  96         uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
  97         uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
  98         uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
  99         uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
 100         uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
 101         uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
 102         uint32_t DCHUBBUB_ARB_SAT_LEVEL;
 103         uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
 104         uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
 105         uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
 106         uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
 107         uint32_t DCHUBBUB_TEST_DEBUG_DATA;
 108         uint32_t DCHUBBUB_SDPIF_FB_TOP;
 109         uint32_t DCHUBBUB_SDPIF_FB_BASE;
 110         uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
 111         uint32_t DCHUBBUB_SDPIF_AGP_BASE;
 112         uint32_t DCHUBBUB_SDPIF_AGP_BOT;
 113         uint32_t DCHUBBUB_SDPIF_AGP_TOP;
 114         uint32_t DCHUBBUB_CRC_CTRL;
 115         uint32_t DCHUBBUB_SOFT_RESET;
 116         uint32_t DCN_VM_FB_LOCATION_BASE;
 117         uint32_t DCN_VM_FB_LOCATION_TOP;
 118         uint32_t DCN_VM_FB_OFFSET;
 119         uint32_t DCN_VM_AGP_BOT;
 120         uint32_t DCN_VM_AGP_TOP;
 121         uint32_t DCN_VM_AGP_BASE;
 122         uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
 123         uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
 124 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 125         uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;
 126         uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;
 127         uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;
 128         uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;
 129         uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;
 130         uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;
 131         uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;
 132         uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;
 133         uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;
 134         uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;
 135         uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;
 136         uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;
 137         uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
 138         uint32_t DCHVM_CTRL0;
 139         uint32_t DCHVM_MEM_CTRL;
 140         uint32_t DCHVM_CLK_CTRL;
 141         uint32_t DCHVM_RIOMMU_CTRL0;
 142         uint32_t DCHVM_RIOMMU_STAT0;
 143 #endif
 144 };
 145 
 146 /* set field name */
 147 #define HUBBUB_SF(reg_name, field_name, post_fix)\
 148         .field_name = reg_name ## __ ## field_name ## post_fix
 149 
 150 #define HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh)\
 151                 HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
 152                 HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \
 153                 HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
 154                 HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
 155                 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
 156                 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
 157                 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
 158                 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
 159                 HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
 160                 HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
 161                 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \
 162                 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \
 163                 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \
 164                 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \
 165                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \
 166                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \
 167                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \
 168                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh)
 169 
 170 #define HUBBUB_MASK_SH_LIST_STUTTER(mask_sh) \
 171                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \
 172                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \
 173                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \
 174                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \
 175                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \
 176                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \
 177                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \
 178                 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh)
 179 
 180 #define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\
 181                 HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
 182                 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
 183                 HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
 184                 HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
 185                 HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
 186                 HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
 187                 HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
 188                 HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh)
 189 
 190 #define DCN_HUBBUB_REG_FIELD_LIST(type) \
 191                 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
 192                 type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
 193                 type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
 194                 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
 195                 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
 196                 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
 197                 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
 198                 type DCHUBBUB_ARB_SAT_LEVEL;\
 199                 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
 200                 type DCHUBBUB_GLOBAL_TIMER_REFDIV;\
 201                 type DCHUBBUB_GLOBAL_SOFT_RESET; \
 202                 type SDPIF_FB_TOP;\
 203                 type SDPIF_FB_BASE;\
 204                 type SDPIF_FB_OFFSET;\
 205                 type SDPIF_AGP_BASE;\
 206                 type SDPIF_AGP_BOT;\
 207                 type SDPIF_AGP_TOP;\
 208                 type FB_BASE;\
 209                 type FB_TOP;\
 210                 type FB_OFFSET;\
 211                 type AGP_BOT;\
 212                 type AGP_TOP;\
 213                 type AGP_BASE;\
 214                 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;\
 215                 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;\
 216                 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;\
 217                 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;\
 218                 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
 219                 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
 220                 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
 221                 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
 222                 type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
 223                 type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
 224 
 225 #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
 226                 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
 227                 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;\
 228                 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;\
 229                 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;\
 230                 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;\
 231                 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;\
 232                 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\
 233                 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
 234 
 235 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 236 #define HUBBUB_HVM_REG_FIELD_LIST(type) \
 237                 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\
 238                 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\
 239                 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\
 240                 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\
 241                 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\
 242                 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\
 243                 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\
 244                 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\
 245                 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\
 246                 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\
 247                 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\
 248                 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\
 249                 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\
 250                 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
 251                 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
 252                 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
 253                 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
 254                 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\
 255                 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\
 256                 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\
 257                 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\
 258                 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\
 259                 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\
 260                 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\
 261                 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\
 262                 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\
 263                 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\
 264                 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\
 265                 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\
 266                 type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\
 267                 type HOSTVM_INIT_REQ; \
 268                 type HVM_GPUVMRET_PWR_REQ_DIS; \
 269                 type HVM_GPUVMRET_FORCE_REQ; \
 270                 type HVM_GPUVMRET_POWER_STATUS; \
 271                 type HVM_DISPCLK_R_GATE_DIS; \
 272                 type HVM_DISPCLK_G_GATE_DIS; \
 273                 type HVM_DCFCLK_R_GATE_DIS; \
 274                 type HVM_DCFCLK_G_GATE_DIS; \
 275                 type TR_REQ_REQCLKREQ_MODE; \
 276                 type TW_RSP_COMPCLKREQ_MODE; \
 277                 type HOSTVM_PREFETCH_REQ; \
 278                 type HOSTVM_POWERSTATUS; \
 279                 type RIOMMU_ACTIVE; \
 280                 type HOSTVM_PREFETCH_DONE
 281 #endif
 282 
 283 struct dcn_hubbub_shift {
 284         DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
 285         HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
 286 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 287         HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
 288 #endif
 289 };
 290 
 291 struct dcn_hubbub_mask {
 292         DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
 293         HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
 294 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 295         HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
 296 #endif
 297 };
 298 
 299 struct dc;
 300 
 301 struct dcn10_hubbub {
 302         struct hubbub base;
 303         const struct dcn_hubbub_registers *regs;
 304         const struct dcn_hubbub_shift *shifts;
 305         const struct dcn_hubbub_mask *masks;
 306         unsigned int debug_test_index_pstate;
 307         struct dcn_watermark_set watermarks;
 308 };
 309 
 310 void hubbub1_update_dchub(
 311         struct hubbub *hubbub,
 312         struct dchub_init_data *dh_data);
 313 
 314 bool hubbub1_verify_allow_pstate_change_high(
 315         struct hubbub *hubbub);
 316 
 317 void hubbub1_wm_change_req_wa(struct hubbub *hubbub);
 318 
 319 void hubbub1_program_watermarks(
 320                 struct hubbub *hubbub,
 321                 struct dcn_watermark_set *watermarks,
 322                 unsigned int refclk_mhz,
 323                 bool safe_to_lower);
 324 
 325 void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
 326 
 327 bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);
 328 
 329 void hubbub1_toggle_watermark_change_req(
 330                 struct hubbub *hubbub);
 331 
 332 void hubbub1_wm_read_state(struct hubbub *hubbub,
 333                 struct dcn_hubbub_wm *wm);
 334 
 335 void hubbub1_soft_reset(struct hubbub *hubbub, bool reset);
 336 void hubbub1_construct(struct hubbub *hubbub,
 337         struct dc_context *ctx,
 338         const struct dcn_hubbub_registers *hubbub_regs,
 339         const struct dcn_hubbub_shift *hubbub_shift,
 340         const struct dcn_hubbub_mask *hubbub_mask);
 341 
 342 void hubbub1_program_urgent_watermarks(
 343                 struct hubbub *hubbub,
 344                 struct dcn_watermark_set *watermarks,
 345                 unsigned int refclk_mhz,
 346                 bool safe_to_lower);
 347 void hubbub1_program_stutter_watermarks(
 348                 struct hubbub *hubbub,
 349                 struct dcn_watermark_set *watermarks,
 350                 unsigned int refclk_mhz,
 351                 bool safe_to_lower);
 352 void hubbub1_program_pstate_watermarks(
 353                 struct hubbub *hubbub,
 354                 struct dcn_watermark_set *watermarks,
 355                 unsigned int refclk_mhz,
 356                 bool safe_to_lower);
 357 
 358 #endif

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