root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c

DEFINITIONS

1. dcn10_ipp_destroy
2. dcn10_ipp_construct
3. dcn20_ipp_construct

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include <linux/slab.h>
  27 
  28 #include "dm_services.h"
  29 #include "dcn10_ipp.h"
  30 #include "reg_helper.h"
  31 
  32 #define REG(reg) \
  33         (ippn10->regs->reg)
  34 
  35 #undef FN
  36 #define FN(reg_name, field_name) \
  37         ippn10->ipp_shift->field_name, ippn10->ipp_mask->field_name
  38 
  39 #define CTX \
  40         ippn10->base.ctx
  41 
  42 /*****************************************/
  43 /* Constructor, Destructor               */
  44 /*****************************************/
  45 
  46 static void dcn10_ipp_destroy(struct input_pixel_processor **ipp)
  47 {
  48         kfree(TO_DCN10_IPP(*ipp));
  49         *ipp = NULL;
  50 }
  51 
  52 static const struct ipp_funcs dcn10_ipp_funcs = {
  53         .ipp_destroy                    = dcn10_ipp_destroy
  54 };
  55 
  56 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  57 static const struct ipp_funcs dcn20_ipp_funcs = {
  58         .ipp_destroy                    = dcn10_ipp_destroy
  59 };
  60 #endif
  61 
  62 void dcn10_ipp_construct(
  63         struct dcn10_ipp *ippn10,
  64         struct dc_context *ctx,
  65         int inst,
  66         const struct dcn10_ipp_registers *regs,
  67         const struct dcn10_ipp_shift *ipp_shift,
  68         const struct dcn10_ipp_mask *ipp_mask)
  69 {
  70         ippn10->base.ctx = ctx;
  71         ippn10->base.inst = inst;
  72         ippn10->base.funcs = &dcn10_ipp_funcs;
  73 
  74         ippn10->regs = regs;
  75         ippn10->ipp_shift = ipp_shift;
  76         ippn10->ipp_mask = ipp_mask;
  77 }
  78 
  79 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  80 void dcn20_ipp_construct(
  81         struct dcn10_ipp *ippn10,
  82         struct dc_context *ctx,
  83         int inst,
  84         const struct dcn10_ipp_registers *regs,
  85         const struct dcn10_ipp_shift *ipp_shift,
  86         const struct dcn10_ipp_mask *ipp_mask)
  87 {
  88         ippn10->base.ctx = ctx;
  89         ippn10->base.inst = inst;
  90         ippn10->base.funcs = &dcn20_ipp_funcs;
  91 
  92         ippn10->regs = regs;
  93         ippn10->ipp_shift = ipp_shift;
  94         ippn10->ipp_mask = ipp_mask;
  95 }
  96 #endif