root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

/* [<][>][^][v][top][bottom][index][help] */

INCLUDED FROM


   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DC_LINK_ENCODER__DCN10_H__
  27 #define __DC_LINK_ENCODER__DCN10_H__
  28 
  29 #include "link_encoder.h"
  30 
  31 #define TO_DCN10_LINK_ENC(link_encoder)\
  32         container_of(link_encoder, struct dcn10_link_encoder, base)
  33 
  34 
  35 #define AUX_REG_LIST(id)\
  36         SRI(AUX_CONTROL, DP_AUX, id), \
  37         SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
  38 
  39 #define HPD_REG_LIST(id)\
  40         SRI(DC_HPD_CONTROL, HPD, id)
  41 
  42 #define LE_DCN_COMMON_REG_LIST(id) \
  43         SRI(DIG_BE_CNTL, DIG, id), \
  44         SRI(DIG_BE_EN_CNTL, DIG, id), \
  45         SRI(TMDS_CTL_BITS, DIG, id), \
  46         SRI(DP_CONFIG, DP, id), \
  47         SRI(DP_DPHY_CNTL, DP, id), \
  48         SRI(DP_DPHY_PRBS_CNTL, DP, id), \
  49         SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
  50         SRI(DP_DPHY_SYM0, DP, id), \
  51         SRI(DP_DPHY_SYM1, DP, id), \
  52         SRI(DP_DPHY_SYM2, DP, id), \
  53         SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
  54         SRI(DP_LINK_CNTL, DP, id), \
  55         SRI(DP_LINK_FRAMING_CNTL, DP, id), \
  56         SRI(DP_MSE_SAT0, DP, id), \
  57         SRI(DP_MSE_SAT1, DP, id), \
  58         SRI(DP_MSE_SAT2, DP, id), \
  59         SRI(DP_MSE_SAT_UPDATE, DP, id), \
  60         SRI(DP_SEC_CNTL, DP, id), \
  61         SRI(DP_VID_STREAM_CNTL, DP, id), \
  62         SRI(DP_DPHY_FAST_TRAINING, DP, id), \
  63         SRI(DP_SEC_CNTL1, DP, id), \
  64         SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
  65         SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
  66         SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
  67 
  68 
  69 #define LE_DCN10_REG_LIST(id)\
  70         LE_DCN_COMMON_REG_LIST(id)
  71 
  72 struct dcn10_link_enc_aux_registers {
  73         uint32_t AUX_CONTROL;
  74         uint32_t AUX_DPHY_RX_CONTROL0;
  75 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
  76         uint32_t AUX_DPHY_TX_CONTROL;
  77 #endif
  78 };
  79 
  80 struct dcn10_link_enc_hpd_registers {
  81         uint32_t DC_HPD_CONTROL;
  82 };
  83 
  84 struct dcn10_link_enc_registers {
  85         uint32_t DIG_BE_CNTL;
  86         uint32_t DIG_BE_EN_CNTL;
  87         uint32_t DP_CONFIG;
  88         uint32_t DP_DPHY_CNTL;
  89         uint32_t DP_DPHY_INTERNAL_CTRL;
  90         uint32_t DP_DPHY_PRBS_CNTL;
  91         uint32_t DP_DPHY_SCRAM_CNTL;
  92         uint32_t DP_DPHY_SYM0;
  93         uint32_t DP_DPHY_SYM1;
  94         uint32_t DP_DPHY_SYM2;
  95         uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
  96         uint32_t DP_LINK_CNTL;
  97         uint32_t DP_LINK_FRAMING_CNTL;
  98         uint32_t DP_MSE_SAT0;
  99         uint32_t DP_MSE_SAT1;
 100         uint32_t DP_MSE_SAT2;
 101         uint32_t DP_MSE_SAT_UPDATE;
 102         uint32_t DP_SEC_CNTL;
 103         uint32_t DP_VID_STREAM_CNTL;
 104         uint32_t DP_DPHY_FAST_TRAINING;
 105         uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
 106         uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
 107         uint32_t DP_SEC_CNTL1;
 108         uint32_t TMDS_CTL_BITS;
 109 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 110         /* DCCG  */
 111         uint32_t CLOCK_ENABLE;
 112         /* DIG */
 113         uint32_t DIG_LANE_ENABLE;
 114         /* UNIPHY */
 115         uint32_t CHANNEL_XBAR_CNTL;
 116         /* indirect registers */
 117         uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
 118         uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
 119         uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
 120         uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
 121         uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
 122         uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
 123         uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
 124         uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
 125 #endif
 126 };
 127 
 128 #define LE_SF(reg_name, field_name, post_fix)\
 129         .field_name = reg_name ## __ ## field_name ## post_fix
 130 
 131 #define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
 132         LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
 133         LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
 134         LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
 135         LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
 136         LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
 137         LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
 138         LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
 139         LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
 140         LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
 141         LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
 142         LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
 143         LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
 144         LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
 145         LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
 146         LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
 147         LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
 148         LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
 149         LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
 150         LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
 151         LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
 152         LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
 153         LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
 154         LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
 155         LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
 156         LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
 157         LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
 158         LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
 159         LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
 160         LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
 161         LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
 162         LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
 163         LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
 164         LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
 165         LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
 166         LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
 167         LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
 168         LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
 169         LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
 170         LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
 171         LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
 172         LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
 173         LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
 174         LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
 175         LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
 176         LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
 177         LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
 178         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
 179         LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
 180 
 181 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
 182         type DIG_ENABLE;\
 183         type DIG_HPD_SELECT;\
 184         type DIG_MODE;\
 185         type DIG_FE_SOURCE_SELECT;\
 186         type DPHY_BYPASS;\
 187         type DPHY_ATEST_SEL_LANE0;\
 188         type DPHY_ATEST_SEL_LANE1;\
 189         type DPHY_ATEST_SEL_LANE2;\
 190         type DPHY_ATEST_SEL_LANE3;\
 191         type DPHY_PRBS_EN;\
 192         type DPHY_PRBS_SEL;\
 193         type DPHY_SYM1;\
 194         type DPHY_SYM2;\
 195         type DPHY_SYM3;\
 196         type DPHY_SYM4;\
 197         type DPHY_SYM5;\
 198         type DPHY_SYM6;\
 199         type DPHY_SYM7;\
 200         type DPHY_SYM8;\
 201         type DPHY_SCRAMBLER_BS_COUNT;\
 202         type DPHY_SCRAMBLER_ADVANCE;\
 203         type DPHY_RX_FAST_TRAINING_CAPABLE;\
 204         type DPHY_LOAD_BS_COUNT;\
 205         type DPHY_TRAINING_PATTERN_SEL;\
 206         type DP_DPHY_HBR2_PATTERN_CONTROL;\
 207         type DP_LINK_TRAINING_COMPLETE;\
 208         type DP_IDLE_BS_INTERVAL;\
 209         type DP_VBID_DISABLE;\
 210         type DP_VID_ENHANCED_FRAME_MODE;\
 211         type DP_VID_STREAM_ENABLE;\
 212         type DP_UDI_LANES;\
 213         type DP_SEC_GSP0_LINE_NUM;\
 214         type DP_SEC_GSP0_PRIORITY;\
 215         type DP_MSE_SAT_SRC0;\
 216         type DP_MSE_SAT_SRC1;\
 217         type DP_MSE_SAT_SRC2;\
 218         type DP_MSE_SAT_SRC3;\
 219         type DP_MSE_SAT_SLOT_COUNT0;\
 220         type DP_MSE_SAT_SLOT_COUNT1;\
 221         type DP_MSE_SAT_SLOT_COUNT2;\
 222         type DP_MSE_SAT_SLOT_COUNT3;\
 223         type DP_MSE_SAT_UPDATE;\
 224         type DP_MSE_16_MTP_KEEPOUT;\
 225         type DC_HPD_EN;\
 226         type TMDS_CTL0;\
 227         type AUX_HPD_SEL;\
 228         type AUX_LS_READ_EN;\
 229         type AUX_RX_RECEIVE_WINDOW
 230 
 231 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 232 
 233 #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
 234                 type RDPCS_PHY_DP_TX0_DATA_EN;\
 235                 type RDPCS_PHY_DP_TX1_DATA_EN;\
 236                 type RDPCS_PHY_DP_TX2_DATA_EN;\
 237                 type RDPCS_PHY_DP_TX3_DATA_EN;\
 238                 type RDPCS_PHY_DP_TX0_PSTATE;\
 239                 type RDPCS_PHY_DP_TX1_PSTATE;\
 240                 type RDPCS_PHY_DP_TX2_PSTATE;\
 241                 type RDPCS_PHY_DP_TX3_PSTATE;\
 242                 type RDPCS_PHY_DP_TX0_MPLL_EN;\
 243                 type RDPCS_PHY_DP_TX1_MPLL_EN;\
 244                 type RDPCS_PHY_DP_TX2_MPLL_EN;\
 245                 type RDPCS_PHY_DP_TX3_MPLL_EN;\
 246                 type RDPCS_TX_FIFO_LANE0_EN;\
 247                 type RDPCS_TX_FIFO_LANE1_EN;\
 248                 type RDPCS_TX_FIFO_LANE2_EN;\
 249                 type RDPCS_TX_FIFO_LANE3_EN;\
 250                 type RDPCS_EXT_REFCLK_EN;\
 251                 type RDPCS_TX_FIFO_EN;\
 252                 type UNIPHY_LINK_ENABLE;\
 253                 type UNIPHY_CHANNEL0_INVERT;\
 254                 type UNIPHY_CHANNEL1_INVERT;\
 255                 type UNIPHY_CHANNEL2_INVERT;\
 256                 type UNIPHY_CHANNEL3_INVERT;\
 257                 type UNIPHY_LINK_ENABLE_HPD_MASK;\
 258                 type UNIPHY_LANE_STAGGER_DELAY;\
 259                 type RDPCS_SRAMCLK_BYPASS;\
 260                 type RDPCS_SRAMCLK_EN;\
 261                 type RDPCS_SRAMCLK_CLOCK_ON;\
 262                 type DPCS_TX_FIFO_EN;\
 263                 type RDPCS_PHY_DP_TX0_DISABLE;\
 264                 type RDPCS_PHY_DP_TX1_DISABLE;\
 265                 type RDPCS_PHY_DP_TX2_DISABLE;\
 266                 type RDPCS_PHY_DP_TX3_DISABLE;\
 267                 type RDPCS_PHY_DP_TX0_CLK_RDY;\
 268                 type RDPCS_PHY_DP_TX1_CLK_RDY;\
 269                 type RDPCS_PHY_DP_TX2_CLK_RDY;\
 270                 type RDPCS_PHY_DP_TX3_CLK_RDY;\
 271                 type RDPCS_PHY_DP_TX0_REQ;\
 272                 type RDPCS_PHY_DP_TX1_REQ;\
 273                 type RDPCS_PHY_DP_TX2_REQ;\
 274                 type RDPCS_PHY_DP_TX3_REQ;\
 275                 type RDPCS_PHY_DP_TX0_ACK;\
 276                 type RDPCS_PHY_DP_TX1_ACK;\
 277                 type RDPCS_PHY_DP_TX2_ACK;\
 278                 type RDPCS_PHY_DP_TX3_ACK;\
 279                 type RDPCS_PHY_DP_TX0_RESET;\
 280                 type RDPCS_PHY_DP_TX1_RESET;\
 281                 type RDPCS_PHY_DP_TX2_RESET;\
 282                 type RDPCS_PHY_DP_TX3_RESET;\
 283                 type RDPCS_PHY_RESET;\
 284                 type RDPCS_PHY_CR_MUX_SEL;\
 285                 type RDPCS_PHY_REF_RANGE;\
 286                 type RDPCS_PHY_DP4_POR;\
 287                 type RDPCS_SRAM_BYPASS;\
 288                 type RDPCS_SRAM_EXT_LD_DONE;\
 289                 type RDPCS_PHY_DP_TX0_TERM_CTRL;\
 290                 type RDPCS_PHY_DP_TX1_TERM_CTRL;\
 291                 type RDPCS_PHY_DP_TX2_TERM_CTRL;\
 292                 type RDPCS_PHY_DP_TX3_TERM_CTRL;\
 293                 type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
 294                 type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
 295                 type RDPCS_PHY_DP_MPLLB_SSC_EN;\
 296                 type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
 297                 type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
 298                 type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
 299                 type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
 300                 type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
 301                 type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
 302                 type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
 303                 type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
 304                 type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
 305                 type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
 306                 type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
 307                 type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
 308                 type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
 309                 type RDPCS_PHY_TX_VBOOST_LVL;\
 310                 type RDPCS_PHY_HDMIMODE_ENABLE;\
 311                 type RDPCS_PHY_DP_REF_CLK_EN;\
 312                 type RDPCS_PLL_UPDATE_DATA;\
 313                 type RDPCS_SRAM_INIT_DONE;\
 314                 type RDPCS_TX_CR_ADDR;\
 315                 type RDPCS_TX_CR_DATA;\
 316                 type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
 317                 type RDPCS_PHY_DP_MPLLB_STATE;\
 318                 type RDPCS_PHY_DP_TX0_WIDTH;\
 319                 type RDPCS_PHY_DP_TX0_RATE;\
 320                 type RDPCS_PHY_DP_TX1_WIDTH;\
 321                 type RDPCS_PHY_DP_TX1_RATE;\
 322                 type RDPCS_PHY_DP_TX2_WIDTH;\
 323                 type RDPCS_PHY_DP_TX2_RATE;\
 324                 type RDPCS_PHY_DP_TX3_WIDTH;\
 325                 type RDPCS_PHY_DP_TX3_RATE;\
 326                 type DPCS_SYMCLK_CLOCK_ON;\
 327                 type DPCS_SYMCLK_GATE_DIS;\
 328                 type DPCS_SYMCLK_EN;\
 329                 type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
 330                 type RDPCS_SYMCLK_DIV2_GATE_DIS;\
 331                 type RDPCS_SYMCLK_DIV2_EN;\
 332                 type DPCS_TX_DATA_SWAP;\
 333                 type DPCS_TX_DATA_ORDER_INVERT;\
 334                 type DPCS_TX_FIFO_RD_START_DELAY;\
 335                 type RDPCS_TX_FIFO_RD_START_DELAY;\
 336                 type RDPCS_REG_FIFO_ERROR_MASK;\
 337                 type RDPCS_TX_FIFO_ERROR_MASK;\
 338                 type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
 339                 type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
 340                 type RDPCS_PHY_DPALT_DISABLE;\
 341                 type RDPCS_PHY_DPALT_DISABLE_ACK;\
 342                 type RDPCS_PHY_DP_MPLLB_V2I;\
 343                 type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
 344                 type RDPCS_PHY_DP_MPLLB_CP_INT;\
 345                 type RDPCS_PHY_DP_MPLLB_CP_PROP;\
 346                 type RDPCS_PHY_RX_REF_LD_VAL;\
 347                 type RDPCS_PHY_RX_VCO_LD_VAL;\
 348                 type DPCSTX_DEBUG_CONFIG; \
 349                 type RDPCSTX_DEBUG_CONFIG
 350 
 351 #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
 352         type DIG_LANE0EN;\
 353         type DIG_LANE1EN;\
 354         type DIG_LANE2EN;\
 355         type DIG_LANE3EN;\
 356         type DIG_CLK_EN;\
 357         type SYMCLKA_CLOCK_ENABLE;\
 358         type DPHY_FEC_EN;\
 359         type DPHY_FEC_READY_SHADOW;\
 360         type DPHY_FEC_ACTIVE_STATUS;\
 361         DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
 362         type VCO_LD_VAL_OVRD;\
 363         type VCO_LD_VAL_OVRD_EN;\
 364         type REF_LD_VAL_OVRD;\
 365         type REF_LD_VAL_OVRD_EN;\
 366         type AUX_RX_START_WINDOW; \
 367         type AUX_RX_HALF_SYM_DETECT_LEN; \
 368         type AUX_RX_TRANSITION_FILTER_EN; \
 369         type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
 370         type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
 371         type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
 372         type AUX_RX_PHASE_DETECT_LEN; \
 373         type AUX_RX_DETECTION_THRESHOLD; \
 374         type AUX_TX_PRECHARGE_LEN; \
 375         type AUX_TX_PRECHARGE_SYMBOLS; \
 376         type AUX_MODE_DET_CHECK_DELAY;\
 377         type DPCS_DBG_CBUS_DIS
 378 #endif
 379 
 380 struct dcn10_link_enc_shift {
 381         DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 382 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 383         DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 384 #endif
 385 };
 386 
 387 struct dcn10_link_enc_mask {
 388         DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 389 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 390         DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 391 #endif
 392 };
 393 
 394 struct dcn10_link_encoder {
 395         struct link_encoder base;
 396         const struct dcn10_link_enc_registers *link_regs;
 397         const struct dcn10_link_enc_aux_registers *aux_regs;
 398         const struct dcn10_link_enc_hpd_registers *hpd_regs;
 399         const struct dcn10_link_enc_shift *link_shift;
 400         const struct dcn10_link_enc_mask *link_mask;
 401 };
 402 
 403 
 404 void dcn10_link_encoder_construct(
 405         struct dcn10_link_encoder *enc10,
 406         const struct encoder_init_data *init_data,
 407         const struct encoder_feature_support *enc_features,
 408         const struct dcn10_link_enc_registers *link_regs,
 409         const struct dcn10_link_enc_aux_registers *aux_regs,
 410         const struct dcn10_link_enc_hpd_registers *hpd_regs,
 411         const struct dcn10_link_enc_shift *link_shift,
 412         const struct dcn10_link_enc_mask *link_mask);
 413 
 414 bool dcn10_link_encoder_validate_dvi_output(
 415         const struct dcn10_link_encoder *enc10,
 416         enum signal_type connector_signal,
 417         enum signal_type signal,
 418         const struct dc_crtc_timing *crtc_timing);
 419 
 420 bool dcn10_link_encoder_validate_rgb_output(
 421         const struct dcn10_link_encoder *enc10,
 422         const struct dc_crtc_timing *crtc_timing);
 423 
 424 bool dcn10_link_encoder_validate_dp_output(
 425         const struct dcn10_link_encoder *enc10,
 426         const struct dc_crtc_timing *crtc_timing);
 427 
 428 bool dcn10_link_encoder_validate_wireless_output(
 429         const struct dcn10_link_encoder *enc10,
 430         const struct dc_crtc_timing *crtc_timing);
 431 
 432 bool dcn10_link_encoder_validate_output_with_stream(
 433         struct link_encoder *enc,
 434         const struct dc_stream_state *stream);
 435 
 436 /****************** HW programming ************************/
 437 
 438 /* initialize HW */  /* why do we initialze aux in here? */
 439 void dcn10_link_encoder_hw_init(struct link_encoder *enc);
 440 
 441 void dcn10_link_encoder_destroy(struct link_encoder **enc);
 442 
 443 /* program DIG_MODE in DIG_BE */
 444 /* TODO can this be combined with enable_output? */
 445 void dcn10_link_encoder_setup(
 446         struct link_encoder *enc,
 447         enum signal_type signal);
 448 
 449 void enc1_configure_encoder(
 450         struct dcn10_link_encoder *enc10,
 451         const struct dc_link_settings *link_settings);
 452 
 453 /* enables TMDS PHY output */
 454 /* TODO: still need depth or just pass in adjusted pixel clock? */
 455 void dcn10_link_encoder_enable_tmds_output(
 456         struct link_encoder *enc,
 457         enum clock_source_id clock_source,
 458         enum dc_color_depth color_depth,
 459         enum signal_type signal,
 460         uint32_t pixel_clock);
 461 
 462 /* enables DP PHY output */
 463 void dcn10_link_encoder_enable_dp_output(
 464         struct link_encoder *enc,
 465         const struct dc_link_settings *link_settings,
 466         enum clock_source_id clock_source);
 467 
 468 /* enables DP PHY output in MST mode */
 469 void dcn10_link_encoder_enable_dp_mst_output(
 470         struct link_encoder *enc,
 471         const struct dc_link_settings *link_settings,
 472         enum clock_source_id clock_source);
 473 
 474 /* disable PHY output */
 475 void dcn10_link_encoder_disable_output(
 476         struct link_encoder *enc,
 477         enum signal_type signal);
 478 
 479 /* set DP lane settings */
 480 void dcn10_link_encoder_dp_set_lane_settings(
 481         struct link_encoder *enc,
 482         const struct link_training_settings *link_settings);
 483 
 484 void dcn10_link_encoder_dp_set_phy_pattern(
 485         struct link_encoder *enc,
 486         const struct encoder_set_dp_phy_pattern_param *param);
 487 
 488 /* programs DP MST VC payload allocation */
 489 void dcn10_link_encoder_update_mst_stream_allocation_table(
 490         struct link_encoder *enc,
 491         const struct link_mst_stream_allocation_table *table);
 492 
 493 void dcn10_link_encoder_connect_dig_be_to_fe(
 494         struct link_encoder *enc,
 495         enum engine_id engine,
 496         bool connect);
 497 
 498 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
 499         struct link_encoder *enc,
 500         uint32_t index);
 501 
 502 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
 503 
 504 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
 505 
 506 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
 507                         bool exit_link_training_required);
 508 
 509 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
 510                         unsigned int sdp_transmit_line_num_deadline);
 511 
 512 bool dcn10_is_dig_enabled(struct link_encoder *enc);
 513 
 514 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
 515 
 516 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
 517 
 518 enum signal_type dcn10_get_dig_mode(
 519         struct link_encoder *enc);
 520 #endif /* __DC_LINK_ENCODER__DCN10_H__ */

/* [<][>][^][v][top][bottom][index][help] */