drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link

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This source file includes following definitions.
enc2_fec_set_enable
enc2_fec_set_ready
enc2_fec_is_active
link_enc2_read_state
update_cfg_data
dcn20_link_encoder_enable_dp_output
enc2_hw_init
dcn20_link_encoder_construct
   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include "reg_helper.h"
  27 
  28 #include "core_types.h"
  29 #include "link_encoder.h"
  30 #include "dcn20_link_encoder.h"
  31 #include "stream_encoder.h"
  32 #include "i2caux_interface.h"
  33 #include "dc_bios_types.h"
  34 
  35 #include "gpio_service_interface.h"
  36 
  37 #define CTX \
  38         enc10->base.ctx
  39 #define DC_LOGGER \
  40         enc10->base.ctx->logger
  41 
  42 #define REG(reg)\
  43         (enc10->link_regs->reg)
  44 
  45 #undef FN
  46 #define FN(reg_name, field_name) \
  47         enc10->link_shift->field_name, enc10->link_mask->field_name
  48 
  49 #define IND_REG(index) \
  50         (enc10->link_regs->index)
  51 
  52 
  53 static struct mpll_cfg dcn2_mpll_cfg[] = {
  54         // RBR
  55         {
  56                 .hdmimode_enable = 1,
  57                 .ref_range = 3,
  58                 .ref_clk_mpllb_div = 2,
  59                 .mpllb_ssc_en = 1,
  60                 .mpllb_div5_clk_en = 1,
  61                 .mpllb_multiplier = 226,
  62                 .mpllb_fracn_en = 1,
  63                 .mpllb_fracn_quot = 39321,
  64                 .mpllb_fracn_rem = 3,
  65                 .mpllb_fracn_den = 5,
  66                 .mpllb_ssc_up_spread = 0,
  67                 .mpllb_ssc_peak = 38221,
  68                 .mpllb_ssc_stepsize = 49314,
  69                 .mpllb_div_clk_en = 0,
  70                 .mpllb_div_multiplier = 0,
  71                 .mpllb_hdmi_div = 0,
  72                 .mpllb_tx_clk_div = 2,
  73                 .tx_vboost_lvl = 4,
  74                 .mpllb_pmix_en = 1,
  75                 .mpllb_word_div2_en = 0,
  76                 .mpllb_ana_v2i = 2,
  77                 .mpllb_ana_freq_vco = 2,
  78                 .mpllb_ana_cp_int = 7,
  79                 .mpllb_ana_cp_prop = 18,
  80                 .hdmi_pixel_clk_div = 0,
  81         },
  82         // HBR
  83         {
  84                 .hdmimode_enable = 1,
  85                 .ref_range = 3,
  86                 .ref_clk_mpllb_div = 2,
  87                 .mpllb_ssc_en = 1,
  88                 .mpllb_div5_clk_en = 1,
  89                 .mpllb_multiplier = 184,
  90                 .mpllb_fracn_en = 0,
  91                 .mpllb_fracn_quot = 0,
  92                 .mpllb_fracn_rem = 0,
  93                 .mpllb_fracn_den = 1,
  94                 .mpllb_ssc_up_spread = 0,
  95                 .mpllb_ssc_peak = 31850,
  96                 .mpllb_ssc_stepsize = 41095,
  97                 .mpllb_div_clk_en = 0,
  98                 .mpllb_div_multiplier = 0,
  99                 .mpllb_hdmi_div = 0,
 100                 .mpllb_tx_clk_div = 1,
 101                 .tx_vboost_lvl = 4,
 102                 .mpllb_pmix_en = 1,
 103                 .mpllb_word_div2_en = 0,
 104                 .mpllb_ana_v2i = 2,
 105                 .mpllb_ana_freq_vco = 3,
 106                 .mpllb_ana_cp_int = 7,
 107                 .mpllb_ana_cp_prop = 18,
 108                 .hdmi_pixel_clk_div = 0,
 109         },
 110         //HBR2
 111         {
 112                 .hdmimode_enable = 1,
 113                 .ref_range = 3,
 114                 .ref_clk_mpllb_div = 2,
 115                 .mpllb_ssc_en = 1,
 116                 .mpllb_div5_clk_en = 1,
 117                 .mpllb_multiplier = 184,
 118                 .mpllb_fracn_en = 0,
 119                 .mpllb_fracn_quot = 0,
 120                 .mpllb_fracn_rem = 0,
 121                 .mpllb_fracn_den = 1,
 122                 .mpllb_ssc_up_spread = 0,
 123                 .mpllb_ssc_peak = 31850,
 124                 .mpllb_ssc_stepsize = 41095,
 125                 .mpllb_div_clk_en = 0,
 126                 .mpllb_div_multiplier = 0,
 127                 .mpllb_hdmi_div = 0,
 128                 .mpllb_tx_clk_div = 0,
 129                 .tx_vboost_lvl = 4,
 130                 .mpllb_pmix_en = 1,
 131                 .mpllb_word_div2_en = 0,
 132                 .mpllb_ana_v2i = 2,
 133                 .mpllb_ana_freq_vco = 3,
 134                 .mpllb_ana_cp_int = 7,
 135                 .mpllb_ana_cp_prop = 18,
 136                 .hdmi_pixel_clk_div = 0,
 137         },
 138         //HBR3
 139         {
 140                 .hdmimode_enable = 1,
 141                 .ref_range = 3,
 142                 .ref_clk_mpllb_div = 2,
 143                 .mpllb_ssc_en = 1,
 144                 .mpllb_div5_clk_en = 1,
 145                 .mpllb_multiplier = 292,
 146                 .mpllb_fracn_en = 0,
 147                 .mpllb_fracn_quot = 0,
 148                 .mpllb_fracn_rem = 0,
 149                 .mpllb_fracn_den = 1,
 150                 .mpllb_ssc_up_spread = 0,
 151                 .mpllb_ssc_peak = 47776,
 152                 .mpllb_ssc_stepsize = 61642,
 153                 .mpllb_div_clk_en = 0,
 154                 .mpllb_div_multiplier = 0,
 155                 .mpllb_hdmi_div = 0,
 156                 .mpllb_tx_clk_div = 0,
 157                 .tx_vboost_lvl = 4,
 158                 .mpllb_pmix_en = 1,
 159                 .mpllb_word_div2_en = 0,
 160                 .mpllb_ana_v2i = 2,
 161                 .mpllb_ana_freq_vco = 0,
 162                 .mpllb_ana_cp_int = 7,
 163                 .mpllb_ana_cp_prop = 18,
 164                 .hdmi_pixel_clk_div = 0,
 165         },
 166 };
 167 
 168 void enc2_fec_set_enable(struct link_encoder *enc, bool enable)
 169 {
 170         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 171 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 172         DC_LOG_DSC("%s FEC at link encoder inst %d",
 173                         enable ? "Enabling" : "Disabling", enc->id.enum_id);
 174 #endif
 175         REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);
 176 }
 177 
 178 void enc2_fec_set_ready(struct link_encoder *enc, bool ready)
 179 {
 180         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 181 
 182         REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready);
 183 }
 184 
 185 bool enc2_fec_is_active(struct link_encoder *enc)
 186 {
 187         uint32_t active = 0;
 188         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 189 
 190         REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active);
 191 
 192         return (active != 0);
 193 }
 194 
 195 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 196 /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state
 197  * into a dcn_dsc_state struct.
 198  */
 199 void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
 200 {
 201         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 202 
 203         REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
 204         REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
 205         REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
 206 }
 207 #endif
 208 
 209 static bool update_cfg_data(
 210                 struct dcn10_link_encoder *enc10,
 211                 const struct dc_link_settings *link_settings,
 212                 struct dpcssys_phy_seq_cfg *cfg)
 213 {
 214         int i;
 215 
 216         cfg->load_sram_fw = false;
 217 
 218         for (i = 0; i < link_settings->lane_count; i++)
 219                 cfg->lane_en[i] = true;
 220 
 221         switch (link_settings->link_rate) {
 222         case LINK_RATE_LOW:
 223                 cfg->mpll_cfg = dcn2_mpll_cfg[0];
 224                 break;
 225         case LINK_RATE_HIGH:
 226                 cfg->mpll_cfg = dcn2_mpll_cfg[1];
 227                 break;
 228         case LINK_RATE_HIGH2:
 229                 cfg->mpll_cfg = dcn2_mpll_cfg[2];
 230                 break;
 231         case LINK_RATE_HIGH3:
 232                 cfg->mpll_cfg = dcn2_mpll_cfg[3];
 233                 break;
 234         default:
 235                 DC_LOG_ERROR("%s: No supported link rate found %X!\n",
 236                                 __func__, link_settings->link_rate);
 237                 return false;
 238         }
 239 
 240         return true;
 241 }
 242 
 243 void dcn20_link_encoder_enable_dp_output(
 244         struct link_encoder *enc,
 245         const struct dc_link_settings *link_settings,
 246         enum clock_source_id clock_source)
 247 {
 248         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 249         struct dcn20_link_encoder *enc20 = (struct dcn20_link_encoder *) enc10;
 250         struct dpcssys_phy_seq_cfg *cfg = &enc20->phy_seq_cfg;
 251 
 252         if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
 253                 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
 254                 return;
 255         }
 256 
 257         if (!update_cfg_data(enc10, link_settings, cfg))
 258                 return;
 259 
 260         enc1_configure_encoder(enc10, link_settings);
 261 
 262         dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
 263 
 264 }
 265 
 266 #define AUX_REG(reg)\
 267         (enc10->aux_regs->reg)
 268 
 269 #define AUX_REG_READ(reg_name) \
 270                 dm_read_reg(CTX, AUX_REG(reg_name))
 271 
 272 #define AUX_REG_WRITE(reg_name, val) \
 273                         dm_write_reg(CTX, AUX_REG(reg_name), val)
 274 void enc2_hw_init(struct link_encoder *enc)
 275 {
 276         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 277 
 278 /*
 279         00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
 280         01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
 281         02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
 282         03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
 283         04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
 284         05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
 285         06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
 286         07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
 287 */
 288 
 289 /*
 290         AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
 291         AUX_RX_START_WINDOW = 1 [6:4]
 292         AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
 293         AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
 294         AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
 295         AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
 296         AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
 297         AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
 298         AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
 299         AUX_RX_DETECTION_THRESHOLD [30:28] = 1
 300 */
 301         AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
 302 
 303         AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
 304 
 305         //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
 306         // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
 307         // 27MHz -> 0xd
 308         // 100MHz -> 0x32
 309         // 48MHz -> 0x18
 310 
 311         // Set TMDS_CTL0 to 1.  This is a legacy setting.
 312         REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
 313 
 314         dcn10_aux_initialize(enc10);
 315 }
 316 
 317 static const struct link_encoder_funcs dcn20_link_enc_funcs = {
 318 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 319         .read_state = link_enc2_read_state,
 320 #endif
 321         .validate_output_with_stream =
 322                 dcn10_link_encoder_validate_output_with_stream,
 323         .hw_init = enc2_hw_init,
 324         .setup = dcn10_link_encoder_setup,
 325         .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
 326         .enable_dp_output = dcn20_link_encoder_enable_dp_output,
 327         .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
 328         .disable_output = dcn10_link_encoder_disable_output,
 329         .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
 330         .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
 331         .update_mst_stream_allocation_table =
 332                 dcn10_link_encoder_update_mst_stream_allocation_table,
 333         .psr_program_dp_dphy_fast_training =
 334                         dcn10_psr_program_dp_dphy_fast_training,
 335         .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
 336         .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
 337         .enable_hpd = dcn10_link_encoder_enable_hpd,
 338         .disable_hpd = dcn10_link_encoder_disable_hpd,
 339         .is_dig_enabled = dcn10_is_dig_enabled,
 340         .destroy = dcn10_link_encoder_destroy,
 341         .fec_set_enable = enc2_fec_set_enable,
 342         .fec_set_ready = enc2_fec_set_ready,
 343         .fec_is_active = enc2_fec_is_active,
 344         .get_dig_mode = dcn10_get_dig_mode,
 345         .get_dig_frontend = dcn10_get_dig_frontend,
 346 };
 347 
 348 void dcn20_link_encoder_construct(
 349         struct dcn20_link_encoder *enc20,
 350         const struct encoder_init_data *init_data,
 351         const struct encoder_feature_support *enc_features,
 352         const struct dcn10_link_enc_registers *link_regs,
 353         const struct dcn10_link_enc_aux_registers *aux_regs,
 354         const struct dcn10_link_enc_hpd_registers *hpd_regs,
 355         const struct dcn10_link_enc_shift *link_shift,
 356         const struct dcn10_link_enc_mask *link_mask)
 357 {
 358         struct bp_encoder_cap_info bp_cap_info = {0};
 359         const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
 360         enum bp_result result = BP_RESULT_OK;
 361         struct dcn10_link_encoder *enc10 = &enc20->enc10;
 362 
 363         enc10->base.funcs = &dcn20_link_enc_funcs;
 364         enc10->base.ctx = init_data->ctx;
 365         enc10->base.id = init_data->encoder;
 366 
 367         enc10->base.hpd_source = init_data->hpd_source;
 368         enc10->base.connector = init_data->connector;
 369 
 370         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 371 
 372         enc10->base.features = *enc_features;
 373 
 374         enc10->base.transmitter = init_data->transmitter;
 375 
 376         /* set the flag to indicate whether driver poll the I2C data pin
 377          * while doing the DP sink detect
 378          */
 379 
 380 /*      if (dal_adapter_service_is_feature_supported(as,
 381                 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 382                 enc10->base.features.flags.bits.
 383                         DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 384 
 385         enc10->base.output_signals =
 386                 SIGNAL_TYPE_DVI_SINGLE_LINK |
 387                 SIGNAL_TYPE_DVI_DUAL_LINK |
 388                 SIGNAL_TYPE_LVDS |
 389                 SIGNAL_TYPE_DISPLAY_PORT |
 390                 SIGNAL_TYPE_DISPLAY_PORT_MST |
 391                 SIGNAL_TYPE_EDP |
 392                 SIGNAL_TYPE_HDMI_TYPE_A;
 393 
 394         /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 395          * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 396          * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 397          * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 398          * Prefer DIG assignment is decided by board design.
 399          * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 400          * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 401          * By this, adding DIGG should not hurt DCE 8.0.
 402          * This will let DCE 8.1 share DCE 8.0 as much as possible
 403          */
 404 
 405         enc10->link_regs = link_regs;
 406         enc10->aux_regs = aux_regs;
 407         enc10->hpd_regs = hpd_regs;
 408         enc10->link_shift = link_shift;
 409         enc10->link_mask = link_mask;
 410 
 411         switch (enc10->base.transmitter) {
 412         case TRANSMITTER_UNIPHY_A:
 413                 enc10->base.preferred_engine = ENGINE_ID_DIGA;
 414         break;
 415         case TRANSMITTER_UNIPHY_B:
 416                 enc10->base.preferred_engine = ENGINE_ID_DIGB;
 417         break;
 418         case TRANSMITTER_UNIPHY_C:
 419                 enc10->base.preferred_engine = ENGINE_ID_DIGC;
 420         break;
 421         case TRANSMITTER_UNIPHY_D:
 422                 enc10->base.preferred_engine = ENGINE_ID_DIGD;
 423         break;
 424         case TRANSMITTER_UNIPHY_E:
 425                 enc10->base.preferred_engine = ENGINE_ID_DIGE;
 426         break;
 427         case TRANSMITTER_UNIPHY_F:
 428                 enc10->base.preferred_engine = ENGINE_ID_DIGF;
 429         break;
 430         case TRANSMITTER_UNIPHY_G:
 431                 enc10->base.preferred_engine = ENGINE_ID_DIGG;
 432         break;
 433         default:
 434                 ASSERT_CRITICAL(false);
 435                 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 436         }
 437 
 438         /* default to one to mirror Windows behavior */
 439         enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
 440 
 441         result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
 442                                                 enc10->base.id, &bp_cap_info);
 443 
 444         /* Override features with DCE-specific values */
 445         if (result == BP_RESULT_OK) {
 446                 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
 447                                 bp_cap_info.DP_HBR2_EN;
 448                 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
 449                                 bp_cap_info.DP_HBR3_EN;
 450                 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
 451                 enc10->base.features.flags.bits.DP_IS_USB_C =
 452                                 bp_cap_info.DP_IS_USB_C;
 453         } else {
 454                 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 455                                 __func__,
 456                                 result);
 457         }
 458         if (enc10->base.ctx->dc->debug.hdmi20_disable) {
 459                 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
 460         }
 461 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c

DEFINITIONS
