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24 #ifndef __DC_DWBC_DCN20_H__
25 #define __DC_DWBC_DCN20_H__
26
27 #define TO_DCN20_DWBC(dwbc_base) \
28 container_of(dwbc_base, struct dcn20_dwbc, base)
29
30
31 #define BASE_INNER(seg) \
32 DCE_BASE__INST0_SEG ## seg
33
34 #define BASE(seg) \
35 BASE_INNER(seg)
36
37 #define SR(reg_name)\
38 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
39 mm ## reg_name
40
41 #define SRI(reg_name, block, id)\
42 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
43 mm ## block ## id ## _ ## reg_name
44
45 #define SRI2(reg_name, block, id)\
46 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
47 mm ## reg_name
48
49 #define SRII(reg_name, block, id)\
50 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
51 mm ## block ## id ## _ ## reg_name
52
53 #define SF(reg_name, field_name, post_fix)\
54 .field_name = reg_name ## __ ## field_name ## post_fix
55
56
57 #define DWBC_COMMON_REG_LIST_DCN2_0(inst) \
58 SRI2(WB_ENABLE, CNV, inst),\
59 SRI2(WB_EC_CONFIG, CNV, inst),\
60 SRI2(CNV_MODE, CNV, inst),\
61 SRI2(CNV_WINDOW_START, CNV, inst),\
62 SRI2(CNV_WINDOW_SIZE, CNV, inst),\
63 SRI2(CNV_UPDATE, CNV, inst),\
64 SRI2(CNV_SOURCE_SIZE, CNV, inst),\
65 SRI2(CNV_TEST_CNTL, CNV, inst),\
66 SRI2(CNV_TEST_CRC_RED, CNV, inst),\
67 SRI2(CNV_TEST_CRC_GREEN, CNV, inst),\
68 SRI2(CNV_TEST_CRC_BLUE, CNV, inst),\
69 SRI2(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\
70 SRI2(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\
71 SRI2(WBSCL_MODE, WBSCL, inst),\
72 SRI2(WBSCL_TAP_CONTROL, WBSCL, inst),\
73 SRI2(WBSCL_DEST_SIZE, WBSCL, inst),\
74 SRI2(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\
75 SRI2(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\
76 SRI2(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\
77 SRI2(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\
78 SRI2(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\
79 SRI2(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\
80 SRI2(WBSCL_ROUND_OFFSET, WBSCL, inst),\
81 SRI2(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\
82 SRI2(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\
83 SRI2(WBSCL_TEST_CNTL, WBSCL, inst),\
84 SRI2(WBSCL_TEST_CRC_RED, WBSCL, inst),\
85 SRI2(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\
86 SRI2(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\
87 SRI2(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\
88 SRI2(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\
89 SRI2(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\
90 SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\
91 SRI2(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\
92 SRI2(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\
93 SRI2(WBSCL_DEBUG, WBSCL, inst),\
94 SRI2(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\
95 SRI2(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\
96 SRI2(WB_DEBUG_CTRL, CNV, inst),\
97 SRI2(WB_DBG_MODE, CNV, inst),\
98 SRI2(WB_HW_DEBUG, CNV, inst),\
99 SRI2(CNV_TEST_DEBUG_INDEX, CNV, inst),\
100 SRI2(CNV_TEST_DEBUG_DATA, CNV, inst),\
101 SRI2(WB_SOFT_RESET, CNV, inst),\
102 SRI2(WB_WARM_UP_MODE_CTL1, CNV, inst),\
103 SRI2(WB_WARM_UP_MODE_CTL2, CNV, inst)
104
105 #define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
106 SF(WB_ENABLE, WB_ENABLE, mask_sh),\
107 SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
108 SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
109 SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
110 SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
111 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
113 SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
114 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
115 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
116 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\
117 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\
118 SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\
119 SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\
120 SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
121 SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\
122 SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
123 SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
124 SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
125 SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
126 SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
127 SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
128 SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
129 SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
130 SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
131 SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
132 SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\
133 SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\
134 SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\
135 SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\
136 SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\
137 SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\
138 SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\
139 SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\
140 SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\
141 SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\
142 SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\
143 SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\
144 SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\
145 SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\
146 SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\
147 SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\
148 SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\
149 SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\
150 SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\
151 SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\
152 SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\
153 SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\
154 SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
155 SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\
156 SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\
157 SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
158 SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
159 SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\
160 SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\
161 SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\
162 SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
163 SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\
164 SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\
165 SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
166 SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
167 SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
168 SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
169 SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
170 SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\
171 SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\
172 SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\
173 SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\
174 SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\
175 SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\
176 SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\
177 SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\
178 SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\
179 SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\
180 SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\
181 SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\
182 SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\
183 SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\
184 SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\
185 SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\
186 SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\
187 SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\
188 SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\
189 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\
190 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\
191 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\
192 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\
193 SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\
194 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\
195 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\
196 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\
197 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\
198 SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\
199 SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\
200 SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\
201 SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\
202 SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\
203 SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\
204 SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\
205 SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\
206 SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\
207 SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\
208 SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\
209 SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\
210 SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\
211 SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\
212 SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\
213 SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\
214 SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\
215 SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\
216 SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\
217 SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\
218 SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\
219 SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\
220 SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\
221 SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\
222 SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\
223 SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\
224 SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\
225 SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\
226 SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\
227 SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)
228
229 #define DWBC_REG_FIELD_LIST_DCN2_0(type) \
230 type WB_ENABLE;\
231 type DISPCLK_R_WB_GATE_DIS;\
232 type DISPCLK_G_WB_GATE_DIS;\
233 type DISPCLK_G_WBSCL_GATE_DIS;\
234 type WB_TEST_CLK_SEL;\
235 type WB_LB_LS_DIS;\
236 type WB_LB_SD_DIS;\
237 type WB_LUT_LS_DIS;\
238 type WBSCL_LB_MEM_PWR_MODE_SEL;\
239 type WBSCL_LB_MEM_PWR_DIS;\
240 type WBSCL_LB_MEM_PWR_FORCE;\
241 type WBSCL_LB_MEM_PWR_STATE;\
242 type WB_RAM_PW_SAVE_MODE;\
243 type WBSCL_LUT_MEM_PWR_STATE;\
244 type CNV_OUT_BPC;\
245 type CNV_FRAME_CAPTURE_RATE;\
246 type CNV_WINDOW_CROP_EN;\
247 type CNV_STEREO_TYPE;\
248 type CNV_INTERLACED_MODE;\
249 type CNV_EYE_SELECTION;\
250 type CNV_STEREO_POLARITY;\
251 type CNV_INTERLACED_FIELD_ORDER;\
252 type CNV_STEREO_SPLIT;\
253 type CNV_NEW_CONTENT;\
254 type CNV_FRAME_CAPTURE_EN_CURRENT;\
255 type CNV_FRAME_CAPTURE_EN;\
256 type CNV_WINDOW_START_X;\
257 type CNV_WINDOW_START_Y;\
258 type CNV_WINDOW_WIDTH;\
259 type CNV_WINDOW_HEIGHT;\
260 type CNV_UPDATE_PENDING;\
261 type CNV_UPDATE_TAKEN;\
262 type CNV_UPDATE_LOCK;\
263 type CNV_SOURCE_WIDTH;\
264 type CNV_SOURCE_HEIGHT;\
265 type CNV_TEST_CRC_EN;\
266 type CNV_TEST_CRC_CONT_EN;\
267 type CNV_TEST_CRC_RED_MASK;\
268 type CNV_TEST_CRC_SIG_RED;\
269 type CNV_TEST_CRC_GREEN_MASK;\
270 type CNV_TEST_CRC_SIG_GREEN;\
271 type CNV_TEST_CRC_BLUE_MASK;\
272 type CNV_TEST_CRC_SIG_BLUE;\
273 type WB_DEBUG_EN;\
274 type WB_DEBUG_SEL;\
275 type WB_DBG_MODE_EN;\
276 type WB_DBG_DIN_FMT;\
277 type WB_DBG_36MODE;\
278 type WB_DBG_CMAP;\
279 type WB_DBG_PXLRATE_ERROR;\
280 type WB_DBG_SOURCE_WIDTH;\
281 type WB_HW_DEBUG;\
282 type CNV_TEST_DEBUG_INDEX;\
283 type CNV_TEST_DEBUG_WRITE_EN;\
284 type CNV_TEST_DEBUG_DATA;\
285 type WB_SOFT_RESET;\
286 type WBSCL_COEF_RAM_TAP_PAIR_IDX;\
287 type WBSCL_COEF_RAM_PHASE;\
288 type WBSCL_COEF_RAM_FILTER_TYPE;\
289 type WBSCL_COEF_RAM_SEL;\
290 type WBSCL_COEF_RAM_SEL_CURRENT;\
291 type WBSCL_COEF_RAM_RD_SEL;\
292 type WBSCL_COEF_RAM_EVEN_TAP_COEF;\
293 type WBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\
294 type WBSCL_COEF_RAM_ODD_TAP_COEF;\
295 type WBSCL_COEF_RAM_ODD_TAP_COEF_EN;\
296 type WBSCL_MODE;\
297 type WBSCL_OUT_BIT_DEPTH;\
298 type WBSCL_V_NUM_OF_TAPS_Y_RGB;\
299 type WBSCL_V_NUM_OF_TAPS_CBCR;\
300 type WBSCL_H_NUM_OF_TAPS_Y_RGB;\
301 type WBSCL_H_NUM_OF_TAPS_CBCR;\
302 type WBSCL_DEST_HEIGHT;\
303 type WBSCL_DEST_WIDTH;\
304 type WBSCL_H_SCALE_RATIO;\
305 type WBSCL_H_INIT_FRAC_Y_RGB;\
306 type WBSCL_H_INIT_INT_Y_RGB;\
307 type WBSCL_H_INIT_FRAC_CBCR;\
308 type WBSCL_H_INIT_INT_CBCR;\
309 type WBSCL_V_SCALE_RATIO;\
310 type WBSCL_V_INIT_FRAC_Y_RGB;\
311 type WBSCL_V_INIT_INT_Y_RGB;\
312 type WBSCL_V_INIT_FRAC_CBCR;\
313 type WBSCL_V_INIT_INT_CBCR;\
314 type WBSCL_ROUND_OFFSET_Y_RGB;\
315 type WBSCL_ROUND_OFFSET_CBCR;\
316 type WBSCL_DATA_OVERFLOW_FLAG;\
317 type WBSCL_DATA_OVERFLOW_ACK;\
318 type WBSCL_DATA_OVERFLOW_MASK;\
319 type WBSCL_DATA_OVERFLOW_INT_STATUS;\
320 type WBSCL_DATA_OVERFLOW_INT_TYPE;\
321 type WBSCL_HOST_CONFLICT_FLAG;\
322 type WBSCL_HOST_CONFLICT_ACK;\
323 type WBSCL_HOST_CONFLICT_MASK;\
324 type WBSCL_HOST_CONFLICT_INT_STATUS;\
325 type WBSCL_HOST_CONFLICT_INT_TYPE;\
326 type WBSCL_TEST_CRC_EN;\
327 type WBSCL_TEST_CRC_CONT_EN;\
328 type WBSCL_TEST_CRC_RED_MASK;\
329 type WBSCL_TEST_CRC_SIG_RED;\
330 type WBSCL_TEST_CRC_GREEN_MASK;\
331 type WBSCL_TEST_CRC_SIG_GREEN;\
332 type WBSCL_TEST_CRC_BLUE_MASK;\
333 type WBSCL_TEST_CRC_SIG_BLUE;\
334 type WBSCL_BACKPRESSURE_CNT_EN;\
335 type WB_MCIF_Y_MAX_BACKPRESSURE;\
336 type WB_MCIF_C_MAX_BACKPRESSURE;\
337 type WBSCL_CLAMP_UPPER_Y_RGB;\
338 type WBSCL_CLAMP_LOWER_Y_RGB;\
339 type WBSCL_CLAMP_UPPER_CBCR;\
340 type WBSCL_CLAMP_LOWER_CBCR;\
341 type WBSCL_OUTSIDE_PIX_STRATEGY;\
342 type WBSCL_BLACK_COLOR_G_Y;\
343 type WBSCL_BLACK_COLOR_B_CB;\
344 type WBSCL_BLACK_COLOR_R_CR;\
345 type WBSCL_DEBUG;\
346 type WBSCL_TEST_DEBUG_INDEX;\
347 type WBSCL_TEST_DEBUG_WRITE_EN;\
348 type WBSCL_TEST_DEBUG_DATA;\
349 type WIDTH_WARMUP;\
350 type HEIGHT_WARMUP;\
351 type GMC_WARM_UP_ENABLE;\
352 type DATA_VALUE_WARMUP;\
353 type MODE_WARMUP;\
354 type DATA_DEPTH_WARMUP; \
355
356 struct dcn20_dwbc_registers {
357
358 uint32_t WB_ENABLE;
359 uint32_t WB_EC_CONFIG;
360 uint32_t CNV_MODE;
361 uint32_t CNV_WINDOW_START;
362 uint32_t CNV_WINDOW_SIZE;
363 uint32_t CNV_UPDATE;
364 uint32_t CNV_SOURCE_SIZE;
365 uint32_t CNV_TEST_CNTL;
366 uint32_t CNV_TEST_CRC_RED;
367 uint32_t CNV_TEST_CRC_GREEN;
368 uint32_t CNV_TEST_CRC_BLUE;
369 uint32_t WB_DEBUG_CTRL;
370 uint32_t WB_DBG_MODE;
371 uint32_t WB_HW_DEBUG;
372 uint32_t CNV_TEST_DEBUG_INDEX;
373 uint32_t CNV_TEST_DEBUG_DATA;
374 uint32_t WB_SOFT_RESET;
375 uint32_t WBSCL_COEF_RAM_SELECT;
376 uint32_t WBSCL_COEF_RAM_TAP_DATA;
377 uint32_t WBSCL_MODE;
378 uint32_t WBSCL_TAP_CONTROL;
379 uint32_t WBSCL_DEST_SIZE;
380 uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO;
381 uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB;
382 uint32_t WBSCL_HORZ_FILTER_INIT_CBCR;
383 uint32_t WBSCL_VERT_FILTER_SCALE_RATIO;
384 uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB;
385 uint32_t WBSCL_VERT_FILTER_INIT_CBCR;
386 uint32_t WBSCL_ROUND_OFFSET;
387 uint32_t WBSCL_OVERFLOW_STATUS;
388 uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS;
389 uint32_t WBSCL_TEST_CNTL;
390 uint32_t WBSCL_TEST_CRC_RED;
391 uint32_t WBSCL_TEST_CRC_GREEN;
392 uint32_t WBSCL_TEST_CRC_BLUE;
393 uint32_t WBSCL_BACKPRESSURE_CNT_EN;
394 uint32_t WB_MCIF_BACKPRESSURE_CNT;
395 uint32_t WBSCL_CLAMP_Y_RGB;
396 uint32_t WBSCL_CLAMP_CBCR;
397 uint32_t WBSCL_OUTSIDE_PIX_STRATEGY;
398 uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR;
399 uint32_t WBSCL_DEBUG;
400 uint32_t WBSCL_TEST_DEBUG_INDEX;
401 uint32_t WBSCL_TEST_DEBUG_DATA;
402 uint32_t WB_WARM_UP_MODE_CTL1;
403 uint32_t WB_WARM_UP_MODE_CTL2;
404 };
405
406
407 struct dcn20_dwbc_mask {
408 DWBC_REG_FIELD_LIST_DCN2_0(uint32_t)
409 };
410
411 struct dcn20_dwbc_shift {
412 DWBC_REG_FIELD_LIST_DCN2_0(uint8_t)
413 };
414
415 struct dcn20_dwbc {
416 struct dwbc base;
417 const struct dcn20_dwbc_registers *dwbc_regs;
418 const struct dcn20_dwbc_shift *dwbc_shift;
419 const struct dcn20_dwbc_mask *dwbc_mask;
420 };
421
422 void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
423 struct dc_context *ctx,
424 const struct dcn20_dwbc_registers *dwbc_regs,
425 const struct dcn20_dwbc_shift *dwbc_shift,
426 const struct dcn20_dwbc_mask *dwbc_mask,
427 int inst);
428
429 bool dwb2_disable(struct dwbc *dwbc);
430
431 bool dwb2_is_enabled(struct dwbc *dwbc);
432
433 void dwb2_set_stereo(struct dwbc *dwbc,
434 struct dwb_stereo_params *stereo_params);
435
436 void dwb2_set_new_content(struct dwbc *dwbc,
437 bool is_new_content);
438
439 void dwb2_config_dwb_cnv(struct dwbc *dwbc,
440 struct dc_dwb_params *params);
441
442 void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
443
444 bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
445 uint32_t src_height,
446 uint32_t dest_height,
447 struct scaling_taps num_taps,
448 enum dwb_subsample_position subsample_position);
449
450 bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
451 uint32_t src_width,
452 uint32_t dest_width,
453 struct scaling_taps num_taps);
454
455
456 #endif
457
458