root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h

INCLUDED FROM

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DC_HUBBUB_DCN20_H__
  27 #define __DC_HUBBUB_DCN20_H__
  28 
  29 #include "dcn10/dcn10_hubbub.h"
  30 #include "dcn20_vmid.h"
  31 
  32 #define HUBBUB_REG_LIST_DCN20_COMMON()\
  33         HUBBUB_REG_LIST_DCN_COMMON(), \
  34         SR(DCHUBBUB_CRC_CTRL), \
  35         SR(DCN_VM_FB_LOCATION_BASE),\
  36         SR(DCN_VM_FB_LOCATION_TOP),\
  37         SR(DCN_VM_FB_OFFSET),\
  38         SR(DCN_VM_AGP_BOT),\
  39         SR(DCN_VM_AGP_TOP),\
  40         SR(DCN_VM_AGP_BASE)
  41 
  42 #define TO_DCN20_HUBBUB(hubbub)\
  43         container_of(hubbub, struct dcn20_hubbub, base)
  44 
  45 #define HUBBUB_REG_LIST_DCN20_COMMON()\
  46         HUBBUB_REG_LIST_DCN_COMMON(), \
  47         SR(DCHUBBUB_CRC_CTRL), \
  48         SR(DCN_VM_FB_LOCATION_BASE),\
  49         SR(DCN_VM_FB_LOCATION_TOP),\
  50         SR(DCN_VM_FB_OFFSET),\
  51         SR(DCN_VM_AGP_BOT),\
  52         SR(DCN_VM_AGP_TOP),\
  53         SR(DCN_VM_AGP_BASE)
  54 
  55 #define HUBBUB_REG_LIST_DCN20(id)\
  56         HUBBUB_REG_LIST_DCN20_COMMON(), \
  57         HUBBUB_SR_WATERMARK_REG_LIST(), \
  58         HUBBUB_VM_REG_LIST(),\
  59         SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\
  60         SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB)
  61 
  62 
  63 #define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\
  64         HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
  65         HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
  66         HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
  67         HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \
  68         HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
  69         HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
  70         HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
  71         HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
  72         HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
  73         HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \
  74         HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh)
  75 
  76 struct dcn20_hubbub {
  77         struct hubbub base;
  78         const struct dcn_hubbub_registers *regs;
  79         const struct dcn_hubbub_shift *shifts;
  80         const struct dcn_hubbub_mask *masks;
  81         unsigned int debug_test_index_pstate;
  82         struct dcn_watermark_set watermarks;
  83         struct dcn20_vmid vmid[16];
  84 };
  85 
  86 void hubbub2_construct(struct dcn20_hubbub *hubbub,
  87         struct dc_context *ctx,
  88         const struct dcn_hubbub_registers *hubbub_regs,
  89         const struct dcn_hubbub_shift *hubbub_shift,
  90         const struct dcn_hubbub_mask *hubbub_mask);
  91 
  92 bool hubbub2_dcc_support_swizzle(
  93                 enum swizzle_mode_values swizzle,
  94                 unsigned int bytes_per_element,
  95                 enum segment_order *segment_order_horz,
  96                 enum segment_order *segment_order_vert);
  97 
  98 bool hubbub2_dcc_support_pixel_format(
  99                 enum surface_pixel_format format,
 100                 unsigned int *bytes_per_element);
 101 
 102 bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
 103                 const struct dc_dcc_surface_param *input,
 104                 struct dc_surface_dcc_cap *output);
 105 
 106 bool hubbub2_initialize_vmids(struct hubbub *hubbub,
 107                 const struct dc_dcc_surface_param *input,
 108                 struct dc_surface_dcc_cap *output);
 109 
 110 int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
 111                 struct dcn_hubbub_phys_addr_config *pa_config);
 112 void hubbub2_init_vm_ctx(struct hubbub *hubbub,
 113                 struct dcn_hubbub_virt_addr_config *va_config,
 114                 int vmid);
 115 void hubbub2_update_dchub(struct hubbub *hubbub,
 116                 struct dchub_init_data *dh_data);
 117 
 118 void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
 119                 unsigned int dccg_ref_freq_inKhz,
 120                 unsigned int *dchub_ref_freq_inKhz);
 121 
 122 void hubbub2_wm_read_state(struct hubbub *hubbub,
 123                 struct dcn_hubbub_wm *wm);
 124 
 125 #endif