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26 #ifndef __DC_MEM_INPUT_DCN20_H__
27 #define __DC_MEM_INPUT_DCN20_H__
28
29 #include "../dcn10/dcn10_hubp.h"
30
31 #define TO_DCN20_HUBP(hubp)\
32 container_of(hubp, struct dcn20_hubp, base)
33
34 #define HUBP_REG_LIST_DCN2_COMMON(id)\
35 HUBP_REG_LIST_DCN(id),\
36 HUBP_REG_LIST_DCN_VM(id),\
37 SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
38 SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
39 SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\
40 SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\
41 SRI(CURSOR_SETTINGS, HUBPREQ, id), \
42 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
43 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
44 SRI(CURSOR_SIZE, CURSOR0_, id), \
45 SRI(CURSOR_CONTROL, CURSOR0_, id), \
46 SRI(CURSOR_POSITION, CURSOR0_, id), \
47 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
48 SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \
49 SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \
50 SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \
51 SRI(DMDATA_CNTL, CURSOR0_, id), \
52 SRI(DMDATA_SW_CNTL, CURSOR0_, id), \
53 SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \
54 SRI(DMDATA_SW_DATA, CURSOR0_, id), \
55 SRI(DMDATA_STATUS, CURSOR0_, id),\
56 SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\
57 SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\
58 SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\
59 SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\
60 SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\
61 SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
62 SRI(VMID_SETTINGS_0, HUBPREQ, id)
63
64 #define HUBP_REG_LIST_DCN20(id)\
65 HUBP_REG_LIST_DCN2_COMMON(id),\
66 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
67 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)
68
69 #define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\
70 HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
71 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
72 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
73 HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
74 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
75 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
76 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
77 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
78 HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
79 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
80 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
81 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
82 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
83 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
84 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
85 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
86 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
87 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
88 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
89 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
90 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
91 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
92 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
93 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
94 HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
95 HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
96 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
97 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
98 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
99 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
100 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
101 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
102 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
103 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
104 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
105 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
106 HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
107 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
108 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
109 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
110 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
111 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
112 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
113 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
114 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
115 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
116 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
117
118
119 #define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\
120 HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\
121 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
122 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
123 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
124
125
126 #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\
127 HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\
128 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
129 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
130 HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
131
132
133 #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \
134 HUBP_COMMON_REG_VARIABLE_LIST; \
135 uint32_t DMDATA_ADDRESS_HIGH; \
136 uint32_t DMDATA_ADDRESS_LOW; \
137 uint32_t DMDATA_CNTL; \
138 uint32_t DMDATA_SW_CNTL; \
139 uint32_t DMDATA_QOS_CNTL; \
140 uint32_t DMDATA_SW_DATA; \
141 uint32_t DMDATA_STATUS;\
142 uint32_t DCSURF_FLIP_CONTROL2;\
143 uint32_t FLIP_PARAMETERS_0;\
144 uint32_t FLIP_PARAMETERS_1;\
145 uint32_t FLIP_PARAMETERS_2;\
146 uint32_t DCN_CUR1_TTU_CNTL0;\
147 uint32_t DCN_CUR1_TTU_CNTL1;\
148 uint32_t VMID_SETTINGS_0
149
150
151 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
152 #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \
153 DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \
154 uint32_t FLIP_PARAMETERS_3;\
155 uint32_t FLIP_PARAMETERS_4;\
156 uint32_t FLIP_PARAMETERS_5;\
157 uint32_t FLIP_PARAMETERS_6;\
158 uint32_t VBLANK_PARAMETERS_5;\
159 uint32_t VBLANK_PARAMETERS_6
160 #endif
161
162 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
163 DCN_HUBP_REG_FIELD_BASE_LIST(type); \
164 type DMDATA_ADDRESS_HIGH;\
165 type DMDATA_MODE;\
166 type DMDATA_UPDATED;\
167 type DMDATA_REPEAT;\
168 type DMDATA_SIZE;\
169 type DMDATA_SW_UPDATED;\
170 type DMDATA_SW_REPEAT;\
171 type DMDATA_SW_SIZE;\
172 type DMDATA_QOS_MODE;\
173 type DMDATA_QOS_LEVEL;\
174 type DMDATA_DL_DELTA;\
175 type DMDATA_DONE;\
176 type DST_Y_PER_VM_FLIP;\
177 type DST_Y_PER_ROW_FLIP;\
178 type REFCYC_PER_PTE_GROUP_FLIP_L;\
179 type REFCYC_PER_META_CHUNK_FLIP_L;\
180 type HUBP_VREADY_AT_OR_AFTER_VSYNC;\
181 type HUBP_DISABLE_STOP_DATA_DURING_VM;\
182 type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\
183 type SURFACE_GSL_ENABLE;\
184 type SURFACE_TRIPLE_BUFFER_ENABLE;\
185 type VMID
186
187 #ifdef CONFIG_DRM_AMD_DC_DCN2_1
188 #define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
189 DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\
190 type REFCYC_PER_VM_GROUP_FLIP;\
191 type REFCYC_PER_VM_REQ_FLIP;\
192 type REFCYC_PER_VM_GROUP_VBLANK;\
193 type REFCYC_PER_VM_REQ_VBLANK;\
194 type REFCYC_PER_PTE_GROUP_FLIP_C; \
195 type REFCYC_PER_META_CHUNK_FLIP_C; \
196 type VM_GROUP_SIZE
197 #endif
198
199
200 struct dcn_hubp2_registers {
201 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
202 DCN21_HUBP_REG_COMMON_VARIABLE_LIST;
203 #else
204 DCN2_HUBP_REG_COMMON_VARIABLE_LIST;
205 #endif
206 };
207
208 struct dcn_hubp2_shift {
209 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
210 DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
211 #else
212 DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
213 #endif
214 };
215
216 struct dcn_hubp2_mask {
217 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
218 DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
219 #else
220 DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
221 #endif
222 };
223
224 struct dcn20_hubp {
225 struct hubp base;
226 struct dcn_hubp_state state;
227 const struct dcn_hubp2_registers *hubp_regs;
228 const struct dcn_hubp2_shift *hubp_shift;
229 const struct dcn_hubp2_mask *hubp_mask;
230 };
231
232 bool hubp2_construct(
233 struct dcn20_hubp *hubp2,
234 struct dc_context *ctx,
235 uint32_t inst,
236 const struct dcn_hubp2_registers *hubp_regs,
237 const struct dcn_hubp2_shift *hubp_shift,
238 const struct dcn_hubp2_mask *hubp_mask);
239
240 void hubp2_setup_interdependent(
241 struct hubp *hubp,
242 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
243 struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
244
245 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
246 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
247
248 void hubp2_cursor_set_attributes(
249 struct hubp *hubp,
250 const struct dc_cursor_attributes *attr);
251
252 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
253 struct vm_system_aperture_param *apt);
254
255 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
256 unsigned int cursor_width,
257 enum dc_cursor_color_format cursor_mode);
258
259 void hubp2_dmdata_set_attributes(
260 struct hubp *hubp,
261 const struct dc_dmdata_attributes *attr);
262
263 void hubp2_dmdata_load(
264 struct hubp *hubp,
265 uint32_t dmdata_sw_size,
266 const uint32_t *dmdata_sw_data);
267
268 bool hubp2_dmdata_status_done(struct hubp *hubp);
269
270 void hubp2_enable_triplebuffer(
271 struct hubp *hubp,
272 bool enable);
273
274 bool hubp2_is_triplebuffer_enabled(
275 struct hubp *hubp);
276
277 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);
278
279 void hubp2_program_deadline(
280 struct hubp *hubp,
281 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
282 struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
283
284 bool hubp2_program_surface_flip_and_addr(
285 struct hubp *hubp,
286 const struct dc_plane_address *address,
287 bool flip_immediate);
288
289 void hubp2_dcc_control(struct hubp *hubp, bool enable,
290 enum hubp_ind_block_size independent_64b_blks);
291
292 void hubp2_program_size(
293 struct hubp *hubp,
294 enum surface_pixel_format format,
295 const struct plane_size *plane_size,
296 struct dc_plane_dcc_param *dcc);
297
298 void hubp2_program_rotation(
299 struct hubp *hubp,
300 enum dc_rotation_angle rotation,
301 bool horizontal_mirror);
302
303 void hubp2_program_pixel_format(
304 struct hubp *hubp,
305 enum surface_pixel_format format);
306
307 void hubp2_program_surface_config(
308 struct hubp *hubp,
309 enum surface_pixel_format format,
310 union dc_tiling_info *tiling_info,
311 struct plane_size *plane_size,
312 enum dc_rotation_angle rotation,
313 struct dc_plane_dcc_param *dcc,
314 bool horizontal_mirror,
315 unsigned int compat_level);
316
317 bool hubp2_is_flip_pending(struct hubp *hubp);
318
319 void hubp2_set_blank(struct hubp *hubp, bool blank);
320
321 void hubp2_cursor_set_position(
322 struct hubp *hubp,
323 const struct dc_cursor_position *pos,
324 const struct dc_cursor_mi_param *param);
325
326 void hubp2_clk_cntl(struct hubp *hubp, bool enable);
327
328 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
329
330 void hubp2_clear_underflow(struct hubp *hubp);
331
332 void hubp2_read_state_common(struct hubp *hubp);
333
334 void hubp2_read_state(struct hubp *hubp);
335
336 #endif
337
338