This source file includes following definitions.
- dcn20_dpp_destroy
- dcn20_dpp_create
- dcn20_ipp_create
- dcn20_opp_create
- dcn20_aux_engine_create
- dcn20_i2c_hw_create
- dcn20_mpc_create
- dcn20_hubbub_create
- dcn20_timing_generator_create
- dcn20_link_encoder_create
- dcn20_clock_source_create
- read_dce_straps
- dcn20_create_audio
- dcn20_stream_encoder_create
- dcn20_hwseq_create
- dcn20_clock_source_destroy
- dcn20_dsc_create
- dcn20_dsc_destroy
- destruct
- dcn20_hubp_create
- get_pixel_clock_parameters
- build_clamping_params
- build_pipe_hw_param
- dcn20_build_mapped_resource
- acquire_dsc
- release_dsc
- add_dsc_to_stream_resource
- remove_dsc_from_stream_resource
- dcn20_add_stream_to_ctx
- dcn20_remove_stream_from_ctx
- swizzle_to_dml_params
- dcn20_split_stream_for_odm
- dcn20_split_stream_for_mpc
- dcn20_populate_dml_writeback_from_context
- dcn20_populate_dml_pipes_from_context
- dcn20_calc_max_scaled_time
- dcn20_set_mcif_arb_params
- dcn20_validate_dsc
- dcn20_find_secondary_pipe
- dcn20_fast_validate_bw
- dcn20_calculate_wm
- dcn20_calculate_dlg_params
- dcn20_validate_bandwidth_internal
- dcn20_validate_bandwidth
- dcn20_acquire_idle_pipe_for_layer
- dcn20_get_dcc_compression_cap
- dcn20_destroy_resource_pool
- dcn20_get_default_swizzle_mode
- dcn20_dwbc_create
- dcn20_mmhubbub_create
- dcn20_pp_smu_create
- dcn20_pp_smu_destroy
- cap_soc_clocks
- update_bounding_box
- patch_bounding_box
- get_asic_rev_soc_bb
- get_asic_rev_ip_params
- get_dml_project_version
- init_soc_bounding_box
- construct
- dcn20_create_resource_pool
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26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29 #include "dc.h"
30
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dcn20/dcn20_resource.h"
34
35 #include "dcn10/dcn10_hubp.h"
36 #include "dcn10/dcn10_ipp.h"
37 #include "dcn20_hubbub.h"
38 #include "dcn20_mpc.h"
39 #include "dcn20_hubp.h"
40 #include "irq/dcn20/irq_service_dcn20.h"
41 #include "dcn20_dpp.h"
42 #include "dcn20_optc.h"
43 #include "dcn20_hwseq.h"
44 #include "dce110/dce110_hw_sequencer.h"
45 #include "dcn10/dcn10_resource.h"
46 #include "dcn20_opp.h"
47
48 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
49 #include "dcn20_dsc.h"
50 #endif
51
52 #include "dcn20_link_encoder.h"
53 #include "dcn20_stream_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
57 #include "virtual/virtual_stream_encoder.h"
58 #include "dce110/dce110_resource.h"
59 #include "dml/display_mode_vba.h"
60 #include "dcn20_dccg.h"
61 #include "dcn20_vmid.h"
62
63 #include "navi10_ip_offset.h"
64
65 #include "dcn/dcn_2_0_0_offset.h"
66 #include "dcn/dcn_2_0_0_sh_mask.h"
67
68 #include "nbio/nbio_2_3_offset.h"
69
70 #include "dcn20/dcn20_dwb.h"
71 #include "dcn20/dcn20_mmhubbub.h"
72
73 #include "mmhub/mmhub_2_0_0_offset.h"
74 #include "mmhub/mmhub_2_0_0_sh_mask.h"
75
76 #include "reg_helper.h"
77 #include "dce/dce_abm.h"
78 #include "dce/dce_dmcu.h"
79 #include "dce/dce_aux.h"
80 #include "dce/dce_i2c.h"
81 #include "vm_helper.h"
82
83 #include "amdgpu_socbb.h"
84
85
86 #define SOC_BOUNDING_BOX_VALID false
87 #define DC_LOGGER_INIT(logger)
88
89 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
90 .odm_capable = 1,
91 .gpuvm_enable = 0,
92 .hostvm_enable = 0,
93 .gpuvm_max_page_table_levels = 4,
94 .hostvm_max_page_table_levels = 4,
95 .hostvm_cached_page_table_levels = 0,
96 .pte_group_size_bytes = 2048,
97 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
98 .num_dsc = 6,
99 #else
100 .num_dsc = 0,
101 #endif
102 .rob_buffer_size_kbytes = 168,
103 .det_buffer_size_kbytes = 164,
104 .dpte_buffer_size_in_pte_reqs_luma = 84,
105 .pde_proc_buffer_size_64k_reqs = 48,
106 .dpp_output_buffer_pixels = 2560,
107 .opp_output_buffer_lines = 1,
108 .pixel_chunk_size_kbytes = 8,
109 .pte_chunk_size_kbytes = 2,
110 .meta_chunk_size_kbytes = 2,
111 .writeback_chunk_size_kbytes = 2,
112 .line_buffer_size_bits = 789504,
113 .is_line_buffer_bpp_fixed = 0,
114 .line_buffer_fixed_bpp = 0,
115 .dcc_supported = true,
116 .max_line_buffer_lines = 12,
117 .writeback_luma_buffer_size_kbytes = 12,
118 .writeback_chroma_buffer_size_kbytes = 8,
119 .writeback_chroma_line_buffer_width_pixels = 4,
120 .writeback_max_hscl_ratio = 1,
121 .writeback_max_vscl_ratio = 1,
122 .writeback_min_hscl_ratio = 1,
123 .writeback_min_vscl_ratio = 1,
124 .writeback_max_hscl_taps = 12,
125 .writeback_max_vscl_taps = 12,
126 .writeback_line_buffer_luma_buffer_size = 0,
127 .writeback_line_buffer_chroma_buffer_size = 14643,
128 .cursor_buffer_size = 8,
129 .cursor_chunk_size = 2,
130 .max_num_otg = 6,
131 .max_num_dpp = 6,
132 .max_num_wb = 1,
133 .max_dchub_pscl_bw_pix_per_clk = 4,
134 .max_pscl_lb_bw_pix_per_clk = 2,
135 .max_lb_vscl_bw_pix_per_clk = 4,
136 .max_vscl_hscl_bw_pix_per_clk = 4,
137 .max_hscl_ratio = 8,
138 .max_vscl_ratio = 8,
139 .hscl_mults = 4,
140 .vscl_mults = 4,
141 .max_hscl_taps = 8,
142 .max_vscl_taps = 8,
143 .dispclk_ramp_margin_percent = 1,
144 .underscan_factor = 1.10,
145 .min_vblank_lines = 32,
146 .dppclk_delay_subtotal = 77,
147 .dppclk_delay_scl_lb_only = 16,
148 .dppclk_delay_scl = 50,
149 .dppclk_delay_cnvc_formatter = 8,
150 .dppclk_delay_cnvc_cursor = 6,
151 .dispclk_delay_subtotal = 87,
152 .dcfclk_cstate_latency = 10,
153 .max_inter_dcn_tile_repeaters = 8,
154
155 .xfc_supported = true,
156 .xfc_fill_bw_overhead_percent = 10.0,
157 .xfc_fill_constant_bytes = 0,
158 };
159
160 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
161
162 .clock_limits = {
163 {
164 .state = 0,
165 .dcfclk_mhz = 560.0,
166 .fabricclk_mhz = 560.0,
167 .dispclk_mhz = 513.0,
168 .dppclk_mhz = 513.0,
169 .phyclk_mhz = 540.0,
170 .socclk_mhz = 560.0,
171 .dscclk_mhz = 171.0,
172 .dram_speed_mts = 8960.0,
173 },
174 {
175 .state = 1,
176 .dcfclk_mhz = 694.0,
177 .fabricclk_mhz = 694.0,
178 .dispclk_mhz = 642.0,
179 .dppclk_mhz = 642.0,
180 .phyclk_mhz = 600.0,
181 .socclk_mhz = 694.0,
182 .dscclk_mhz = 214.0,
183 .dram_speed_mts = 11104.0,
184 },
185 {
186 .state = 2,
187 .dcfclk_mhz = 875.0,
188 .fabricclk_mhz = 875.0,
189 .dispclk_mhz = 734.0,
190 .dppclk_mhz = 734.0,
191 .phyclk_mhz = 810.0,
192 .socclk_mhz = 875.0,
193 .dscclk_mhz = 245.0,
194 .dram_speed_mts = 14000.0,
195 },
196 {
197 .state = 3,
198 .dcfclk_mhz = 1000.0,
199 .fabricclk_mhz = 1000.0,
200 .dispclk_mhz = 1100.0,
201 .dppclk_mhz = 1100.0,
202 .phyclk_mhz = 810.0,
203 .socclk_mhz = 1000.0,
204 .dscclk_mhz = 367.0,
205 .dram_speed_mts = 16000.0,
206 },
207 {
208 .state = 4,
209 .dcfclk_mhz = 1200.0,
210 .fabricclk_mhz = 1200.0,
211 .dispclk_mhz = 1284.0,
212 .dppclk_mhz = 1284.0,
213 .phyclk_mhz = 810.0,
214 .socclk_mhz = 1200.0,
215 .dscclk_mhz = 428.0,
216 .dram_speed_mts = 16000.0,
217 },
218
219 {
220 .state = 5,
221 .dcfclk_mhz = 1200.0,
222 .fabricclk_mhz = 1200.0,
223 .dispclk_mhz = 1284.0,
224 .dppclk_mhz = 1284.0,
225 .phyclk_mhz = 810.0,
226 .socclk_mhz = 1200.0,
227 .dscclk_mhz = 428.0,
228 .dram_speed_mts = 16000.0,
229 },
230 },
231 .num_states = 5,
232 .sr_exit_time_us = 8.6,
233 .sr_enter_plus_exit_time_us = 10.9,
234 .urgent_latency_us = 4.0,
235 .urgent_latency_pixel_data_only_us = 4.0,
236 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
237 .urgent_latency_vm_data_only_us = 4.0,
238 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
239 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
240 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
241 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
242 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
243 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
244 .max_avg_sdp_bw_use_normal_percent = 40.0,
245 .max_avg_dram_bw_use_normal_percent = 40.0,
246 .writeback_latency_us = 12.0,
247 .ideal_dram_bw_after_urgent_percent = 40.0,
248 .max_request_size_bytes = 256,
249 .dram_channel_width_bytes = 2,
250 .fabric_datapath_to_dcn_data_return_bytes = 64,
251 .dcn_downspread_percent = 0.5,
252 .downspread_percent = 0.38,
253 .dram_page_open_time_ns = 50.0,
254 .dram_rw_turnaround_time_ns = 17.5,
255 .dram_return_buffer_per_channel_bytes = 8192,
256 .round_trip_ping_latency_dcfclk_cycles = 131,
257 .urgent_out_of_order_return_per_channel_bytes = 256,
258 .channel_interleave_bytes = 256,
259 .num_banks = 8,
260 .num_chans = 16,
261 .vmm_page_size_bytes = 4096,
262 .dram_clock_change_latency_us = 404.0,
263 .dummy_pstate_latency_us = 5.0,
264 .writeback_dram_clock_change_latency_us = 23.0,
265 .return_bus_width_bytes = 64,
266 .dispclk_dppclk_vco_speed_mhz = 3850,
267 .xfc_bus_transport_time_us = 20,
268 .xfc_xbuf_latency_tolerance_us = 4,
269 .use_urgent_burst_bw = 0
270 };
271
272 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
273 .clock_limits = {
274 {
275 .state = 0,
276 .dcfclk_mhz = 560.0,
277 .fabricclk_mhz = 560.0,
278 .dispclk_mhz = 513.0,
279 .dppclk_mhz = 513.0,
280 .phyclk_mhz = 540.0,
281 .socclk_mhz = 560.0,
282 .dscclk_mhz = 171.0,
283 .dram_speed_mts = 8960.0,
284 },
285 {
286 .state = 1,
287 .dcfclk_mhz = 694.0,
288 .fabricclk_mhz = 694.0,
289 .dispclk_mhz = 642.0,
290 .dppclk_mhz = 642.0,
291 .phyclk_mhz = 600.0,
292 .socclk_mhz = 694.0,
293 .dscclk_mhz = 214.0,
294 .dram_speed_mts = 11104.0,
295 },
296 {
297 .state = 2,
298 .dcfclk_mhz = 875.0,
299 .fabricclk_mhz = 875.0,
300 .dispclk_mhz = 734.0,
301 .dppclk_mhz = 734.0,
302 .phyclk_mhz = 810.0,
303 .socclk_mhz = 875.0,
304 .dscclk_mhz = 245.0,
305 .dram_speed_mts = 14000.0,
306 },
307 {
308 .state = 3,
309 .dcfclk_mhz = 1000.0,
310 .fabricclk_mhz = 1000.0,
311 .dispclk_mhz = 1100.0,
312 .dppclk_mhz = 1100.0,
313 .phyclk_mhz = 810.0,
314 .socclk_mhz = 1000.0,
315 .dscclk_mhz = 367.0,
316 .dram_speed_mts = 16000.0,
317 },
318 {
319 .state = 4,
320 .dcfclk_mhz = 1200.0,
321 .fabricclk_mhz = 1200.0,
322 .dispclk_mhz = 1284.0,
323 .dppclk_mhz = 1284.0,
324 .phyclk_mhz = 810.0,
325 .socclk_mhz = 1200.0,
326 .dscclk_mhz = 428.0,
327 .dram_speed_mts = 16000.0,
328 },
329
330 {
331 .state = 5,
332 .dcfclk_mhz = 1200.0,
333 .fabricclk_mhz = 1200.0,
334 .dispclk_mhz = 1284.0,
335 .dppclk_mhz = 1284.0,
336 .phyclk_mhz = 810.0,
337 .socclk_mhz = 1200.0,
338 .dscclk_mhz = 428.0,
339 .dram_speed_mts = 16000.0,
340 },
341 },
342 .num_states = 5,
343 .sr_exit_time_us = 8.6,
344 .sr_enter_plus_exit_time_us = 10.9,
345 .urgent_latency_us = 4.0,
346 .urgent_latency_pixel_data_only_us = 4.0,
347 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
348 .urgent_latency_vm_data_only_us = 4.0,
349 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
350 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
351 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
352 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
353 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
354 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
355 .max_avg_sdp_bw_use_normal_percent = 40.0,
356 .max_avg_dram_bw_use_normal_percent = 40.0,
357 .writeback_latency_us = 12.0,
358 .ideal_dram_bw_after_urgent_percent = 40.0,
359 .max_request_size_bytes = 256,
360 .dram_channel_width_bytes = 2,
361 .fabric_datapath_to_dcn_data_return_bytes = 64,
362 .dcn_downspread_percent = 0.5,
363 .downspread_percent = 0.38,
364 .dram_page_open_time_ns = 50.0,
365 .dram_rw_turnaround_time_ns = 17.5,
366 .dram_return_buffer_per_channel_bytes = 8192,
367 .round_trip_ping_latency_dcfclk_cycles = 131,
368 .urgent_out_of_order_return_per_channel_bytes = 256,
369 .channel_interleave_bytes = 256,
370 .num_banks = 8,
371 .num_chans = 8,
372 .vmm_page_size_bytes = 4096,
373 .dram_clock_change_latency_us = 404.0,
374 .dummy_pstate_latency_us = 5.0,
375 .writeback_dram_clock_change_latency_us = 23.0,
376 .return_bus_width_bytes = 64,
377 .dispclk_dppclk_vco_speed_mhz = 3850,
378 .xfc_bus_transport_time_us = 20,
379 .xfc_xbuf_latency_tolerance_us = 4,
380 .use_urgent_burst_bw = 0
381 };
382
383 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
384
385 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
386 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
387 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
388 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
389 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
390 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
391 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
392 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
393 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
394 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
395 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
396 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
397 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
398 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
399 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
400 #endif
401
402
403 enum dcn20_clk_src_array_id {
404 DCN20_CLK_SRC_PLL0,
405 DCN20_CLK_SRC_PLL1,
406 DCN20_CLK_SRC_PLL2,
407 DCN20_CLK_SRC_PLL3,
408 DCN20_CLK_SRC_PLL4,
409 DCN20_CLK_SRC_PLL5,
410 DCN20_CLK_SRC_TOTAL
411 };
412
413
414
415
416
417
418 #undef BASE_INNER
419 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
420
421 #define BASE(seg) BASE_INNER(seg)
422
423 #define SR(reg_name)\
424 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
425 mm ## reg_name
426
427 #define SRI(reg_name, block, id)\
428 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
429 mm ## block ## id ## _ ## reg_name
430
431 #define SRIR(var_name, reg_name, block, id)\
432 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
433 mm ## block ## id ## _ ## reg_name
434
435 #define SRII(reg_name, block, id)\
436 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
437 mm ## block ## id ## _ ## reg_name
438
439 #define DCCG_SRII(reg_name, block, id)\
440 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
441 mm ## block ## id ## _ ## reg_name
442
443
444 #define NBIO_BASE_INNER(seg) \
445 NBIO_BASE__INST0_SEG ## seg
446
447 #define NBIO_BASE(seg) \
448 NBIO_BASE_INNER(seg)
449
450 #define NBIO_SR(reg_name)\
451 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
452 mm ## reg_name
453
454
455 #define MMHUB_BASE_INNER(seg) \
456 MMHUB_BASE__INST0_SEG ## seg
457
458 #define MMHUB_BASE(seg) \
459 MMHUB_BASE_INNER(seg)
460
461 #define MMHUB_SR(reg_name)\
462 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
463 mmMM ## reg_name
464
465 static const struct bios_registers bios_regs = {
466 NBIO_SR(BIOS_SCRATCH_3),
467 NBIO_SR(BIOS_SCRATCH_6)
468 };
469
470 #define clk_src_regs(index, pllid)\
471 [index] = {\
472 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
473 }
474
475 static const struct dce110_clk_src_regs clk_src_regs[] = {
476 clk_src_regs(0, A),
477 clk_src_regs(1, B),
478 clk_src_regs(2, C),
479 clk_src_regs(3, D),
480 clk_src_regs(4, E),
481 clk_src_regs(5, F)
482 };
483
484 static const struct dce110_clk_src_shift cs_shift = {
485 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
486 };
487
488 static const struct dce110_clk_src_mask cs_mask = {
489 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
490 };
491
492 static const struct dce_dmcu_registers dmcu_regs = {
493 DMCU_DCN10_REG_LIST()
494 };
495
496 static const struct dce_dmcu_shift dmcu_shift = {
497 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
498 };
499
500 static const struct dce_dmcu_mask dmcu_mask = {
501 DMCU_MASK_SH_LIST_DCN10(_MASK)
502 };
503
504 static const struct dce_abm_registers abm_regs = {
505 ABM_DCN20_REG_LIST()
506 };
507
508 static const struct dce_abm_shift abm_shift = {
509 ABM_MASK_SH_LIST_DCN20(__SHIFT)
510 };
511
512 static const struct dce_abm_mask abm_mask = {
513 ABM_MASK_SH_LIST_DCN20(_MASK)
514 };
515
516 #define audio_regs(id)\
517 [id] = {\
518 AUD_COMMON_REG_LIST(id)\
519 }
520
521 static const struct dce_audio_registers audio_regs[] = {
522 audio_regs(0),
523 audio_regs(1),
524 audio_regs(2),
525 audio_regs(3),
526 audio_regs(4),
527 audio_regs(5),
528 audio_regs(6),
529 };
530
531 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
532 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
533 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
534 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
535
536 static const struct dce_audio_shift audio_shift = {
537 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
538 };
539
540 static const struct dce_audio_mask audio_mask = {
541 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
542 };
543
544 #define stream_enc_regs(id)\
545 [id] = {\
546 SE_DCN2_REG_LIST(id)\
547 }
548
549 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
550 stream_enc_regs(0),
551 stream_enc_regs(1),
552 stream_enc_regs(2),
553 stream_enc_regs(3),
554 stream_enc_regs(4),
555 stream_enc_regs(5),
556 };
557
558 static const struct dcn10_stream_encoder_shift se_shift = {
559 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
560 };
561
562 static const struct dcn10_stream_encoder_mask se_mask = {
563 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
564 };
565
566
567 #define aux_regs(id)\
568 [id] = {\
569 DCN2_AUX_REG_LIST(id)\
570 }
571
572 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
573 aux_regs(0),
574 aux_regs(1),
575 aux_regs(2),
576 aux_regs(3),
577 aux_regs(4),
578 aux_regs(5)
579 };
580
581 #define hpd_regs(id)\
582 [id] = {\
583 HPD_REG_LIST(id)\
584 }
585
586 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
587 hpd_regs(0),
588 hpd_regs(1),
589 hpd_regs(2),
590 hpd_regs(3),
591 hpd_regs(4),
592 hpd_regs(5)
593 };
594
595 #define link_regs(id, phyid)\
596 [id] = {\
597 LE_DCN10_REG_LIST(id), \
598 UNIPHY_DCN2_REG_LIST(phyid), \
599 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
600 }
601
602 static const struct dcn10_link_enc_registers link_enc_regs[] = {
603 link_regs(0, A),
604 link_regs(1, B),
605 link_regs(2, C),
606 link_regs(3, D),
607 link_regs(4, E),
608 link_regs(5, F)
609 };
610
611 static const struct dcn10_link_enc_shift le_shift = {
612 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
613 };
614
615 static const struct dcn10_link_enc_mask le_mask = {
616 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
617 };
618
619 #define ipp_regs(id)\
620 [id] = {\
621 IPP_REG_LIST_DCN20(id),\
622 }
623
624 static const struct dcn10_ipp_registers ipp_regs[] = {
625 ipp_regs(0),
626 ipp_regs(1),
627 ipp_regs(2),
628 ipp_regs(3),
629 ipp_regs(4),
630 ipp_regs(5),
631 };
632
633 static const struct dcn10_ipp_shift ipp_shift = {
634 IPP_MASK_SH_LIST_DCN20(__SHIFT)
635 };
636
637 static const struct dcn10_ipp_mask ipp_mask = {
638 IPP_MASK_SH_LIST_DCN20(_MASK),
639 };
640
641 #define opp_regs(id)\
642 [id] = {\
643 OPP_REG_LIST_DCN20(id),\
644 }
645
646 static const struct dcn20_opp_registers opp_regs[] = {
647 opp_regs(0),
648 opp_regs(1),
649 opp_regs(2),
650 opp_regs(3),
651 opp_regs(4),
652 opp_regs(5),
653 };
654
655 static const struct dcn20_opp_shift opp_shift = {
656 OPP_MASK_SH_LIST_DCN20(__SHIFT)
657 };
658
659 static const struct dcn20_opp_mask opp_mask = {
660 OPP_MASK_SH_LIST_DCN20(_MASK)
661 };
662
663 #define aux_engine_regs(id)\
664 [id] = {\
665 AUX_COMMON_REG_LIST0(id), \
666 .AUXN_IMPCAL = 0, \
667 .AUXP_IMPCAL = 0, \
668 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
669 }
670
671 static const struct dce110_aux_registers aux_engine_regs[] = {
672 aux_engine_regs(0),
673 aux_engine_regs(1),
674 aux_engine_regs(2),
675 aux_engine_regs(3),
676 aux_engine_regs(4),
677 aux_engine_regs(5)
678 };
679
680 #define tf_regs(id)\
681 [id] = {\
682 TF_REG_LIST_DCN20(id),\
683 }
684
685 static const struct dcn2_dpp_registers tf_regs[] = {
686 tf_regs(0),
687 tf_regs(1),
688 tf_regs(2),
689 tf_regs(3),
690 tf_regs(4),
691 tf_regs(5),
692 };
693
694 static const struct dcn2_dpp_shift tf_shift = {
695 TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
696 };
697
698 static const struct dcn2_dpp_mask tf_mask = {
699 TF_REG_LIST_SH_MASK_DCN20(_MASK)
700 };
701
702 #define dwbc_regs_dcn2(id)\
703 [id] = {\
704 DWBC_COMMON_REG_LIST_DCN2_0(id),\
705 }
706
707 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
708 dwbc_regs_dcn2(0),
709 };
710
711 static const struct dcn20_dwbc_shift dwbc20_shift = {
712 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
713 };
714
715 static const struct dcn20_dwbc_mask dwbc20_mask = {
716 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
717 };
718
719 #define mcif_wb_regs_dcn2(id)\
720 [id] = {\
721 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
722 }
723
724 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
725 mcif_wb_regs_dcn2(0),
726 };
727
728 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
729 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
730 };
731
732 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
733 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
734 };
735
736 static const struct dcn20_mpc_registers mpc_regs = {
737 MPC_REG_LIST_DCN2_0(0),
738 MPC_REG_LIST_DCN2_0(1),
739 MPC_REG_LIST_DCN2_0(2),
740 MPC_REG_LIST_DCN2_0(3),
741 MPC_REG_LIST_DCN2_0(4),
742 MPC_REG_LIST_DCN2_0(5),
743 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
744 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
745 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
746 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
747 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
748 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
749 };
750
751 static const struct dcn20_mpc_shift mpc_shift = {
752 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
753 };
754
755 static const struct dcn20_mpc_mask mpc_mask = {
756 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
757 };
758
759 #define tg_regs(id)\
760 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
761
762
763 static const struct dcn_optc_registers tg_regs[] = {
764 tg_regs(0),
765 tg_regs(1),
766 tg_regs(2),
767 tg_regs(3),
768 tg_regs(4),
769 tg_regs(5)
770 };
771
772 static const struct dcn_optc_shift tg_shift = {
773 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
774 };
775
776 static const struct dcn_optc_mask tg_mask = {
777 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
778 };
779
780 #define hubp_regs(id)\
781 [id] = {\
782 HUBP_REG_LIST_DCN20(id)\
783 }
784
785 static const struct dcn_hubp2_registers hubp_regs[] = {
786 hubp_regs(0),
787 hubp_regs(1),
788 hubp_regs(2),
789 hubp_regs(3),
790 hubp_regs(4),
791 hubp_regs(5)
792 };
793
794 static const struct dcn_hubp2_shift hubp_shift = {
795 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
796 };
797
798 static const struct dcn_hubp2_mask hubp_mask = {
799 HUBP_MASK_SH_LIST_DCN20(_MASK)
800 };
801
802 static const struct dcn_hubbub_registers hubbub_reg = {
803 HUBBUB_REG_LIST_DCN20(0)
804 };
805
806 static const struct dcn_hubbub_shift hubbub_shift = {
807 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
808 };
809
810 static const struct dcn_hubbub_mask hubbub_mask = {
811 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
812 };
813
814 #define vmid_regs(id)\
815 [id] = {\
816 DCN20_VMID_REG_LIST(id)\
817 }
818
819 static const struct dcn_vmid_registers vmid_regs[] = {
820 vmid_regs(0),
821 vmid_regs(1),
822 vmid_regs(2),
823 vmid_regs(3),
824 vmid_regs(4),
825 vmid_regs(5),
826 vmid_regs(6),
827 vmid_regs(7),
828 vmid_regs(8),
829 vmid_regs(9),
830 vmid_regs(10),
831 vmid_regs(11),
832 vmid_regs(12),
833 vmid_regs(13),
834 vmid_regs(14),
835 vmid_regs(15)
836 };
837
838 static const struct dcn20_vmid_shift vmid_shifts = {
839 DCN20_VMID_MASK_SH_LIST(__SHIFT)
840 };
841
842 static const struct dcn20_vmid_mask vmid_masks = {
843 DCN20_VMID_MASK_SH_LIST(_MASK)
844 };
845
846 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
847 #define dsc_regsDCN20(id)\
848 [id] = {\
849 DSC_REG_LIST_DCN20(id)\
850 }
851
852 static const struct dcn20_dsc_registers dsc_regs[] = {
853 dsc_regsDCN20(0),
854 dsc_regsDCN20(1),
855 dsc_regsDCN20(2),
856 dsc_regsDCN20(3),
857 dsc_regsDCN20(4),
858 dsc_regsDCN20(5)
859 };
860
861 static const struct dcn20_dsc_shift dsc_shift = {
862 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
863 };
864
865 static const struct dcn20_dsc_mask dsc_mask = {
866 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
867 };
868 #endif
869
870 static const struct dccg_registers dccg_regs = {
871 DCCG_REG_LIST_DCN2()
872 };
873
874 static const struct dccg_shift dccg_shift = {
875 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
876 };
877
878 static const struct dccg_mask dccg_mask = {
879 DCCG_MASK_SH_LIST_DCN2(_MASK)
880 };
881
882 static const struct resource_caps res_cap_nv10 = {
883 .num_timing_generator = 6,
884 .num_opp = 6,
885 .num_video_plane = 6,
886 .num_audio = 7,
887 .num_stream_encoder = 6,
888 .num_pll = 6,
889 .num_dwb = 1,
890 .num_ddc = 6,
891 .num_vmid = 16,
892 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
893 .num_dsc = 6,
894 #endif
895 };
896
897 static const struct dc_plane_cap plane_cap = {
898 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
899 .blends_with_above = true,
900 .blends_with_below = true,
901 .per_pixel_alpha = true,
902
903 .pixel_format_support = {
904 .argb8888 = true,
905 .nv12 = true,
906 .fp16 = true
907 },
908
909 .max_upscale_factor = {
910 .argb8888 = 16000,
911 .nv12 = 16000,
912 .fp16 = 1
913 },
914
915 .max_downscale_factor = {
916 .argb8888 = 250,
917 .nv12 = 250,
918 .fp16 = 1
919 }
920 };
921 static const struct resource_caps res_cap_nv14 = {
922 .num_timing_generator = 5,
923 .num_opp = 5,
924 .num_video_plane = 5,
925 .num_audio = 6,
926 .num_stream_encoder = 5,
927 .num_pll = 5,
928 .num_dwb = 1,
929 .num_ddc = 5,
930 };
931
932 static const struct dc_debug_options debug_defaults_drv = {
933 .disable_dmcu = true,
934 .force_abm_enable = false,
935 .timing_trace = false,
936 .clock_trace = true,
937 .disable_pplib_clock_request = true,
938 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
939 .force_single_disp_pipe_split = true,
940 .disable_dcc = DCC_ENABLE,
941 .vsr_support = true,
942 .performance_trace = false,
943 .max_downscale_src_width = 5120,
944 .disable_pplib_wm_range = false,
945 .scl_reset_length10 = true,
946 .sanity_checks = false,
947 .disable_tri_buf = true,
948 .underflow_assert_delay_us = 0xFFFFFFFF,
949 };
950
951 static const struct dc_debug_options debug_defaults_diags = {
952 .disable_dmcu = true,
953 .force_abm_enable = false,
954 .timing_trace = true,
955 .clock_trace = true,
956 .disable_dpp_power_gate = true,
957 .disable_hubp_power_gate = true,
958 .disable_clock_gate = true,
959 .disable_pplib_clock_request = true,
960 .disable_pplib_wm_range = true,
961 .disable_stutter = true,
962 .scl_reset_length10 = true,
963 .underflow_assert_delay_us = 0xFFFFFFFF,
964 };
965
966 void dcn20_dpp_destroy(struct dpp **dpp)
967 {
968 kfree(TO_DCN20_DPP(*dpp));
969 *dpp = NULL;
970 }
971
972 struct dpp *dcn20_dpp_create(
973 struct dc_context *ctx,
974 uint32_t inst)
975 {
976 struct dcn20_dpp *dpp =
977 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
978
979 if (!dpp)
980 return NULL;
981
982 if (dpp2_construct(dpp, ctx, inst,
983 &tf_regs[inst], &tf_shift, &tf_mask))
984 return &dpp->base;
985
986 BREAK_TO_DEBUGGER();
987 kfree(dpp);
988 return NULL;
989 }
990
991 struct input_pixel_processor *dcn20_ipp_create(
992 struct dc_context *ctx, uint32_t inst)
993 {
994 struct dcn10_ipp *ipp =
995 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
996
997 if (!ipp) {
998 BREAK_TO_DEBUGGER();
999 return NULL;
1000 }
1001
1002 dcn20_ipp_construct(ipp, ctx, inst,
1003 &ipp_regs[inst], &ipp_shift, &ipp_mask);
1004 return &ipp->base;
1005 }
1006
1007
1008 struct output_pixel_processor *dcn20_opp_create(
1009 struct dc_context *ctx, uint32_t inst)
1010 {
1011 struct dcn20_opp *opp =
1012 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1013
1014 if (!opp) {
1015 BREAK_TO_DEBUGGER();
1016 return NULL;
1017 }
1018
1019 dcn20_opp_construct(opp, ctx, inst,
1020 &opp_regs[inst], &opp_shift, &opp_mask);
1021 return &opp->base;
1022 }
1023
1024 struct dce_aux *dcn20_aux_engine_create(
1025 struct dc_context *ctx,
1026 uint32_t inst)
1027 {
1028 struct aux_engine_dce110 *aux_engine =
1029 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1030
1031 if (!aux_engine)
1032 return NULL;
1033
1034 dce110_aux_engine_construct(aux_engine, ctx, inst,
1035 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1036 &aux_engine_regs[inst]);
1037
1038 return &aux_engine->base;
1039 }
1040 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1041
1042 static const struct dce_i2c_registers i2c_hw_regs[] = {
1043 i2c_inst_regs(1),
1044 i2c_inst_regs(2),
1045 i2c_inst_regs(3),
1046 i2c_inst_regs(4),
1047 i2c_inst_regs(5),
1048 i2c_inst_regs(6),
1049 };
1050
1051 static const struct dce_i2c_shift i2c_shifts = {
1052 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1053 };
1054
1055 static const struct dce_i2c_mask i2c_masks = {
1056 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1057 };
1058
1059 struct dce_i2c_hw *dcn20_i2c_hw_create(
1060 struct dc_context *ctx,
1061 uint32_t inst)
1062 {
1063 struct dce_i2c_hw *dce_i2c_hw =
1064 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1065
1066 if (!dce_i2c_hw)
1067 return NULL;
1068
1069 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1070 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1071
1072 return dce_i2c_hw;
1073 }
1074 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1075 {
1076 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1077 GFP_KERNEL);
1078
1079 if (!mpc20)
1080 return NULL;
1081
1082 dcn20_mpc_construct(mpc20, ctx,
1083 &mpc_regs,
1084 &mpc_shift,
1085 &mpc_mask,
1086 6);
1087
1088 return &mpc20->base;
1089 }
1090
1091 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1092 {
1093 int i;
1094 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1095 GFP_KERNEL);
1096
1097 if (!hubbub)
1098 return NULL;
1099
1100 hubbub2_construct(hubbub, ctx,
1101 &hubbub_reg,
1102 &hubbub_shift,
1103 &hubbub_mask);
1104
1105 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1106 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1107
1108 vmid->ctx = ctx;
1109
1110 vmid->regs = &vmid_regs[i];
1111 vmid->shifts = &vmid_shifts;
1112 vmid->masks = &vmid_masks;
1113 }
1114
1115 return &hubbub->base;
1116 }
1117
1118 struct timing_generator *dcn20_timing_generator_create(
1119 struct dc_context *ctx,
1120 uint32_t instance)
1121 {
1122 struct optc *tgn10 =
1123 kzalloc(sizeof(struct optc), GFP_KERNEL);
1124
1125 if (!tgn10)
1126 return NULL;
1127
1128 tgn10->base.inst = instance;
1129 tgn10->base.ctx = ctx;
1130
1131 tgn10->tg_regs = &tg_regs[instance];
1132 tgn10->tg_shift = &tg_shift;
1133 tgn10->tg_mask = &tg_mask;
1134
1135 dcn20_timing_generator_init(tgn10);
1136
1137 return &tgn10->base;
1138 }
1139
1140 static const struct encoder_feature_support link_enc_feature = {
1141 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1142 .max_hdmi_pixel_clock = 600000,
1143 .hdmi_ycbcr420_supported = true,
1144 .dp_ycbcr420_supported = true,
1145 .flags.bits.IS_HBR2_CAPABLE = true,
1146 .flags.bits.IS_HBR3_CAPABLE = true,
1147 .flags.bits.IS_TPS3_CAPABLE = true,
1148 .flags.bits.IS_TPS4_CAPABLE = true
1149 };
1150
1151 struct link_encoder *dcn20_link_encoder_create(
1152 const struct encoder_init_data *enc_init_data)
1153 {
1154 struct dcn20_link_encoder *enc20 =
1155 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1156
1157 if (!enc20)
1158 return NULL;
1159
1160 dcn20_link_encoder_construct(enc20,
1161 enc_init_data,
1162 &link_enc_feature,
1163 &link_enc_regs[enc_init_data->transmitter],
1164 &link_enc_aux_regs[enc_init_data->channel - 1],
1165 &link_enc_hpd_regs[enc_init_data->hpd_source],
1166 &le_shift,
1167 &le_mask);
1168
1169 return &enc20->enc10.base;
1170 }
1171
1172 struct clock_source *dcn20_clock_source_create(
1173 struct dc_context *ctx,
1174 struct dc_bios *bios,
1175 enum clock_source_id id,
1176 const struct dce110_clk_src_regs *regs,
1177 bool dp_clk_src)
1178 {
1179 struct dce110_clk_src *clk_src =
1180 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1181
1182 if (!clk_src)
1183 return NULL;
1184
1185 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1186 regs, &cs_shift, &cs_mask)) {
1187 clk_src->base.dp_clk_src = dp_clk_src;
1188 return &clk_src->base;
1189 }
1190
1191 kfree(clk_src);
1192 BREAK_TO_DEBUGGER();
1193 return NULL;
1194 }
1195
1196 static void read_dce_straps(
1197 struct dc_context *ctx,
1198 struct resource_straps *straps)
1199 {
1200 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1201 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1202 }
1203
1204 static struct audio *dcn20_create_audio(
1205 struct dc_context *ctx, unsigned int inst)
1206 {
1207 return dce_audio_create(ctx, inst,
1208 &audio_regs[inst], &audio_shift, &audio_mask);
1209 }
1210
1211 struct stream_encoder *dcn20_stream_encoder_create(
1212 enum engine_id eng_id,
1213 struct dc_context *ctx)
1214 {
1215 struct dcn10_stream_encoder *enc1 =
1216 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1217
1218 if (!enc1)
1219 return NULL;
1220
1221 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1222 if (eng_id >= ENGINE_ID_DIGD)
1223 eng_id++;
1224 }
1225
1226 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1227 &stream_enc_regs[eng_id],
1228 &se_shift, &se_mask);
1229
1230 return &enc1->base;
1231 }
1232
1233 static const struct dce_hwseq_registers hwseq_reg = {
1234 HWSEQ_DCN2_REG_LIST()
1235 };
1236
1237 static const struct dce_hwseq_shift hwseq_shift = {
1238 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1239 };
1240
1241 static const struct dce_hwseq_mask hwseq_mask = {
1242 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1243 };
1244
1245 struct dce_hwseq *dcn20_hwseq_create(
1246 struct dc_context *ctx)
1247 {
1248 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1249
1250 if (hws) {
1251 hws->ctx = ctx;
1252 hws->regs = &hwseq_reg;
1253 hws->shifts = &hwseq_shift;
1254 hws->masks = &hwseq_mask;
1255 }
1256 return hws;
1257 }
1258
1259 static const struct resource_create_funcs res_create_funcs = {
1260 .read_dce_straps = read_dce_straps,
1261 .create_audio = dcn20_create_audio,
1262 .create_stream_encoder = dcn20_stream_encoder_create,
1263 .create_hwseq = dcn20_hwseq_create,
1264 };
1265
1266 static const struct resource_create_funcs res_create_maximus_funcs = {
1267 .read_dce_straps = NULL,
1268 .create_audio = NULL,
1269 .create_stream_encoder = NULL,
1270 .create_hwseq = dcn20_hwseq_create,
1271 };
1272
1273 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1274 {
1275 kfree(TO_DCE110_CLK_SRC(*clk_src));
1276 *clk_src = NULL;
1277 }
1278
1279 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1280
1281 struct display_stream_compressor *dcn20_dsc_create(
1282 struct dc_context *ctx, uint32_t inst)
1283 {
1284 struct dcn20_dsc *dsc =
1285 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1286
1287 if (!dsc) {
1288 BREAK_TO_DEBUGGER();
1289 return NULL;
1290 }
1291
1292 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1293 return &dsc->base;
1294 }
1295
1296 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1297 {
1298 kfree(container_of(*dsc, struct dcn20_dsc, base));
1299 *dsc = NULL;
1300 }
1301
1302 #endif
1303
1304 static void destruct(struct dcn20_resource_pool *pool)
1305 {
1306 unsigned int i;
1307
1308 for (i = 0; i < pool->base.stream_enc_count; i++) {
1309 if (pool->base.stream_enc[i] != NULL) {
1310 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1311 pool->base.stream_enc[i] = NULL;
1312 }
1313 }
1314
1315 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1316 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1317 if (pool->base.dscs[i] != NULL)
1318 dcn20_dsc_destroy(&pool->base.dscs[i]);
1319 }
1320 #endif
1321
1322 if (pool->base.mpc != NULL) {
1323 kfree(TO_DCN20_MPC(pool->base.mpc));
1324 pool->base.mpc = NULL;
1325 }
1326 if (pool->base.hubbub != NULL) {
1327 kfree(pool->base.hubbub);
1328 pool->base.hubbub = NULL;
1329 }
1330 for (i = 0; i < pool->base.pipe_count; i++) {
1331 if (pool->base.dpps[i] != NULL)
1332 dcn20_dpp_destroy(&pool->base.dpps[i]);
1333
1334 if (pool->base.ipps[i] != NULL)
1335 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1336
1337 if (pool->base.hubps[i] != NULL) {
1338 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1339 pool->base.hubps[i] = NULL;
1340 }
1341
1342 if (pool->base.irqs != NULL) {
1343 dal_irq_service_destroy(&pool->base.irqs);
1344 }
1345 }
1346
1347 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1348 if (pool->base.engines[i] != NULL)
1349 dce110_engine_destroy(&pool->base.engines[i]);
1350 if (pool->base.hw_i2cs[i] != NULL) {
1351 kfree(pool->base.hw_i2cs[i]);
1352 pool->base.hw_i2cs[i] = NULL;
1353 }
1354 if (pool->base.sw_i2cs[i] != NULL) {
1355 kfree(pool->base.sw_i2cs[i]);
1356 pool->base.sw_i2cs[i] = NULL;
1357 }
1358 }
1359
1360 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1361 if (pool->base.opps[i] != NULL)
1362 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1363 }
1364
1365 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1366 if (pool->base.timing_generators[i] != NULL) {
1367 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1368 pool->base.timing_generators[i] = NULL;
1369 }
1370 }
1371
1372 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1373 if (pool->base.dwbc[i] != NULL) {
1374 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1375 pool->base.dwbc[i] = NULL;
1376 }
1377 if (pool->base.mcif_wb[i] != NULL) {
1378 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1379 pool->base.mcif_wb[i] = NULL;
1380 }
1381 }
1382
1383 for (i = 0; i < pool->base.audio_count; i++) {
1384 if (pool->base.audios[i])
1385 dce_aud_destroy(&pool->base.audios[i]);
1386 }
1387
1388 for (i = 0; i < pool->base.clk_src_count; i++) {
1389 if (pool->base.clock_sources[i] != NULL) {
1390 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1391 pool->base.clock_sources[i] = NULL;
1392 }
1393 }
1394
1395 if (pool->base.dp_clock_source != NULL) {
1396 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1397 pool->base.dp_clock_source = NULL;
1398 }
1399
1400
1401 if (pool->base.abm != NULL)
1402 dce_abm_destroy(&pool->base.abm);
1403
1404 if (pool->base.dmcu != NULL)
1405 dce_dmcu_destroy(&pool->base.dmcu);
1406
1407 if (pool->base.dccg != NULL)
1408 dcn_dccg_destroy(&pool->base.dccg);
1409
1410 if (pool->base.pp_smu != NULL)
1411 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1412
1413 }
1414
1415 struct hubp *dcn20_hubp_create(
1416 struct dc_context *ctx,
1417 uint32_t inst)
1418 {
1419 struct dcn20_hubp *hubp2 =
1420 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1421
1422 if (!hubp2)
1423 return NULL;
1424
1425 if (hubp2_construct(hubp2, ctx, inst,
1426 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1427 return &hubp2->base;
1428
1429 BREAK_TO_DEBUGGER();
1430 kfree(hubp2);
1431 return NULL;
1432 }
1433
1434 static void get_pixel_clock_parameters(
1435 struct pipe_ctx *pipe_ctx,
1436 struct pixel_clk_params *pixel_clk_params)
1437 {
1438 const struct dc_stream_state *stream = pipe_ctx->stream;
1439 struct pipe_ctx *odm_pipe;
1440 int opp_cnt = 1;
1441
1442 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1443 opp_cnt++;
1444
1445 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1446 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1447 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1448 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1449
1450 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1451 LINK_RATE_REF_FREQ_IN_KHZ;
1452 pixel_clk_params->flags.ENABLE_SS = 0;
1453 pixel_clk_params->color_depth =
1454 stream->timing.display_color_depth;
1455 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1456 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1457
1458 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1459 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1460
1461 if (opp_cnt == 4)
1462 pixel_clk_params->requested_pix_clk_100hz /= 4;
1463 else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1464 pixel_clk_params->requested_pix_clk_100hz /= 2;
1465
1466 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1467 pixel_clk_params->requested_pix_clk_100hz *= 2;
1468
1469 }
1470
1471 static void build_clamping_params(struct dc_stream_state *stream)
1472 {
1473 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1474 stream->clamping.c_depth = stream->timing.display_color_depth;
1475 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1476 }
1477
1478 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1479 {
1480
1481 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1482
1483 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1484 pipe_ctx->clock_source,
1485 &pipe_ctx->stream_res.pix_clk_params,
1486 &pipe_ctx->pll_settings);
1487
1488 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1489
1490 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1491 &pipe_ctx->stream->bit_depth_params);
1492 build_clamping_params(pipe_ctx->stream);
1493
1494 return DC_OK;
1495 }
1496
1497 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1498 {
1499 enum dc_status status = DC_OK;
1500 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520 if (!pipe_ctx)
1521 return DC_ERROR_UNEXPECTED;
1522
1523
1524 status = build_pipe_hw_param(pipe_ctx);
1525
1526 return status;
1527 }
1528
1529 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1530
1531 static void acquire_dsc(struct resource_context *res_ctx,
1532 const struct resource_pool *pool,
1533 struct display_stream_compressor **dsc,
1534 int pipe_idx)
1535 {
1536 int i;
1537
1538 ASSERT(*dsc == NULL);
1539 *dsc = NULL;
1540
1541 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1542 *dsc = pool->dscs[pipe_idx];
1543 res_ctx->is_dsc_acquired[pipe_idx] = true;
1544 return;
1545 }
1546
1547
1548 for (i = 0; i < pool->res_cap->num_dsc; i++)
1549 if (!res_ctx->is_dsc_acquired[i]) {
1550 *dsc = pool->dscs[i];
1551 res_ctx->is_dsc_acquired[i] = true;
1552 break;
1553 }
1554 }
1555
1556 static void release_dsc(struct resource_context *res_ctx,
1557 const struct resource_pool *pool,
1558 struct display_stream_compressor **dsc)
1559 {
1560 int i;
1561
1562 for (i = 0; i < pool->res_cap->num_dsc; i++)
1563 if (pool->dscs[i] == *dsc) {
1564 res_ctx->is_dsc_acquired[i] = false;
1565 *dsc = NULL;
1566 break;
1567 }
1568 }
1569
1570 #endif
1571
1572
1573 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1574 static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
1575 struct dc_state *dc_ctx,
1576 struct dc_stream_state *dc_stream)
1577 {
1578 enum dc_status result = DC_OK;
1579 int i;
1580 const struct resource_pool *pool = dc->res_pool;
1581
1582
1583 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1584 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1585
1586 if (pipe_ctx->stream != dc_stream)
1587 continue;
1588
1589 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
1590
1591
1592 if (!pipe_ctx->stream_res.dsc) {
1593 dm_output_to_console("No DSCs available\n");
1594 result = DC_NO_DSC_RESOURCE;
1595 }
1596
1597 break;
1598 }
1599
1600 return result;
1601 }
1602
1603
1604 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1605 struct dc_state *new_ctx,
1606 struct dc_stream_state *dc_stream)
1607 {
1608 struct pipe_ctx *pipe_ctx = NULL;
1609 int i;
1610
1611 for (i = 0; i < MAX_PIPES; i++) {
1612 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1613 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1614
1615 if (pipe_ctx->stream_res.dsc)
1616 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1617 }
1618 }
1619
1620 if (!pipe_ctx)
1621 return DC_ERROR_UNEXPECTED;
1622 else
1623 return DC_OK;
1624 }
1625 #endif
1626
1627
1628 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1629 {
1630 enum dc_status result = DC_ERROR_UNEXPECTED;
1631
1632 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1633
1634 if (result == DC_OK)
1635 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1636
1637 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1638
1639 if (result == DC_OK && dc_stream->timing.flags.DSC)
1640 result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1641 #endif
1642
1643 if (result == DC_OK)
1644 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1645
1646 return result;
1647 }
1648
1649
1650 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1651 {
1652 enum dc_status result = DC_OK;
1653
1654 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1655 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1656 #endif
1657
1658 return result;
1659 }
1660
1661
1662 static void swizzle_to_dml_params(
1663 enum swizzle_mode_values swizzle,
1664 unsigned int *sw_mode)
1665 {
1666 switch (swizzle) {
1667 case DC_SW_LINEAR:
1668 *sw_mode = dm_sw_linear;
1669 break;
1670 case DC_SW_4KB_S:
1671 *sw_mode = dm_sw_4kb_s;
1672 break;
1673 case DC_SW_4KB_S_X:
1674 *sw_mode = dm_sw_4kb_s_x;
1675 break;
1676 case DC_SW_4KB_D:
1677 *sw_mode = dm_sw_4kb_d;
1678 break;
1679 case DC_SW_4KB_D_X:
1680 *sw_mode = dm_sw_4kb_d_x;
1681 break;
1682 case DC_SW_64KB_S:
1683 *sw_mode = dm_sw_64kb_s;
1684 break;
1685 case DC_SW_64KB_S_X:
1686 *sw_mode = dm_sw_64kb_s_x;
1687 break;
1688 case DC_SW_64KB_S_T:
1689 *sw_mode = dm_sw_64kb_s_t;
1690 break;
1691 case DC_SW_64KB_D:
1692 *sw_mode = dm_sw_64kb_d;
1693 break;
1694 case DC_SW_64KB_D_X:
1695 *sw_mode = dm_sw_64kb_d_x;
1696 break;
1697 case DC_SW_64KB_D_T:
1698 *sw_mode = dm_sw_64kb_d_t;
1699 break;
1700 case DC_SW_64KB_R_X:
1701 *sw_mode = dm_sw_64kb_r_x;
1702 break;
1703 case DC_SW_VAR_S:
1704 *sw_mode = dm_sw_var_s;
1705 break;
1706 case DC_SW_VAR_S_X:
1707 *sw_mode = dm_sw_var_s_x;
1708 break;
1709 case DC_SW_VAR_D:
1710 *sw_mode = dm_sw_var_d;
1711 break;
1712 case DC_SW_VAR_D_X:
1713 *sw_mode = dm_sw_var_d_x;
1714 break;
1715
1716 default:
1717 ASSERT(0);
1718 break;
1719 }
1720 }
1721
1722 static bool dcn20_split_stream_for_odm(
1723 struct resource_context *res_ctx,
1724 const struct resource_pool *pool,
1725 struct pipe_ctx *prev_odm_pipe,
1726 struct pipe_ctx *next_odm_pipe)
1727 {
1728 int pipe_idx = next_odm_pipe->pipe_idx;
1729
1730 *next_odm_pipe = *prev_odm_pipe;
1731
1732 next_odm_pipe->pipe_idx = pipe_idx;
1733 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1734 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1735 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1736 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1737 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1738 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1739 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1740 next_odm_pipe->stream_res.dsc = NULL;
1741 #endif
1742 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1743 ASSERT(!next_odm_pipe->next_odm_pipe);
1744 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1745 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1746 }
1747 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1748 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1749 ASSERT(next_odm_pipe->top_pipe == NULL);
1750
1751 if (prev_odm_pipe->plane_state) {
1752 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1753 int new_width;
1754
1755
1756 sd->h_active /= 2;
1757
1758
1759 if (sd->recout.x + 16 >= sd->h_active)
1760 return false;
1761 new_width = sd->h_active - sd->recout.x;
1762 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1763 sd->ratios.horz, sd->recout.width - new_width));
1764 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1765 sd->ratios.horz_c, sd->recout.width - new_width));
1766 sd->recout.width = new_width;
1767
1768
1769 sd = &next_odm_pipe->plane_res.scl_data;
1770
1771 sd->h_active /= 2;
1772
1773 if (new_width <= 16)
1774 return false;
1775 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1776 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1777 sd->ratios.horz, sd->recout.width - new_width));
1778 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1779 sd->ratios.horz_c, sd->recout.width - new_width));
1780 sd->recout.width = new_width;
1781 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1782 sd->ratios.horz, sd->h_active - sd->recout.x));
1783 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1784 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1785 sd->recout.x = 0;
1786 }
1787 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1788 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1789 if (next_odm_pipe->stream->timing.flags.DSC == 1) {
1790 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1791 ASSERT(next_odm_pipe->stream_res.dsc);
1792 if (next_odm_pipe->stream_res.dsc == NULL)
1793 return false;
1794 }
1795 #endif
1796
1797 return true;
1798 }
1799
1800 static void dcn20_split_stream_for_mpc(
1801 struct resource_context *res_ctx,
1802 const struct resource_pool *pool,
1803 struct pipe_ctx *primary_pipe,
1804 struct pipe_ctx *secondary_pipe)
1805 {
1806 int pipe_idx = secondary_pipe->pipe_idx;
1807 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1808
1809 *secondary_pipe = *primary_pipe;
1810 secondary_pipe->bottom_pipe = sec_bot_pipe;
1811
1812 secondary_pipe->pipe_idx = pipe_idx;
1813 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1814 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1815 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1816 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1817 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1818 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1819 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1820 secondary_pipe->stream_res.dsc = NULL;
1821 #endif
1822 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1823 ASSERT(!secondary_pipe->bottom_pipe);
1824 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1825 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1826 }
1827 primary_pipe->bottom_pipe = secondary_pipe;
1828 secondary_pipe->top_pipe = primary_pipe;
1829
1830 ASSERT(primary_pipe->plane_state);
1831 resource_build_scaling_params(primary_pipe);
1832 resource_build_scaling_params(secondary_pipe);
1833 }
1834
1835 void dcn20_populate_dml_writeback_from_context(
1836 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1837 {
1838 int pipe_cnt, i;
1839
1840 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1841 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1842
1843 if (!res_ctx->pipe_ctx[i].stream)
1844 continue;
1845
1846
1847 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1848 pipes[pipe_cnt].dout.num_active_wb++;
1849 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1850 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1851 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1852 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1853 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1854 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1855 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1856 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1857 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1858 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1859 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1860 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1861 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1862 else
1863 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1864 } else
1865 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1866
1867 pipe_cnt++;
1868 }
1869
1870 }
1871
1872 int dcn20_populate_dml_pipes_from_context(
1873 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1874 {
1875 int pipe_cnt, i;
1876 bool synchronized_vblank = true;
1877
1878 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1879 if (!res_ctx->pipe_ctx[i].stream)
1880 continue;
1881
1882 if (pipe_cnt < 0) {
1883 pipe_cnt = i;
1884 continue;
1885 }
1886 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
1887 res_ctx->pipe_ctx[pipe_cnt].stream,
1888 res_ctx->pipe_ctx[i].stream)) {
1889 synchronized_vblank = false;
1890 break;
1891 }
1892 }
1893
1894 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1895 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
1896 int output_bpc;
1897
1898 if (!res_ctx->pipe_ctx[i].stream)
1899 continue;
1900
1901
1902
1903
1904
1905 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1906 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
1907
1908 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
1909 #endif
1910 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
1911 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
1912
1913 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
1914 (timing->v_total - timing->v_addressable
1915 - timing->v_border_top - timing->v_border_bottom) / 2;
1916
1917 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
1918 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
1919 }
1920 pipes[pipe_cnt].pipe.src.dcc = false;
1921 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
1922 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
1923 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
1924 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
1925 - timing->h_addressable
1926 - timing->h_border_left
1927 - timing->h_border_right;
1928 pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
1929 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
1930 - timing->v_addressable
1931 - timing->v_border_top
1932 - timing->v_border_bottom;
1933 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
1934 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
1935 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
1936 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
1937 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
1938 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
1939 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1940 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
1941 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1942 pipes[pipe_cnt].dout.dp_lanes = 4;
1943 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
1944 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
1945 pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe
1946 || res_ctx->pipe_ctx[i].next_odm_pipe;
1947 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
1948 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
1949 == res_ctx->pipe_ctx[i].plane_state)
1950 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
1951 else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
1952 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
1953
1954 while (first_pipe->prev_odm_pipe)
1955 first_pipe = first_pipe->prev_odm_pipe;
1956 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
1957 }
1958
1959 switch (res_ctx->pipe_ctx[i].stream->signal) {
1960 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1961 case SIGNAL_TYPE_DISPLAY_PORT:
1962 pipes[pipe_cnt].dout.output_type = dm_dp;
1963 break;
1964 case SIGNAL_TYPE_EDP:
1965 pipes[pipe_cnt].dout.output_type = dm_edp;
1966 break;
1967 case SIGNAL_TYPE_HDMI_TYPE_A:
1968 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1969 case SIGNAL_TYPE_DVI_DUAL_LINK:
1970 pipes[pipe_cnt].dout.output_type = dm_hdmi;
1971 break;
1972 default:
1973
1974 pipes[pipe_cnt].dout.output_type = dm_dp;
1975 pipes[pipe_cnt].dout.dp_lanes = 4;
1976 }
1977
1978 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
1979 case COLOR_DEPTH_666:
1980 output_bpc = 6;
1981 break;
1982 case COLOR_DEPTH_888:
1983 output_bpc = 8;
1984 break;
1985 case COLOR_DEPTH_101010:
1986 output_bpc = 10;
1987 break;
1988 case COLOR_DEPTH_121212:
1989 output_bpc = 12;
1990 break;
1991 case COLOR_DEPTH_141414:
1992 output_bpc = 14;
1993 break;
1994 case COLOR_DEPTH_161616:
1995 output_bpc = 16;
1996 break;
1997 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
1998 case COLOR_DEPTH_999:
1999 output_bpc = 9;
2000 break;
2001 case COLOR_DEPTH_111111:
2002 output_bpc = 11;
2003 break;
2004 #endif
2005 default:
2006 output_bpc = 8;
2007 break;
2008 }
2009
2010 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2011 case PIXEL_ENCODING_RGB:
2012 case PIXEL_ENCODING_YCBCR444:
2013 pipes[pipe_cnt].dout.output_format = dm_444;
2014 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2015 break;
2016 case PIXEL_ENCODING_YCBCR420:
2017 pipes[pipe_cnt].dout.output_format = dm_420;
2018 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3) / 2;
2019 break;
2020 case PIXEL_ENCODING_YCBCR422:
2021 if (true)
2022 pipes[pipe_cnt].dout.output_format = dm_s422;
2023 else
2024 pipes[pipe_cnt].dout.output_format = dm_n422;
2025 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
2026 break;
2027 default:
2028 pipes[pipe_cnt].dout.output_format = dm_444;
2029 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2030 }
2031
2032
2033 pipes[pipe_cnt].dout.output_bpc = 12;
2034
2035
2036
2037
2038 pipes[pipe_cnt].pipe.src.num_cursors = 2;
2039 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2040 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2041 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
2042 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
2043
2044 if (!res_ctx->pipe_ctx[i].plane_state) {
2045 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2046 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
2047 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2048 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2049 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2050 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2051 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2052 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2053 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
2054 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64;
2055 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2056 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width;
2057 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height;
2058 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;
2059 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height;
2060 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2061 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2062 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2063 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0;
2064 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2065 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2066 pipes[pipe_cnt].pipe.src.is_hsplit = 0;
2067 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2068 pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
2069 pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
2070 } else {
2071 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2072 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2073
2074 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2075 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
2076 && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2077 || (res_ctx->pipe_ctx[i].top_pipe
2078 && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
2079 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2080 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2081 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2082 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2083 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2084 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2085 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2086 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
2087 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2088 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2089 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2090 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2091 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2092 } else {
2093 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2094 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2095 }
2096 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2097 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2098 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2099 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2100 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2101 if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
2102 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2103 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
2104 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2105 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
2106 } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
2107 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2108 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
2109 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2110 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
2111 }
2112
2113 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2114 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2115 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2116 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2117 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2118 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2119 scl->ratios.vert.value != dc_fixpt_one.value
2120 || scl->ratios.horz.value != dc_fixpt_one.value
2121 || scl->ratios.vert_c.value != dc_fixpt_one.value
2122 || scl->ratios.horz_c.value != dc_fixpt_one.value
2123 || dc->debug.always_scale;
2124 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2125 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2126 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2127 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2128
2129 pipes[pipe_cnt].pipe.src.macro_tile_size =
2130 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2131 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2132 &pipes[pipe_cnt].pipe.src.sw_mode);
2133
2134 switch (pln->format) {
2135 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2136 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2137 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2138 break;
2139 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2140 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2141 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2142 break;
2143 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2144 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2145 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2146 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2147 break;
2148 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2149 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2150 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2151 break;
2152 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2153 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2154 break;
2155 default:
2156 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2157 break;
2158 }
2159 }
2160
2161 pipe_cnt++;
2162 }
2163
2164
2165 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2166
2167 return pipe_cnt;
2168 }
2169
2170 unsigned int dcn20_calc_max_scaled_time(
2171 unsigned int time_per_pixel,
2172 enum mmhubbub_wbif_mode mode,
2173 unsigned int urgent_watermark)
2174 {
2175 unsigned int time_per_byte = 0;
2176 unsigned int total_y_free_entry = 0x200;
2177 unsigned int total_c_free_entry = 0x140;
2178 unsigned int small_free_entry, max_free_entry;
2179 unsigned int buf_lh_capability;
2180 unsigned int max_scaled_time;
2181
2182 if (mode == PACKED_444)
2183 time_per_byte = time_per_pixel/4;
2184 else if (mode == PLANAR_420_8BPC)
2185 time_per_byte = time_per_pixel;
2186 else if (mode == PLANAR_420_10BPC)
2187 time_per_byte = time_per_pixel * 819/1024;
2188
2189 if (time_per_byte == 0)
2190 time_per_byte = 1;
2191
2192 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2193 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2194 buf_lh_capability = max_free_entry*time_per_byte*32/16;
2195 max_scaled_time = buf_lh_capability - urgent_watermark;
2196 return max_scaled_time;
2197 }
2198
2199 void dcn20_set_mcif_arb_params(
2200 struct dc *dc,
2201 struct dc_state *context,
2202 display_e2e_pipe_params_st *pipes,
2203 int pipe_cnt)
2204 {
2205 enum mmhubbub_wbif_mode wbif_mode;
2206 struct mcif_arb_params *wb_arb_params;
2207 int i, j, k, dwb_pipe;
2208
2209
2210 dwb_pipe = 0;
2211 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2212
2213 if (!context->res_ctx.pipe_ctx[i].stream)
2214 continue;
2215
2216 for (j = 0; j < MAX_DWB_PIPES; j++) {
2217 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2218 continue;
2219
2220
2221 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2222
2223 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2224 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2225 wbif_mode = PLANAR_420_8BPC;
2226 else
2227 wbif_mode = PLANAR_420_10BPC;
2228 } else
2229 wbif_mode = PACKED_444;
2230
2231 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2232 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2233 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2234 }
2235 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
2236 wb_arb_params->slice_lines = 32;
2237 wb_arb_params->arbitration_slice = 2;
2238 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2239 wbif_mode,
2240 wb_arb_params->cli_watermark[0]);
2241
2242 dwb_pipe++;
2243
2244 if (dwb_pipe >= MAX_DWB_PIPES)
2245 return;
2246 }
2247 if (dwb_pipe >= MAX_DWB_PIPES)
2248 return;
2249 }
2250 }
2251
2252 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2253 static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2254 {
2255 int i;
2256
2257
2258 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2259 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2260 struct dc_stream_state *stream = pipe_ctx->stream;
2261 struct dsc_config dsc_cfg;
2262 struct pipe_ctx *odm_pipe;
2263 int opp_cnt = 1;
2264
2265 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2266 opp_cnt++;
2267
2268
2269 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2270 continue;
2271
2272 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2273 + stream->timing.h_border_right) / opp_cnt;
2274 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2275 + stream->timing.v_border_bottom;
2276 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2277 dsc_cfg.color_depth = stream->timing.display_color_depth;
2278 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2279 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2280
2281 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2282 return false;
2283 }
2284 return true;
2285 }
2286 #endif
2287
2288 static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2289 struct resource_context *res_ctx,
2290 const struct resource_pool *pool,
2291 const struct pipe_ctx *primary_pipe)
2292 {
2293 struct pipe_ctx *secondary_pipe = NULL;
2294
2295 if (dc && primary_pipe) {
2296 int j;
2297 int preferred_pipe_idx = 0;
2298
2299
2300
2301
2302
2303
2304
2305
2306 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2307 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2308 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2309 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2310 secondary_pipe->pipe_idx = preferred_pipe_idx;
2311 }
2312 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2313 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2314 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2315 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2316 secondary_pipe->pipe_idx = preferred_pipe_idx;
2317 }
2318 }
2319
2320
2321
2322
2323
2324
2325
2326 if (secondary_pipe == NULL) {
2327 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2328 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL) {
2329 preferred_pipe_idx = j;
2330
2331 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2332 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2333 secondary_pipe->pipe_idx = preferred_pipe_idx;
2334 break;
2335 }
2336 }
2337 }
2338 }
2339
2340
2341
2342
2343 ASSERT(secondary_pipe);
2344
2345
2346
2347
2348 if (secondary_pipe == NULL) {
2349 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2350 preferred_pipe_idx = j;
2351
2352 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2353 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2354 secondary_pipe->pipe_idx = preferred_pipe_idx;
2355 break;
2356 }
2357 }
2358 }
2359 }
2360
2361 return secondary_pipe;
2362 }
2363
2364 bool dcn20_fast_validate_bw(
2365 struct dc *dc,
2366 struct dc_state *context,
2367 display_e2e_pipe_params_st *pipes,
2368 int *pipe_cnt_out,
2369 int *pipe_split_from,
2370 int *vlevel_out)
2371 {
2372 bool out = false;
2373
2374 int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
2375 bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
2376 bool force_split = false;
2377 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2378 bool failed_non_odm_dsc = false;
2379 #endif
2380 int split_threshold = dc->res_pool->pipe_count / 2;
2381 bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
2382
2383
2384 ASSERT(pipes);
2385 if (!pipes)
2386 return false;
2387
2388
2389 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2390 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2391 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2392
2393 if (pipe->prev_odm_pipe)
2394 continue;
2395
2396 pipe->next_odm_pipe = NULL;
2397 while (odm_pipe) {
2398 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2399
2400 odm_pipe->plane_state = NULL;
2401 odm_pipe->stream = NULL;
2402 odm_pipe->top_pipe = NULL;
2403 odm_pipe->bottom_pipe = NULL;
2404 odm_pipe->prev_odm_pipe = NULL;
2405 odm_pipe->next_odm_pipe = NULL;
2406 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2407 if (odm_pipe->stream_res.dsc)
2408 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2409 #endif
2410
2411 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2412 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2413 odm_pipe = next_odm_pipe;
2414 }
2415 if (pipe->plane_state)
2416 resource_build_scaling_params(pipe);
2417 }
2418
2419
2420 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2421 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2422 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2423
2424 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2425 continue;
2426
2427 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2428 if (hsplit_pipe->bottom_pipe)
2429 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2430 hsplit_pipe->plane_state = NULL;
2431 hsplit_pipe->stream = NULL;
2432 hsplit_pipe->top_pipe = NULL;
2433 hsplit_pipe->bottom_pipe = NULL;
2434
2435
2436 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2437 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2438 if (pipe->plane_state)
2439 resource_build_scaling_params(pipe);
2440 }
2441
2442 if (dc->res_pool->funcs->populate_dml_pipes)
2443 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2444 &context->res_ctx, pipes);
2445 else
2446 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2447 &context->res_ctx, pipes);
2448
2449 *pipe_cnt_out = pipe_cnt;
2450
2451 if (!pipe_cnt) {
2452 out = true;
2453 goto validate_out;
2454 }
2455
2456 context->bw_ctx.dml.ip.odm_capable = 0;
2457
2458 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2459
2460 context->bw_ctx.dml.ip.odm_capable = odm_capable;
2461
2462 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2463
2464 if (vlevel <= context->bw_ctx.dml.soc.num_states)
2465 if (!dcn20_validate_dsc(dc, context)) {
2466 failed_non_odm_dsc = true;
2467 vlevel = context->bw_ctx.dml.soc.num_states + 1;
2468 }
2469 #endif
2470
2471 if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
2472 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2473
2474 if (vlevel > context->bw_ctx.dml.soc.num_states)
2475 goto validate_fail;
2476
2477 if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
2478 || (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
2479 context->commit_hints.full_update_needed = true;
2480
2481
2482 for (i = 0; i < MAX_PIPES; i++)
2483 pipe_split_from[i] = -1;
2484
2485
2486 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2487 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2488 bool exit_loop = false;
2489
2490 if (!pipe->stream || pipe->top_pipe)
2491 continue;
2492
2493 if (dc->debug.force_single_disp_pipe_split) {
2494 if (!force_split)
2495 force_split = true;
2496 else {
2497 force_split = false;
2498 exit_loop = true;
2499 }
2500 }
2501 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2502 if (avoid_split)
2503 avoid_split = false;
2504 else {
2505 avoid_split = true;
2506 exit_loop = true;
2507 }
2508 }
2509 if (exit_loop)
2510 break;
2511 }
2512
2513 if (context->stream_count > split_threshold)
2514 avoid_split = true;
2515
2516 vlevel_unsplit = vlevel;
2517 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2518 if (!context->res_ctx.pipe_ctx[i].stream)
2519 continue;
2520 for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
2521 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
2522 break;
2523 pipe_idx++;
2524 }
2525
2526 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2527 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2528 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2529 bool need_split = true;
2530 bool need_split3d;
2531
2532 if (!pipe->stream || pipe_split_from[i] >= 0)
2533 continue;
2534
2535 pipe_idx++;
2536
2537 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2538 force_split = true;
2539 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
2540 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
2541 }
2542 if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2543 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
2544 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2545 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2546 ASSERT(hsplit_pipe);
2547 if (!dcn20_split_stream_for_odm(
2548 &context->res_ctx, dc->res_pool,
2549 pipe, hsplit_pipe))
2550 goto validate_fail;
2551 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2552 dcn20_build_mapped_resource(dc, context, pipe->stream);
2553 }
2554
2555 if (!pipe->plane_state)
2556 continue;
2557
2558 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2559 continue;
2560
2561 need_split3d = ((pipe->stream->view_format ==
2562 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2563 pipe->stream->view_format ==
2564 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2565 (pipe->stream->timing.timing_3d_format ==
2566 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2567 pipe->stream->timing.timing_3d_format ==
2568 TIMING_3D_FORMAT_SIDE_BY_SIDE));
2569
2570 if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
2571 need_split = false;
2572 vlevel = vlevel_unsplit;
2573 context->bw_ctx.dml.vba.maxMpcComb = 0;
2574 } else
2575 need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
2576
2577
2578 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2579 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2580 goto validate_fail;
2581
2582 if (need_split3d || need_split || force_split) {
2583 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2584
2585 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2586 ASSERT(hsplit_pipe || force_split);
2587 if (!hsplit_pipe)
2588 continue;
2589
2590 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2591 if (!dcn20_split_stream_for_odm(
2592 &context->res_ctx, dc->res_pool,
2593 pipe, hsplit_pipe))
2594 goto validate_fail;
2595 dcn20_build_mapped_resource(dc, context, pipe->stream);
2596 } else
2597 dcn20_split_stream_for_mpc(
2598 &context->res_ctx, dc->res_pool,
2599 pipe, hsplit_pipe);
2600 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2601 }
2602 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2603
2604 ASSERT(0);
2605 }
2606 }
2607 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2608
2609 if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
2610 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2611 DML_FAIL_DSC_VALIDATION_FAILURE;
2612 goto validate_fail;
2613 }
2614 #endif
2615
2616 *vlevel_out = vlevel;
2617
2618 out = true;
2619 goto validate_out;
2620
2621 validate_fail:
2622 out = false;
2623
2624 validate_out:
2625 return out;
2626 }
2627
2628 void dcn20_calculate_wm(
2629 struct dc *dc, struct dc_state *context,
2630 display_e2e_pipe_params_st *pipes,
2631 int *out_pipe_cnt,
2632 int *pipe_split_from,
2633 int vlevel)
2634 {
2635 int pipe_cnt, i, pipe_idx;
2636
2637 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2638 if (!context->res_ctx.pipe_ctx[i].stream)
2639 continue;
2640
2641 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2642 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2643
2644 if (pipe_split_from[i] < 0) {
2645 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2646 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2647 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2648 pipes[pipe_cnt].pipe.dest.odm_combine =
2649 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
2650 else
2651 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2652 pipe_idx++;
2653 } else {
2654 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2655 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2656 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2657 pipes[pipe_cnt].pipe.dest.odm_combine =
2658 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
2659 else
2660 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2661 }
2662
2663 if (dc->config.forced_clocks) {
2664 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2665 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2666 }
2667 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2668 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2669 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2670 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2671
2672 pipe_cnt++;
2673 }
2674
2675 if (pipe_cnt != pipe_idx) {
2676 if (dc->res_pool->funcs->populate_dml_pipes)
2677 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2678 &context->res_ctx, pipes);
2679 else
2680 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2681 &context->res_ctx, pipes);
2682 }
2683
2684 *out_pipe_cnt = pipe_cnt;
2685
2686 pipes[0].clks_cfg.voltage = vlevel;
2687 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2688 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2689
2690
2691 if (vlevel < 1) {
2692 pipes[0].clks_cfg.voltage = 1;
2693 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2694 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2695 }
2696 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2697 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2698 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2699 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2700 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2701
2702 if (vlevel < 2) {
2703 pipes[0].clks_cfg.voltage = 2;
2704 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2705 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2706 }
2707 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2708 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2709 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2710 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2711 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2712
2713 if (vlevel < 3) {
2714 pipes[0].clks_cfg.voltage = 3;
2715 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2716 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2717 }
2718 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2719 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2720 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2721 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2722 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2723
2724 pipes[0].clks_cfg.voltage = vlevel;
2725 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2726 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2727 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2728 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2729 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2730 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2731 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2732 }
2733
2734 void dcn20_calculate_dlg_params(
2735 struct dc *dc, struct dc_state *context,
2736 display_e2e_pipe_params_st *pipes,
2737 int pipe_cnt,
2738 int vlevel)
2739 {
2740 int i, j, pipe_idx, pipe_idx_unsplit;
2741 bool visited[MAX_PIPES] = { 0 };
2742
2743
2744 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2745
2746 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2747 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2748 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
2749 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
2750 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
2751 context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
2752 context->bw_ctx.bw.dcn.clk.p_state_change_support =
2753 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2754 != dm_dram_clock_change_unsupported;
2755 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2756
2757
2758
2759
2760
2761
2762 for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
2763 if (!context->res_ctx.pipe_ctx[i].stream)
2764 continue;
2765
2766 if (!visited[pipe_idx]) {
2767 display_pipe_source_params_st *src = &pipes[pipe_idx_unsplit].pipe.src;
2768 display_pipe_dest_params_st *dst = &pipes[pipe_idx_unsplit].pipe.dest;
2769
2770 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2771 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2772 dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2773 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2774
2775
2776
2777
2778 if (src->is_hsplit)
2779 for (j = pipe_idx + 1; j < pipe_cnt; j++) {
2780 display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2781 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2782
2783 if (src_j->is_hsplit && !visited[j]
2784 && src->hsplit_grp == src_j->hsplit_grp) {
2785 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2786 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2787 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2788 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2789 visited[j] = true;
2790 }
2791 }
2792 visited[pipe_idx] = true;
2793 pipe_idx_unsplit++;
2794 }
2795 pipe_idx++;
2796 }
2797
2798 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2799 if (!context->res_ctx.pipe_ctx[i].stream)
2800 continue;
2801 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2802 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2803 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2804 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2805 ASSERT(visited[pipe_idx]);
2806 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2807 pipe_idx++;
2808 }
2809
2810 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
2811 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
2812 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
2813 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
2814
2815 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2816 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2817
2818 if (!context->res_ctx.pipe_ctx[i].stream)
2819 continue;
2820
2821 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2822 &context->res_ctx.pipe_ctx[i].dlg_regs,
2823 &context->res_ctx.pipe_ctx[i].ttu_regs,
2824 pipes,
2825 pipe_cnt,
2826 pipe_idx,
2827 cstate_en,
2828 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2829 false, false, false);
2830
2831 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2832 &context->res_ctx.pipe_ctx[i].rq_regs,
2833 pipes[pipe_idx].pipe);
2834 pipe_idx++;
2835 }
2836 }
2837
2838 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
2839 bool fast_validate)
2840 {
2841 bool out = false;
2842
2843 BW_VAL_TRACE_SETUP();
2844
2845 int vlevel = 0;
2846 int pipe_split_from[MAX_PIPES];
2847 int pipe_cnt = 0;
2848 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2849 DC_LOGGER_INIT(dc->ctx->logger);
2850
2851 BW_VAL_TRACE_COUNT();
2852
2853 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
2854
2855 if (pipe_cnt == 0)
2856 goto validate_out;
2857
2858 if (!out)
2859 goto validate_fail;
2860
2861 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2862
2863 if (fast_validate) {
2864 BW_VAL_TRACE_SKIP(fast);
2865 goto validate_out;
2866 }
2867
2868 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
2869 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2870
2871 BW_VAL_TRACE_END_WATERMARKS();
2872
2873 goto validate_out;
2874
2875 validate_fail:
2876 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2877 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2878
2879 BW_VAL_TRACE_SKIP(fail);
2880 out = false;
2881
2882 validate_out:
2883 kfree(pipes);
2884
2885 BW_VAL_TRACE_FINISH();
2886
2887 return out;
2888 }
2889
2890
2891 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2892 bool fast_validate)
2893 {
2894 bool voltage_supported = false;
2895 bool full_pstate_supported = false;
2896 bool dummy_pstate_supported = false;
2897 double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
2898
2899 if (fast_validate)
2900 return dcn20_validate_bandwidth_internal(dc, context, true);
2901
2902
2903
2904 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2905 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2906
2907 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
2908 (voltage_supported && full_pstate_supported)) {
2909 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
2910 goto restore_dml_state;
2911 }
2912
2913
2914 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2915
2916 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
2917 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2918
2919 if (voltage_supported && dummy_pstate_supported) {
2920 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
2921 goto restore_dml_state;
2922 }
2923
2924
2925 ASSERT(false);
2926
2927 restore_dml_state:
2928 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
2929 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
2930
2931 return voltage_supported;
2932 }
2933
2934 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
2935 struct dc_state *state,
2936 const struct resource_pool *pool,
2937 struct dc_stream_state *stream)
2938 {
2939 struct resource_context *res_ctx = &state->res_ctx;
2940 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
2941 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
2942
2943 if (!head_pipe)
2944 ASSERT(0);
2945
2946 if (!idle_pipe)
2947 return NULL;
2948
2949 idle_pipe->stream = head_pipe->stream;
2950 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2951 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2952
2953 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2954 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2955 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2956 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2957
2958 return idle_pipe;
2959 }
2960
2961 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2962 const struct dc_dcc_surface_param *input,
2963 struct dc_surface_dcc_cap *output)
2964 {
2965 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2966 dc->res_pool->hubbub,
2967 input,
2968 output);
2969 }
2970
2971 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2972 {
2973 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2974
2975 destruct(dcn20_pool);
2976 kfree(dcn20_pool);
2977 *pool = NULL;
2978 }
2979
2980
2981 static struct dc_cap_funcs cap_funcs = {
2982 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2983 };
2984
2985
2986 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
2987 {
2988 enum dc_status result = DC_OK;
2989
2990 enum surface_pixel_format surf_pix_format = plane_state->format;
2991 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2992
2993 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
2994
2995 if (bpp == 64)
2996 swizzle = DC_SW_64KB_D;
2997 else
2998 swizzle = DC_SW_64KB_S;
2999
3000 plane_state->tiling_info.gfx9.swizzle = swizzle;
3001 return result;
3002 }
3003
3004 static struct resource_funcs dcn20_res_pool_funcs = {
3005 .destroy = dcn20_destroy_resource_pool,
3006 .link_enc_create = dcn20_link_encoder_create,
3007 .validate_bandwidth = dcn20_validate_bandwidth,
3008 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3009 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
3010 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3011 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
3012 .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
3013 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
3014 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
3015 };
3016
3017 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3018 {
3019 int i;
3020 uint32_t pipe_count = pool->res_cap->num_dwb;
3021
3022 ASSERT(pipe_count > 0);
3023
3024 for (i = 0; i < pipe_count; i++) {
3025 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3026 GFP_KERNEL);
3027
3028 if (!dwbc20) {
3029 dm_error("DC: failed to create dwbc20!\n");
3030 return false;
3031 }
3032 dcn20_dwbc_construct(dwbc20, ctx,
3033 &dwbc20_regs[i],
3034 &dwbc20_shift,
3035 &dwbc20_mask,
3036 i);
3037 pool->dwbc[i] = &dwbc20->base;
3038 }
3039 return true;
3040 }
3041
3042 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3043 {
3044 int i;
3045 uint32_t pipe_count = pool->res_cap->num_dwb;
3046
3047 ASSERT(pipe_count > 0);
3048
3049 for (i = 0; i < pipe_count; i++) {
3050 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3051 GFP_KERNEL);
3052
3053 if (!mcif_wb20) {
3054 dm_error("DC: failed to create mcif_wb20!\n");
3055 return false;
3056 }
3057
3058 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3059 &mcif_wb20_regs[i],
3060 &mcif_wb20_shift,
3061 &mcif_wb20_mask,
3062 i);
3063
3064 pool->mcif_wb[i] = &mcif_wb20->base;
3065 }
3066 return true;
3067 }
3068
3069 struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
3070 {
3071 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
3072
3073 if (!pp_smu)
3074 return pp_smu;
3075
3076 dm_pp_get_funcs(ctx, pp_smu);
3077
3078 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3079 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3080
3081 return pp_smu;
3082 }
3083
3084 void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
3085 {
3086 if (pp_smu && *pp_smu) {
3087 kfree(*pp_smu);
3088 *pp_smu = NULL;
3089 }
3090 }
3091
3092 static void cap_soc_clocks(
3093 struct _vcs_dpi_soc_bounding_box_st *bb,
3094 struct pp_smu_nv_clock_table max_clocks)
3095 {
3096 int i;
3097
3098
3099 for (i = 0; i < bb->num_states; i++) {
3100 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3101 && max_clocks.dcfClockInKhz != 0)
3102 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3103
3104 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3105 && max_clocks.uClockInKhz != 0)
3106 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3107
3108 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3109 && max_clocks.fabricClockInKhz != 0)
3110 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3111
3112 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3113 && max_clocks.displayClockInKhz != 0)
3114 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3115
3116 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3117 && max_clocks.dppClockInKhz != 0)
3118 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3119
3120 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3121 && max_clocks.phyClockInKhz != 0)
3122 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3123
3124 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3125 && max_clocks.socClockInKhz != 0)
3126 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3127
3128 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3129 && max_clocks.dscClockInKhz != 0)
3130 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3131 }
3132
3133
3134 for (i = bb->num_states - 1; i > 1; i--) {
3135 bool duplicate = true;
3136
3137 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3138 duplicate = false;
3139 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3140 duplicate = false;
3141 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3142 duplicate = false;
3143 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3144 duplicate = false;
3145 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3146 duplicate = false;
3147 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3148 duplicate = false;
3149 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3150 duplicate = false;
3151 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3152 duplicate = false;
3153
3154 if (duplicate)
3155 bb->num_states--;
3156 }
3157 }
3158
3159 static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
3160 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3161 {
3162 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
3163 int i;
3164 int num_calculated_states = 0;
3165 int min_dcfclk = 0;
3166
3167 if (num_states == 0)
3168 return;
3169
3170 memset(calculated_states, 0, sizeof(calculated_states));
3171
3172 if (dc->bb_overrides.min_dcfclk_mhz > 0)
3173 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
3174 else
3175
3176
3177 min_dcfclk = 507;
3178
3179 for (i = 0; i < num_states; i++) {
3180 int min_fclk_required_by_uclk;
3181 calculated_states[i].state = i;
3182 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
3183
3184
3185 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
3186
3187 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3188 min_dcfclk : min_fclk_required_by_uclk;
3189
3190 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3191 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3192
3193 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3194 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3195
3196 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3197 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3198 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
3199
3200 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
3201
3202 num_calculated_states++;
3203 }
3204
3205 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3206 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3207 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3208
3209 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3210 bb->num_states = num_calculated_states;
3211
3212
3213 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3214 bb->clock_limits[num_calculated_states].state = bb->num_states;
3215 }
3216
3217 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
3218 {
3219 kernel_fpu_begin();
3220 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3221 && dc->bb_overrides.sr_exit_time_ns) {
3222 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3223 }
3224
3225 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3226 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3227 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3228 bb->sr_enter_plus_exit_time_us =
3229 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3230 }
3231
3232 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3233 && dc->bb_overrides.urgent_latency_ns) {
3234 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3235 }
3236
3237 if ((int)(bb->dram_clock_change_latency_us * 1000)
3238 != dc->bb_overrides.dram_clock_change_latency_ns
3239 && dc->bb_overrides.dram_clock_change_latency_ns) {
3240 bb->dram_clock_change_latency_us =
3241 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3242 }
3243 kernel_fpu_end();
3244 }
3245
3246 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3247 uint32_t hw_internal_rev)
3248 {
3249 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3250 return &dcn2_0_nv14_soc;
3251
3252 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3253 return &dcn2_0_nv12_soc;
3254
3255 return &dcn2_0_soc;
3256 }
3257
3258 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3259 uint32_t hw_internal_rev)
3260 {
3261
3262 return &dcn2_0_ip;
3263 }
3264
3265 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3266 {
3267 return DML_PROJECT_NAVI10v2;
3268 }
3269
3270 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3271 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3272
3273 static bool init_soc_bounding_box(struct dc *dc,
3274 struct dcn20_resource_pool *pool)
3275 {
3276 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
3277 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3278 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3279 struct _vcs_dpi_ip_params_st *loaded_ip =
3280 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3281
3282 DC_LOGGER_INIT(dc->ctx->logger);
3283
3284 if (!bb && !SOC_BOUNDING_BOX_VALID) {
3285 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3286 return false;
3287 }
3288
3289 if (bb && !SOC_BOUNDING_BOX_VALID) {
3290 int i;
3291
3292 dcn2_0_nv12_soc.sr_exit_time_us =
3293 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
3294 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
3295 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
3296 dcn2_0_nv12_soc.urgent_latency_us =
3297 fixed16_to_double_to_cpu(bb->urgent_latency_us);
3298 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
3299 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
3300 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
3301 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
3302 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
3303 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
3304 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
3305 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
3306 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
3307 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
3308 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
3309 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
3310 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
3311 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
3312 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
3313 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
3314 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
3315 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
3316 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
3317 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
3318 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
3319 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
3320 dcn2_0_nv12_soc.writeback_latency_us =
3321 fixed16_to_double_to_cpu(bb->writeback_latency_us);
3322 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
3323 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
3324 dcn2_0_nv12_soc.max_request_size_bytes =
3325 le32_to_cpu(bb->max_request_size_bytes);
3326 dcn2_0_nv12_soc.dram_channel_width_bytes =
3327 le32_to_cpu(bb->dram_channel_width_bytes);
3328 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
3329 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
3330 dcn2_0_nv12_soc.dcn_downspread_percent =
3331 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
3332 dcn2_0_nv12_soc.downspread_percent =
3333 fixed16_to_double_to_cpu(bb->downspread_percent);
3334 dcn2_0_nv12_soc.dram_page_open_time_ns =
3335 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
3336 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
3337 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
3338 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
3339 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
3340 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
3341 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
3342 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
3343 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
3344 dcn2_0_nv12_soc.channel_interleave_bytes =
3345 le32_to_cpu(bb->channel_interleave_bytes);
3346 dcn2_0_nv12_soc.num_banks =
3347 le32_to_cpu(bb->num_banks);
3348 dcn2_0_nv12_soc.num_chans =
3349 le32_to_cpu(bb->num_chans);
3350 dcn2_0_nv12_soc.vmm_page_size_bytes =
3351 le32_to_cpu(bb->vmm_page_size_bytes);
3352 dcn2_0_nv12_soc.dram_clock_change_latency_us =
3353 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
3354
3355 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3356 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
3357 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
3358 dcn2_0_nv12_soc.return_bus_width_bytes =
3359 le32_to_cpu(bb->return_bus_width_bytes);
3360 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
3361 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
3362 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
3363 le32_to_cpu(bb->xfc_bus_transport_time_us);
3364 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
3365 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
3366 dcn2_0_nv12_soc.use_urgent_burst_bw =
3367 le32_to_cpu(bb->use_urgent_burst_bw);
3368 dcn2_0_nv12_soc.num_states =
3369 le32_to_cpu(bb->num_states);
3370
3371 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3372 dcn2_0_nv12_soc.clock_limits[i].state =
3373 le32_to_cpu(bb->clock_limits[i].state);
3374 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
3375 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
3376 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
3377 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
3378 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
3379 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
3380 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
3381 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
3382 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
3383 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
3384 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
3385 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
3386 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
3387 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
3388 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
3389 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3390 }
3391 }
3392
3393 if (pool->base.pp_smu) {
3394 struct pp_smu_nv_clock_table max_clocks = {0};
3395 unsigned int uclk_states[8] = {0};
3396 unsigned int num_states = 0;
3397 enum pp_smu_status status;
3398 bool clock_limits_available = false;
3399 bool uclk_states_available = false;
3400
3401 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3402 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3403 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3404
3405 uclk_states_available = (status == PP_SMU_RESULT_OK);
3406 }
3407
3408 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3409 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3410 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3411
3412
3413 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3414 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
3415 clock_limits_available = (status == PP_SMU_RESULT_OK);
3416 }
3417
3418 if (clock_limits_available && uclk_states_available && num_states)
3419 update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3420 else if (clock_limits_available)
3421 cap_soc_clocks(loaded_bb, max_clocks);
3422 }
3423
3424 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3425 loaded_ip->max_num_dpp = pool->base.pipe_count;
3426 patch_bounding_box(dc, loaded_bb);
3427
3428 return true;
3429 }
3430
3431 static bool construct(
3432 uint8_t num_virtual_links,
3433 struct dc *dc,
3434 struct dcn20_resource_pool *pool)
3435 {
3436 int i;
3437 struct dc_context *ctx = dc->ctx;
3438 struct irq_service_init_data init_data;
3439 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3440 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3441 struct _vcs_dpi_ip_params_st *loaded_ip =
3442 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3443 enum dml_project dml_project_version =
3444 get_dml_project_version(ctx->asic_id.hw_internal_rev);
3445
3446 ctx->dc_bios->regs = &bios_regs;
3447 pool->base.funcs = &dcn20_res_pool_funcs;
3448
3449 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3450 pool->base.res_cap = &res_cap_nv14;
3451 pool->base.pipe_count = 5;
3452 pool->base.mpcc_count = 5;
3453 } else {
3454 pool->base.res_cap = &res_cap_nv10;
3455 pool->base.pipe_count = 6;
3456 pool->base.mpcc_count = 6;
3457 }
3458
3459
3460
3461 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3462
3463 dc->caps.max_downscale_ratio = 200;
3464 dc->caps.i2c_speed_in_khz = 100;
3465 dc->caps.max_cursor_size = 256;
3466 dc->caps.dmdata_alloc_size = 2048;
3467
3468 dc->caps.max_slave_planes = 1;
3469 dc->caps.post_blend_color_processing = true;
3470 dc->caps.force_dp_tps4_for_cp2520 = true;
3471 dc->caps.hw_3d_lut = true;
3472
3473 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
3474 dc->debug = debug_defaults_drv;
3475 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3476 pool->base.pipe_count = 4;
3477 pool->base.mpcc_count = pool->base.pipe_count;
3478 dc->debug = debug_defaults_diags;
3479 } else {
3480 dc->debug = debug_defaults_diags;
3481 }
3482
3483 dc->work_arounds.dedcn20_305_wa = true;
3484
3485
3486 if (dc->vm_helper)
3487 vm_helper_init(dc->vm_helper, 16);
3488
3489
3490
3491
3492
3493 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3494 dcn20_clock_source_create(ctx, ctx->dc_bios,
3495 CLOCK_SOURCE_COMBO_PHY_PLL0,
3496 &clk_src_regs[0], false);
3497 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3498 dcn20_clock_source_create(ctx, ctx->dc_bios,
3499 CLOCK_SOURCE_COMBO_PHY_PLL1,
3500 &clk_src_regs[1], false);
3501 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3502 dcn20_clock_source_create(ctx, ctx->dc_bios,
3503 CLOCK_SOURCE_COMBO_PHY_PLL2,
3504 &clk_src_regs[2], false);
3505 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3506 dcn20_clock_source_create(ctx, ctx->dc_bios,
3507 CLOCK_SOURCE_COMBO_PHY_PLL3,
3508 &clk_src_regs[3], false);
3509 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3510 dcn20_clock_source_create(ctx, ctx->dc_bios,
3511 CLOCK_SOURCE_COMBO_PHY_PLL4,
3512 &clk_src_regs[4], false);
3513 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3514 dcn20_clock_source_create(ctx, ctx->dc_bios,
3515 CLOCK_SOURCE_COMBO_PHY_PLL5,
3516 &clk_src_regs[5], false);
3517 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3518
3519 pool->base.dp_clock_source =
3520 dcn20_clock_source_create(ctx, ctx->dc_bios,
3521 CLOCK_SOURCE_ID_DP_DTO,
3522 &clk_src_regs[0], true);
3523
3524 for (i = 0; i < pool->base.clk_src_count; i++) {
3525 if (pool->base.clock_sources[i] == NULL) {
3526 dm_error("DC: failed to create clock sources!\n");
3527 BREAK_TO_DEBUGGER();
3528 goto create_fail;
3529 }
3530 }
3531
3532 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3533 if (pool->base.dccg == NULL) {
3534 dm_error("DC: failed to create dccg!\n");
3535 BREAK_TO_DEBUGGER();
3536 goto create_fail;
3537 }
3538
3539 pool->base.dmcu = dcn20_dmcu_create(ctx,
3540 &dmcu_regs,
3541 &dmcu_shift,
3542 &dmcu_mask);
3543 if (pool->base.dmcu == NULL) {
3544 dm_error("DC: failed to create dmcu!\n");
3545 BREAK_TO_DEBUGGER();
3546 goto create_fail;
3547 }
3548
3549 pool->base.abm = dce_abm_create(ctx,
3550 &abm_regs,
3551 &abm_shift,
3552 &abm_mask);
3553 if (pool->base.abm == NULL) {
3554 dm_error("DC: failed to create abm!\n");
3555 BREAK_TO_DEBUGGER();
3556 goto create_fail;
3557 }
3558
3559 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3560
3561
3562 if (!init_soc_bounding_box(dc, pool)) {
3563 dm_error("DC: failed to initialize soc bounding box!\n");
3564 BREAK_TO_DEBUGGER();
3565 goto create_fail;
3566 }
3567
3568 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
3569
3570 if (!dc->debug.disable_pplib_wm_range) {
3571 struct pp_smu_wm_range_sets ranges = {0};
3572 int i = 0;
3573
3574 ranges.num_reader_wm_sets = 0;
3575
3576 if (loaded_bb->num_states == 1) {
3577 ranges.reader_wm_sets[0].wm_inst = i;
3578 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3579 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3580 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3581 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3582
3583 ranges.num_reader_wm_sets = 1;
3584 } else if (loaded_bb->num_states > 1) {
3585 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
3586 ranges.reader_wm_sets[i].wm_inst = i;
3587 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3588 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3589 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3590 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
3591
3592 ranges.num_reader_wm_sets = i + 1;
3593 }
3594
3595 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3596 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3597 }
3598
3599 ranges.num_writer_wm_sets = 1;
3600
3601 ranges.writer_wm_sets[0].wm_inst = 0;
3602 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3603 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3604 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3605 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3606
3607
3608 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3609 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3610 }
3611
3612 init_data.ctx = dc->ctx;
3613 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3614 if (!pool->base.irqs)
3615 goto create_fail;
3616
3617
3618 for (i = 0; i < pool->base.pipe_count; i++) {
3619 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3620 if (pool->base.hubps[i] == NULL) {
3621 BREAK_TO_DEBUGGER();
3622 dm_error(
3623 "DC: failed to create memory input!\n");
3624 goto create_fail;
3625 }
3626
3627 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3628 if (pool->base.ipps[i] == NULL) {
3629 BREAK_TO_DEBUGGER();
3630 dm_error(
3631 "DC: failed to create input pixel processor!\n");
3632 goto create_fail;
3633 }
3634
3635 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3636 if (pool->base.dpps[i] == NULL) {
3637 BREAK_TO_DEBUGGER();
3638 dm_error(
3639 "DC: failed to create dpps!\n");
3640 goto create_fail;
3641 }
3642 }
3643 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3644 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3645 if (pool->base.engines[i] == NULL) {
3646 BREAK_TO_DEBUGGER();
3647 dm_error(
3648 "DC:failed to create aux engine!!\n");
3649 goto create_fail;
3650 }
3651 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3652 if (pool->base.hw_i2cs[i] == NULL) {
3653 BREAK_TO_DEBUGGER();
3654 dm_error(
3655 "DC:failed to create hw i2c!!\n");
3656 goto create_fail;
3657 }
3658 pool->base.sw_i2cs[i] = NULL;
3659 }
3660
3661 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3662 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3663 if (pool->base.opps[i] == NULL) {
3664 BREAK_TO_DEBUGGER();
3665 dm_error(
3666 "DC: failed to create output pixel processor!\n");
3667 goto create_fail;
3668 }
3669 }
3670
3671 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3672 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3673 ctx, i);
3674 if (pool->base.timing_generators[i] == NULL) {
3675 BREAK_TO_DEBUGGER();
3676 dm_error("DC: failed to create tg!\n");
3677 goto create_fail;
3678 }
3679 }
3680
3681 pool->base.timing_generator_count = i;
3682
3683 pool->base.mpc = dcn20_mpc_create(ctx);
3684 if (pool->base.mpc == NULL) {
3685 BREAK_TO_DEBUGGER();
3686 dm_error("DC: failed to create mpc!\n");
3687 goto create_fail;
3688 }
3689
3690 pool->base.hubbub = dcn20_hubbub_create(ctx);
3691 if (pool->base.hubbub == NULL) {
3692 BREAK_TO_DEBUGGER();
3693 dm_error("DC: failed to create hubbub!\n");
3694 goto create_fail;
3695 }
3696
3697 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3698 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3699 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3700 if (pool->base.dscs[i] == NULL) {
3701 BREAK_TO_DEBUGGER();
3702 dm_error("DC: failed to create display stream compressor %d!\n", i);
3703 goto create_fail;
3704 }
3705 }
3706 #endif
3707
3708 if (!dcn20_dwbc_create(ctx, &pool->base)) {
3709 BREAK_TO_DEBUGGER();
3710 dm_error("DC: failed to create dwbc!\n");
3711 goto create_fail;
3712 }
3713 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3714 BREAK_TO_DEBUGGER();
3715 dm_error("DC: failed to create mcif_wb!\n");
3716 goto create_fail;
3717 }
3718
3719 if (!resource_construct(num_virtual_links, dc, &pool->base,
3720 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3721 &res_create_funcs : &res_create_maximus_funcs)))
3722 goto create_fail;
3723
3724 dcn20_hw_sequencer_construct(dc);
3725
3726 dc->caps.max_planes = pool->base.pipe_count;
3727
3728 for (i = 0; i < dc->caps.max_planes; ++i)
3729 dc->caps.planes[i] = plane_cap;
3730
3731 dc->cap_funcs = cap_funcs;
3732
3733 return true;
3734
3735 create_fail:
3736
3737 destruct(pool);
3738
3739 return false;
3740 }
3741
3742 struct resource_pool *dcn20_create_resource_pool(
3743 const struct dc_init_data *init_data,
3744 struct dc *dc)
3745 {
3746 struct dcn20_resource_pool *pool =
3747 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3748
3749 if (!pool)
3750 return NULL;
3751
3752 if (construct(init_data->num_virtual_links, dc, pool))
3753 return &pool->base;
3754
3755 BREAK_TO_DEBUGGER();
3756 kfree(pool);
3757 return NULL;
3758 }