drivers/gpu/drm/amd/display/dc/dcn20/dcn20

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   1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice shall be included in
  11  * all copies or substantial portions of the Software.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19  * OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * Authors: AMD
  22  *
  23  */
  24 
  25 #ifndef __DC_MPCC_DCN20_H__
  26 #define __DC_MPCC_DCN20_H__
  27 
  28 #include "dcn10/dcn10_mpc.h"
  29 
  30 #define TO_DCN20_MPC(mpc_base) \
  31         container_of(mpc_base, struct dcn20_mpc, base)
  32 
  33 #define MPC_REG_LIST_DCN2_0(inst)\
  34         MPC_COMMON_REG_LIST_DCN1_0(inst),\
  35         SRII(MPCC_TOP_GAIN, MPCC, inst),\
  36         SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
  37         SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
  38         SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
  39         SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
  40         SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
  41         SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
  42         SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
  43         SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
  44         SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
  45         SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\
  46         SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\
  47         SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
  48         SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\
  49         SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
  50         SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\
  51         SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\
  52         SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\
  53         SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\
  54         SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\
  55         SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\
  56         SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\
  57         SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\
  58         SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\
  59         SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\
  60         SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
  61         SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\
  62         SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
  63         SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\
  64         SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\
  65         SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\
  66         SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
  67         SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
  68         SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\
  69         SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\
  70         SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
  71 
  72 #define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) \
  73         MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\
  74         SRII(CSC_MODE, MPC_OUT, inst),\
  75         SRII(CSC_C11_C12_A, MPC_OUT, inst),\
  76         SRII(CSC_C33_C34_A, MPC_OUT, inst),\
  77         SRII(CSC_C11_C12_B, MPC_OUT, inst),\
  78         SRII(CSC_C33_C34_B, MPC_OUT, inst),\
  79         SRII(DENORM_CONTROL, MPC_OUT, inst),\
  80         SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
  81         SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)
  82 
  83 #define MPC_REG_VARIABLE_LIST_DCN2_0 \
  84         MPC_COMMON_REG_VARIABLE_LIST \
  85         uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
  86         uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \
  87         uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \
  88         uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \
  89         uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \
  90         uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \
  91         uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \
  92         uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \
  93         uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \
  94         uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \
  95         uint32_t MPCC_OGAM_RAMA_END_CNTL2_B[MAX_MPCC]; \
  96         uint32_t MPCC_OGAM_RAMA_END_CNTL1_G[MAX_MPCC]; \
  97         uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \
  98         uint32_t MPCC_OGAM_RAMA_END_CNTL1_R[MAX_MPCC]; \
  99         uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \
 100         uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \
 101         uint32_t MPCC_OGAM_RAMA_REGION_32_33[MAX_MPCC]; \
 102         uint32_t MPCC_OGAM_RAMB_START_CNTL_B[MAX_MPCC]; \
 103         uint32_t MPCC_OGAM_RAMB_START_CNTL_G[MAX_MPCC]; \
 104         uint32_t MPCC_OGAM_RAMB_START_CNTL_R[MAX_MPCC]; \
 105         uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_B[MAX_MPCC]; \
 106         uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_G[MAX_MPCC]; \
 107         uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_R[MAX_MPCC]; \
 108         uint32_t MPCC_OGAM_RAMB_END_CNTL1_B[MAX_MPCC]; \
 109         uint32_t MPCC_OGAM_RAMB_END_CNTL2_B[MAX_MPCC]; \
 110         uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \
 111         uint32_t MPCC_OGAM_RAMB_END_CNTL2_G[MAX_MPCC]; \
 112         uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \
 113         uint32_t MPCC_OGAM_RAMB_END_CNTL2_R[MAX_MPCC]; \
 114         uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \
 115         uint32_t MPCC_OGAM_RAMB_REGION_32_33[MAX_MPCC];\
 116         uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\
 117         uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\
 118         uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\
 119         uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\
 120         uint32_t MPCC_OGAM_MODE[MAX_MPCC];\
 121         uint32_t CSC_MODE[MAX_OPP]; \
 122         uint32_t CSC_C11_C12_A[MAX_OPP]; \
 123         uint32_t CSC_C33_C34_A[MAX_OPP]; \
 124         uint32_t CSC_C11_C12_B[MAX_OPP]; \
 125         uint32_t CSC_C33_C34_B[MAX_OPP]; \
 126         uint32_t DENORM_CONTROL[MAX_OPP]; \
 127         uint32_t DENORM_CLAMP_G_Y[MAX_OPP]; \
 128         uint32_t DENORM_CLAMP_B_CB[MAX_OPP];
 129 
 130 #define MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
 131         MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
 132         SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
 133         SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
 134         SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
 135         SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
 136         SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
 137         SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
 138         SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
 139         SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
 140         SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
 141         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
 142         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
 143         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
 144         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
 145         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
 146         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
 147         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
 148         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
 149         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
 150         SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
 151         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\
 152         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
 153         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\
 154         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
 155         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\
 156         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\
 157         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\
 158         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
 159         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
 160         SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
 161         SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
 162         SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
 163         SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
 164         SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
 165         SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
 166         SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\
 167         SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
 168         SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\
 169         SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
 170         SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
 171         SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
 172         SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
 173         SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
 174         SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
 175         SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh)
 176 
 177 
 178 #define MPC_REG_FIELD_LIST_DCN2_0(type) \
 179         MPC_REG_FIELD_LIST(type)\
 180         type MPCC_BG_BPC;\
 181         type MPCC_BOT_GAIN_MODE;\
 182         type MPCC_TOP_GAIN;\
 183         type MPCC_BOT_GAIN_INSIDE;\
 184         type MPCC_BOT_GAIN_OUTSIDE;\
 185         type MPC_OCSC_MODE;\
 186         type MPC_OCSC_C11_A;\
 187         type MPC_OCSC_C12_A;\
 188         type MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;\
 189         type MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;\
 190         type MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;\
 191         type MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;\
 192         type MPCC_OGAM_RAMA_EXP_REGION_END_B;\
 193         type MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;\
 194         type MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;\
 195         type MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;\
 196         type MPCC_OGAM_RAMA_EXP_REGION_START_B;\
 197         type MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;\
 198         type MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET;\
 199         type MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS;\
 200         type MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET;\
 201         type MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS;\
 202         type MPCC_OGAM_RAMB_EXP_REGION_END_B;\
 203         type MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B;\
 204         type MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B;\
 205         type MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;\
 206         type MPCC_OGAM_RAMB_EXP_REGION_START_B;\
 207         type MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B;\
 208         type MPCC_OGAM_MEM_PWR_FORCE;\
 209         type MPCC_OGAM_LUT_INDEX;\
 210         type MPCC_OGAM_LUT_WRITE_EN_MASK;\
 211         type MPCC_OGAM_LUT_RAM_SEL;\
 212         type MPCC_OGAM_CONFIG_STATUS;\
 213         type MPCC_OGAM_LUT_DATA;\
 214         type MPCC_OGAM_MODE;\
 215         type MPC_OUT_DENORM_MODE;\
 216         type MPC_OUT_DENORM_CLAMP_MAX_R_CR;\
 217         type MPC_OUT_DENORM_CLAMP_MIN_R_CR;\
 218         type MPC_OUT_DENORM_CLAMP_MAX_G_Y;\
 219         type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\
 220         type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\
 221         type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\
 222         type MPCC_DISABLED;\
 223         type MPCC_OGAM_MEM_PWR_DIS;
 224 
 225 struct dcn20_mpc_registers {
 226         MPC_REG_VARIABLE_LIST_DCN2_0
 227 };
 228 
 229 struct dcn20_mpc_shift {
 230         MPC_REG_FIELD_LIST_DCN2_0(uint8_t)
 231 };
 232 
 233 struct dcn20_mpc_mask {
 234         MPC_REG_FIELD_LIST_DCN2_0(uint32_t)
 235 };
 236 
 237 struct dcn20_mpc {
 238         struct mpc base;
 239 
 240         int mpcc_in_use_mask;
 241         int num_mpcc;
 242         const struct dcn20_mpc_registers *mpc_regs;
 243         const struct dcn20_mpc_shift *mpc_shift;
 244         const struct dcn20_mpc_mask *mpc_mask;
 245 };
 246 
 247 void dcn20_mpc_construct(struct dcn20_mpc *mpcc20,
 248         struct dc_context *ctx,
 249         const struct dcn20_mpc_registers *mpc_regs,
 250         const struct dcn20_mpc_shift *mpc_shift,
 251         const struct dcn20_mpc_mask *mpc_mask,
 252         int num_mpcc);
 253 
 254 void mpc2_update_blending(
 255         struct mpc *mpc,
 256         struct mpcc_blnd_cfg *blnd_cfg,
 257         int mpcc_id);
 258 
 259 void mpc2_set_denorm(
 260         struct mpc *mpc,
 261         int opp_id,
 262         enum dc_color_depth output_depth);
 263 
 264 void mpc2_set_denorm_clamp(
 265         struct mpc *mpc,
 266         int opp_id,
 267         struct mpc_denorm_clamp denorm_clamp);
 268 
 269 void mpc2_set_output_csc(
 270         struct mpc *mpc,
 271         int opp_id,
 272         const uint16_t *regval,
 273         enum mpc_output_csc_mode ocsc_mode);
 274 
 275 void mpc2_set_ocsc_default(
 276         struct mpc *mpc,
 277         int opp_id,
 278         enum dc_color_space color_space,
 279         enum mpc_output_csc_mode ocsc_mode);
 280 
 281 void mpc2_set_output_gamma(
 282         struct mpc *mpc,
 283         int mpcc_id,
 284         const struct pwl_params *params);
 285 
 286 void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
 287 void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
 288 void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
 289 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h

INCLUDED FROM
